From nobody Fri Sep 25 11:05:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E1E42E7396; Mon, 14 Sep 2026 01:47:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789350464; cv=none; b=bEZWUvLgSQqkGoDtwKOmq/2c3eEhT/C9Zasn4eAvINBnPY6u9nhWD/walvv3BCilco0Qz2LEV8HDXX6fmWD9vim8a0FIp4hUXgz3E7B3V1LuwrDKlkowGy8MM68vEyeq3pX3diGuLtniG9bDhsOVyP1l6YrMSBZwI86unSwpegU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789350464; c=relaxed/simple; bh=pxJzxFGmovWLPUDuWUNj9KZYnkLCj1OxBc/huuuNsV4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=E37W/Gyq3/WEpm0+ca9veYHeXGNKcgqJLhS0dGaRsr3rMmafMGb5Z760aBi0Ea0XZMTSootloPM3uMhsvY2GF4dGPh9CP/U/1gkA3FSoF5myTF4QUFL2F1sWS9t2WYjv1BkG9ESgUQkT1yEVwrt7mZpsx3G4b/XVuRm6oXQ5kMQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=USWZnZbs; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="USWZnZbs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789350462; x=1820886462; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pxJzxFGmovWLPUDuWUNj9KZYnkLCj1OxBc/huuuNsV4=; b=USWZnZbspViz1l+3PSa24zVlix11Def6CRMJLp572yzqu0nFNQfiDAiV JJsXXZC3ZmLhJlSiGdMbEw+jM3s1Kvps5f87iGfndV/DRdXcZk+kizg56 EDPfXDA+0dunKsgwVzqijfNJVBevo3L2TlTt0hc6nJiFWKb1aiqbqKq9g Pt5wpDHPX2TTJFi1VjKa/l2LS8pzt78h9YcAGpj30pAkF2g9R2uv1RA/7 xkO2F0w3DlPmj/XPD4mGKQUsmFdm8D6MztsSq55TPxADvkAviIx9726Yb 4dEegg756mkVy9pYAl60yK9ByyD2J/CEAEcSA7sqqpYrzVuhO8s22Leyi A==; X-CSE-ConnectionGUID: mxNAPk0TReeS0SNay+MGjQ== X-CSE-MsgGUID: ufqe9Jj4TJ6itDRq7fMUIA== X-IronPort-AV: E=McAfee;i="6800,10657,11904"; a="93530599" X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="93530599" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2026 18:47:39 -0700 X-CSE-ConnectionGUID: 0pdkMLfaRoih3Gp+j6Jvqg== X-CSE-MsgGUID: LhH+G2tcRX6hZ6KNfCFD3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="276664150" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa005.jf.intel.com with ESMTP; 13 Sep 2026 18:47:37 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v11 01/10] perf dwarf-regs: Fix DWARF register index bounds check Date: Mon, 14 Sep 2026 09:40:40 +0800 Message-Id: <20260914014049.2061519-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> References: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tighten bounds validation in __get_dwarf_regnum_for_perf_regnum_xxx() helpers by changing perf_regnum > ARRAY_SIZE() to perf_regnum >=3D ARRAY_SIZE(). This fixes an off-by-one condition where perf_regnum =3D=3D ARRAY_SIZE() could pass validation and cause out-of-bounds access for dwarf_xxx_regnums[]. Signed-off-by: Dapeng Mi --- tools/perf/util/dwarf-regs-arch/dwarf-regs-csky.c | 2 +- tools/perf/util/dwarf-regs-arch/dwarf-regs-powerpc.c | 2 +- tools/perf/util/dwarf-regs-arch/dwarf-regs-s390.c | 2 +- tools/perf/util/dwarf-regs-arch/dwarf-regs-x86.c | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/perf/util/dwarf-regs-arch/dwarf-regs-csky.c b/tools/perf= /util/dwarf-regs-arch/dwarf-regs-csky.c index cb44b774f8d9..7f976aa3cfa2 100644 --- a/tools/perf/util/dwarf-regs-arch/dwarf-regs-csky.c +++ b/tools/perf/util/dwarf-regs-arch/dwarf-regs-csky.c @@ -118,7 +118,7 @@ int __get_dwarf_regnum_for_perf_regnum_csky(int perf_re= gnum, unsigned int flags) if (flags & EF_CSKY_ABIV2) idx++; =20 - if (perf_regnum < 0 || perf_regnum > (int)ARRAY_SIZE(dwarf_csky_regnums)= || + if (perf_regnum < 0 || perf_regnum >=3D (int)ARRAY_SIZE(dwarf_csky_regnum= s) || dwarf_csky_regnums[perf_regnum][idx] =3D=3D 0) return -ENOENT; =20 diff --git a/tools/perf/util/dwarf-regs-arch/dwarf-regs-powerpc.c b/tools/p= erf/util/dwarf-regs-arch/dwarf-regs-powerpc.c index 51892a09725b..98e7f2b2791c 100644 --- a/tools/perf/util/dwarf-regs-arch/dwarf-regs-powerpc.c +++ b/tools/perf/util/dwarf-regs-arch/dwarf-regs-powerpc.c @@ -128,7 +128,7 @@ int __get_dwarf_regnum_for_perf_regnum_powerpc(int perf= _regnum) if (perf_regnum =3D=3D 0) return 0; =20 - if (perf_regnum < 0 || perf_regnum > (int)ARRAY_SIZE(dwarf_powerpc_regnu= ms) || + if (perf_regnum < 0 || perf_regnum >=3D (int)ARRAY_SIZE(dwarf_powerpc_reg= nums) || dwarf_powerpc_regnums[perf_regnum] =3D=3D 0) return -ENOENT; =20 diff --git a/tools/perf/util/dwarf-regs-arch/dwarf-regs-s390.c b/tools/perf= /util/dwarf-regs-arch/dwarf-regs-s390.c index 310a37451bdc..9cef846ef9c0 100644 --- a/tools/perf/util/dwarf-regs-arch/dwarf-regs-s390.c +++ b/tools/perf/util/dwarf-regs-arch/dwarf-regs-s390.c @@ -45,7 +45,7 @@ int __get_dwarf_regnum_for_perf_regnum_s390(int perf_regn= um) if (perf_regnum =3D=3D 0) return 0; =20 - if (perf_regnum < 0 || perf_regnum > (int)ARRAY_SIZE(dwarf_s390_regnums)= || + if (perf_regnum < 0 || perf_regnum >=3D (int)ARRAY_SIZE(dwarf_s390_regnum= s) || dwarf_s390_regnums[perf_regnum] =3D=3D 0) return -ENOENT; =20 diff --git a/tools/perf/util/dwarf-regs-arch/dwarf-regs-x86.c b/tools/perf/= util/dwarf-regs-arch/dwarf-regs-x86.c index cadef120aeb4..c2a70e03b1a9 100644 --- a/tools/perf/util/dwarf-regs-arch/dwarf-regs-x86.c +++ b/tools/perf/util/dwarf-regs-arch/dwarf-regs-x86.c @@ -197,7 +197,7 @@ int __get_dwarf_regnum_for_perf_regnum_i386(int perf_re= gnum) if (perf_regnum =3D=3D 0) return 0; =20 - if (perf_regnum < 0 || perf_regnum > (int)ARRAY_SIZE(dwarf_i386_regnums)= || + if (perf_regnum < 0 || perf_regnum >=3D (int)ARRAY_SIZE(dwarf_i386_regnum= s) || dwarf_i386_regnums[perf_regnum] =3D=3D 0) return -ENOENT; =20 @@ -252,7 +252,7 @@ int __get_dwarf_regnum_for_perf_regnum_x86_64(int perf_= regnum) if (perf_regnum =3D=3D 0) return 0; =20 - if (perf_regnum < 0 || perf_regnum > (int)ARRAY_SIZE(dwarf_x86_64_regnum= s) || + if (perf_regnum < 0 || perf_regnum >=3D (int)ARRAY_SIZE(dwarf_x86_64_regn= ums) || dwarf_x86_64_regnums[perf_regnum] =3D=3D 0) return -ENOENT; =20 --=20 2.34.1 From nobody Fri Sep 25 11:05:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36FAB2F8EBB; Mon, 14 Sep 2026 01:47:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; 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d="scan'208";a="93530607" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2026 18:47:42 -0700 X-CSE-ConnectionGUID: fDuKeHvjT3GU05AtqwEzWg== X-CSE-MsgGUID: 2fy07q8mT0mRGrUb/T1uaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="276664158" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa005.jf.intel.com with ESMTP; 13 Sep 2026 18:47:40 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v11 02/10] perf util: Add missed fields in _attr__fprintf() and __attr_swap() Date: Mon, 14 Sep 2026 09:40:41 +0800 Message-Id: <20260914014049.2061519-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> References: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some new introduced perf_event_attr fields, like config3 and config4, are forgotten to add into perf_event_attr__fprintf() and perf_event__attr_swap() helpers. Add these missed fields into these 2 helpers. The aux_action is an exception. aux_action aliases bitfields (e.g. aux_start_paused) in a union. Bitfields and plain u32 fields follow different endian rules, so both views cannot be swapped correctly at the same time. Leave aux_action unswapped until the ABI is represented in a byte-order-safe form. Signed-off-by: Dapeng Mi --- tools/perf/util/perf_event_attr_fprintf.c | 4 ++++ tools/perf/util/session.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/tools/perf/util/perf_event_attr_fprintf.c b/tools/perf/util/pe= rf_event_attr_fprintf.c index 3933639d76c5..cc817294ad3d 100644 --- a/tools/perf/util/perf_event_attr_fprintf.c +++ b/tools/perf/util/perf_event_attr_fprintf.c @@ -405,6 +405,10 @@ int perf_event_attr__fprintf(FILE *fp, struct perf_eve= nt_attr *attr, PRINT_ATTRf_bf(aux_pause, p_unsigned); PRINT_ATTRf_bf(aux_resume, p_unsigned); } + if (attr_size >=3D offsetof(struct perf_event_attr, config4)) + PRINT_ATTRf(config3, p_hex); + if (attr_size > offsetof(struct perf_event_attr, config4)) + PRINT_ATTRf(config4, p_hex); =20 return ret; } diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index 3237870a1a34..212506aa8baa 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -629,6 +629,16 @@ do { \ bswap_field_32(aux_watermark); bswap_field_16(sample_max_stack); bswap_field_32(aux_sample_size); + /* + * aux_action aliases bitfields (e.g. aux_start_paused) in a union. + * Bitfields and plain u32 fields follow different endian rules, so + * both views cannot be swapped correctly at the same time. + * Leave aux_action unswapped until the ABI is represented in a + * byte-order-safe form. + */ + bswap_field_64(sig_data); + bswap_field_64(config3); + bswap_field_64(config4); =20 /* * After read_format are bitfields. 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Signed-off-by: Dapeng Mi --- tools/arch/x86/include/asm/msr-index.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/includ= e/asm/msr-index.h index 18c4be75e927..9c26d4075c5f 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -350,6 +350,13 @@ #define ARCH_PEBS_LBR_SHIFT 40 #define ARCH_PEBS_LBR (0x3ull << ARCH_PEBS_LBR_SHIFT) #define ARCH_PEBS_VECR_XMM BIT_ULL(49) +#define ARCH_PEBS_VECR_YMMH BIT_ULL(50) +#define ARCH_PEBS_VECR_EGPRS BIT_ULL(51) +#define ARCH_PEBS_VECR_OPMASK BIT_ULL(53) +#define ARCH_PEBS_VECR_ZMMH BIT_ULL(54) +#define ARCH_PEBS_VECR_H16ZMM BIT_ULL(55) +#define ARCH_PEBS_VECR_EXT_SHIFT 49 +#define ARCH_PEBS_VECR_EXT (0x7full << ARCH_PEBS_VECR_EXT_SHIFT) #define ARCH_PEBS_GPR BIT_ULL(61) #define ARCH_PEBS_AUX BIT_ULL(62) #define ARCH_PEBS_EN BIT_ULL(63) --=20 2.34.1 From nobody Fri Sep 25 11:05:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51E202E7165; Mon, 14 Sep 2026 01:47:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789350472; cv=none; b=kCruJEMjBnHkbGhNzJU/FL2RizfnfROtQS4vUyZ44wI1awG4kKsMnO/v+R25OjGz86AFTutzStCYji0qBKNnea/CRlAahkR36EyuQlb+ZSvcUBcwdxe7oaytMhIeFCEBr2YKfNFtQn1Tg+HuTj+IeZKYsRfXqC4KhSkkknbWjF8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789350472; c=relaxed/simple; bh=JG2Ey0DrEQayiqAXqRA60RZMoTa6uzAtzRyQQST9Eo4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=P1JT6eiNNJXTTLF3DBVjzNAI21LCBpcDbE6yJn4u/cuXdwSRBR1eNT58AStGUN+AkPhxM9lJoNwxBPjHcn9lRD3fgsInst0o5pDQVuAzjJjannDf5LpUfhAn+Iq6EmTDD08CB21yskVQSDeWI4jjMVryfxX+k0/jyb480dFFPyI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IlyTr/J3; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IlyTr/J3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789350469; x=1820886469; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JG2Ey0DrEQayiqAXqRA60RZMoTa6uzAtzRyQQST9Eo4=; b=IlyTr/J3RfdaeLJ419s3xDQxNYrNaHrs5mHFt+4D+mw3f5ov0q1iUhwQ eQSPL2zvWJuvGUER0AIU4cK4umuXuBnlIGyN1Ee21DB8xvRv0PA9Ugi2f euy76jIAhTvZaojPwy1TaCHaVLxDgN9BBoLWYehQL6UYfslDpB/6ozv8J pezQz5jKddYZ01GSsgCaTqWX7ztqXz3WavdjBGlm4x4vZIP3kr75guCg8 +hRrAgBKEqhaOOToXX0VWWDyCSUQYUheX3CNVtp1JWT4k5SPsPWKGPQ0U 8l2b2ZX10v2egK5MyrJ50wrKq8y5Zc91xfA7EOX8+X/OSXKar33Mroins Q==; X-CSE-ConnectionGUID: KGbgzq5DQu2FiWo/bM9+sQ== X-CSE-MsgGUID: y6lwT2VOR1mzEVtO3ICtMA== X-IronPort-AV: E=McAfee;i="6800,10657,11904"; a="93530630" X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="93530630" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2026 18:47:49 -0700 X-CSE-ConnectionGUID: 2T52nNYJQVCtAFuJp3pZmw== X-CSE-MsgGUID: cqG/7XTISQWpQOis4eJ3zw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="276664169" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa005.jf.intel.com with ESMTP; 13 Sep 2026 18:47:46 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi , Kan Liang Subject: [Patch v11 04/10] perf headers: Sync perf_event.h/perf_regs.h with the kernel headers Date: Mon, 14 Sep 2026 09:40:43 +0800 Message-Id: <20260914014049.2061519-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> References: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Sync the UAPI header changes of supporting SIMD/eGPRs/SSP sampling into corresponding tools UAPI headers. Additionally, support the new introduced perf_event_attr fields in the perf_event_attr__fprintf and perf_event__attr_swap() helpers, and add sanity check for the new introduced __reserved_4 field in perf_attr_check(). Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Dapeng Mi --- tools/arch/x86/include/uapi/asm/perf_regs.h | 53 +++++++++++++++++++++ tools/include/uapi/linux/perf_event.h | 49 +++++++++++++++++-- tools/perf/util/header.c | 3 +- tools/perf/util/perf_event_attr_fprintf.c | 11 ++++- tools/perf/util/session.c | 7 +++ 5 files changed, 117 insertions(+), 6 deletions(-) diff --git a/tools/arch/x86/include/uapi/asm/perf_regs.h b/tools/arch/x86/i= nclude/uapi/asm/perf_regs.h index 7c9d2bb3833b..faaa82df688d 100644 --- a/tools/arch/x86/include/uapi/asm/perf_regs.h +++ b/tools/arch/x86/include/uapi/asm/perf_regs.h @@ -2,6 +2,8 @@ #ifndef _ASM_X86_PERF_REGS_H #define _ASM_X86_PERF_REGS_H =20 +#include + enum perf_event_x86_regs { PERF_REG_X86_AX, PERF_REG_X86_BX, @@ -27,9 +29,35 @@ enum perf_event_x86_regs { PERF_REG_X86_R13, PERF_REG_X86_R14, PERF_REG_X86_R15, + /* + * The eGPRs/SSP and XMM have overlaps. Only one can be used + * at a time. The ABI PERF_SAMPLE_REGS_ABI_SIMD is used to + * distinguish which one is used. If PERF_SAMPLE_REGS_ABI_SIMD + * is set, then eGPRs/SSP is used, otherwise, XMM is used. + * + * Extended GPRs (eGPRs) + */ + PERF_REG_X86_R16, + PERF_REG_X86_R17, + PERF_REG_X86_R18, + PERF_REG_X86_R19, + PERF_REG_X86_R20, + PERF_REG_X86_R21, + PERF_REG_X86_R22, + PERF_REG_X86_R23, + PERF_REG_X86_R24, + PERF_REG_X86_R25, + PERF_REG_X86_R26, + PERF_REG_X86_R27, + PERF_REG_X86_R28, + PERF_REG_X86_R29, + PERF_REG_X86_R30, + PERF_REG_X86_R31, + PERF_REG_X86_SSP, /* These are the limits for the GPRs. */ PERF_REG_X86_32_MAX =3D PERF_REG_X86_GS + 1, PERF_REG_X86_64_MAX =3D PERF_REG_X86_R15 + 1, + PERF_REG_MISC_MAX =3D PERF_REG_X86_SSP + 1, =20 /* These all need two bits set because they are 128bit */ PERF_REG_X86_XMM0 =3D 32, @@ -54,5 +82,30 @@ enum perf_event_x86_regs { }; =20 #define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1)) +#define PERF_X86_EGPRS_MASK __GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R= 16) + +enum { + PERF_X86_SIMD_XMM_REGS =3D 16, + PERF_X86_SIMD_YMM_REGS =3D 16, + PERF_X86_SIMD_ZMM_REGS =3D 32, + PERF_X86_SIMD_VEC_REGS_MAX =3D PERF_X86_SIMD_ZMM_REGS, + + PERF_X86_SIMD_OPMASK_REGS =3D 8, + PERF_X86_SIMD_PRED_REGS_MAX =3D PERF_X86_SIMD_OPMASK_REGS, +}; + +#define PERF_X86_SIMD_PRED_MASK __GENMASK(PERF_X86_SIMD_PRED_REGS_MAX - 1,= 0) +#define PERF_X86_SIMD_VEC_MASK __GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - = 1, 0) + +#define PERF_X86_H16ZMM_BASE 16 + +enum { + /* 1 qword =3D 8 bytes */ + PERF_X86_OPMASK_QWORDS =3D 1, + PERF_X86_XMM_QWORDS =3D 2, + PERF_X86_YMM_QWORDS =3D 4, + PERF_X86_ZMM_QWORDS =3D 8, + PERF_X86_SIMD_QWORDS_MAX =3D PERF_X86_ZMM_QWORDS, +}; =20 #endif /* _ASM_X86_PERF_REGS_H */ diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/lin= ux/perf_event.h index fd10aa8d697f..c49fc76292f7 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -314,8 +314,9 @@ enum { */ enum perf_sample_regs_abi { PERF_SAMPLE_REGS_ABI_NONE =3D 0, - PERF_SAMPLE_REGS_ABI_32 =3D 1, - PERF_SAMPLE_REGS_ABI_64 =3D 2, + PERF_SAMPLE_REGS_ABI_32 =3D (1 << 0), + PERF_SAMPLE_REGS_ABI_64 =3D (1 << 1), + PERF_SAMPLE_REGS_ABI_SIMD =3D (1 << 2), }; =20 /* @@ -383,6 +384,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER7 128 /* Add: sig_data */ #define PERF_ATTR_SIZE_VER8 136 /* Add: config3 */ #define PERF_ATTR_SIZE_VER9 144 /* add: config4 */ +#define PERF_ATTR_SIZE_VER10 176 /* Add: sample_simd_{vec|pred}_reg_* */ =20 /* * 'struct perf_event_attr' contains various attributes that define @@ -547,6 +549,29 @@ struct perf_event_attr { =20 __u64 config3; /* extension of config2 */ __u64 config4; /* extension of config3 */ + + /* + * Defines the sampling SIMD/PRED(predicate) registers bitmap and + * qwords (8 bytes) length. + * + * sample_simd_regs_enabled !=3D 0 indicates there are SIMD/PRED + * registers to be sampled, the SIMD/PRED registers bitmap and + * qwords length are represented in + * sample_simd_{vec|pred}_reg_{intr|user} and + * sample_simd_{vec|pred}_reg_qwords fields separately. + * + * sample_simd_regs_enabled =3D=3D 0 indicates no SIMD/PRED registers + * are sampled. + */ + __u16 sample_simd_regs_enabled; + __u16 sample_simd_pred_reg_qwords; + __u16 sample_simd_vec_reg_qwords; + __u16 __reserved_4; + + __u32 sample_simd_pred_reg_intr; + __u32 sample_simd_pred_reg_user; + __u64 sample_simd_vec_reg_intr; + __u64 sample_simd_vec_reg_user; }; =20 /* @@ -1020,7 +1045,15 @@ enum perf_event_type { * } && PERF_SAMPLE_BRANCH_STACK * * { u64 abi; # enum perf_sample_regs_abi - * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER + * u64 regs[weight(mask)]; + * struct { + * u64 nr_vectors; # 0 ... weight(sample_simd_vec_reg_user) + * u64 vector_qwords; # 0 ... sample_simd_vec_reg_qwords + * u64 nr_pred; # 0 ... weight(sample_simd_pred_reg_user) + * u64 pred_qwords; # 0 ... sample_simd_pred_reg_qwords + * u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords]; + * } && (abi & PERF_SAMPLE_REGS_ABI_SIMD) + * } && PERF_SAMPLE_REGS_USER * * { u64 size; * char data[size]; @@ -1047,7 +1080,15 @@ enum perf_event_type { * { u64 data_src; } && PERF_SAMPLE_DATA_SRC * { u64 transaction; } && PERF_SAMPLE_TRANSACTION * { u64 abi; # enum perf_sample_regs_abi - * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR + * u64 regs[weight(mask)]; + * struct { + * u64 nr_vectors; # 0 ... weight(sample_simd_vec_reg_intr) + * u64 vector_qwords; # 0 ... sample_simd_vec_reg_qwords + * u64 nr_pred; # 0 ... weight(sample_simd_pred_reg_intr) + * u64 pred_qwords; # 0 ... sample_simd_pred_reg_qwords + * u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords]; + * } && (abi & PERF_SAMPLE_REGS_ABI_SIMD) + * } && PERF_SAMPLE_REGS_INTR * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR * { u64 cgroup;} && PERF_SAMPLE_CGROUP * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c index 7db7da090a1e..97665c1b892b 100644 --- a/tools/perf/util/header.c +++ b/tools/perf/util/header.c @@ -2163,7 +2163,8 @@ static void free_event_desc(struct evsel *events) =20 static bool perf_attr_check(struct perf_event_attr *attr) { - if (attr->__reserved_1 || attr->__reserved_2 || attr->__reserved_3) { + if (attr->__reserved_1 || attr->__reserved_2 || + attr->__reserved_3 || attr->__reserved_4) { pr_warning("Reserved bits are set unexpectedly. " "Please update perf tool.\n"); return false; diff --git a/tools/perf/util/perf_event_attr_fprintf.c b/tools/perf/util/pe= rf_event_attr_fprintf.c index cc817294ad3d..2e8be9a357dc 100644 --- a/tools/perf/util/perf_event_attr_fprintf.c +++ b/tools/perf/util/perf_event_attr_fprintf.c @@ -407,8 +407,17 @@ int perf_event_attr__fprintf(FILE *fp, struct perf_eve= nt_attr *attr, } if (attr_size >=3D offsetof(struct perf_event_attr, config4)) PRINT_ATTRf(config3, p_hex); - if (attr_size > offsetof(struct perf_event_attr, config4)) + if (attr_size >=3D offsetof(struct perf_event_attr, sample_simd_regs_enab= led)) PRINT_ATTRf(config4, p_hex); + if (attr_size > offsetof(struct perf_event_attr, sample_simd_vec_reg_user= )) { + PRINT_ATTRf(sample_simd_regs_enabled, p_unsigned); + PRINT_ATTRf(sample_simd_pred_reg_qwords, p_unsigned); + PRINT_ATTRf(sample_simd_pred_reg_intr, p_hex); + PRINT_ATTRf(sample_simd_pred_reg_user, p_hex); + PRINT_ATTRf(sample_simd_vec_reg_qwords, p_unsigned); + PRINT_ATTRf(sample_simd_vec_reg_intr, p_hex); + PRINT_ATTRf(sample_simd_vec_reg_user, p_hex); + } =20 return ret; } diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index 212506aa8baa..c7ac0e7c5c04 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -639,6 +639,13 @@ do { \ bswap_field_64(sig_data); bswap_field_64(config3); bswap_field_64(config4); + bswap_field_16(sample_simd_regs_enabled); + bswap_field_16(sample_simd_pred_reg_qwords); + bswap_field_16(sample_simd_vec_reg_qwords); + bswap_field_32(sample_simd_pred_reg_intr); + bswap_field_32(sample_simd_pred_reg_user); + bswap_field_64(sample_simd_vec_reg_intr); + bswap_field_64(sample_simd_vec_reg_user); =20 /* * After read_format are bitfields. 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The original XMM registers space in sample_regs_user/sample_regs_intr is reclaimed to represent the eGPRs and SSP when SIMD registers sampling is supported with the new SIMD sampling fields in the perf_event_attr structure. This necessitates a way to distinguish which register layout is used for the sample_regs_user/sample_regs_intr bitmap. To address this, a new "abi" argument is added to the helpers perf_intr_reg_mask(), perf_user_reg_mask(), and perf_reg_name(). When "abi & PERF_SAMPLE_REGS_ABI_SIMD" is true, it indicates the eGPRs and SSP layout is represented; otherwise, the legacy XMM registers are represented. Please note that PERF_SAMPLE_REGS_ABI_SIMD is set by default on platforms that support SIMD register sampling, even when no eGPR or SSP register is requested (for example, -Iax). As a result, sample_regs_intr and sample_regs_usr always use the new GPR layout on platforms with SIMD register sampling support. The patch only supports eGPRs and SSP sampling, the complete SIMD registers sampling would be supported in the next patch. Signed-off-by: Dapeng Mi --- tools/perf/builtin-script.c | 2 +- tools/perf/util/evsel.c | 27 +++- tools/perf/util/evsel.h | 7 + tools/perf/util/parse-regs-options.c | 35 +++-- .../perf/util/perf-regs-arch/perf_regs_x86.c | 124 +++++++++++++++--- tools/perf/util/perf_regs.c | 12 +- tools/perf/util/perf_regs.h | 10 +- tools/perf/util/record.h | 7 + .../scripting-engines/trace-event-python.c | 2 +- tools/perf/util/session.c | 13 +- tools/perf/util/synthetic-events.c | 4 + 11 files changed, 198 insertions(+), 45 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index ad8ca08ceb5f..ec3ce841b33e 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -734,7 +734,7 @@ static int perf_sample__fprintf_regs(struct regs_dump *= regs, uint64_t mask, for_each_set_bit(r, (unsigned long *) &mask, sizeof(mask) * 8) { u64 val =3D regs->regs[i++]; printed +=3D fprintf(fp, "%5s:0x%"PRIx64" ", - perf_reg_name(r, e_machine, e_flags), + perf_reg_name(r, e_machine, e_flags, regs->abi), val); } =20 diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index ce429eb247b6..bcd919c6bde8 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -1125,19 +1125,22 @@ static void __evsel__config_callchain(struct evsel = *evsel, const struct record_o } =20 if (param->record_mode =3D=3D CALLCHAIN_DWARF) { + int abi =3D -1; /* -1 indicates only basic GPRs are needed. */ + if (!function) { uint16_t e_machine =3D evsel__e_machine(evsel, /*e_flags=3D*/NULL); =20 evsel__set_sample_bit(evsel, REGS_USER); evsel__set_sample_bit(evsel, STACK_USER); if (opts->sample_user_regs && - DWARF_MINIMAL_REGS(e_machine) !=3D perf_user_reg_mask(EM_HOST)) { + DWARF_MINIMAL_REGS(e_machine) !=3D perf_user_reg_mask(EM_HOST, &abi= )) { attr->sample_regs_user |=3D DWARF_MINIMAL_REGS(e_machine); pr_warning("WARNING: The use of --call-graph=3Ddwarf may require all t= he user registers, " "specifying a subset with --user-regs may render DWARF unwinding u= nreliable, " "so the minimal registers set (IP, SP) is explicitly forced.\n"); } else { - attr->sample_regs_user |=3D perf_user_reg_mask(EM_HOST); + abi =3D -1; + attr->sample_regs_user |=3D perf_user_reg_mask(EM_HOST, &abi); } attr->sample_stack_user =3D param->dump_size; attr->exclude_callchain_user =3D 1; @@ -1663,12 +1666,18 @@ void evsel__config(struct evsel *evsel, const struc= t record_opts *opts, if (opts->sample_intr_regs && !evsel->no_aux_samples && !evsel__is_dummy_event(evsel)) { attr->sample_regs_intr =3D opts->sample_intr_regs; + attr->sample_simd_regs_enabled =3D + evsel__is_non_software_event(evsel) ? + !!opts->sample_simd_regs_enabled : 0; evsel__set_sample_bit(evsel, REGS_INTR); } =20 if (opts->sample_user_regs && !evsel->no_aux_samples && !evsel__is_dummy_event(evsel)) { attr->sample_regs_user |=3D opts->sample_user_regs; + attr->sample_simd_regs_enabled =3D + evsel__is_non_software_event(evsel) ? + !!opts->sample_simd_regs_enabled : 0; evsel__set_sample_bit(evsel, REGS_USER); } =20 @@ -3683,6 +3692,13 @@ int __evsel__parse_sample(struct evsel *evsel, union= perf_event *event, regs->mask =3D mask; regs->regs =3D (u64 *)array; array =3D (void *)array + sz; + + if (regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) { + /* Skip SIMD-regs header. */ + sz =3D 4 * sizeof(u64); + OVERFLOW_CHECK(array, sz, max_size); + array =3D (void *)array + sz; + } } } =20 @@ -3740,6 +3756,13 @@ int __evsel__parse_sample(struct evsel *evsel, union= perf_event *event, regs->mask =3D mask; regs->regs =3D (u64 *)array; array =3D (void *)array + sz; + + if (regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) { + /* Skip SIMD-regs header. */ + sz =3D 4 * sizeof(u64); + OVERFLOW_CHECK(array, sz, max_size); + array =3D (void *)array + sz; + } } } =20 diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index d9ecc6628217..6f759b0e86e9 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -587,6 +587,13 @@ static inline bool evsel__is_dummy_event(struct evsel = *evsel) (evsel->core.attr.config =3D=3D PERF_COUNT_SW_DUMMY); } =20 +static inline bool evsel__is_non_software_event(struct evsel *evsel) +{ + return (evsel->core.attr.type !=3D PERF_TYPE_SOFTWARE) && + (evsel->core.attr.type !=3D PERF_TYPE_TRACEPOINT) && + (evsel->core.attr.type !=3D PERF_TYPE_BREAKPOINT); +} + struct perf_session *evsel__session(struct evsel *evsel); struct perf_env *evsel__env(struct evsel *evsel); uint16_t evsel__e_machine(struct evsel *evsel, uint32_t *e_flags); diff --git a/tools/perf/util/parse-regs-options.c b/tools/perf/util/parse-r= egs-options.c index c93c2f0c8105..70a1cc90b2c1 100644 --- a/tools/perf/util/parse-regs-options.c +++ b/tools/perf/util/parse-regs-options.c @@ -6,11 +6,14 @@ #include #include "util/debug.h" #include +#include #include #include "util/perf_regs.h" #include "util/parse-regs-options.h" +#include "record.h" =20 -static void list_perf_regs(FILE *fp, uint64_t mask) +static void +list_perf_regs(FILE *fp, uint64_t mask, int abi) { const char *last_name =3D NULL; =20 @@ -21,7 +24,7 @@ static void list_perf_regs(FILE *fp, uint64_t mask) if (((1ULL << reg) & mask) =3D=3D 0) continue; =20 - name =3D perf_reg_name(reg, EM_HOST, EF_HOST); + name =3D perf_reg_name(reg, EM_HOST, EF_HOST, abi); if (name && (!last_name || strcmp(last_name, name))) fprintf(fp, "%s%s", reg > 0 ? " " : "", name); last_name =3D name; @@ -29,7 +32,8 @@ static void list_perf_regs(FILE *fp, uint64_t mask) fputc('\n', fp); } =20 -static uint64_t name_to_perf_reg_mask(const char *to_match, uint64_t mask) +static uint64_t +name_to_perf_reg_mask(const char *to_match, uint64_t mask, int abi) { uint64_t reg_mask =3D 0; =20 @@ -39,7 +43,7 @@ static uint64_t name_to_perf_reg_mask(const char *to_matc= h, uint64_t mask) if (((1ULL << reg) & mask) =3D=3D 0) continue; =20 - name =3D perf_reg_name(reg, EM_HOST, EF_HOST); + name =3D perf_reg_name(reg, EM_HOST, EF_HOST, abi); if (!name) continue; =20 @@ -53,9 +57,12 @@ static int __parse_regs(const struct option *opt, const char *str, int unset, bool in= tr) { uint64_t *mode =3D (uint64_t *)opt->value; + struct record_opts *opts; char *s, *os =3D NULL, *p; + const char *warn; int ret =3D -1; uint64_t mask; + int abi =3D 0; =20 if (unset) return 0; @@ -66,11 +73,16 @@ __parse_regs(const struct option *opt, const char *str,= int unset, bool intr) if (*mode) return -1; =20 - mask =3D intr ? perf_intr_reg_mask(EM_HOST) : perf_user_reg_mask(EM_HOST); + mask =3D intr ? perf_intr_reg_mask(EM_HOST, &abi) : + perf_user_reg_mask(EM_HOST, &abi); + opts =3D intr ? container_of(opt->value, struct record_opts, sample_intr_= regs) : + container_of(opt->value, struct record_opts, sample_user_regs); =20 /* str may be NULL in case no arg is passed to -I */ if (!str) { *mode =3D mask; + if (abi & PERF_SAMPLE_REGS_ABI_SIMD) + opts->sample_simd_regs_enabled =3D 1; return 0; } =20 @@ -79,6 +91,7 @@ __parse_regs(const struct option *opt, const char *str, i= nt unset, bool intr) if (!s) return -1; =20 + warn =3D "Unknown register \"%s\", check man page or run \"perf record %s= ?\"\n"; for (;;) { uint64_t reg_mask; =20 @@ -87,14 +100,16 @@ __parse_regs(const struct option *opt, const char *str= , int unset, bool intr) *p =3D '\0'; =20 if (!strcmp(s, "?")) { - list_perf_regs(stderr, mask); + list_perf_regs(stderr, mask, abi); goto error; } =20 - reg_mask =3D name_to_perf_reg_mask(s, mask); - if (reg_mask =3D=3D 0) { - ui__warning("Unknown register \"%s\", check man page or run \"perf reco= rd %s?\"\n", - s, intr ? "-I" : "--user-regs=3D"); + reg_mask =3D name_to_perf_reg_mask(s, mask, abi); + if (reg_mask) { + if (abi & PERF_SAMPLE_REGS_ABI_SIMD) + opts->sample_simd_regs_enabled =3D 1; + } else { + ui__warning(warn, s, intr ? "-I" : "--user-regs=3D"); goto error; } *mode |=3D reg_mask; diff --git a/tools/perf/util/perf-regs-arch/perf_regs_x86.c b/tools/perf/ut= il/perf-regs-arch/perf_regs_x86.c index b6d20522b4e8..ae26d991cdc9 100644 --- a/tools/perf/util/perf-regs-arch/perf_regs_x86.c +++ b/tools/perf/util/perf-regs-arch/perf_regs_x86.c @@ -235,26 +235,26 @@ int __perf_sdt_arg_parse_op_x86(char *old_op, char **= new_op) return SDT_ARG_VALID; } =20 -uint64_t __perf_reg_mask_x86(bool intr) +static uint64_t __arch__reg_mask(u64 sample_type, u64 mask, bool has_simd_= regs) { struct perf_event_attr attr =3D { - .type =3D PERF_TYPE_HARDWARE, - .config =3D PERF_COUNT_HW_CPU_CYCLES, - .sample_type =3D PERF_SAMPLE_REGS_INTR, - .sample_regs_intr =3D PERF_REG_EXTENDED_MASK, - .precise_ip =3D 1, - .disabled =3D 1, - .exclude_kernel =3D 1, + .type =3D PERF_TYPE_HARDWARE, + .config =3D PERF_COUNT_HW_CPU_CYCLES, + .sample_type =3D sample_type, + .precise_ip =3D 1, + .disabled =3D 1, + .exclude_kernel =3D 1, + .sample_simd_regs_enabled =3D has_simd_regs, }; int fd; - - if (!intr) - return PERF_REGS_MASK; - /* * In an unnamed union, init it here to build on older gcc versions */ attr.sample_period =3D 1; + if (sample_type =3D=3D PERF_SAMPLE_REGS_INTR) + attr.sample_regs_intr =3D mask; + else + attr.sample_regs_user =3D mask; =20 if (perf_pmus__num_core_pmus() > 1) { struct perf_pmu *pmu =3D NULL; @@ -276,13 +276,38 @@ uint64_t __perf_reg_mask_x86(bool intr) /*group_fd=3D*/-1, /*flags=3D*/0); if (fd !=3D -1) { close(fd); - return (PERF_REG_EXTENDED_MASK | PERF_REGS_MASK); + return mask; + } + + return 0; +} + +uint64_t __perf_reg_mask_x86(bool intr, int *abi) +{ + u64 sample_type =3D intr ? PERF_SAMPLE_REGS_INTR : PERF_SAMPLE_REGS_USER; + uint64_t mask =3D PERF_REGS_MASK; + + /* -1 indicates only basic GPRs are needed. */ + if (*abi < 0) + return PERF_REGS_MASK; + + *abi =3D 0; + mask |=3D __arch__reg_mask(sample_type, + GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R16), + true); + mask |=3D __arch__reg_mask(sample_type, BIT_ULL(PERF_REG_X86_SSP), true); + + if (mask !=3D PERF_REGS_MASK) { + *abi |=3D PERF_SAMPLE_REGS_ABI_SIMD; + } else { + mask |=3D __arch__reg_mask(sample_type, PERF_REG_EXTENDED_MASK, + false); } =20 - return PERF_REGS_MASK; + return mask; } =20 -const char *__perf_reg_name_x86(int id) +static const char *__arch_reg_gpr_name(int id) { switch (id) { case PERF_REG_X86_AX: @@ -333,7 +358,60 @@ const char *__perf_reg_name_x86(int id) return "R14"; case PERF_REG_X86_R15: return "R15"; + default: + return NULL; + } + + return NULL; +} =20 +static const char *__arch_reg_egpr_name(int id) +{ + switch (id) { + case PERF_REG_X86_R16: + return "R16"; + case PERF_REG_X86_R17: + return "R17"; + case PERF_REG_X86_R18: + return "R18"; + case PERF_REG_X86_R19: + return "R19"; + case PERF_REG_X86_R20: + return "R20"; + case PERF_REG_X86_R21: + return "R21"; + case PERF_REG_X86_R22: + return "R22"; + case PERF_REG_X86_R23: + return "R23"; + case PERF_REG_X86_R24: + return "R24"; + case PERF_REG_X86_R25: + return "R25"; + case PERF_REG_X86_R26: + return "R26"; + case PERF_REG_X86_R27: + return "R27"; + case PERF_REG_X86_R28: + return "R28"; + case PERF_REG_X86_R29: + return "R29"; + case PERF_REG_X86_R30: + return "R30"; + case PERF_REG_X86_R31: + return "R31"; + case PERF_REG_X86_SSP: + return "SSP"; + default: + return NULL; + } + + return NULL; +} + +static const char *__arch_reg_xmm_name(int id) +{ + switch (id) { #define XMM(x) \ case PERF_REG_X86_XMM ## x: \ case PERF_REG_X86_XMM ## x + 1: \ @@ -362,6 +440,22 @@ const char *__perf_reg_name_x86(int id) return NULL; } =20 +const char *__perf_reg_name_x86(int id, int abi) +{ + const char *name; + + name =3D __arch_reg_gpr_name(id); + if (name) + return name; + + if (abi & PERF_SAMPLE_REGS_ABI_SIMD) + name =3D __arch_reg_egpr_name(id); + else + name =3D __arch_reg_xmm_name(id); + + return name; +} + uint64_t __perf_reg_ip_x86(void) { return PERF_REG_X86_IP; diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c index 558c143abbab..089ededbae94 100644 --- a/tools/perf/util/perf_regs.c +++ b/tools/perf/util/perf_regs.c @@ -38,7 +38,7 @@ int perf_sdt_arg_parse_op(uint16_t e_machine, char *old_o= p, char **new_op) return ret; } =20 -uint64_t perf_intr_reg_mask(uint16_t e_machine) +uint64_t perf_intr_reg_mask(uint16_t e_machine, int *abi /*inout*/) { uint64_t mask =3D 0; =20 @@ -70,7 +70,7 @@ uint64_t perf_intr_reg_mask(uint16_t e_machine) break; case EM_386: case EM_X86_64: - mask =3D __perf_reg_mask_x86(/*intr=3D*/true); + mask =3D __perf_reg_mask_x86(/*intr=3D*/true, abi); break; default: pr_debug("Unknown ELF machine %d, interrupt sampling register mask will = be empty.\n", @@ -81,7 +81,7 @@ uint64_t perf_intr_reg_mask(uint16_t e_machine) return mask; } =20 -uint64_t perf_user_reg_mask(uint16_t e_machine) +uint64_t perf_user_reg_mask(uint16_t e_machine, int *abi /*inout*/) { uint64_t mask =3D 0; =20 @@ -113,7 +113,7 @@ uint64_t perf_user_reg_mask(uint16_t e_machine) break; case EM_386: case EM_X86_64: - mask =3D __perf_reg_mask_x86(/*intr=3D*/false); + mask =3D __perf_reg_mask_x86(/*intr=3D*/false, abi); break; default: pr_debug("Unknown ELF machine %d, user sampling register mask will be em= pty.\n", @@ -124,7 +124,7 @@ uint64_t perf_user_reg_mask(uint16_t e_machine) return mask; } =20 -const char *perf_reg_name(int id, uint16_t e_machine, uint32_t e_flags) +const char *perf_reg_name(int id, uint16_t e_machine, uint32_t e_flags, in= t abi) { const char *reg_name =3D NULL; =20 @@ -156,7 +156,7 @@ const char *perf_reg_name(int id, uint16_t e_machine, u= int32_t e_flags) break; case EM_386: case EM_X86_64: - reg_name =3D __perf_reg_name_x86(id); + reg_name =3D __perf_reg_name_x86(id, abi); break; default: break; diff --git a/tools/perf/util/perf_regs.h b/tools/perf/util/perf_regs.h index 79be2b791509..1c78549127cc 100644 --- a/tools/perf/util/perf_regs.h +++ b/tools/perf/util/perf_regs.h @@ -13,10 +13,10 @@ enum { }; =20 int perf_sdt_arg_parse_op(uint16_t e_machine, char *old_op, char **new_op); -uint64_t perf_intr_reg_mask(uint16_t e_machine); -uint64_t perf_user_reg_mask(uint16_t e_machine); +uint64_t perf_intr_reg_mask(uint16_t e_machine, int *abi /*inout*/); +uint64_t perf_user_reg_mask(uint16_t e_machine, int *abi /*inout*/); =20 -const char *perf_reg_name(int id, uint16_t e_machine, uint32_t e_flags); +const char *perf_reg_name(int id, uint16_t e_machine, uint32_t e_flags, in= t abi); int perf_reg_value(u64 *valp, struct regs_dump *regs, int id); uint64_t perf_arch_reg_ip(uint16_t e_machine); uint64_t perf_arch_reg_sp(uint16_t e_machine); @@ -66,8 +66,8 @@ uint64_t __perf_reg_sp_s390(void); int __perf_sdt_arg_parse_op_s390(char *old_op, char **new_op); =20 int __perf_sdt_arg_parse_op_x86(char *old_op, char **new_op); -uint64_t __perf_reg_mask_x86(bool intr); -const char *__perf_reg_name_x86(int id); +uint64_t __perf_reg_mask_x86(bool intr, int *abi); +const char *__perf_reg_name_x86(int id, int abi); uint64_t __perf_reg_ip_x86(void); uint64_t __perf_reg_sp_x86(void); =20 diff --git a/tools/perf/util/record.h b/tools/perf/util/record.h index 93627c9a7338..411bb7276ad7 100644 --- a/tools/perf/util/record.h +++ b/tools/perf/util/record.h @@ -62,6 +62,13 @@ struct record_opts { u64 branch_stack; u64 sample_intr_regs; u64 sample_user_regs; + u16 sample_simd_regs_enabled; + u16 sample_vec_reg_qwords; + u16 sample_pred_reg_qwords; + u32 sample_intr_pred_regs; + u32 sample_user_pred_regs; + u64 sample_intr_vec_regs; + u64 sample_user_vec_regs; u64 default_interval; u64 user_interval; size_t auxtrace_snapshot_size; diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools= /perf/util/scripting-engines/trace-event-python.c index 7e8e3a7df1b1..11877b56548f 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -730,7 +730,7 @@ static void regs_map(struct regs_dump *regs, uint64_t m= ask, uint16_t e_machine, =20 printed +=3D scnprintf(bf + printed, size - printed, "%5s:0x%" PRIx64 " ", - perf_reg_name(r, e_machine, e_flags), val); + perf_reg_name(r, e_machine, e_flags, regs->abi), val); } } =20 diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index c7ac0e7c5c04..90d4e45f09f0 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -1433,15 +1433,16 @@ static void branch_stack__printf(struct perf_sample= *sample, } } =20 -static void regs_dump__printf(u64 mask, u64 *regs, uint16_t e_machine, uin= t32_t e_flags) +static void regs_dump__printf(u64 mask, struct regs_dump *regs, + uint16_t e_machine, uint32_t e_flags) { unsigned rid, i =3D 0; =20 for_each_set_bit(rid, (unsigned long *) &mask, sizeof(mask) * 8) { - u64 val =3D regs[i++]; + u64 val =3D regs->regs[i++]; =20 printf(".... %-5s 0x%016" PRIx64 "\n", - perf_reg_name(rid, e_machine, e_flags), val); + perf_reg_name(rid, e_machine, e_flags, regs->abi), val); } } =20 @@ -1449,11 +1450,13 @@ static const char *regs_abi[] =3D { [PERF_SAMPLE_REGS_ABI_NONE] =3D "none", [PERF_SAMPLE_REGS_ABI_32] =3D "32-bit", [PERF_SAMPLE_REGS_ABI_64] =3D "64-bit", + [PERF_SAMPLE_REGS_ABI_SIMD | PERF_SAMPLE_REGS_ABI_32] =3D "32-bit SIMD", + [PERF_SAMPLE_REGS_ABI_SIMD | PERF_SAMPLE_REGS_ABI_64] =3D "64-bit SIMD", }; =20 static inline const char *regs_dump_abi(struct regs_dump *d) { - if (d->abi > PERF_SAMPLE_REGS_ABI_64) + if (d->abi >=3D ARRAY_SIZE(regs_abi) || !regs_abi[d->abi]) return "unknown"; =20 return regs_abi[d->abi]; @@ -1469,7 +1472,7 @@ static void regs__printf(const char *type, struct reg= s_dump *regs, mask, regs_dump_abi(regs)); =20 - regs_dump__printf(mask, regs->regs, e_machine, e_flags); + regs_dump__printf(mask, regs, e_machine, e_flags); } =20 static void regs_user__printf(struct perf_sample *sample, uint16_t e_machi= ne, uint32_t e_flags) diff --git a/tools/perf/util/synthetic-events.c b/tools/perf/util/synthetic= -events.c index 0c150193cca8..2779f63a442c 100644 --- a/tools/perf/util/synthetic-events.c +++ b/tools/perf/util/synthetic-events.c @@ -1644,6 +1644,8 @@ size_t perf_event__sample_event_size(const struct per= f_sample *sample, u64 type, if (sample->user_regs && sample->user_regs->abi) { result +=3D sizeof(u64); sz =3D hweight64(sample->user_regs->mask) * sizeof(u64); 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d="scan'208";a="93530655" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2026 18:47:57 -0700 X-CSE-ConnectionGUID: yZjTcbiVTEaWIRbJDQ5QFw== X-CSE-MsgGUID: P5+4ssBwSJmsUqYGYqu3TQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="276664191" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa005.jf.intel.com with ESMTP; 13 Sep 2026 18:47:53 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v11 06/10] perf regs: Support x86 SIMD registers sampling Date: Mon, 14 Sep 2026 09:40:45 +0800 Message-Id: <20260914014049.2061519-7-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> References: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the newly introduced SIMD register sampling format by adding the following 5 functions: uint64_t perf_intr_simd_reg_class_mask(uint16_t e_machine, bool pred); uint64_t perf_user_simd_reg_class_mask(uint16_t e_machine, bool pred); uint64_t perf_intr_simd_reg_class_bitmap_qwords(uint16_t e_machine, int reg= _c, uint16_t *qwords, bool pred); uint64_t perf_user_simd_reg_class_bitmap_qwords(uint16_t e_machine, int reg= _c, uint16_t *qwords, bool pred); const char *perf_simd_reg_class_name(uint16_t e_machine, int id, bool pred); The perf_{intr|user}_simd_reg_class_mask() functions retrieve the bitmap of kernel supported SIMD/PRED register classes on current platform for intr-regs and user-regs sampling, such as OPMASK/XMM/YMM/ZMM on x86 platforms. The perf_{intr|user}_simd_reg_class_bitmap_qwords() functions retrieve the bitmap and qwords length of a certain class of SIMD/PRED register on current platform for intr-regs and user-regs sampling. For example, for the XMM registers on x86 platforms, the returned bitmap is 0xffff (XMM0 ~ XMM15) and the qwords length is 2 (128 bits for each XMM register). The perf_simd_reg_class_name() function gets the register class name for a certain register class index. Additionally, the function __parse_regs() is enhanced to support parsing these newly introduced SIMD/PRED registers. Currently, each class of register can only be sampled collectively; sampling a specific SIMD register is not supported. For example, all XMM registers are sampled together rather than sampling only XMM0. When multiple overlapping register types, such as XMM and YMM, are sampled simultaneously, only the superset (YMM registers) is sampled. With this patch, all supported sampling registers on x86 platforms are displayed as follows. $perf record --intr-regs=3D? available registers: AX BX CX DX SI DI BP SP IP FLAGS CS SS R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 SSP XMM0-15 YMM0-15 ZMM0-31 OPMASK0-7 $perf record --user-regs=3D? available registers: AX BX CX DX SI DI BP SP IP FLAGS CS SS R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 SSP XMM0-15 YMM0-15 ZMM0-31 OPMASK0-7 Signed-off-by: Dapeng Mi Reviewed-by: Ian Rogers --- tools/perf/Documentation/perf-record.txt | 10 +- tools/perf/util/evsel.c | 21 ++ tools/perf/util/parse-regs-options.c | 185 +++++++++- .../perf/util/perf-regs-arch/perf_regs_x86.c | 316 +++++++++++++++++- tools/perf/util/perf_regs.c | 72 ++++ tools/perf/util/perf_regs.h | 11 + 6 files changed, 596 insertions(+), 19 deletions(-) diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Document= ation/perf-record.txt index 2c6510c5a87b..388455f9b07b 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -515,12 +515,16 @@ Capture machine state (registers) at interrupt, i.e.,= on counter overflows for each sample. List of captured registers depends on the architecture. This = option is off by default. It is possible to select the registers to sample using = their symbolic names, e.g. on x86, ax, si. To list the available registers use ---intr-regs=3D\?. To name registers, pass a comma separated list such as ---intr-regs=3Dax,bx. The list of register is architecture dependent. +--intr-regs=3D\?. On supported architectures, SIMD registers are displayed= as +groups (e.g., on x86: XMM0-15,YMM0-15,ZMM0-31). To name registers, pass a = comma +separated list such as --intr-regs=3Dax,bx,zmm. Please notice SIMD registe= rs must +be assigned as a complete set, sampling individual SIMD registers (e.g., z= mm0) +is not supported. The list of register is architecture dependent. =20 --user-regs:: Similar to -I, but capture user registers at sample time. To list the avai= lable -user registers use --user-regs=3D\?. +user registers use --user-regs=3D\?. For SIMD registers, only complete reg= ister +sets are allowed like -I. =20 --running-time:: Record running and enabled time for read events (:S) diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index bcd919c6bde8..df16780bf887 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -31,6 +31,7 @@ #include #include #include +#include =20 #include #include @@ -1672,6 +1673,16 @@ void evsel__config(struct evsel *evsel, const struct= record_opts *opts, evsel__set_sample_bit(evsel, REGS_INTR); } =20 + if ((opts->sample_intr_vec_regs || opts->sample_intr_pred_regs) && + !evsel->no_aux_samples && !evsel__is_dummy_event(evsel)) { + attr->sample_simd_regs_enabled =3D !!opts->sample_simd_regs_enabled; + attr->sample_simd_vec_reg_intr =3D opts->sample_intr_vec_regs; + attr->sample_simd_vec_reg_qwords =3D opts->sample_vec_reg_qwords; + attr->sample_simd_pred_reg_intr =3D opts->sample_intr_pred_regs; + attr->sample_simd_pred_reg_qwords =3D opts->sample_pred_reg_qwords; + evsel__set_sample_bit(evsel, REGS_INTR); + } + if (opts->sample_user_regs && !evsel->no_aux_samples && !evsel__is_dummy_event(evsel)) { attr->sample_regs_user |=3D opts->sample_user_regs; @@ -1681,6 +1692,16 @@ void evsel__config(struct evsel *evsel, const struct= record_opts *opts, evsel__set_sample_bit(evsel, REGS_USER); } =20 + if ((opts->sample_user_vec_regs || opts->sample_user_pred_regs) && + !evsel->no_aux_samples && !evsel__is_dummy_event(evsel)) { + attr->sample_simd_regs_enabled =3D !!opts->sample_simd_regs_enabled; + attr->sample_simd_vec_reg_user =3D opts->sample_user_vec_regs; + attr->sample_simd_vec_reg_qwords =3D opts->sample_vec_reg_qwords; + attr->sample_simd_pred_reg_user =3D opts->sample_user_pred_regs; + attr->sample_simd_pred_reg_qwords =3D opts->sample_pred_reg_qwords; + evsel__set_sample_bit(evsel, REGS_USER); + } + if (target__has_cpu(&opts->target) || opts->sample_cpu) evsel__set_sample_bit(evsel, CPU); =20 diff --git a/tools/perf/util/parse-regs-options.c b/tools/perf/util/parse-r= egs-options.c index 70a1cc90b2c1..709fcfb077a2 100644 --- a/tools/perf/util/parse-regs-options.c +++ b/tools/perf/util/parse-regs-options.c @@ -13,11 +13,10 @@ #include "record.h" =20 static void -list_perf_regs(FILE *fp, uint64_t mask, int abi) +__list_gp_regs(FILE *fp, uint64_t mask, int abi) { const char *last_name =3D NULL; =20 - fprintf(fp, "available registers: "); for (int reg =3D 0; reg < 64; reg++) { const char *name; =20 @@ -29,14 +28,68 @@ list_perf_regs(FILE *fp, uint64_t mask, int abi) fprintf(fp, "%s%s", reg > 0 ? " " : "", name); last_name =3D name; } +} + +static void +__list_simd_regs(FILE *fp, uint64_t mask, bool intr, bool pred) +{ + uint64_t bitmap =3D 0; + uint16_t qwords =3D 0; + const char *name; + int i =3D 0; + + for (int reg_c =3D 0; reg_c < 64; reg_c++) { + if (((1ULL << reg_c) & mask) =3D=3D 0) + continue; + + name =3D perf_simd_reg_class_name(EM_HOST, reg_c, pred); + bitmap =3D intr ? + perf_intr_simd_reg_class_bitmap_qwords(EM_HOST, reg_c, &qwords, pred) : + perf_user_simd_reg_class_bitmap_qwords(EM_HOST, reg_c, &qwords, pred); + if (name && bitmap) + fprintf(fp, "%s%s0-%d", i++ > 0 ? " " : "", + name, fls64(bitmap) - 1); + } +} + +static void +list_perf_regs(FILE *fp, uint64_t mask, uint64_t simd_mask, + uint64_t pred_mask, int abi, bool intr) +{ + bool printed =3D false; + + fprintf(fp, "available registers: "); + + if (mask) { + __list_gp_regs(fp, mask, abi); + printed =3D true; + } + + if (simd_mask) { + if (printed) + fprintf(fp, " "); + __list_simd_regs(fp, simd_mask, intr, /*pred=3D*/false); + printed =3D true; + } + + if (pred_mask) { + if (printed) + fprintf(fp, " "); + __list_simd_regs(fp, pred_mask, intr, /*pred=3D*/true); + printed =3D true; + } + fputc('\n', fp); } =20 static uint64_t -name_to_perf_reg_mask(const char *to_match, uint64_t mask, int abi) +name_to_gp_reg_mask(const char *to_match, uint64_t mask, int abi) { uint64_t reg_mask =3D 0; =20 + if (!mask) + return reg_mask; + for (int reg =3D 0; reg < 64; reg++) { const char *name; =20 @@ -53,26 +106,116 @@ name_to_perf_reg_mask(const char *to_match, uint64_t = mask, int abi) return reg_mask; } =20 +static bool +name_to_simd_reg_mask(struct record_opts *opts, const char *to_match, + uint64_t mask, bool intr, bool pred) +{ + bool matched =3D false; + uint64_t bitmap; + uint16_t qwords; + int reg_c; + + if (!mask) + return false; + + for (reg_c =3D 0; reg_c < 64; reg_c++) { + const char *name; + + if (((1ULL << reg_c) & mask) =3D=3D 0) + continue; + + name =3D perf_simd_reg_class_name(EM_HOST, reg_c, pred); + if (!name) + continue; + + if (!strcasecmp(to_match, name)) { + matched =3D true; + break; + } + } + + if (!matched) + return false; + + if (intr) { + bitmap =3D perf_intr_simd_reg_class_bitmap_qwords(EM_HOST, + reg_c, &qwords, pred); + } else { + bitmap =3D perf_user_simd_reg_class_bitmap_qwords(EM_HOST, + reg_c, &qwords, pred); + } + + /* + * Assume higher width SIMD registers are always the superset of lower + * width SIMD registers. So only pick the largest qwords and bitmap. + */ + if (pred) { + opts->sample_pred_reg_qwords =3D + MAX(qwords, opts->sample_pred_reg_qwords); + if (intr && + hweight64(bitmap) > hweight32(opts->sample_intr_pred_regs)) + opts->sample_intr_pred_regs =3D bitmap; + if (!intr && + hweight64(bitmap) > hweight32(opts->sample_user_pred_regs)) + opts->sample_user_pred_regs =3D bitmap; + + /* + * sample_intr_pred_regs and sample_user_pred_regs share + * sample_pred_reg_qwords. If both are set, keep their bitmaps identical. + */ + if (opts->sample_intr_pred_regs && opts->sample_user_pred_regs) { + uint64_t max_pred_regs =3D MAX(opts->sample_intr_pred_regs, + opts->sample_user_pred_regs); + + opts->sample_intr_pred_regs =3D max_pred_regs; + opts->sample_user_pred_regs =3D max_pred_regs; + } + } else { + opts->sample_vec_reg_qwords =3D + MAX(qwords, opts->sample_vec_reg_qwords); + if (intr && + hweight64(bitmap) > hweight64(opts->sample_intr_vec_regs)) + opts->sample_intr_vec_regs =3D bitmap; + if (!intr && + hweight64(bitmap) > hweight64(opts->sample_user_vec_regs)) + opts->sample_user_vec_regs =3D bitmap; + + /* + * sample_intr_vec_regs and sample_user_vec_regs share + * sample_vec_reg_qwords. If both are set, keep their bitmaps identical. + */ + if (opts->sample_intr_vec_regs && opts->sample_user_vec_regs) { + uint64_t max_vec_regs =3D MAX(opts->sample_intr_vec_regs, + opts->sample_user_vec_regs); + + opts->sample_intr_vec_regs =3D max_vec_regs; + opts->sample_user_vec_regs =3D max_vec_regs; + } + } + + if (opts->sample_pred_reg_qwords || opts->sample_vec_reg_qwords) + opts->sample_simd_regs_enabled =3D 1; + + return true; +} + static int __parse_regs(const struct option *opt, const char *str, int unset, bool in= tr) { uint64_t *mode =3D (uint64_t *)opt->value; struct record_opts *opts; char *s, *os =3D NULL, *p; + uint64_t simd_mask; + uint64_t pred_mask; + uint64_t mask; const char *warn; + bool matched; int ret =3D -1; - uint64_t mask; int abi =3D 0; =20 if (unset) return 0; =20 - /* - * cannot set it twice - */ - if (*mode) - return -1; - mask =3D intr ? perf_intr_reg_mask(EM_HOST, &abi) : perf_user_reg_mask(EM_HOST, &abi); opts =3D intr ? container_of(opt->value, struct record_opts, sample_intr_= regs) : @@ -91,6 +234,14 @@ __parse_regs(const struct option *opt, const char *str,= int unset, bool intr) if (!s) return -1; =20 + if (intr) { + simd_mask =3D perf_intr_simd_reg_class_mask(EM_HOST, /*pred=3D*/false); + pred_mask =3D perf_intr_simd_reg_class_mask(EM_HOST, /*pred=3D*/true); + } else { + simd_mask =3D perf_user_simd_reg_class_mask(EM_HOST, /*pred=3D*/false); + pred_mask =3D perf_user_simd_reg_class_mask(EM_HOST, /*pred=3D*/true); + } + warn =3D "Unknown register \"%s\", check man page or run \"perf record %s= ?\"\n"; for (;;) { uint64_t reg_mask; @@ -100,17 +251,23 @@ __parse_regs(const struct option *opt, const char *st= r, int unset, bool intr) *p =3D '\0'; =20 if (!strcmp(s, "?")) { - list_perf_regs(stderr, mask, abi); + list_perf_regs(stderr, mask, simd_mask, pred_mask, abi, intr); goto error; } =20 - reg_mask =3D name_to_perf_reg_mask(s, mask, abi); + reg_mask =3D name_to_gp_reg_mask(s, mask, abi); if (reg_mask) { if (abi & PERF_SAMPLE_REGS_ABI_SIMD) opts->sample_simd_regs_enabled =3D 1; } else { - ui__warning(warn, s, intr ? "-I" : "--user-regs=3D"); - goto error; + matched =3D name_to_simd_reg_mask(opts, s, simd_mask, + intr, /*pred=3D*/false) || + name_to_simd_reg_mask(opts, s, pred_mask, + intr, /*pred=3D*/true); + if (!matched) { + ui__warning(warn, s, intr ? "-I" : "--user-regs=3D"); + goto error; + } } *mode |=3D reg_mask; =20 diff --git a/tools/perf/util/perf-regs-arch/perf_regs_x86.c b/tools/perf/ut= il/perf-regs-arch/perf_regs_x86.c index ae26d991cdc9..fb6cf34f42f2 100644 --- a/tools/perf/util/perf-regs-arch/perf_regs_x86.c +++ b/tools/perf/util/perf-regs-arch/perf_regs_x86.c @@ -282,6 +282,7 @@ static uint64_t __arch__reg_mask(u64 sample_type, u64 m= ask, bool has_simd_regs) return 0; } =20 +static bool __support_simd_sampling(bool intr); uint64_t __perf_reg_mask_x86(bool intr, int *abi) { u64 sample_type =3D intr ? PERF_SAMPLE_REGS_INTR : PERF_SAMPLE_REGS_USER; @@ -300,8 +301,14 @@ uint64_t __perf_reg_mask_x86(bool intr, int *abi) if (mask !=3D PERF_REGS_MASK) { *abi |=3D PERF_SAMPLE_REGS_ABI_SIMD; } else { - mask |=3D __arch__reg_mask(sample_type, PERF_REG_EXTENDED_MASK, - false); + /* + * Use the SIMD sampling interface for XMM registers + * when available. + */ + if (!__support_simd_sampling(intr)) { + mask |=3D __arch__reg_mask(sample_type, + PERF_REG_EXTENDED_MASK, false); + } } =20 return mask; @@ -465,3 +472,308 @@ uint64_t __perf_reg_sp_x86(void) { return PERF_REG_X86_SP; } + +enum { + PERF_REG_CLASS_X86_OPMASK =3D 0, + PERF_REG_CLASS_X86_XMM, + PERF_REG_CLASS_X86_YMM, + PERF_REG_CLASS_X86_ZMM, + PERF_REG_X86_MAX_SIMD_CLASSES, +}; + +#define PERF_REG_CLASS_X86_PRED_MASK (BIT(PERF_REG_CLASS_X86_OPMASK)) +#define PERF_REG_CLASS_X86_SIMD_MASK (BIT(PERF_REG_CLASS_X86_XMM) | \ + BIT(PERF_REG_CLASS_X86_YMM) | \ + BIT(PERF_REG_CLASS_X86_ZMM)) + +/* + * This function is used to determine whether kernel perf subsystem + * supports which kinds of SIMD registers (OPMASK/XMM/YMM/ZMM) sampling. + * + * @sample_type: PERF_SAMPLE_REGS_INTR or PERF_SAMPLE_REGS_USER + * @qwords: the length of SIMD register, like 1/2/4/8 qwords for + * OPMASK/XMM/YMM/ZMM registers. + * @mask: the bitmask of SIMD register, like 0xffff for XMM0 ~ XMM15 + * @pred: whether It's a predicate SIMD register, like OPMASK register. + * + * Return value: true indicates support, otherwise no support. + */ +static bool +__support_simd_reg_class(uint64_t sample_type, uint16_t qwords, + uint64_t mask, bool pred) +{ + struct perf_event_attr attr =3D { + .type =3D PERF_TYPE_HARDWARE, + .config =3D PERF_COUNT_HW_CPU_CYCLES, + .sample_type =3D sample_type, + .disabled =3D 1, + .exclude_kernel =3D 1, + .sample_simd_regs_enabled =3D 1, + }; + int fd; + + attr.sample_period =3D 1; + + if (!pred) { + attr.sample_simd_vec_reg_qwords =3D qwords; + if (sample_type =3D=3D PERF_SAMPLE_REGS_INTR) + attr.sample_simd_vec_reg_intr =3D mask; + else + attr.sample_simd_vec_reg_user =3D mask; + } else { + attr.sample_simd_pred_reg_qwords =3D PERF_X86_OPMASK_QWORDS; + if (sample_type =3D=3D PERF_SAMPLE_REGS_INTR) + attr.sample_simd_pred_reg_intr =3D PERF_X86_SIMD_PRED_MASK; + else + attr.sample_simd_pred_reg_user =3D PERF_X86_SIMD_PRED_MASK; + } + + if (perf_pmus__num_core_pmus() > 1) { + __u64 type =3D perf_pmus__find_core_pmu()->type; + + attr.config |=3D type << PERF_PMU_TYPE_SHIFT; + } + + event_attr_init(&attr); + + fd =3D sys_perf_event_open(&attr, 0, -1, -1, 0); + if (fd !=3D -1) { + close(fd); + return true; + } + + return false; +} + +#define PERF_X86_SIMD_ZMM_LOW_REGS (PERF_X86_SIMD_ZMM_REGS / 2) + +static bool __arch_has_simd_reg_class(uint64_t sample_type, int reg_class, + uint64_t *mask, uint16_t *qwords) +{ + bool supported =3D false; + uint64_t bits; + + *mask =3D 0; + *qwords =3D 0; + + switch (reg_class) { + case PERF_REG_CLASS_X86_OPMASK: + bits =3D BIT_ULL(PERF_X86_SIMD_OPMASK_REGS) - 1; + supported =3D __support_simd_reg_class(sample_type, + PERF_X86_OPMASK_QWORDS, + bits, true); + if (supported) { + *mask =3D bits; + *qwords =3D PERF_X86_OPMASK_QWORDS; + } + break; + case PERF_REG_CLASS_X86_XMM: + bits =3D BIT_ULL(PERF_X86_SIMD_XMM_REGS) - 1; + supported =3D __support_simd_reg_class(sample_type, + PERF_X86_XMM_QWORDS, + bits, false); + if (supported) { + *mask =3D bits; + *qwords =3D PERF_X86_XMM_QWORDS; + } + break; + case PERF_REG_CLASS_X86_YMM: + bits =3D BIT_ULL(PERF_X86_SIMD_YMM_REGS) - 1; + supported =3D __support_simd_reg_class(sample_type, + PERF_X86_YMM_QWORDS, + bits, false); + if (supported) { + *mask =3D bits; + *qwords =3D PERF_X86_YMM_QWORDS; + } + break; + case PERF_REG_CLASS_X86_ZMM: + bits =3D BIT_ULL(PERF_X86_SIMD_ZMM_REGS) - 1; + supported =3D __support_simd_reg_class(sample_type, + PERF_X86_ZMM_QWORDS, + bits, false); + if (supported) { + *mask =3D bits; + *qwords =3D PERF_X86_ZMM_QWORDS; + break; + } + + bits =3D BIT_ULL(PERF_X86_SIMD_ZMM_LOW_REGS) - 1; + supported =3D __support_simd_reg_class(sample_type, + PERF_X86_ZMM_QWORDS, + bits, false); + if (supported) { + *mask =3D bits; + *qwords =3D PERF_X86_ZMM_QWORDS; + } + break; + default: + break; + } + + return supported; +} + +static bool __support_simd_sampling(bool intr) +{ + static bool intr_simd_sampling_supported; + static bool user_simd_sampling_supported; + static bool intr_cached; + static bool user_cached; + uint64_t mask; + uint16_t qwords; + + if (intr && intr_cached) + return intr_simd_sampling_supported; + if (!intr && user_cached) + return user_simd_sampling_supported; + + if (intr) { + intr_simd_sampling_supported =3D + __arch_has_simd_reg_class(PERF_SAMPLE_REGS_INTR, + PERF_REG_CLASS_X86_XMM, + &mask, &qwords); + intr_cached =3D true; + } else { + user_simd_sampling_supported =3D + __arch_has_simd_reg_class(PERF_SAMPLE_REGS_USER, + PERF_REG_CLASS_X86_XMM, + &mask, &qwords); + user_cached =3D true; + } + + return intr ? intr_simd_sampling_supported : + user_simd_sampling_supported; +} + +/* + * @x86_intr_simd_cached: indicates the data of below 3 + * x86_intr_simd_* items has been retrieved from kernel and cached. + * @x86_intr_simd_reg_class_mask: indicates which kinds of PRED/SIMD + * registers are supported for intr-regs option. Assume kernel perf + * subsystem supports XMM/YMM sampling, then the mask is + * PERF_REG_CLASS_X86_XMM|PERF_REG_CLASS_X86_YMM. + * @x86_intr_simd_mask: indicates register bitmask for each kind of + * supported PRED/SIMD register, like + * x86_intr_simd_mask[PERF_REG_CLASS_X86_XMM] =3D 0xffff. + * @x86_intr_simd_qwords: indicates the register length (qwords unit) + * for each kind of supported PRED/SIMD register, like + * x86_intr_simd_qwords[PERF_REG_CLASS_X86_XMM] =3D 2. + */ +static bool x86_intr_simd_cached; +static uint64_t x86_intr_simd_reg_class_mask; +static uint64_t x86_intr_simd_mask[PERF_REG_X86_MAX_SIMD_CLASSES]; +static uint16_t x86_intr_simd_qwords[PERF_REG_X86_MAX_SIMD_CLASSES]; + +/* + * Similar with above x86_intr_simd_* items, the difference is these + * items are used for user-regs option. + */ +static bool x86_user_simd_cached; +static uint64_t x86_user_simd_reg_class_mask; +static uint64_t x86_user_simd_mask[PERF_REG_X86_MAX_SIMD_CLASSES]; +static uint16_t x86_user_simd_qwords[PERF_REG_X86_MAX_SIMD_CLASSES]; + +static uint64_t __arch__simd_reg_class_mask(bool intr) +{ + uint64_t mask =3D 0; + bool supported; + int reg_c; + + if (!__support_simd_sampling(intr)) + goto done; + + if (intr && x86_intr_simd_cached) + return x86_intr_simd_reg_class_mask; + + if (!intr && x86_user_simd_cached) + return x86_user_simd_reg_class_mask; + + for (reg_c =3D 0; reg_c < PERF_REG_X86_MAX_SIMD_CLASSES; reg_c++) { + supported =3D false; + + if (intr) { + supported =3D __arch_has_simd_reg_class( + PERF_SAMPLE_REGS_INTR, + reg_c, + &x86_intr_simd_mask[reg_c], + &x86_intr_simd_qwords[reg_c]); + } else { + supported =3D __arch_has_simd_reg_class( + PERF_SAMPLE_REGS_USER, + reg_c, + &x86_user_simd_mask[reg_c], + &x86_user_simd_qwords[reg_c]); + } + if (supported) + mask |=3D BIT_ULL(reg_c); + } + +done: + if (intr) { + x86_intr_simd_reg_class_mask =3D mask; + x86_intr_simd_cached =3D true; + } else { + x86_user_simd_reg_class_mask =3D mask; + x86_user_simd_cached =3D true; + } + + return mask; +} + +static uint64_t +__arch__simd_reg_class_bitmap_qwords(bool intr, int reg_c, uint16_t *qword= s) +{ + uint64_t mask =3D 0; + uint64_t class_mask; + + *qwords =3D 0; + class_mask =3D intr ? x86_intr_simd_reg_class_mask : + x86_user_simd_reg_class_mask; + if (!(class_mask & BIT_ULL(reg_c))) + return 0; + + if (intr) { + mask =3D x86_intr_simd_mask[reg_c]; + *qwords =3D x86_intr_simd_qwords[reg_c]; + } else { + mask =3D x86_user_simd_mask[reg_c]; + *qwords =3D x86_user_simd_qwords[reg_c]; + } + + return mask; +} + +uint64_t __perf_simd_reg_class_mask_x86(bool intr, bool pred) +{ + uint64_t mask =3D __arch__simd_reg_class_mask(intr); + + return pred ? mask & PERF_REG_CLASS_X86_PRED_MASK : + mask & PERF_REG_CLASS_X86_SIMD_MASK; +} + +uint64_t __perf_simd_reg_class_bitmap_qwords_x86(int reg_c, uint16_t *qwor= ds, + bool intr, bool pred) +{ + if (intr ? !x86_intr_simd_cached : !x86_user_simd_cached) + __perf_simd_reg_class_mask_x86(intr, pred); + return __arch__simd_reg_class_bitmap_qwords(intr, reg_c, qwords); +} + +const char *__perf_simd_reg_class_name_x86(int id, bool pred __maybe_unuse= d) +{ + switch (id) { + case PERF_REG_CLASS_X86_OPMASK: + return "OPMASK"; + case PERF_REG_CLASS_X86_XMM: + return "XMM"; + case PERF_REG_CLASS_X86_YMM: + return "YMM"; + case PERF_REG_CLASS_X86_ZMM: + return "ZMM"; + default: + return NULL; + } + + return NULL; +} diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c index 089ededbae94..c8242b7e1db5 100644 --- a/tools/perf/util/perf_regs.c +++ b/tools/perf/util/perf_regs.c @@ -252,3 +252,75 @@ uint64_t perf_arch_reg_sp(uint16_t e_machine) return 0; } } + +uint64_t perf_intr_simd_reg_class_mask(uint16_t e_machine, bool pred) +{ + switch (e_machine) { + case EM_386: + case EM_X86_64: + return __perf_simd_reg_class_mask_x86(/*intr=3D*/true, pred); + default: + return 0; + } +} + +uint64_t perf_user_simd_reg_class_mask(uint16_t e_machine, bool pred) +{ + switch (e_machine) { + case EM_386: + case EM_X86_64: + return __perf_simd_reg_class_mask_x86(/*intr=3D*/false, pred); + default: + return 0; + } +} + +uint64_t perf_intr_simd_reg_class_bitmap_qwords(uint16_t e_machine, int re= g_c, + uint16_t *qwords, bool pred) +{ + switch (e_machine) { + case EM_386: + case EM_X86_64: + return __perf_simd_reg_class_bitmap_qwords_x86(reg_c, qwords, + /*intr=3D*/true, + pred); + default: + *qwords =3D 0; + return 0; + } +} + +uint64_t perf_user_simd_reg_class_bitmap_qwords(uint16_t e_machine, int re= g_c, + uint16_t *qwords, bool pred) +{ + switch (e_machine) { + case EM_386: + case EM_X86_64: + return __perf_simd_reg_class_bitmap_qwords_x86(reg_c, qwords, + /*intr=3D*/false, + pred); + default: + *qwords =3D 0; + return 0; + } +} + +const char *perf_simd_reg_class_name(uint16_t e_machine, int id, bool pred) +{ + const char *name =3D NULL; + + switch (e_machine) { + case EM_386: + case EM_X86_64: + name =3D __perf_simd_reg_class_name_x86(id, pred); + break; + default: + break; + } + if (name) + return name; + + pr_debug("Failed to find %s register %d for ELF machine type %u\n", + pred ? "PRED" : "SIMD", id, e_machine); + return "unknown"; +} diff --git a/tools/perf/util/perf_regs.h b/tools/perf/util/perf_regs.h index 1c78549127cc..c9f461b6f11f 100644 --- a/tools/perf/util/perf_regs.h +++ b/tools/perf/util/perf_regs.h @@ -20,6 +20,13 @@ const char *perf_reg_name(int id, uint16_t e_machine, ui= nt32_t e_flags, int abi) int perf_reg_value(u64 *valp, struct regs_dump *regs, int id); uint64_t perf_arch_reg_ip(uint16_t e_machine); uint64_t perf_arch_reg_sp(uint16_t e_machine); +uint64_t perf_intr_simd_reg_class_mask(uint16_t e_machine, bool pred); +uint64_t perf_user_simd_reg_class_mask(uint16_t e_machine, bool pred); +uint64_t perf_intr_simd_reg_class_bitmap_qwords(uint16_t e_machine, int re= g_c, + uint16_t *qwords, bool pred); +uint64_t perf_user_simd_reg_class_bitmap_qwords(uint16_t e_machine, int re= g_c, + uint16_t *qwords, bool pred); +const char *perf_simd_reg_class_name(uint16_t e_machine, int id, bool pred= ); =20 int __perf_sdt_arg_parse_op_arm64(char *old_op, char **new_op); uint64_t __perf_reg_mask_arm64(bool intr); @@ -70,6 +77,10 @@ uint64_t __perf_reg_mask_x86(bool intr, int *abi); const char *__perf_reg_name_x86(int id, int abi); uint64_t __perf_reg_ip_x86(void); uint64_t __perf_reg_sp_x86(void); +uint64_t __perf_simd_reg_class_mask_x86(bool intr, bool pred); +uint64_t __perf_simd_reg_class_bitmap_qwords_x86(int reg_c, uint16_t *qwor= ds, + bool intr, bool pred); +const char *__perf_simd_reg_class_name_x86(int id, bool pred); =20 static inline uint64_t DWARF_MINIMAL_REGS(uint16_t e_machine) { --=20 2.34.1 From nobody Fri Sep 25 11:05:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9F452EEE9E; Mon, 14 Sep 2026 01:48:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="93530665" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2026 18:48:02 -0700 X-CSE-ConnectionGUID: rWCw8vO8SwyvR4oiAq9Rxw== X-CSE-MsgGUID: 5laeSjDCQ0uXcrAc5MjYag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="276664207" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa005.jf.intel.com with ESMTP; 13 Sep 2026 18:47:57 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi , Kan Liang Subject: [Patch v11 07/10] perf regs: Enable dumping of SIMD registers Date: Mon, 14 Sep 2026 09:40:46 +0800 Message-Id: <20260914014049.2061519-8-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> References: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support dumping of SIMD registers with the new PERF_SAMPLE_REGS_ABI_SIMD ABI. Currently, the XMM, YMM, ZMM, OPMASK, eGPRs, and SSP registers on x86 platforms are supported with the PERF_SAMPLE_REGS_ABI_SIMD ABI. An example of the raw format output is displayed below. Example: $perf record -e cycles:p -Iax,bx,r8,r16,r31,ssp,xmm,ymm,zmm,opmask ./test $perf report -D ... ... 3342715685845 0x3afe8 [0xbc8]: PERF_RECORD_SAMPLE(IP, 0x1): 27776/27776: 0xffffffff91d7c18f period: 10000 addr: 0 ... intr regs: mask 0x18001010003 ABI 64-bit SIMD .... AX 0xffffed102de1a606 .... BX 0xffffed102de1a606 .... R8 0x0000000000000001 .... R16 0x0000000000000000 .... R31 0x0000000000000000 .... SSP 0x0000000000000000 ... SIMD ABI nr_vectors 32 vector_qwords 8 nr_pred 8 pred_qwords 1 .... ZMM[0][0] 0x616c2f656d6f682f .... ZMM[0][1] 0x696c2f7265737562 .... ZMM[0][2] 0x0000000000000000 .... ZMM[0][3] 0x0000000000000000 .... ZMM[0][4] 0x0000000000000000 .... ZMM[0][5] 0x0000000000000000 .... ZMM[0][6] 0x0000000000000000 .... ZMM[0][7] 0x0000000000000000 .... ZMM[1][0] 0x702f636578656269 .... ZMM[1][1] 0x65726f632d667265 .... ZMM[1][2] 0x0000000000000000 .... ZMM[1][3] 0x0000000000000000 .... ZMM[1][4] 0x0000000000000000 .... ZMM[1][5] 0x0000000000000000 .... ZMM[1][6] 0x0000000000000000 .... ZMM[1][7] 0x0000000000000000 ... ... .... ZMM[31][0] 0x0000000000000000 .... ZMM[31][1] 0x0000000000000000 .... ZMM[31][2] 0x0000000000000000 .... ZMM[31][3] 0x0000000000000000 .... ZMM[31][4] 0x0000000000000000 .... ZMM[31][5] 0x0000000000000000 .... ZMM[31][6] 0x0000000000000000 .... ZMM[31][7] 0x0000000000000000 .... OPMASK[0] 0x0000000000100221 .... OPMASK[1] 0x0000000000000020 .... OPMASK[2] 0x000000007fffffff .... OPMASK[3] 0x0000000000000000 .... OPMASK[4] 0x0000000000000000 .... OPMASK[5] 0x0000000000000000 .... OPMASK[6] 0x0000000000000000 .... OPMASK[7] 0x0000000000000000 ... ... Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Dapeng Mi --- tools/perf/builtin-script.c | 91 +++++++++++-- tools/perf/util/evsel.c | 68 +++++++++- tools/perf/util/sample.h | 5 + .../scripting-engines/trace-event-python.c | 125 ++++++++++++++++-- tools/perf/util/session.c | 82 ++++++++++++ tools/perf/util/synthetic-events.c | 38 +++++- 6 files changed, 387 insertions(+), 22 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index ec3ce841b33e..0174489d1c0f 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -719,23 +719,96 @@ static int perf_session__check_output_opt(struct perf= _session *session) return 0; } =20 -static int perf_sample__fprintf_regs(struct regs_dump *regs, uint64_t mask, +static int perf_sample__fprintf_regs(struct regs_dump *regs, + struct perf_event_attr *attr, uint16_t e_machine, uint32_t e_flags, - FILE *fp) + FILE *fp, bool intr) { - unsigned i =3D 0, r; + const char *name =3D "unknown"; + int reg_c, idx, pred_base; + unsigned int i =3D 0, j, r; + uint16_t qwords; int printed =3D 0; + uint64_t mask; =20 - if (!regs || !regs->regs) + if (!regs || (!regs->regs && !regs->simd_data)) return 0; =20 printed +=3D fprintf(fp, " ABI:%" PRIu64 " ", regs->abi); =20 + mask =3D intr ? attr->sample_regs_intr : attr->sample_regs_user; for_each_set_bit(r, (unsigned long *) &mask, sizeof(mask) * 8) { - u64 val =3D regs->regs[i++]; + if (!regs->regs) + break; printed +=3D fprintf(fp, "%5s:0x%"PRIx64" ", perf_reg_name(r, e_machine, e_flags, regs->abi), - val); + regs->regs[i++]); + } + + if (!regs->simd_data) + return printed; + + if (!regs->nr_vectors && !regs->nr_pred) + return printed; + + for (reg_c =3D 0; reg_c < 64; reg_c++) { + if (!regs->nr_vectors) + break; + if (intr) { + perf_intr_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/false); + } else { + perf_user_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/false); + } + if (regs->vector_qwords =3D=3D qwords) { + name =3D perf_simd_reg_class_name(e_machine, reg_c, /*pred=3D*/false); + break; + } + } + + for (i =3D 0; i < regs->nr_vectors; i++) { + for (j =3D 0; j < regs->vector_qwords; j++) { + idx =3D i * regs->vector_qwords + j; + if (regs->vector_qwords > 1) { + printed +=3D fprintf(fp, "%5s[%d][%d]:0x%" PRIx64 " ", + name, i, j, regs->simd_data[idx]); + } else { + printed +=3D fprintf(fp, "%5s[%d]:0x%" PRIx64 " ", + name, i, regs->simd_data[idx]); + } + } + } + + name =3D "unknown"; + for (reg_c =3D 0; reg_c < 64; reg_c++) { + if (!regs->nr_pred) + break; + if (intr) { + perf_intr_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/true); + } else { + perf_user_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/true); + } + if (regs->pred_qwords =3D=3D qwords) { + name =3D perf_simd_reg_class_name(e_machine, reg_c, /*pred=3D*/true); + break; + } + } + + pred_base =3D regs->nr_vectors * regs->vector_qwords; + for (i =3D 0; i < regs->nr_pred; i++) { + for (j =3D 0; j < regs->pred_qwords; j++) { + idx =3D pred_base + i * regs->pred_qwords + j; + if (regs->pred_qwords > 1) { + printed +=3D fprintf(fp, "%5s[%d][%d]:0x%" PRIx64 " ", + name, i, j, regs->simd_data[idx]); + } else { + printed +=3D fprintf(fp, "%5s[%d]:0x%" PRIx64 " ", + name, i, regs->simd_data[idx]); + } + } } =20 return printed; @@ -801,7 +874,8 @@ static int perf_sample__fprintf_iregs(struct perf_sampl= e *sample, return 0; =20 return perf_sample__fprintf_regs(perf_sample__intr_regs(sample), - attr->sample_regs_intr, e_machine, e_flags, fp); + attr, e_machine, e_flags, fp, + /*intr=3D*/true); } =20 static int perf_sample__fprintf_uregs(struct perf_sample *sample, @@ -814,7 +888,8 @@ static int perf_sample__fprintf_uregs(struct perf_sampl= e *sample, return 0; =20 return perf_sample__fprintf_regs(perf_sample__user_regs(sample), - attr->sample_regs_user, e_machine, e_flags, fp); + attr, e_machine, e_flags, fp, + /*intr=3D*/false); } =20 static int perf_sample__fprintf_start(struct perf_script *script, diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index df16780bf887..b44fd880d2d5 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -3715,9 +3715,39 @@ int __evsel__parse_sample(struct evsel *evsel, union= perf_event *event, array =3D (void *)array + sz; =20 if (regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) { - /* Skip SIMD-regs header. */ - sz =3D 4 * sizeof(u64); + u64 attr_nr_vectors =3D + hweight64(evsel->core.attr.sample_simd_vec_reg_user); + u64 attr_vec_qwords =3D + evsel->core.attr.sample_simd_vec_reg_qwords; + u64 attr_nr_pred =3D + hweight32(evsel->core.attr.sample_simd_pred_reg_user); + u64 attr_pred_qwords =3D + evsel->core.attr.sample_simd_pred_reg_qwords; + + OVERFLOW_CHECK_u64(array); + regs->nr_vectors =3D *(u64 *)array; + array =3D (void *)array + sizeof(u64); + OVERFLOW_CHECK_u64(array); + regs->vector_qwords =3D *(u64 *)array; + array =3D (void *)array + sizeof(u64); + OVERFLOW_CHECK_u64(array); + regs->nr_pred =3D *(u64 *)array; + array =3D (void *)array + sizeof(u64); + OVERFLOW_CHECK_u64(array); + regs->pred_qwords =3D *(u64 *)array; + array =3D (void *)array + sizeof(u64); + + if (regs->nr_vectors > attr_nr_vectors || + regs->vector_qwords > attr_vec_qwords || + regs->nr_pred > attr_nr_pred || + regs->pred_qwords > attr_pred_qwords) + goto out_efault; + + sz =3D (regs->nr_vectors * regs->vector_qwords + + regs->nr_pred * regs->pred_qwords) * sizeof(u64); OVERFLOW_CHECK(array, sz, max_size); + + regs->simd_data =3D (u64 *)array; array =3D (void *)array + sz; } } @@ -3779,9 +3809,39 @@ int __evsel__parse_sample(struct evsel *evsel, union= perf_event *event, array =3D (void *)array + sz; =20 if (regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) { - /* Skip SIMD-regs header. */ - sz =3D 4 * sizeof(u64); + u64 attr_nr_vectors =3D + hweight64(evsel->core.attr.sample_simd_vec_reg_intr); + u64 attr_vec_qwords =3D + evsel->core.attr.sample_simd_vec_reg_qwords; + u64 attr_nr_pred =3D + hweight32(evsel->core.attr.sample_simd_pred_reg_intr); + u64 attr_pred_qwords =3D + evsel->core.attr.sample_simd_pred_reg_qwords; + + OVERFLOW_CHECK_u64(array); + regs->nr_vectors =3D *(u64 *)array; + array =3D (void *)array + sizeof(u64); + OVERFLOW_CHECK_u64(array); + regs->vector_qwords =3D *(u64 *)array; + array =3D (void *)array + sizeof(u64); + OVERFLOW_CHECK_u64(array); + regs->nr_pred =3D *(u64 *)array; + array =3D (void *)array + sizeof(u64); + OVERFLOW_CHECK_u64(array); + regs->pred_qwords =3D *(u64 *)array; + array =3D (void *)array + sizeof(u64); + + if (regs->nr_vectors > attr_nr_vectors || + regs->vector_qwords > attr_vec_qwords || + regs->nr_pred > attr_nr_pred || + regs->pred_qwords > attr_pred_qwords) + goto out_efault; + + sz =3D (regs->nr_vectors * regs->vector_qwords + + regs->nr_pred * regs->pred_qwords) * sizeof(u64); OVERFLOW_CHECK(array, sz, max_size); + + regs->simd_data =3D (u64 *)array; array =3D (void *)array + sz; } } diff --git a/tools/perf/util/sample.h b/tools/perf/util/sample.h index c4eae8b2fd06..cb4b16654876 100644 --- a/tools/perf/util/sample.h +++ b/tools/perf/util/sample.h @@ -16,6 +16,11 @@ struct regs_dump { u64 abi; u64 mask; u64 *regs; + u64 nr_vectors; + u64 vector_qwords; + u64 nr_pred; + u64 pred_qwords; + u64 *simd_data; =20 /* Cached values/mask filled by first register access. */ u64 cache_regs[PERF_SAMPLE_REGS_CACHE_SIZE]; diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools= /perf/util/scripting-engines/trace-event-python.c index 11877b56548f..239104b0337d 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -711,8 +711,8 @@ static void set_sample_datasrc_in_dict(PyObject *dict, _PyUnicode_FromString(decode)); } =20 -static void regs_map(struct regs_dump *regs, uint64_t mask, uint16_t e_mac= hine, uint32_t e_flags, - char *bf, int size) +static int regs_map(struct regs_dump *regs, uint64_t mask, uint16_t e_mach= ine, + uint32_t e_flags, char *bf, int size) { unsigned int i =3D 0, r; int printed =3D 0; @@ -720,10 +720,10 @@ static void regs_map(struct regs_dump *regs, uint64_t= mask, uint16_t e_machine, bf[0] =3D 0; =20 if (size <=3D 0) - return; + return 0; =20 if (!regs || !regs->regs) - return; + return 0; =20 for_each_set_bit(r, (unsigned long *) &mask, sizeof(mask) * 8) { u64 val =3D regs->regs[i++]; @@ -732,6 +732,90 @@ static void regs_map(struct regs_dump *regs, uint64_t = mask, uint16_t e_machine, "%5s:0x%" PRIx64 " ", perf_reg_name(r, e_machine, e_flags, regs->abi), val); } + + return printed; +} + +static void simd_regs_map(struct regs_dump *regs, struct perf_event_attr *= attr, + uint16_t e_machine, char *bf, int size, int printed, bool intr) +{ + const char *name =3D "unknown"; + int reg_c, idx, pred_base; + unsigned int i =3D 0, j; + uint16_t qwords; + + if (size <=3D 0 || printed >=3D size) + return; + + if (!regs || !regs->simd_data) + return; + + if (!regs->nr_vectors && !regs->nr_pred) + return; + + for (reg_c =3D 0; reg_c < 64; reg_c++) { + if (!regs->nr_vectors) + break; + if (intr) { + perf_intr_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/false); + } else { + perf_user_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/false); + } + if (regs->vector_qwords =3D=3D qwords) { + name =3D perf_simd_reg_class_name(e_machine, reg_c, /*pred=3D*/false); + break; + } + } + + for (i =3D 0; i < regs->nr_vectors; i++) { + for (j =3D 0; j < regs->vector_qwords; j++) { + idx =3D i * regs->vector_qwords + j; + if (regs->vector_qwords > 1) { + printed +=3D scnprintf(bf + printed, size - printed, + "%5s[%d][%d]:0x%" PRIx64 " ", + name, i, j, regs->simd_data[idx]); + } else { + printed +=3D scnprintf(bf + printed, size - printed, + "%5s[%d]:0x%" PRIx64 " ", + name, i, regs->simd_data[idx]); + } + } + } + + name =3D "unknown"; + for (reg_c =3D 0; reg_c < 64; reg_c++) { + if (!regs->nr_pred) + break; + if (intr) { + perf_intr_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/true); + } else { + perf_user_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/true); + } + if (regs->pred_qwords =3D=3D qwords) { + name =3D perf_simd_reg_class_name(e_machine, reg_c, /*pred=3D*/true); + break; + } + } + + pred_base =3D regs->nr_vectors * regs->vector_qwords; + for (i =3D 0; i < regs->nr_pred; i++) { + for (j =3D 0; j < regs->pred_qwords; j++) { + idx =3D pred_base + i * regs->pred_qwords + j; + if (regs->pred_qwords > 1) { + printed +=3D scnprintf(bf + printed, size - printed, + "%5s[%d][%d]:0x%" PRIx64 " ", + name, i, j, regs->simd_data[idx]); + } else { + printed +=3D scnprintf(bf + printed, size - printed, + "%5s[%d]:0x%" PRIx64 " ", + name, i, regs->simd_data[idx]); + } + } + } } =20 #define MAX_REG_SIZE 128 @@ -742,16 +826,36 @@ static int set_regs_in_dict(PyObject *dict, uint32_t e_flags) { struct perf_event_attr *attr =3D &sample->evsel->core.attr; - - int size =3D (__sw_hweight64(attr->sample_regs_intr) * MAX_REG_SIZE) + 1; + int intr_size, user_size, size; + struct regs_dump *regs; char *bf =3D NULL; + int printed; + + intr_size =3D (__sw_hweight64(attr->sample_regs_intr) * MAX_REG_SIZE) + 1; + user_size =3D (__sw_hweight64(attr->sample_regs_user) * MAX_REG_SIZE) + 1; + if (sample->intr_regs && attr->sample_simd_regs_enabled) { + regs =3D sample->intr_regs; + intr_size +=3D (regs->nr_vectors * regs->vector_qwords + + regs->nr_pred * regs->pred_qwords) * MAX_REG_SIZE; + } + if (sample->user_regs && attr->sample_simd_regs_enabled) { + regs =3D sample->user_regs; + user_size +=3D (regs->nr_vectors * regs->vector_qwords + + regs->nr_pred * regs->pred_qwords) * MAX_REG_SIZE; + } + size =3D intr_size > user_size ? intr_size : user_size; =20 if (sample->intr_regs) { bf =3D malloc(size); if (!bf) return -1; =20 - regs_map(sample->intr_regs, attr->sample_regs_intr, e_machine, e_flags, = bf, size); + printed =3D regs_map(sample->intr_regs, attr->sample_regs_intr, + e_machine, e_flags, bf, size); + if (attr->sample_simd_regs_enabled) { + simd_regs_map(sample->intr_regs, attr, e_machine, bf, + size, printed, true); + } =20 pydict_set_item_string_decref(dict, "iregs", _PyUnicode_FromString(bf)); @@ -763,7 +867,12 @@ static int set_regs_in_dict(PyObject *dict, if (!bf) return -1; } - regs_map(sample->user_regs, attr->sample_regs_user, e_machine, e_flags, = bf, size); + printed =3D regs_map(sample->user_regs, attr->sample_regs_user, + e_machine, e_flags, bf, size); + if (attr->sample_simd_regs_enabled) { + simd_regs_map(sample->user_regs, attr, e_machine, bf, + size, printed, false); + } =20 pydict_set_item_string_decref(dict, "uregs", _PyUnicode_FromString(bf)); diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index 90d4e45f09f0..a5b596cd14be 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -1446,6 +1446,86 @@ static void regs_dump__printf(u64 mask, struct regs_= dump *regs, } } =20 +static void simd_regs_dump__printf(uint16_t e_machine, struct regs_dump *r= egs, bool intr) +{ + const char *name =3D "unknown"; + const char *simd_header; + u32 i, j, idx, pred_base; + uint16_t qwords; + int reg_c; + + if (!(regs->abi & PERF_SAMPLE_REGS_ABI_SIMD)) + return; + + if (!regs->nr_vectors && !regs->nr_pred) + return; + + simd_header =3D "... SIMD ABI nr_vectors %" PRIu64 " vector_qwords %" PRI= u64 \ + " nr_pred %" PRIu64 " pred_qwords %" PRIu64 "\n"; + printf(simd_header, regs->nr_vectors, regs->vector_qwords, + regs->nr_pred, regs->pred_qwords); + + for (reg_c =3D 0; reg_c < 64; reg_c++) { + if (!regs->nr_vectors) + break; + if (intr) { + perf_intr_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/false); + } else { + perf_user_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/false); + } + if (regs->vector_qwords =3D=3D qwords) { + name =3D perf_simd_reg_class_name(e_machine, reg_c, /*pred=3D*/false); + break; + } + } + + for (i =3D 0; i < regs->nr_vectors; i++) { + for (j =3D 0; j < regs->vector_qwords; j++) { + idx =3D i * regs->vector_qwords + j; + if (regs->vector_qwords > 1) { + printf(".... %3s[%d][%d] 0x%016" PRIx64 "\n", + name, i, j, regs->simd_data[idx]); + } else { + printf(".... %3s[%d] 0x%016" PRIx64 "\n", + name, i, regs->simd_data[idx]); + } + } + } + + name =3D "unknown"; + for (reg_c =3D 0; reg_c < 64; reg_c++) { + if (!regs->nr_pred) + break; + if (intr) { + perf_intr_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/true); + } else { + perf_user_simd_reg_class_bitmap_qwords(e_machine, reg_c, + &qwords, /*pred=3D*/true); + } + if (regs->pred_qwords =3D=3D qwords) { + name =3D perf_simd_reg_class_name(e_machine, reg_c, /*pred=3D*/true); + break; + } + } + + pred_base =3D regs->nr_vectors * regs->vector_qwords; + for (i =3D 0; i < regs->nr_pred; i++) { + for (j =3D 0; j < regs->pred_qwords; j++) { + idx =3D pred_base + i * regs->pred_qwords + j; + if (regs->pred_qwords > 1) { + printf(".... %3s[%d][%d] 0x%016" PRIx64 "\n", + name, i, j, regs->simd_data[idx]); + } else { + printf(".... %3s[%d] 0x%016" PRIx64 "\n", + name, i, regs->simd_data[idx]); + } + } + } +} + static const char *regs_abi[] =3D { [PERF_SAMPLE_REGS_ABI_NONE] =3D "none", [PERF_SAMPLE_REGS_ABI_32] =3D "32-bit", @@ -1486,6 +1566,7 @@ static void regs_user__printf(struct perf_sample *sam= ple, uint16_t e_machine, ui =20 if (user_regs->regs) regs__printf("user", user_regs, e_machine, e_flags); + simd_regs_dump__printf(e_machine, user_regs, /*intr=3D*/false); } =20 static void regs_intr__printf(struct perf_sample *sample, uint16_t e_machi= ne, uint32_t e_flags) @@ -1499,6 +1580,7 @@ static void regs_intr__printf(struct perf_sample *sam= ple, uint16_t e_machine, ui =20 if (intr_regs->regs) regs__printf("intr", intr_regs, e_machine, e_flags); + simd_regs_dump__printf(e_machine, intr_regs, /*intr=3D*/true); } =20 static void stack_user__printf(struct stack_dump *dump) diff --git a/tools/perf/util/synthetic-events.c b/tools/perf/util/synthetic= -events.c index 2779f63a442c..6c5e2327fdfa 100644 --- a/tools/perf/util/synthetic-events.c +++ b/tools/perf/util/synthetic-events.c @@ -1644,8 +1644,13 @@ size_t perf_event__sample_event_size(const struct pe= rf_sample *sample, u64 type, if (sample->user_regs && sample->user_regs->abi) { result +=3D sizeof(u64); sz =3D hweight64(sample->user_regs->mask) * sizeof(u64); - if (sample->user_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) + if (sample->user_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) { sz +=3D 4 * sizeof(u64); + sz +=3D (sample->user_regs->nr_vectors * + sample->user_regs->vector_qwords + + sample->user_regs->nr_pred * + sample->user_regs->pred_qwords) * sizeof(u64); + } result +=3D sz; } else { result +=3D sizeof(u64); @@ -1674,8 +1679,13 @@ size_t perf_event__sample_event_size(const struct pe= rf_sample *sample, u64 type, if (sample->intr_regs && sample->intr_regs->abi) { result +=3D sizeof(u64); sz =3D hweight64(sample->intr_regs->mask) * sizeof(u64); - if (sample->intr_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) + if (sample->intr_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) { sz +=3D 4 * sizeof(u64); + sz +=3D (sample->intr_regs->nr_vectors * + sample->intr_regs->vector_qwords + + sample->intr_regs->nr_pred * + sample->intr_regs->pred_qwords) * sizeof(u64); + } result +=3D sz; } else { result +=3D sizeof(u64); @@ -1863,6 +1873,18 @@ int perf_event__synthesize_sample(union perf_event *= event, u64 type, u64 read_fo sz =3D hweight64(sample->user_regs->mask) * sizeof(u64); memcpy(array, sample->user_regs->regs, sz); array =3D (void *)array + sz; + if (sample->user_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) { + *array++ =3D sample->user_regs->nr_vectors; + *array++ =3D sample->user_regs->vector_qwords; + *array++ =3D sample->user_regs->nr_pred; + *array++ =3D sample->user_regs->pred_qwords; + sz =3D (sample->user_regs->nr_vectors * + sample->user_regs->vector_qwords + + sample->user_regs->nr_pred * + sample->user_regs->pred_qwords) * sizeof(u64); + memcpy(array, sample->user_regs->simd_data, sz); + array =3D (void *)array + sz; + } } else { *array++ =3D 0; } @@ -1899,6 +1921,18 @@ int perf_event__synthesize_sample(union perf_event *= event, u64 type, u64 read_fo sz =3D hweight64(sample->intr_regs->mask) * sizeof(u64); memcpy(array, sample->intr_regs->regs, sz); array =3D (void *)array + sz; + if (sample->intr_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD) { + *array++ =3D sample->intr_regs->nr_vectors; + *array++ =3D sample->intr_regs->vector_qwords; + *array++ =3D sample->intr_regs->nr_pred; + *array++ =3D sample->intr_regs->pred_qwords; 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d="scan'208";a="276664225" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa005.jf.intel.com with ESMTP; 13 Sep 2026 18:48:03 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v11 08/10] perf dwarf-regs: Add SIMD/eGPRs support for x86 DWARF registers Date: Mon, 14 Sep 2026 09:40:47 +0800 Message-Id: <20260914014049.2061519-9-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> References: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Enhance the x86-specific DWARF register handling by adding support for SIMD and eGPRs registers. This update is based on the "DWARF Register Number Mapping" table from the "System V Application Binary Interface AMD64 Architecture Processor Supplement" (version 1.0). Modifications include: - Updating the x86_64_regidx_table[] array to incorporate SIMD and eGPRs registers. - Enhancing the __get_dwarf_regnum_for_perf_regnum_x86_64() function to retrieve the DWARF register index for eGPRs. Since currently libdw doesn't support SIMD and APX eGPRs registers yet, still keep the original return value for get_libdw_frame_nregs() helper. Signed-off-by: Dapeng Mi --- .../util/dwarf-regs-arch/dwarf-regs-x86.c | 138 +++++++++++++++--- tools/perf/util/dwarf-regs.c | 9 +- tools/perf/util/include/dwarf-regs.h | 7 +- tools/perf/util/unwind-libdw.c | 6 +- 4 files changed, 132 insertions(+), 28 deletions(-) diff --git a/tools/perf/util/dwarf-regs-arch/dwarf-regs-x86.c b/tools/perf/= util/dwarf-regs-arch/dwarf-regs-x86.c index c2a70e03b1a9..bb17d779036a 100644 --- a/tools/perf/util/dwarf-regs-arch/dwarf-regs-x86.c +++ b/tools/perf/util/dwarf-regs-arch/dwarf-regs-x86.c @@ -90,22 +90,22 @@ static const struct dwarf_regs_idx x86_64_regidx_table[= ] =3D { { "r14", 14 }, { "r14d", 14 }, { "r14w", 14 }, { "r14b", 14 }, { "r15", 15 }, { "r15d", 15 }, { "r15w", 15 }, { "r15b", 15 }, // 16 - Return Address RA - { "xmm0", 17}, - { "xmm1", 18}, - { "xmm2", 19}, - { "xmm3", 20}, - { "xmm4", 21}, - { "xmm5", 22}, - { "xmm6", 23}, - { "xmm7", 24}, - { "xmm8", 25}, - { "xmm9", 26}, - { "xmm10", 27}, - { "xmm11", 28}, - { "xmm12", 29}, - { "xmm13", 30}, - { "xmm14", 31}, - { "xmm15", 32}, + { "zmm0", 17 }, { "ymm0", 17 }, { "xmm0", 17 }, + { "zmm1", 18 }, { "ymm1", 18 }, { "xmm1", 18 }, + { "zmm2", 19 }, { "ymm2", 19 }, { "xmm2", 19 }, + { "zmm3", 20 }, { "ymm3", 20 }, { "xmm3", 20 }, + { "zmm4", 21 }, { "ymm4", 21 }, { "xmm4", 21 }, + { "zmm5", 22 }, { "ymm5", 22 }, { "xmm5", 22 }, + { "zmm6", 23 }, { "ymm6", 23 }, { "xmm6", 23 }, + { "zmm7", 24 }, { "ymm7", 24 }, { "xmm7", 24 }, + { "zmm8", 25 }, { "ymm8", 25 }, { "xmm8", 25 }, + { "zmm9", 26 }, { "ymm9", 26 }, { "xmm9", 26 }, + { "zmm10", 27 }, { "ymm10", 27 }, { "xmm10", 27 }, + { "zmm11", 28 }, { "ymm11", 28 }, { "xmm11", 28 }, + { "zmm12", 29 }, { "ymm12", 29 }, { "xmm12", 29 }, + { "zmm13", 30 }, { "ymm13", 30 }, { "xmm13", 30 }, + { "zmm14", 31 }, { "ymm14", 31 }, { "xmm14", 31 }, + { "zmm15", 32 }, { "ymm15", 32 }, { "xmm15", 32 }, { "st0", 33}, { "st1", 34}, { "st2", 35}, @@ -129,7 +129,7 @@ static const struct dwarf_regs_idx x86_64_regidx_table[= ] =3D { { "ds", 53}, { "fs", 54}, { "gs", 55}, - // 56-47 - reserved + // 56-57 - reserved { "fs.base", 58}, { "gs.base", 59}, // 60-61 - reserved @@ -138,6 +138,49 @@ static const struct dwarf_regs_idx x86_64_regidx_table= [] =3D { { "mxcsr", 64}, // 128-bit Media Control and Status { "fcw", 65}, // x87 Control Word { "fsw", 66}, // x87 Status Word + // 67-82 - Upper Vector Registers 16=E2=80=9331 + { "zmm16", 67 }, { "ymm16", 67 }, { "xmm16", 67 }, + { "zmm17", 68 }, { "ymm17", 68 }, { "xmm17", 68 }, + { "zmm18", 69 }, { "ymm18", 69 }, { "xmm18", 69 }, + { "zmm19", 70 }, { "ymm19", 70 }, { "xmm19", 70 }, + { "zmm20", 71 }, { "ymm20", 71 }, { "xmm20", 71 }, + { "zmm21", 72 }, { "ymm21", 72 }, { "xmm21", 72 }, + { "zmm22", 73 }, { "ymm22", 73 }, { "xmm22", 73 }, + { "zmm23", 74 }, { "ymm23", 74 }, { "xmm23", 74 }, + { "zmm24", 75 }, { "ymm24", 75 }, { "xmm24", 75 }, + { "zmm25", 76 }, { "ymm25", 76 }, { "xmm25", 76 }, + { "zmm26", 77 }, { "ymm26", 77 }, { "xmm26", 77 }, + { "zmm27", 78 }, { "ymm27", 78 }, { "xmm27", 78 }, + { "zmm28", 79 }, { "ymm28", 79 }, { "xmm28", 79 }, + { "zmm29", 80 }, { "ymm29", 80 }, { "xmm29", 80 }, + { "zmm30", 81 }, { "ymm30", 81 }, { "xmm30", 81 }, + { "zmm31", 82 }, { "ymm31", 82 }, { "xmm31", 82 }, + // 118-125 - Vector Mask Registers 0=E2=80=937 + { "k0", 118 }, + { "k1", 119 }, + { "k2", 120 }, + { "k3", 121 }, + { "k4", 122 }, + { "k5", 123 }, + { "k6", 124 }, + { "k7", 125 }, + // 130-145 - APX Integer Registers 16-31 + { "r16", 130 }, { "r16d", 130 }, { "r16w", 130 }, { "r16b", 130 }, + { "r17", 131 }, { "r17d", 131 }, { "r17w", 131 }, { "r17b", 131 }, + { "r18", 132 }, { "r18d", 132 }, { "r18w", 132 }, { "r18b", 132 }, + { "r19", 133 }, { "r19d", 133 }, { "r19w", 133 }, { "r19b", 133 }, + { "r20", 134 }, { "r20d", 134 }, { "r20w", 134 }, { "r20b", 134 }, + { "r21", 135 }, { "r21d", 135 }, { "r21w", 135 }, { "r21b", 135 }, + { "r22", 136 }, { "r22d", 136 }, { "r22w", 136 }, { "r22b", 136 }, + { "r23", 137 }, { "r23d", 137 }, { "r23w", 137 }, { "r23b", 137 }, + { "r24", 138 }, { "r24d", 138 }, { "r24w", 138 }, { "r24b", 138 }, + { "r25", 139 }, { "r25d", 139 }, { "r25w", 139 }, { "r25b", 139 }, + { "r26", 140 }, { "r26d", 140 }, { "r26w", 140 }, { "r26b", 140 }, + { "r27", 141 }, { "r27d", 141 }, { "r27w", 141 }, { "r27b", 141 }, + { "r28", 142 }, { "r28d", 142 }, { "r28w", 142 }, { "r28b", 142 }, + { "r29", 143 }, { "r29d", 143 }, { "r29w", 143 }, { "r29b", 143 }, + { "r30", 144 }, { "r30d", 144 }, { "r30w", 144 }, { "r30b", 144 }, + { "r31", 145 }, { "r31d", 145 }, { "r31w", 145 }, { "r31b", 145 }, // End of regular dwarf registers. { "rip", DWARF_REG_PC }, { "eip", DWARF_REG_PC }, { "ip", DWARF_REG_PC }, }; @@ -204,7 +247,7 @@ int __get_dwarf_regnum_for_perf_regnum_i386(int perf_re= gnum) return dwarf_i386_regnums[perf_regnum]; } =20 -int __get_dwarf_regnum_for_perf_regnum_x86_64(int perf_regnum) +int __get_dwarf_regnum_for_perf_regnum_x86_64(int perf_regnum, int abi) { static const int dwarf_x86_64_regnums[] =3D { [PERF_REG_X86_AX] =3D 0, @@ -248,13 +291,66 @@ int __get_dwarf_regnum_for_perf_regnum_x86_64(int per= f_regnum) [PERF_REG_X86_XMM14] =3D 31, [PERF_REG_X86_XMM15] =3D 32, }; + static const int dwarf_x86_64_regnums_apx[] =3D { + [PERF_REG_X86_AX] =3D 0, + [PERF_REG_X86_BX] =3D 3, + [PERF_REG_X86_CX] =3D 2, + [PERF_REG_X86_DX] =3D 1, + [PERF_REG_X86_SI] =3D 4, + [PERF_REG_X86_DI] =3D 5, + [PERF_REG_X86_BP] =3D 6, + [PERF_REG_X86_SP] =3D 7, + [PERF_REG_X86_IP] =3D 16, + [PERF_REG_X86_FLAGS] =3D 49, + [PERF_REG_X86_CS] =3D 51, + [PERF_REG_X86_SS] =3D 52, + [PERF_REG_X86_DS] =3D 53, + [PERF_REG_X86_ES] =3D 50, + [PERF_REG_X86_FS] =3D 54, + [PERF_REG_X86_GS] =3D 55, + [PERF_REG_X86_R8] =3D 8, + [PERF_REG_X86_R9] =3D 9, + [PERF_REG_X86_R10] =3D 10, + [PERF_REG_X86_R11] =3D 11, + [PERF_REG_X86_R12] =3D 12, + [PERF_REG_X86_R13] =3D 13, + [PERF_REG_X86_R14] =3D 14, + [PERF_REG_X86_R15] =3D 15, + [PERF_REG_X86_R16] =3D 130, + [PERF_REG_X86_R17] =3D 131, + [PERF_REG_X86_R18] =3D 132, + [PERF_REG_X86_R19] =3D 133, + [PERF_REG_X86_R20] =3D 134, + [PERF_REG_X86_R21] =3D 135, + [PERF_REG_X86_R22] =3D 136, + [PERF_REG_X86_R23] =3D 137, + [PERF_REG_X86_R24] =3D 138, + [PERF_REG_X86_R25] =3D 139, + [PERF_REG_X86_R26] =3D 140, + [PERF_REG_X86_R27] =3D 141, + [PERF_REG_X86_R28] =3D 142, + [PERF_REG_X86_R29] =3D 143, + [PERF_REG_X86_R30] =3D 144, + [PERF_REG_X86_R31] =3D 145, + }; =20 if (perf_regnum =3D=3D 0) return 0; =20 - if (perf_regnum < 0 || perf_regnum >=3D (int)ARRAY_SIZE(dwarf_x86_64_regn= ums) || - dwarf_x86_64_regnums[perf_regnum] =3D=3D 0) + if (perf_regnum < 0) + return -ENOENT; + + if (!(abi & PERF_SAMPLE_REGS_ABI_SIMD) && + (perf_regnum >=3D (int)ARRAY_SIZE(dwarf_x86_64_regnums) || + dwarf_x86_64_regnums[perf_regnum] =3D=3D 0)) + return -ENOENT; + + if ((abi & PERF_SAMPLE_REGS_ABI_SIMD) && + (perf_regnum >=3D (int)ARRAY_SIZE(dwarf_x86_64_regnums_apx) || + dwarf_x86_64_regnums_apx[perf_regnum] =3D=3D 0)) return -ENOENT; =20 - return dwarf_x86_64_regnums[perf_regnum]; + return abi & PERF_SAMPLE_REGS_ABI_SIMD ? + dwarf_x86_64_regnums_apx[perf_regnum] : + dwarf_x86_64_regnums[perf_regnum]; } diff --git a/tools/perf/util/dwarf-regs.c b/tools/perf/util/dwarf-regs.c index 797f455eba0d..67f38342247e 100644 --- a/tools/perf/util/dwarf-regs.c +++ b/tools/perf/util/dwarf-regs.c @@ -158,6 +158,10 @@ static int get_libdw_frame_nregs(unsigned int machine,= unsigned int flags __mayb { switch (machine) { case EM_X86_64: + /* + * Since libdw doesn't support SIMD and APX eGPR register yet, + * still keep nregs to 17. + */ return 17; case EM_386: return 9; @@ -187,13 +191,14 @@ static int get_libdw_frame_nregs(unsigned int machine= , unsigned int flags __mayb } =20 int get_dwarf_regnum_for_perf_regnum(int perf_regnum, unsigned int machine, - unsigned int flags, bool only_libdw_supported) + unsigned int flags, + bool only_libdw_supported, int abi) { int reg; =20 switch (machine) { case EM_X86_64: - reg =3D __get_dwarf_regnum_for_perf_regnum_x86_64(perf_regnum); + reg =3D __get_dwarf_regnum_for_perf_regnum_x86_64(perf_regnum, abi); break; case EM_386: reg =3D __get_dwarf_regnum_for_perf_regnum_i386(perf_regnum); diff --git a/tools/perf/util/include/dwarf-regs.h b/tools/perf/util/include= /dwarf-regs.h index 46a764cf322f..92cf0af93e9e 100644 --- a/tools/perf/util/include/dwarf-regs.h +++ b/tools/perf/util/include/dwarf-regs.h @@ -103,7 +103,7 @@ int __get_csky_regnum(const char *name, unsigned int fl= ags); int __get_dwarf_regnum_i386(const char *name); int __get_dwarf_regnum_x86_64(const char *name); int __get_dwarf_regnum_for_perf_regnum_i386(int perf_regnum); -int __get_dwarf_regnum_for_perf_regnum_x86_64(int perf_regnum); +int __get_dwarf_regnum_for_perf_regnum_x86_64(int perf_regnum, int abi); =20 int __get_dwarf_regnum_for_perf_regnum_arm(int perf_regnum); int __get_dwarf_regnum_for_perf_regnum_arm64(int perf_regnum); @@ -125,8 +125,9 @@ int get_dwarf_regnum(const char *name, unsigned int mac= hine, unsigned int flags) /* * get_dwarf_regnum - Returns DWARF regnum from perf register number. */ -int get_dwarf_regnum_for_perf_regnum(int perf_regnum, unsigned int machine= , unsigned int flags, - bool only_libdw_supported); +int get_dwarf_regnum_for_perf_regnum(int perf_regnum, unsigned int machine, + unsigned int flags, + bool only_libdw_supported, int abi); =20 void get_powerpc_regs(u32 raw_insn, int is_source, struct annotated_op_loc= *op_loc); =20 diff --git a/tools/perf/util/unwind-libdw.c b/tools/perf/util/unwind-libdw.c index 8d9fa6fd81c3..ebea101e1001 100644 --- a/tools/perf/util/unwind-libdw.c +++ b/tools/perf/util/unwind-libdw.c @@ -290,7 +290,8 @@ static bool libdw_set_initial_registers(Dwfl_Thread *th= read, void *arg) int dwarf_reg =3D get_dwarf_regnum_for_perf_regnum(perf_reg, e_machine, e_flags, - /*only_libdw_supported=3D*/true); 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d="scan'208";a="276664237" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa005.jf.intel.com with ESMTP; 13 Sep 2026 18:48:08 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v11 09/10] perf tests: Add x86 eGPRs/SSP registers sampling test Date: Mon, 14 Sep 2026 09:40:48 +0800 Message-Id: <20260914014049.2061519-10-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> References: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Validate that eGPRs (extended general purpose registers) and SSP (shadow stack pointer) registers can be sampled correctly on x86 platforms. Signed-off-by: Dapeng Mi --- tools/perf/tests/shell/record.sh | 119 +++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/tools/perf/tests/shell/record.sh b/tools/perf/tests/shell/reco= rd.sh index 625240809fce..770a546f8d45 100755 --- a/tools/perf/tests/shell/record.sh +++ b/tools/perf/tests/shell/record.sh @@ -131,6 +131,124 @@ check_system_wide() { perf report -i "${perfdata}" -q | grep -q "${testsym}" } =20 +check_ext_reg_capture() { + local script_field=3D"$1" + local ext_reg=3D"$2" + + perf script -F ip,sym,"${script_field}" -i "${perfdata}" 2>/dev/null | \ + grep -q -i "${ext_reg}:" +} + +get_x86_extended_regs() { + local advertised_ext_regs=3D"$1" + local ext_regs=3D"" + + if echo "${advertised_ext_regs}" | grep -q -i R16 + then + ext_regs=3D"${ext_regs} R16" + fi + if echo "${advertised_ext_regs}" | grep -q -i R31 + then + ext_regs=3D"${ext_regs} R31" + fi + if echo "${advertised_ext_regs}" | grep -q -i SSP + then + ext_regs=3D"${ext_regs} SSP" + fi + + echo "${ext_regs}" | xargs +} + +validate_extd_regs_sampling() { + local regs_opt=3D"$1" + local extd_regs=3D"$2" + local script_field=3D"$3" + local ret=3D0 + local reg + + for reg in ${extd_regs} + do + perf_record_with_retry "${perfdata}" \ + "check_ext_reg_capture ${script_field} ${reg}" "perf test -w thloop"= \ + -e br_inst_retired.near_call ${regs_opt}=3D${reg} -c 1000 \ + --per-thread || ret=3D$? + + if [ $ret -ne 0 ] + then + echo "Extended register capture test [Failed record ${regs_opt}=3D${= reg}]" + return 1 + fi + done + + return 0 +} + +test_extd_register_capture() { + local arch + local intr_regs + local user_regs + local intr_ext_regs + local user_ext_regs + local tested=3D0 + + echo "Extended register capture test" + if ! perf list pmu | grep -q 'br_inst_retired.near_call' + then + echo "Extended register capture test [Skipped missing event]" + return + fi + + intr_regs=3D$(perf record --intr-regs=3D\? 2>&1 || true) + user_regs=3D$(perf record --user-regs=3D\? 2>&1 || true) + + intr_ext_regs=3D"" + user_ext_regs=3D"" + + arch=3D$(uname -m) + case ${arch} in + x86_64|i386) + intr_ext_regs=3D$(get_x86_extended_regs "${intr_regs}") + user_ext_regs=3D$(get_x86_extended_regs "${user_regs}") + ;; + *) + echo "Extended register capture test [Skipped non-x86 platform]" + return + ;; + esac + + if [ -z "${intr_ext_regs}" ] + then + echo "Extended register capture test [Skipped missing intr extended re= gisters]" + elif ! validate_extd_regs_sampling "--intr-regs" "${intr_ext_regs}" "ire= gs" + then + echo "Extended register capture test [Failed intr extended register sa= mpling]" + err=3D1 + return + else + tested=3D1 + fi + + if [ -z "${user_ext_regs}" ] + then + echo "Extended register capture test [Skipped missing user extended re= gisters]" + elif ! validate_extd_regs_sampling "--user-regs" "${user_ext_regs}" "ure= gs" + then + echo "Extended register capture test [Failed user extended register sa= mpling]" + err=3D1 + return + else + tested=3D1 + fi + + if [ ${tested} -eq 0 ] + then + echo "Extended register capture test [Skipped missing extended registe= rs]" + return + fi + + echo "Extended register capture test [Success]" +} + test_system_wide() { echo "Basic --system-wide mode test" local ret=3D0 @@ -491,6 +609,7 @@ fi =20 test_per_thread test_register_capture +test_extd_register_capture test_system_wide test_workload test_branch_counter --=20 2.34.1 From nobody Fri Sep 25 11:05:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 399622FE074; Mon, 14 Sep 2026 01:48:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789350498; cv=none; b=iB2Lw9xdPrDBC3I90TcK/8DvkS0Uo2LHF+M9yddSpWcQUc5dQd031yWg5H2lfznBohIyuXEMyTWPYLM1ssYXrd2HnS6PTaM2ObGk0st0bJGTd0eJF8EDlhO1S99+mZG/NsHEOyYwjYJ6JFQFAG91YWqL0hyw4eOXv1+C1bMgR/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789350498; c=relaxed/simple; bh=3kFg9Qpz7u59REwfaQSuPRHtJv7hZafpOxBAJnX5ADA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HlJtyr+A6XslTaSBWnCxo4IWC1pNJO8qbc+o70tytNmFxjbjdTCJa/p0cWvEIY2o0KifNhC3fCMSrwoqca2pRGuf0ys0SLMlgdJqB1cLb7kkQ402/FwI7Q+XbPzbSmYw0DVhvFH2mPaOx5kqUpd+eAvWNaRHy6wU5RVFEeOuUXg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=V8lotReU; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="V8lotReU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789350497; x=1820886497; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3kFg9Qpz7u59REwfaQSuPRHtJv7hZafpOxBAJnX5ADA=; b=V8lotReUdrWpdZKwV+OZAxPDsg/5v9cM6S7E6CPkDA33k/C5FQ3FgXMJ nvWNfksGTiYPG2coV6q2ELaQE/2aZRK1xXlRH1MmQ7y3SoyIn2SZNZv/K CL+gHb0oCVggzptnFJbNIdUmhM5plsoNOYBtLX+0j0kwM4YmbiDL2cKvt mc70otuyd1OL9D2ILX8QqdLSmx9uqUch3F3tCCXIC0S8wVw7bEfa18Ms7 hqnx0mzoYjZ8AUnd4iauOsbWxNVDsrqNM0PQGcvurluE0BeH+1abhEMIL ZZstA6cwQF27TTKty8Pzb5AcwWe46gmG53zSvWkRiUVzVj9QK6Fool/4o w==; X-CSE-ConnectionGUID: uS7kDkVOS26H2kvgTrA2fQ== X-CSE-MsgGUID: c1DME0MdRZ2smMgSVBbOog== X-IronPort-AV: E=McAfee;i="6800,10657,11904"; a="93530688" X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="93530688" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2026 18:48:17 -0700 X-CSE-ConnectionGUID: iSt2LkgZTaeaazQyk1VSYQ== X-CSE-MsgGUID: PZ/rz66tRlqG+LzlZ1Y9aw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="276664245" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa005.jf.intel.com with ESMTP; 13 Sep 2026 18:48:13 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v11 10/10] perf tests: Add SIMD registers sampling test Date: Mon, 14 Sep 2026 09:40:49 +0800 Message-Id: <20260914014049.2061519-11-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> References: <20260914014049.2061519-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Validate that SIMD registers (XMM/YMM/ZMM/OPMASK on x86) can be sampled correctly with hardware support. Signed-off-by: Dapeng Mi --- tools/perf/tests/shell/record.sh | 138 +++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/tools/perf/tests/shell/record.sh b/tools/perf/tests/shell/reco= rd.sh index 770a546f8d45..4a4931cb5ba9 100755 --- a/tools/perf/tests/shell/record.sh +++ b/tools/perf/tests/shell/record.sh @@ -249,6 +249,143 @@ test_extd_register_capture() { echo "Extended register capture test [Success]" } =20 +extract_x86_advertised_simd_classes() { + local regs_output=3D"$1" + + echo "${regs_output}" \ + | grep -oE '(ZMM|YMM|XMM|OPMASK)[0-9]+-[0-9]+' \ + | sed -E 's/[0-9]+-[0-9]+$//' \ + | tr '[:upper:]' '[:lower:]' \ + | sort -u +} + +ordered_x86_simd_classes() { + local advertised_classes=3D"$1" + local simd_classes=3D"" + + if echo "${advertised_classes}" | grep -qw zmm + then + simd_classes=3D"${simd_classes} zmm" + fi + if echo "${advertised_classes}" | grep -qw ymm + then + simd_classes=3D"${simd_classes} ymm" + fi + if echo "${advertised_classes}" | grep -qw xmm + then + simd_classes=3D"${simd_classes} xmm" + fi + if echo "${advertised_classes}" | grep -qw opmask + then + simd_classes=3D"${simd_classes} opmask" + fi + + echo "${simd_classes}" | xargs +} + +check_simd_reg_capture() { + local script_field=3D"$1" + local simd_reg=3D"$2" + + perf script -F ip,sym,"${script_field}" -i "${perfdata}" 2>/dev/null | \ + grep -q -i "${simd_reg}\[" +} + +validate_simd_regs_sampling() { + local regs_opt=3D"$1" + local simd_classes=3D"$2" + local script_field=3D"$3" + local simd_class + local ret=3D0 + + for simd_class in ${simd_classes} + do + perf_record_with_retry "${perfdata}" \ + "check_simd_reg_capture ${script_field} ${simd_class}" "perf test -w= thloop" \ + -e br_inst_retired.near_call ${regs_opt}=3D${simd_class} -c 1000 \ + --per-thread || ret=3D$? + + if [ $ret -ne 0 ] + then + echo "SIMD register capture test [Failed record ${regs_opt}=3D${simd= _class}]" + return 1 + fi + done + + return 0 +} + +test_simd_register_capture() { + local arch + local intr_regs + local user_regs + local simd_classes + local user_simd_classes + local advertised_intr_classes + local advertised_user_classes + local tested=3D0 + + echo "SIMD register capture test" + if ! perf list pmu | grep -q 'br_inst_retired.near_call' + then + echo "SIMD register capture test [Skipped missing event]" + return + fi + + intr_regs=3D$(perf record --intr-regs=3D\? 2>&1 || true) + user_regs=3D$(perf record --user-regs=3D\? 2>&1 || true) + + simd_classes=3D"" + user_simd_classes=3D"" + + arch=3D$(uname -m) + case ${arch} in + x86_64|i386) + advertised_intr_classes=3D$(extract_x86_advertised_simd_classes "${int= r_regs}") + advertised_user_classes=3D$(extract_x86_advertised_simd_classes "${use= r_regs}") + + simd_classes=3D$(ordered_x86_simd_classes "${advertised_intr_classes}") + user_simd_classes=3D$(ordered_x86_simd_classes "${advertised_user_clas= ses}") + ;; + *) + echo "SIMD register capture test [Skipped non-x86 platform]" + return + ;; + esac + + if [ -z "${simd_classes}" ] + then + echo "SIMD register capture test [Skipped missing intr SIMD registers]" + elif ! validate_simd_regs_sampling "--intr-regs" "${simd_classes}" "ireg= s" + then + echo "SIMD register capture test [Failed intr SIMD register sampling]" + err=3D1 + return + else + tested=3D1 + fi + + if [ -z "${user_simd_classes}" ] + then + echo "SIMD register capture test [Skipped missing user SIMD registers]" + elif ! validate_simd_regs_sampling "--user-regs" "${user_simd_classes}" = "uregs" + then + echo "SIMD register capture test [Failed user SIMD register sampling]" + err=3D1 + return + else + tested=3D1 + fi + + if [ ${tested} -eq 0 ] + then + echo "SIMD register capture test [Skipped missing SIMD registers]" + return + fi + + echo "SIMD register capture test [Success]" +} + test_system_wide() { echo "Basic --system-wide mode test" local ret=3D0 @@ -610,6 +747,7 @@ fi test_per_thread test_register_capture test_extd_register_capture +test_simd_register_capture test_system_wide test_workload test_branch_counter --=20 2.34.1