From nobody Fri Sep 25 11:05:04 2026 Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9176266B72 for ; Mon, 14 Sep 2026 01:34:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.204.34.129 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789349697; cv=none; b=PLvkOoU7qazR+N+bt/KWGmUkPxWAETmeBamXMUXZPwSViL15WJwIsf4Sr6ogppO1/v9lQa/hIczAjwzssvN5HESZCX3cR9E8x5i/MSONemweeUCNBXczAG3FCBGX2eRIf9B/9Jf/Sq62ZQmxH6Fr/xC8rjqxNd29NQZrCc289A4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789349697; c=relaxed/simple; bh=Ffd900KJHpTvxtNoi18pAZ+vvWpl6BZ204optPEhJuQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=S28sFHcDOlm4kcrzbju+hv0PCht1KWwUHxog/atGye37uypV7woyTTfapEImfszmwgepkddJzq4n0Y9KwpD715T+b9+t8q2vfi/2fnK88L1grgCePjfikXdMcjC9UZbnRPr166Zf+0hSCiGO1X46elV6Td2/28KWJgKyMtDKI/c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=airkyi.com; spf=pass smtp.mailfrom=airkyi.com; dkim=pass (1024-bit key) header.d=airkyi.com header.i=@airkyi.com header.b=kDKdItZZ; arc=none smtp.client-ip=54.204.34.129 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=airkyi.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=airkyi.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=airkyi.com header.i=@airkyi.com header.b="kDKdItZZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=airkyi.com; s=altu2504; t=1789349633; bh=bLhZHimfeAemx102sKi3S3oU0Nrf9TQfYCxAQtyW+4U=; h=From:To:Subject:Date:Message-Id; b=kDKdItZZzKPRq9w3NtMmR1/D0+JwwUafwgiHJhpIu6MxZNlTYRYscK0xoVDwfBuIU jn5UMec3x4IJ6jvW77prHIC6Jy6hT47aITM00jogw9cG37BuboVOtiSiqtFrvNynkL 0O4WkQk6awgmiBPJ2baiLoosD17cuNMd/jbH5ZxQ= X-QQ-mid: esmtpsz11t1789349631t83d0eebd X-QQ-Originating-IP: UDkduqCMmPjnwTw37M0pn7cnoB9fgqMlUFCVtwTX2S4= Received: from DESKTOP-8BT1A2O.localdomain ( [61.154.14.86]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 14 Sep 2026 09:33:47 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 6289182345882749368 From: Chaoyi Chen To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Chaoyi Chen Subject: [PATCH v5 1/3] drm/rockchip: dsi: Add maximum per lane bit rate calculation Date: Mon, 14 Sep 2026 09:33:29 +0800 Message-Id: <20260914013331.108-2-kernel@airkyi.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260914013331.108-1-kernel@airkyi.com> References: <20260914013331.108-1-kernel@airkyi.com> X-QQ-SENDSIZE: 520 Feedback-ID: esmtpsz:airkyi.com:qybglogicsvrgz:qybglogicsvrgz6b-0 X-QQ-XMAILINFO: M3ziZXKDk+iOHFRGvweTdBwdFQUSbUWuTT0Y8fC3DVtF6xFLtZK7bMi3 1DSXGmn7DXxyiBfjQ/BK7W47UNXyAjiHrsGzGF6PdgubhG16ii/+uFEYbIAj0R7edDHx/i1 HX87i5WbgEVhWXgiWGkcXZhBTajDpO6V6u70w/RFygweMiJnN+S3g16nGXXnCOMSfHZNbnG EUq5tG12EbaIOJL/TuNayzC5JkS9Tuxn4KAWytdMboxQAOfwiVajp32lSuQ3KxYrDuPmUtf bdeaZUP+69qHiYadNt953vNGJkc+4iELiHwWVV1t40LMnnq1MIAPbvzW0rWbSdXLu1jkS2S uIDMQWhmU+1iakGQm5CuwubQeAfS7avG/FswsP6+qmr6RBd15ZikfeqfL6NR3c+KxU3bAlI M8it2GqN1jNKVLH3XMZEOaRzPAEFv8monWdTQG+B6yX5+gABCyKwrT2PnoOtEmIDlvykQmm 3/CLYCBx2xqxWVKqsK/Y2CBWJER4P+7Znzb8cqOJU/zcYzULyGXsyOkdHjZxyU1feDnK4HO MzLDLJI+xqGVHVYqahjOk1igJOU0y0l83yyL/BAT5MOc00rIGIJKYue/KIFM5DdHroXN4WT yPRvzm+YjRPY40B3fvG28rt3TDaqmFHvisQWS5OjB9yE9ic3TSQ4Ck0sXQfg4rQ8KILGXe9 0k+/oAZCHbCejszxDtSqE5nGTTQt5kXioztLoludUrJY7IQwFWQhwOauDGHRT5by2F0cXdz 1bzzaXR9iT+e0pTcBDbP2qYsPVU3DC92GVtO7hACmA6WTCkthV6Z/1w3qZ4WHMx3+0E3UiO v3PuI0lxrguWApRZ9ftAcxtYX+IeMzPaHofBQIYsGEKWbT4jTZIBEhHnFFuC6ceS/X/z4R5 ZG2xD8vEPsV92e8obsmsKjzFU2iz9DmmbKLbZ1CJ+H43p/eOmfUKXvQrHXUh1xriXjIQrIH ER2xS2VO+beCUnC21T7CtIv7rrAp0OchX35dAGqeyPMSBlge3hX6OH8gk6HdqRdmMZTscOg 31AsZ++A== X-QQ-XMRINFO: MPJ6Tf5t3I/ylTmHUqvI8+Wpn+Gzalws3A== X-QQ-RECHKSPAM: 0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chaoyi Chen Different chips have varying support for the maximum bit rate per lane. Add calculation for the maximum per lane bit rate for various chip platforms. Signed-off-by: Chaoyi Chen --- Changes in v5: - Change the upper bound check for target_mbps from < to <=3D (sashiko). (no changes since v4) Changes in v3: - Rebase to Linux v7.2 Changes in v2: - Fix the unit conversion for max_mbps. - Split the lane rate calculation into a separate patch. --- drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/= drm/rockchip/dw-mipi-dsi-rockchip.c index 3547d91b25d3..6a476c2c1303 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -268,6 +268,7 @@ struct rockchip_dw_dsi_chip_data { =20 unsigned int flags; unsigned int max_data_lanes; + unsigned long max_bit_rate_per_lane; }; =20 struct dw_mipi_dsi_rockchip { @@ -565,7 +566,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct= drm_display_mode *mode, int bpp; unsigned long mpclk, tmp; unsigned int target_mbps =3D 1000; - unsigned int max_mbps =3D dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; + unsigned int max_mbps; unsigned long best_freq =3D 0; unsigned long fvco_min, fvco_max, fin, fout; unsigned int min_prediv, max_prediv; @@ -573,6 +574,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct= drm_display_mode *mode, unsigned long _fbdiv, best_fbdiv; unsigned long min_delta =3D ULONG_MAX; =20 + max_mbps =3D dsi->cdata->max_bit_rate_per_lane / USEC_PER_SEC; dsi->format =3D format; bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); if (bpp < 0) { @@ -586,7 +588,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct= drm_display_mode *mode, if (mpclk) { /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ tmp =3D mpclk * (bpp / lanes) * 10 / 8; - if (tmp < max_mbps) + if (tmp <=3D max_mbps) target_mbps =3D tmp; else DRM_DEV_ERROR(dsi->dev, @@ -1503,6 +1505,7 @@ static const struct rockchip_dw_dsi_chip_data px30_ch= ip_data[] =3D { PX30_DSI_FORCETXSTOPMODE), 0), =20 .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1000000000UL, }, { /* sentinel */ } }; @@ -1515,6 +1518,7 @@ static const struct rockchip_dw_dsi_chip_data rk3128_= chip_data[] =3D { RK3128_DSI_FORCERXMODE | RK3128_DSI_FORCETXSTOPMODE), 0), .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1000000000UL, }, { /* sentinel */ } }; @@ -1527,6 +1531,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_= chip_data[] =3D { .lcdsel_lit =3D FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 1), =20 .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1500000000UL, }, { .reg =3D 0xff964000, @@ -1535,6 +1540,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_= chip_data[] =3D { .lcdsel_lit =3D FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 1), =20 .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1500000000UL, }, { /* sentinel */ } }; @@ -1547,6 +1553,7 @@ static const struct rockchip_dw_dsi_chip_data rk3368_= chip_data[] =3D { RK3368_DSI_FORCETXSTOPMODE | RK3368_DSI_FORCERXMODE), 0), .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1500000000UL, }, { /* sentinel */ } }; @@ -1634,6 +1641,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_= chip_data[] =3D { =20 .flags =3D DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1500000000UL, }, { .reg =3D 0xff968000, @@ -1658,6 +1666,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_= chip_data[] =3D { =20 .flags =3D DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1500000000UL, =20 .dphy_rx_init =3D rk3399_dphy_tx1rx1_init, .dphy_rx_power_on =3D rk3399_dphy_tx1rx1_power_on, @@ -1674,6 +1683,7 @@ static const struct rockchip_dw_dsi_chip_data rk3506_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3506_DSI_FORCERXMODE, 0) | FIELD_PREP_WM16_CONST(RK3506_DSI_FORCETXSTOPMODE, 0)), .max_data_lanes =3D 2, + .max_bit_rate_per_lane =3D 1500000000UL, }, { /* sentinel */ } }; @@ -1687,6 +1697,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3568_DSI0_TURNDISABLE, 0) | FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)), .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1200000000UL, }, { .reg =3D 0xfe070000, @@ -1696,6 +1707,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3568_DSI1_TURNDISABLE, 0) | FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)), .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1200000000UL, }, { /* sentinel */ } }; @@ -1708,6 +1720,7 @@ static const struct rockchip_dw_dsi_chip_data rv1126_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RV1126_DSI_FORCERXMODE, 0) | FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)), .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1000000000UL, }, { /* sentinel */ } }; --=20 2.53.0 From nobody Fri Sep 25 11:05:04 2026 Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF7DD2D739B for ; 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charset="utf-8" From: Chaoyi Chen Currently, there are generally two types of DPHY for Rockchip. One is the DPHY used by RK3288/RK3399, whose timing is described by Table A-3 High-Speed Transition Times in the databook. The other is the DPHY used by PX30 and its successors. If its timing is still described using RK3288/RK3399, it may not perform correctly on some DSI panel. Add dphy_get_timing for different D-PHY types to adapt to timing differences. The configuration details are as follows: - RK3288/RK3399: Select the corresponding entry from the timing table based on the data rate. - PX30 and later platforms: Use a fixed timing configuration. Signed-off-by: Chaoyi Chen --- (no changes since v5) Changes in v4: - Add missing RK3506 timing and the fallback path for get_timing (sashiko). Changes in v3: - Rebase to Linux v7.2 Changes in v2: - Add more comment about timing config. --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 49 ++++++++++++++++++- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/= drm/rockchip/dw-mipi-dsi-rockchip.c index 6a476c2c1303..feb484f7c03e 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -247,6 +247,7 @@ enum { BIASEXTR_127_7, }; =20 +struct dw_mipi_dsi_rockchip; struct rockchip_dw_dsi_chip_data { u32 reg; =20 @@ -262,6 +263,9 @@ struct rockchip_dw_dsi_chip_data { u32 lanecfg2_grf_reg; u32 lanecfg2; =20 + int (*dphy_get_timing)(struct dw_mipi_dsi_rockchip *dsi, unsigned int lan= e_mbps, + struct dw_mipi_dsi_dphy_timing *timing); + int (*dphy_rx_init)(struct phy *phy); int (*dphy_rx_power_on)(struct phy *phy); int (*dphy_rx_power_off)(struct phy *phy); @@ -721,8 +725,9 @@ static struct hstt hstt_table[] =3D { }; =20 static int -dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, - struct dw_mipi_dsi_dphy_timing *timing) +dw_mipi_dsi_phy_rk3288_get_timing(struct dw_mipi_dsi_rockchip *dsi, + unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) { int i; =20 @@ -738,6 +743,35 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned i= nt lane_mbps, return 0; } =20 +static const struct dw_mipi_dsi_dphy_timing dphy_timing_px30 =3D { + .clk_lp2hs =3D 0x40, + .clk_hs2lp =3D 0x40, + .data_lp2hs =3D 0x10, + .data_hs2lp =3D 0x14, +}; + +static int +dw_mipi_dsi_phy_px30_get_timing(struct dw_mipi_dsi_rockchip *dsi, + unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) +{ + *timing =3D dphy_timing_px30; + + return 0; +} + +static int +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) +{ + struct dw_mipi_dsi_rockchip *dsi =3D priv_data; + + if (dsi->cdata->dphy_get_timing) + return dsi->cdata->dphy_get_timing(dsi, lane_mbps, timing); + + return dw_mipi_dsi_phy_px30_get_timing(dsi, lane_mbps, timing); +} + static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops =3D { .init =3D dw_mipi_dsi_phy_init, .power_on =3D dw_mipi_dsi_phy_power_on, @@ -1506,6 +1540,7 @@ static const struct rockchip_dw_dsi_chip_data px30_ch= ip_data[] =3D { =20 .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1000000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1519,6 +1554,7 @@ static const struct rockchip_dw_dsi_chip_data rk3128_= chip_data[] =3D { RK3128_DSI_FORCETXSTOPMODE), 0), .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1000000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1532,6 +1568,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_= chip_data[] =3D { =20 .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1500000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_rk3288_get_timing, }, { .reg =3D 0xff964000, @@ -1541,6 +1578,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_= chip_data[] =3D { =20 .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1500000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_rk3288_get_timing, }, { /* sentinel */ } }; @@ -1554,6 +1592,7 @@ static const struct rockchip_dw_dsi_chip_data rk3368_= chip_data[] =3D { RK3368_DSI_FORCERXMODE), 0), .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1500000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1642,6 +1681,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_= chip_data[] =3D { .flags =3D DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1500000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_rk3288_get_timing, }, { .reg =3D 0xff968000, @@ -1671,6 +1711,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_= chip_data[] =3D { .dphy_rx_init =3D rk3399_dphy_tx1rx1_init, .dphy_rx_power_on =3D rk3399_dphy_tx1rx1_power_on, .dphy_rx_power_off =3D rk3399_dphy_tx1rx1_power_off, + .dphy_get_timing =3D dw_mipi_dsi_phy_rk3288_get_timing, }, { /* sentinel */ } }; @@ -1684,6 +1725,7 @@ static const struct rockchip_dw_dsi_chip_data rk3506_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3506_DSI_FORCETXSTOPMODE, 0)), .max_data_lanes =3D 2, .max_bit_rate_per_lane =3D 1500000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1698,6 +1740,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)), .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1200000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { .reg =3D 0xfe070000, @@ -1708,6 +1751,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)), .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1200000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1721,6 +1765,7 @@ static const struct rockchip_dw_dsi_chip_data rv1126_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)), .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1000000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; --=20 2.53.0 From nobody Fri Sep 25 11:05:04 2026 Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2AAE2D77F7 for ; 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charset="utf-8" From: Chaoyi Chen The lane rate is calculated as follows: Lane_Rate =3D Pixel_Clk * (BPP / lanes) * Overhead The overhead factor is set to 1/0.8, equivalent to a 25% overhead. Now let's consider the case of RGB888 (BPP24) with a pclk of 148.5MHz. The lane rate equals 148.5M * (24 / 4) * 1.25 =3D 1113.75 Mbps. However, this is beyond the capability of certain platforms limited to a 1Gbps lane rate. On the other hand, we have observed that some DSI panel actually perform worse with higher overhead. So we are considering relaxing the bandwidth margin requirements. According to the downstream test results, adopting 1/0.9 seems to be a sound approach, corresponding to an overhead of about 11%. Signed-off-by: Chaoyi Chen --- (no changes since v5) Changes in v4: - Fix potential overflow and underflow issues in bandwidth calculation(sashiko). Changes in v3: - Rebase to Linux v7.2 --- drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/= drm/rockchip/dw-mipi-dsi-rockchip.c index feb484f7c03e..03019b99abdc 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -590,8 +590,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct= drm_display_mode *mode, =20 mpclk =3D DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); if (mpclk) { - /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ - tmp =3D mpclk * (bpp / lanes) * 10 / 8; + /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ + tmp =3D DIV_ROUND_UP(mpclk * bpp * 10, lanes * 9); if (tmp <=3D max_mbps) target_mbps =3D tmp; else @@ -601,7 +601,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct= drm_display_mode *mode, =20 /* for external phy only a the mipi_dphy_config is necessary */ if (dsi->phy) { - phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, + phy_mipi_dphy_get_default_config((u32)mode->clock * 1000 * 10 / 9, bpp, lanes, &dsi->phy_opts.mipi_dphy); dsi->lane_mbps =3D target_mbps; --=20 2.53.0