From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93ECE361DDC; Mon, 14 Sep 2026 11:39:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385951; cv=none; b=cudOXmptxjeHNAQmW1I7zgKp7+ZUOpf2H5QjA30ilLzTuydppWeRHt7l/nv/eo8aZdEHaRwhqHMVlNWMKO9mO0OsVDYjWFTcpJdeD/pwKdMgOHE+Qluq1QolV9thIHM7vAqnSpGq5lfVehjXJpTf6Fe4JSi+UX4T+NwjF82xecU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385951; c=relaxed/simple; bh=ZEqXV20UfJpPysNADYTF43diSa/57Iv3c2M4KOvi/ko=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LTr26FtXyDz8Cw7OamltyaTxUI0LIJzka2J6msy9i+0RAAKqo3+pkue2vfHRFwkS493sIxjzIX414+H77nZDMgQ1x8F1HB9f/rxy+4t4Ld7gTuCJ0XYpCKCsAxA1jR+GfsW1lbxlP9plX5Lp+2lYSWyYSoDEkTuJOdMEygFv7UU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=nTFIZwLA; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="nTFIZwLA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789385947; bh=ZEqXV20UfJpPysNADYTF43diSa/57Iv3c2M4KOvi/ko=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nTFIZwLAvoYEUQhGLNQPtycCmX6f14do4EyIYyevvzEQuhLOmNTk8mIMTB7cxHk2+ UV7Z9kO21pvXScf18km+mhF6+JnHUeaOmo8tHsW3sXCRigzL3XovwXV+LzFfsARg68 oemZyBf+yd0c7CprFRGM4xcnYULp7eZfls80hq7da3Np1V0W9YJoEfPHotFlz82tZq +DzpvJXxDJop/710rVCo1YU4ztpcmhxMyrrGVJ1+WAxzC8VpxT+stNqR/nzxWEgLI3 v8/tWFD7q2H1N65j/3QpXgBac5HmRSrYj52RLCAeqdm0Co48e3YuP6PwUlDRBc8d2n 4zTNvqBwCuXpg== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id C940E17E093B; Mon, 14 Sep 2026 13:39:05 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:47 +0200 Subject: [PATCH v12 01/24] dt-bindings: phy: Add mediatek,mt8196-ufsphy variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-1-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Conor Dooley , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=2063; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=bk5EtgAp8+Q6dY7h9oTa6fh/C3fcFtiFpYBT06lrORk=; b=MyHdxbhEWSidqYqe5QwS65OA93k85iycaWolhOsDT7NKNWZKdmlrlOUN2PFGiyEFh1uynD+pa vPu6n9mSJJ5AX2FdPoZm3Bqp93Y+WKm7oWhPOdfkKMqUQyZ+q7xZ8vP X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli The MediaTek MT8196 SoC includes an M-PHY compatible with the already existing mt8183 binding. However, one omission from the original binding was that all of these variants may have an optional reset. Add the new compatible, and also the resets property, with an example. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Acked-by: Conor Dooley Acked-by: Vinod Koul Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- .../devicetree/bindings/phy/mediatek,ufs-phy.yaml | 16 ++++++++++++= ++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/= Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml index 6e2edd43fc2a..ee71dfa4e0c0 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - mediatek,mt8195-ufsphy + - mediatek,mt8196-ufsphy - const: mediatek,mt8183-ufsphy - const: mediatek,mt8183-ufsphy =20 @@ -43,6 +44,10 @@ properties: - const: unipro - const: mp =20 + resets: + items: + - description: Optional UFS M-PHY reset. + "#phy-cells": const: 0 =20 @@ -66,5 +71,16 @@ examples: clock-names =3D "unipro", "mp"; #phy-cells =3D <0>; }; + - | + #include + ufs-phy@16800000 { + compatible =3D "mediatek,mt8196-ufsphy", "mediatek,mt8183-ufsphy"; + reg =3D <0x16800000 0x10000>; + clocks =3D <&ufs_ao_clk 3>, + <&ufs_ao_clk 5>; + clock-names =3D "unipro", "mp"; + resets =3D <&ufs_ao_clk MT8196_UFSAO_RST0_UFS_MPHY>; + #phy-cells =3D <0>; + }; =20 ... --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 886AE3E557E; Mon, 14 Sep 2026 11:39:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385953; cv=none; b=RdhAd6WHjQUY+SM7YByWHK7sh19bJKM/ZH2DzQ3Vn3DCg327M3LI1HdI+moEemk1gbxjHw3J1TH+e+Q8lAvRvnuv90rzLKe0n1Inkqrc9ZqA0JHPcWMN4qodJYoZomMiQ8/anTrImKqgOtm/rio6AFfaTHCYFDDrSjehxuY6FBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385953; c=relaxed/simple; bh=KUKVQoUyB4JGu5VpHFnrd5muxOTTeq3oihV+4CbtGKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=n1foJH6tXDvwv6FS8yVvuLvOLs3KY0cg3cAru69AucqHgLgBKohCahynyKx56vIqTYY05ZWo82nu3WYPUVREqjsmkycH0ZaFKP810kA5yVsGugCK3iyWc1HRzOi6ETaZdNIHHuorX/k2Sr4xZuRcT7oPhc+GSP1FzcY5px55ZdE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=NSLuBQF7; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="NSLuBQF7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789385949; bh=KUKVQoUyB4JGu5VpHFnrd5muxOTTeq3oihV+4CbtGKM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NSLuBQF7SQk1BdTZfaK/Yuqh5kGeout5lvtWRdbX7CDWATC5npfKVEorhzcnQQZww x81UGuNNNJmHBYr1HlPBHfc5wegL5gXlSUcYhJO8Qw1q2LMw9wj7sRWL/ACpvcru4z 3SKlkcfIUZHmZatq+2fpK2qtXj8lgqIYf4eQ/HNS0EIdB8nCS/pMcLEK+EPAqO3cXI CP2AAkULjxAQKQmEBCd2UoaShee2ivuJU/hSfluR0WkvoA7TlQ48jgbDFTZH4miF+U TnVMy75rk7tU+dZ2e+0pffch5wDACRNaqGd3rw7Zvb+1kDfSCX2l2j58GlHEBPagMJ WKv0eldj8Q9PA== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id DC08917E08A1; Mon, 14 Sep 2026 13:39:07 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:48 +0200 Subject: [PATCH v12 02/24] dt-bindings: ufs: mediatek,ufs: Complete the binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-2-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=6907; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=zZ6DKxc1oDfLkwjpDJ4ibY+BAFQLfffNW1zKQtevtUY=; b=qggBbjuJPhIVP/zy7lB9zda7YbFt8jRW94HGqkOiBR27hdb9CaHU5cJ+T4b/9BK7FktSVQC0p XckSLKFa98aD5RefGeeYZxM0C/AnWL5MZWSvcdatdJ1hpYTB4NEkT+P X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli As it stands, the mediatek,ufs.yaml binding is startlingly incomplete. Its one example, which is the only real "user" of this binding in mainline, uses the deprecated freq-table-hz property. The resets, of which there are three optional ones, are completely absent. The clock description for MT8195 is incomplete, as is the one for MT8192. It's not known if the one clock binding for MT8183 is even correct, but I do not have access to the necessary code and documentation to find this out myself. The power supply situation is not much better; the binding describes one required power supply, but it's the UFS card supply, not any of the supplies feeding the controller silicon. No second example is present in the binding, making verification difficult. Disallow freq-table-hz and move to operating-points-v2. It's fine to break compatibility here, as the binding is currently unused and would be impossible to correctly use in its current state. Add the three resets and the corresponding reset-names property. These resets appear to be optional, i.e. not required for the functioning of the device. Move the list of clock names out of the if condition, and expand it for the confirmed clocks I could find by cross-referencing several clock drivers. For MT8195, increase the minimum number of clocks to include the rx_symbol ones, as they're internal to the SoC and should always be present, and should therefore not be omitted. MT8192 gets to have at least 3 clocks, as these were the ones I could quickly confirm from a glance at various trees. I can't say this was an exhaustive search though, but it's better than the current situation. Properly document all supplies, with which pin name on the SoCs they supply. Complete the example with them. Also add a MT8195 example to the binding, using supply labels that I am pretty sure would be the right ones for e.g. the Radxa NIO 12L. Finally, remove the 'ufs_' prefix from all clock names containing it and rename 'ufs' clock to 'main'. Signed-off-by: Nicolas Frattaroli Reviewed-by: Chaotian Jing Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/ufs/mediatek,ufs.yaml | 115 +++++++++++++++++= ---- 1 file changed, 96 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Docu= mentation/devicetree/bindings/ufs/mediatek,ufs.yaml index 15c347f5e660..945cb986b06b 100644 --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml @@ -19,11 +19,25 @@ properties: =20 clocks: minItems: 1 - maxItems: 8 + maxItems: 10 =20 clock-names: minItems: 1 - maxItems: 8 + items: + - const: main + - const: aes + - const: tick + - const: unipro_sysclk + - const: unipro_tick + - const: unipro_mp_bclk + - const: tx_symbol + - const: mem_sub + - const: rx_symbol0 + - const: rx_symbol1 + + operating-points-v2: true + + freq-table-hz: false =20 phys: maxItems: 1 @@ -31,8 +45,36 @@ properties: reg: maxItems: 1 =20 + resets: + items: + - description: reset for the UniPro layer + - description: reset for the cryptography engine + - description: reset for the host controller + + reset-names: + items: + - const: unipro + - const: crypto + - const: hci + + avdd09-supply: + description: Phandle to the 0.9V supply powering the AVDD09_UFS pin + + avdd12-supply: + description: Phandle to the 1.2V supply powering the AVDD12_UFS pin + + avdd12-ckbuf-supply: + description: Phandle to the 1.2V supply powering the AVDD12_CKBUF_UFS = pin + + avdd18-supply: + description: Phandle to the 1.8V supply powering the AVDD18_UFS pin + vcc-supply: true =20 + vccq-supply: true + + vccq2-supply: true + mediatek,ufs-disable-mcq: $ref: /schemas/types.yaml#/definitions/flag description: The mask to disable MCQ (Multi-Circular Queue) for UFS ho= st. @@ -54,29 +96,41 @@ allOf: properties: compatible: contains: - enum: - - mediatek,mt8195-ufshci + const: mediatek,mt8183-ufshci then: properties: clocks: - minItems: 8 + maxItems: 1 clock-names: items: - - const: ufs - - const: ufs_aes - - const: ufs_tick - - const: unipro_sysclk - - const: unipro_tick - - const: unipro_mp_bclk - - const: ufs_tx_symbol - - const: ufs_mem_sub - else: + - const: main + avdd12-ckbuf-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-ufshci + then: properties: clocks: - maxItems: 1 + minItems: 3 + maxItems: 3 clock-names: - items: - - const: ufs + minItems: 3 + maxItems: 3 + avdd09-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-ufshci + then: + properties: + clocks: + minItems: 10 + clock-names: + minItems: 10 + avdd09-supply: false =20 examples: - | @@ -94,9 +148,32 @@ examples: phys =3D <&ufsphy>; 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Mon, 14 Sep 2026 13:39:09 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:49 +0200 Subject: [PATCH v12 03/24] dt-bindings: ufs: mediatek,ufs: Add mt8196 variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-3-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=2407; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=2uW9ZmL2dUd2ijjEcXjW25ZrX/C9ujwAw0nz3p3HPkk=; b=b/gsxIf4usCbuYoePBbDUFjbYW0pBZkCoHNaZIjPP7XQ5LOyNEGQQ7ESLNETQSddF7CgSQdDq Ols7obny22QAreBmQatoOXjSKw1/FG4NyCf3PstSkHBb7bC66s2Jwb6 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli The MediaTek MT8196 SoC's UFS controller uses a different set of supplies. It is therefore not compatible with the MT8195. It also have an additional 0.9V supply pin (AVDD09_UFS_1), that is specific to this SoC, thus not currently described in the binding. Add a compatible for this SoC and new property for the additional supply, and modify the binding correspondingly. Signed-off-by: Nicolas Frattaroli Reviewed-by: Chaotian Jing Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/ufs/mediatek,ufs.yaml | 21 +++++++++++++++++= ++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Docu= mentation/devicetree/bindings/ufs/mediatek,ufs.yaml index 945cb986b06b..99181ec9dda0 100644 --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml @@ -16,6 +16,7 @@ properties: - mediatek,mt8183-ufshci - mediatek,mt8192-ufshci - mediatek,mt8195-ufshci + - mediatek,mt8196-ufshci =20 clocks: minItems: 1 @@ -60,6 +61,9 @@ properties: avdd09-supply: description: Phandle to the 0.9V supply powering the AVDD09_UFS pin =20 + avdd09-1-supply: + description: Phandle to the 0.9V supply powering the AVDD09_UFS_1 pin + avdd12-supply: description: Phandle to the 1.2V supply powering the AVDD12_UFS pin =20 @@ -104,6 +108,7 @@ allOf: clock-names: items: - const: main + avdd09-1-supply: false avdd12-ckbuf-supply: false - if: properties: @@ -119,6 +124,7 @@ allOf: minItems: 3 maxItems: 3 avdd09-supply: false + avdd09-1-supply: false - if: properties: compatible: @@ -131,6 +137,21 @@ allOf: clock-names: minItems: 10 avdd09-supply: false + avdd09-1-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8196-ufshci + then: + properties: + clocks: + minItems: 10 + clock-names: + minItems: 10 + avdd18-supply: false + required: + - operating-points-v2 =20 examples: - | --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE84D445AF4; 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Mon, 14 Sep 2026 13:39:11 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:50 +0200 Subject: [PATCH v12 04/24] scsi: ufs: mediatek: Move MTK_SIP_UFS_CONTROL to mtk_sip_svc.h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-4-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=1832; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=z5h4Zo+etU6eLsizbb7MCmCVs96yTicxCToFv5toJJQ=; b=fDysZEulwV78K2/4lYjohsvA4dn46a1g23+Grk13M7wDcH7UCC7O97ft8LPvOPdERLb20AS1O E/khP4sdh9vD/Ku9upA63IP+6vIubkVAqAX4CFgpfxQ1l/06A4/MAeV X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli SMC commands used by multiple drivers need to live in a shared header file somewhere to avoid code duplication. In order to rework the MPHY reset control to be in the phy-mtk-ufs.c driver, both ufs-mediatek and the phy driver need access to this command. Move it to mtk_sip_svc.h, where other such command definitions already live. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek-sip.h | 1 - include/linux/soc/mediatek/mtk_sip_svc.h | 3 +++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-med= iatek-sip.h index 7d17aedf6fb8..d627dfb4a766 100644 --- a/drivers/ufs/host/ufs-mediatek-sip.h +++ b/drivers/ufs/host/ufs-mediatek-sip.h @@ -11,7 +11,6 @@ /* * SiP (Slicon Partner) commands */ -#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) #define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0) #define UFS_MTK_SIP_DEVICE_RESET BIT(1) #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/m= ediatek/mtk_sip_svc.h index 6c95a29b79fa..36ab3153fe44 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,6 +22,9 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) =20 +/* UFS related SMC call */ +#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) + /* Modem related SMC call */ #define MTK_SIP_KERNEL_CCCI_CONTROL MTK_SIP_SMC_CMD(0x505) =20 --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7A99446075; Mon, 14 Sep 2026 11:39:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385959; cv=none; b=Povv9bMG/UlsYiCnnO0b+5bo3ZFIAQDJ6IYwfsmAaiF2FRatFFpH6XUOEA6Llg+n5DHzyJW/nQAaTXETU4egOay86J3LepPNFnICy0SB4KxKB+ETrj3GbEkJzxuHpOBMZaQ5+4eHHDIrxiB0+gizwQBJQokTaR767Kcomw3D1ME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385959; c=relaxed/simple; bh=bWpqNA2w/lzQwaLDZK22KciiLovKewpkb+MzEY+uZ6Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UNT9Xl5Mqps5CXf6SbIAc5LrMJ28CivhFIu+UI0NwvqkrYL26YiO+pOdTIqNcGtQpwEYRnOfeENPKkw8ffB5+hrUdNHyapBMv4E95qcQ6OJGujpHKOoXnjynwACM6sizXFYHAa3QHZj1TeAkIT84jtkvN+M2zEPsIJSQj/sNkQ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ErzWFKPM; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ErzWFKPM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789385955; bh=bWpqNA2w/lzQwaLDZK22KciiLovKewpkb+MzEY+uZ6Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ErzWFKPMMLQiccPxbjvzR3o+XQiuWEVdCnYG5jydh0hYVay2GtfSusxpTwMOMeins EjYduD1GN4hwwW1mgqki0wAqCzgmeR2MjxGmf2rb8wlfSbeC/A1ClbO1x8a6o3sFcc wFoUQWdsev03n4Plxf7omFwy7AnmC7Hx9aLf1eZbl0cc73nN+HDa6rH6H9voDG6Mn7 ZQyxJmMW//CxKfmDTuXeRp30RbkNksTQxQM7gshf0rU64mpWZIur03TllxOeHvuvnO ECmY+ThNo+/QXrgu3VopZ7EyDHOXYwigd8VoRiA2gywKNxxDfYjS/A4gqkWBlTw2J9 7edY8E0Y9u6wA== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id EFCFC17E0CFC; Mon, 14 Sep 2026 13:39:13 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:51 +0200 Subject: [PATCH v12 05/24] phy: mediatek: ufs: Add support for resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-5-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=4162; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=2rm7VAJlRoymYlJ4TRbEdX+nNHudWfCFJbmQirU4tfo=; b=mSmo4sh7+nJSGxBELxFaxIXHAo5EReiIhJFFi2isX9D70NwuAwzJpAdIFVJgOg4HXt6FouPik A0QUPqJrcURAepnXkGYqDTt1yi6zJq3JRGWRzS4Po+UMVDY2C36DQ5N X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli The MediaTek UFS PHY supports PHY resets. Until now, they've been implemented in the UFS host driver. Since they were never documented in the UFS HCI node's DT bindings, and no mainline DT uses it, it's fine if it's moved to the correct location, which is the PHY driver. Implement the MPHY reset logic in this driver and expose it through the phy subsystem's reset op. The reset itself is optional, as judging by other mainline devices that use this hardware, it's not required for the device to function. If no reset is present, the reset op returns -EOPNOTSUPP, which means that the ufshci driver can detect it's present and not double sleep in its own reset function, where it will call the phy reset. Reviewed-by: Philipp Zabel Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Acked-by: Vinod Koul Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/phy/mediatek/phy-mtk-ufs.c | 71 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 71 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-= mtk-ufs.c index fc19e0fa8ed5..4439a9eb6b7a 100644 --- a/drivers/phy/mediatek/phy-mtk-ufs.c +++ b/drivers/phy/mediatek/phy-mtk-ufs.c @@ -4,12 +4,15 @@ * Author: Stanley Chu */ =20 +#include #include #include #include #include #include #include +#include +#include =20 #include "phy-mtk-io.h" =20 @@ -35,9 +38,17 @@ =20 #define UFSPHY_CLKS_CNT 2 =20 +#define UFS_MTK_SIP_MPHY_CTRL BIT(8) + +enum ufs_mtk_mphy_op { + UFS_MPHY_BACKUP =3D 0, + UFS_MPHY_RESTORE +}; + struct ufs_mtk_phy { struct device *dev; void __iomem *mmio; + struct reset_control *reset; struct clk_bulk_data clks[UFSPHY_CLKS_CNT]; }; =20 @@ -140,9 +151,59 @@ static int ufs_mtk_phy_power_off(struct phy *generic_p= hy) return 0; } =20 +static int ufs_mtk_phy_ctrl(struct ufs_mtk_phy *phy, enum ufs_mtk_mphy_op = op) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_UFS_CONTROL, UFS_MTK_SIP_MPHY_CTRL, op, + 0, 0, 0, 0, 0, &res); + + switch (res.a0) { + case SMCCC_RET_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SMCCC_RET_INVALID_PARAMETER: + return -EINVAL; + default: + return 0; + } +} + +static int ufs_mtk_phy_reset(struct phy *generic_phy) +{ + struct ufs_mtk_phy *phy =3D get_ufs_mtk_phy(generic_phy); + int ret; + + if (!phy->reset) + return -EOPNOTSUPP; + + ret =3D reset_control_assert(phy->reset); + if (ret) + return ret; + + usleep_range(100, 110); + + ret =3D reset_control_deassert(phy->reset); + if (ret) + return ret; + + /* + * To avoid double-sleep and other unintended side-effects in the ufshci + * driver, don't return the phy_ctrl retval here, but just return -EPROTO. + */ + ret =3D ufs_mtk_phy_ctrl(phy, UFS_MPHY_RESTORE); + if (ret) { + dev_err(phy->dev, "UFS_MPHY_RESTORE SMC command failed: %pe\n", + ERR_PTR(ret)); + return -EPROTO; + } + + return 0; +} + static const struct phy_ops ufs_mtk_phy_ops =3D { .power_on =3D ufs_mtk_phy_power_on, .power_off =3D ufs_mtk_phy_power_off, + .reset =3D ufs_mtk_phy_reset, .owner =3D THIS_MODULE, }; =20 @@ -162,8 +223,18 @@ static int ufs_mtk_phy_probe(struct platform_device *p= dev) if (IS_ERR(phy->mmio)) return PTR_ERR(phy->mmio); =20 + phy->reset =3D devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(phy->reset)) + return dev_err_probe(dev, PTR_ERR(phy->reset), "Failed to get reset\n"); + phy->dev =3D dev; =20 + if (phy->reset) { + ret =3D ufs_mtk_phy_ctrl(phy, UFS_MPHY_BACKUP); + if (ret) + return dev_err_probe(dev, ret, "Failed to back up MPHY\n"); + } + ret =3D ufs_mtk_phy_clk_init(phy); if (ret) return ret; --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 552E94457CD; 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Mon, 14 Sep 2026 13:39:15 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:52 +0200 Subject: [PATCH v12 06/24] scsi: ufs: mediatek: Rework resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-6-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=6225; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=Vbiz68FI96aitngRkTHwkJdTr4Wurrjv80SHrHvHjEQ=; b=yCPsWoly9u7odlYmLQaPESu7cdShfCJn5z5ZAESVkKlQIkV9AWynzItBifR7Dfqm15aP6QTox Q5CjznbtOj7DEqVoGgGSKhOcXeJlRRSk+JbNA63T0JLpJ0EZ3aCOy5E X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli Rework the reset control getting in the driver's probe function to use the bulk reset APIs. Use the optional variant instead of defaulting to NULL if the resets fail, so that absent resets can be distinguished from erroneous resets. Also remove all remnants of the MPHY reset ever having lived in this driver. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Reviewed-by: Philipp Zabel Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek-sip.h | 8 ---- drivers/ufs/host/ufs-mediatek.c | 79 +++++++++++++++++++--------------= ---- drivers/ufs/host/ufs-mediatek.h | 7 ++-- 3 files changed, 43 insertions(+), 51 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-med= iatek-sip.h index d627dfb4a766..256598cc3b5b 100644 --- a/drivers/ufs/host/ufs-mediatek-sip.h +++ b/drivers/ufs/host/ufs-mediatek-sip.h @@ -31,11 +31,6 @@ enum ufs_mtk_vcc_num { UFS_VCC_MAX }; =20 -enum ufs_mtk_mphy_op { - UFS_MPHY_BACKUP =3D 0, - UFS_MPHY_RESTORE -}; - /* * SMC call wrapper function */ @@ -84,9 +79,6 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) #define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \ ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_version) =20 -#define ufs_mtk_mphy_ctrl(op, res) \ - ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op) - #define ufs_mtk_mtcmos_ctrl(op, res) \ ufs_mtk_smc(UFS_MTK_SIP_MTCMOS_CTRL, &(res), op) =20 diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 541bbaf92c21..4737a7a8acfc 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -94,6 +94,12 @@ static const char *const ufs_uic_dl_err_str[] =3D { "PA_INIT" }; =20 +static const char *const ufs_reset_names[] =3D { + "hci", + "crypto", + "unipro", +}; + static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -204,49 +210,46 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba) static void ufs_mtk_host_reset(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - struct arm_smccc_res res; - - reset_control_assert(host->hci_reset); - reset_control_assert(host->crypto_reset); - reset_control_assert(host->unipro_reset); - reset_control_assert(host->mphy_reset); - - usleep_range(100, 110); + int ret; =20 - reset_control_deassert(host->unipro_reset); - reset_control_deassert(host->crypto_reset); - reset_control_deassert(host->hci_reset); - reset_control_deassert(host->mphy_reset); + ret =3D reset_control_bulk_assert(MTK_UFS_NUM_RESETS, host->resets); + if (ret) + dev_warn(hba->dev, "Host reset assert failed: %pe\n", ERR_PTR(ret)); =20 - /* restore mphy setting aftre mphy reset */ - if (host->mphy_reset) - ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res); -} + ret =3D phy_reset(host->mphy); =20 -static void ufs_mtk_init_reset_control(struct ufs_hba *hba, - struct reset_control **rc, - char *str) -{ - *rc =3D devm_reset_control_get(hba->dev, str); - if (IS_ERR(*rc)) { - dev_info(hba->dev, "Failed to get reset control %s: %ld\n", - str, PTR_ERR(*rc)); - *rc =3D NULL; + /* + * Only sleep if there is no MPHY or MPHY doesn't have a reset + * implemented (which already sleeps) or the PHY reset function failed + * somehow, just to be safe + */ + if (!host->mphy || ret) { + usleep_range(100, 110); + if (ret && (ret !=3D -EOPNOTSUPP)) + dev_warn(hba->dev, "PHY reset failed: %pe\n", ERR_PTR(ret)); } + + ret =3D reset_control_bulk_deassert(MTK_UFS_NUM_RESETS, host->resets); + if (ret) + dev_warn(hba->dev, "Host reset deassert failed: %pe\n", ERR_PTR(ret)); } =20 -static void ufs_mtk_init_reset(struct ufs_hba *hba) +static int ufs_mtk_init_reset(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); + int ret, i; + + for (i =3D 0; i < MTK_UFS_NUM_RESETS; i++) + host->resets[i].id =3D ufs_reset_names[i]; =20 - ufs_mtk_init_reset_control(hba, &host->hci_reset, - "hci_rst"); - ufs_mtk_init_reset_control(hba, &host->unipro_reset, - "unipro_rst"); - ufs_mtk_init_reset_control(hba, &host->crypto_reset, - "crypto_rst"); - ufs_mtk_init_reset_control(hba, &host->mphy_reset, - "mphy_rst"); + ret =3D devm_reset_control_bulk_get_optional_exclusive(hba->dev, MTK_UFS_= NUM_RESETS, + host->resets); + if (ret) { + dev_err(hba->dev, "Failed to get resets: %pe\n", ERR_PTR(ret)); + return ret; + } + + return 0; } =20 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, @@ -1248,11 +1251,9 @@ static int ufs_mtk_init(struct ufs_hba *hba) if (err) goto out_variant_clear; =20 - ufs_mtk_init_reset(hba); - - /* backup mphy setting if mphy can reset */ - if (host->mphy_reset) - ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res); + err =3D ufs_mtk_init_reset(hba); + if (err) + goto out_variant_clear; =20 /* Enable runtime autosuspend */ hba->caps |=3D UFSHCD_CAP_RPM_AUTOSUSPEND; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 73cdc726f290..f95f12eb9926 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -7,12 +7,14 @@ #define _UFS_MEDIATEK_H =20 #include +#include =20 /* * MCQ define and struct */ #define UFSHCD_MAX_Q_NR 8 #define MTK_MCQ_INVALID_IRQ 0xFFFF +#define MTK_UFS_NUM_RESETS 3 =20 /* REG_UFS_MMIO_OPT_CTRL_0 160h */ #define EHS_EN BIT(0) @@ -175,10 +177,7 @@ struct ufs_mtk_mcq_intr_info { struct ufs_mtk_host { struct phy *mphy; struct regulator *reg_va09; - struct reset_control *hci_reset; - struct reset_control *unipro_reset; - struct reset_control *crypto_reset; - struct reset_control *mphy_reset; + struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS]; struct ufs_hba *hba; struct ufs_mtk_crypt_cfg *crypt; struct ufs_mtk_clk mclk; --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97906445AF4; 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Mon, 14 Sep 2026 13:39:17 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:53 +0200 Subject: [PATCH v12 07/24] scsi: ufs: mediatek: Rework 0.9V regulator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-7-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=7687; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=BerazSHvlZZCBrQcTN1Ugtbg589EmjctN74cY1FV0uQ=; b=2EmfG0+rWFb1Q4+OGNzjgoxLXUK9tR1tafhke1YPcLagqJzan2DN8jG5701XP3EU0RhVpEImf W3g7tFdn1qbCufESjHxSZldz7Fe0cp9qzCnuZExkM4rl03SB1Biop/e X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli The mediatek UFS host driver does some pretty bad stuff with regards to the 0.9V regulator. Instead of just checking for the presence of the regulator, it adds a cap if it's there, and then checks for the cap. It also sleeps to stabilise the supply after enabling the regulator, which is something that should be done by the regulator framework with the appropriate delay properties in the DTS instead of random sleeps in the driver code. Rework this code and rename it to the avdd09 name I've chosen in the binding for this supply name, instead of the downstream "va09" name that isn't used by the datasheets for any of these chips. Reviewed-by: Peter Wang Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 142 +++++++++++++++++++++++++++---------= ---- drivers/ufs/host/ufs-mediatek.h | 3 +- 2 files changed, 96 insertions(+), 49 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 4737a7a8acfc..f43bee50adb2 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -39,6 +39,10 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool= scale_up); #define MAX_SUPP_MAC 64 #define MCQ_QUEUE_OFFSET(c) ((((c) >> 16) & 0xFF) * 0x200) =20 +struct ufs_mtk_soc_data { + bool has_avdd09; +}; + static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] =3D { { .wmanufacturerid =3D UFS_ANY_VENDOR, .model =3D UFS_ANY_MODEL, @@ -49,8 +53,13 @@ static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = =3D { {} }; =20 +static const struct ufs_mtk_soc_data mt8183_data =3D { + .has_avdd09 =3D true, +}; + static const struct of_device_id ufs_mtk_of_match[] =3D { - { .compatible =3D "mediatek,mt8183-ufshci" }, + { .compatible =3D "mediatek,mt8183-ufshci", .data =3D &mt8183_data }, + { .compatible =3D "mediatek,mt8192-ufshci" }, { .compatible =3D "mediatek,mt8195-ufshci" }, {}, }; @@ -107,13 +116,6 @@ static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_= hba *hba) return host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE; } =20 -static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba) -{ - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - - return host->caps & UFS_MTK_CAP_VA09_PWR_CTRL; -} - static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -508,44 +510,70 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hb= a, u32 state, return -ETIMEDOUT; } =20 +static int ufs_mtk_09v_off(struct ufs_mtk_host *host) +{ + struct arm_smccc_res res; + int ret; + + if (!host->reg_avdd09) + return 0; + + ufs_mtk_va09_pwr_ctrl(res, 0); + ret =3D regulator_disable(host->reg_avdd09); + if (ret) { + dev_err(host->hba->dev, "Failed to disable avdd09-supply: %pe\n", + ERR_PTR(ret)); + ufs_mtk_va09_pwr_ctrl(res, 1); + return ret; + } + + return 0; +} + +static int ufs_mtk_09v_on(struct ufs_mtk_host *host) +{ + struct arm_smccc_res res; + int ret; + + if (!host->reg_avdd09) + return 0; + + ret =3D regulator_enable(host->reg_avdd09); + if (ret) { + dev_err(host->hba->dev, "Failed to enable avdd09-supply: %pe\n", + ERR_PTR(ret)); + return ret; + } + + ufs_mtk_va09_pwr_ctrl(res, 1); + + return 0; +} + static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct phy *mphy =3D host->mphy; - struct arm_smccc_res res; - int ret =3D 0; + int ret; =20 - if (!mphy || !(on ^ host->mphy_powered_on)) + if (!mphy || on =3D=3D host->mphy_powered_on) return 0; =20 if (on) { - if (ufs_mtk_is_va09_supported(hba)) { - ret =3D regulator_enable(host->reg_va09); - if (ret < 0) - goto out; - /* wait 200 us to stablize VA09 */ - usleep_range(200, 210); - ufs_mtk_va09_pwr_ctrl(res, 1); - } + ret =3D ufs_mtk_09v_on(host); + if (ret) + return ret; phy_power_on(mphy); } else { phy_power_off(mphy); - if (ufs_mtk_is_va09_supported(hba)) { - ufs_mtk_va09_pwr_ctrl(res, 0); - ret =3D regulator_disable(host->reg_va09); - } - } -out: - if (ret) { - dev_info(hba->dev, - "failed to %s va09: %d\n", - on ? "enable" : "disable", - ret); - } else { - host->mphy_powered_on =3D on; + ret =3D ufs_mtk_09v_off(host); + if (ret) + return ret; } =20 - return ret; + host->mphy_powered_on =3D on; + + return 0; } =20 static int ufs_mtk_get_host_clk(struct device *dev, const char *name, @@ -680,17 +708,6 @@ static void ufs_mtk_init_boost_crypt(struct ufs_hba *h= ba) return; } =20 -static void ufs_mtk_init_va09_pwr_ctrl(struct ufs_hba *hba) -{ - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - - host->reg_va09 =3D regulator_get(hba->dev, "va09"); - if (IS_ERR(host->reg_va09)) - dev_info(hba->dev, "failed to get va09"); - else - host->caps |=3D UFS_MTK_CAP_VA09_PWR_CTRL; -} - static void ufs_mtk_init_host_caps(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -699,9 +716,6 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba) if (of_property_read_bool(np, "mediatek,ufs-boost-crypt")) ufs_mtk_init_boost_crypt(hba); =20 - if (of_property_read_bool(np, "mediatek,ufs-support-va09")) - ufs_mtk_init_va09_pwr_ctrl(hba); - if (of_property_read_bool(np, "mediatek,ufs-disable-ah8")) host->caps |=3D UFS_MTK_CAP_DISABLE_AH8; =20 @@ -1207,6 +1221,36 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba) host->mcq_nr_intr =3D 0; } =20 +/** + * ufs_mtk_get_supplies - acquire variant-specific supplies + * @host: pointer to driver's private &struct ufs_mtk_host instance + * + * Returns 0 on success, negative errno on error. + */ +static int ufs_mtk_get_supplies(struct ufs_mtk_host *host) +{ + struct device *dev =3D host->hba->dev; + const struct ufs_mtk_soc_data *data =3D of_device_get_match_data(dev); + + if (!data || !data->has_avdd09) + return 0; + + host->reg_avdd09 =3D devm_regulator_get_optional(dev, "avdd09"); + if (IS_ERR(host->reg_avdd09)) { + if (PTR_ERR(host->reg_avdd09) =3D=3D -ENODEV) { + host->reg_avdd09 =3D NULL; + return 0; + } + + return dev_err_probe(dev, + PTR_ERR(host->reg_avdd09), + "Failed to get avdd09 regulator: %pe\n", + host->reg_avdd09); + } + + return 0; +} + /** * ufs_mtk_init - find other essential mmio bases * @hba: host controller instance @@ -1290,6 +1334,10 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_init_clocks(hba); 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Mon, 14 Sep 2026 13:39:19 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:54 +0200 Subject: [PATCH v12 08/24] scsi: ufs: mediatek: Add dual 0.9V supply support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-8-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=4943; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=u/D/WxpbgbGO/YXlEsLYW2eKlLgsf5ydTcbshi4YT0w=; b=/rmDKEQpUgBouArhObVXszVEI3XupxFdk0IKNThH6PuLr3m00GlHRkEIpOiKcD92oY3jZK3d2 DJ4SDDXWhjLBD579kj3AZRKeEjaINNkbVGSCbzpO+gvD0fwQhm8PW4s X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= The MT8196 SoC has an additional pin in comparison of the MT8183 SoC, that is used to feed the host controller with a 0.9V supply. In preparation of this SoC support, add in platform data and driver the management a second optional 0.9V regulator named "avdd09-1". Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/ufs/host/ufs-mediatek.c | 91 ++++++++++++++++++++++++++++++-------= ---- drivers/ufs/host/ufs-mediatek.h | 1 + 2 files changed, 69 insertions(+), 23 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index f43bee50adb2..467fc77c90e1 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -41,6 +41,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool = scale_up); =20 struct ufs_mtk_soc_data { bool has_avdd09; + bool has_avdd09_1; }; =20 static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] =3D { @@ -513,18 +514,37 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hb= a, u32 state, static int ufs_mtk_09v_off(struct ufs_mtk_host *host) { struct arm_smccc_res res; - int ret; + int ret, ret2; =20 - if (!host->reg_avdd09) + if (!host->reg_avdd09 && !host->reg_avdd09_1) return 0; =20 ufs_mtk_va09_pwr_ctrl(res, 0); - ret =3D regulator_disable(host->reg_avdd09); - if (ret) { - dev_err(host->hba->dev, "Failed to disable avdd09-supply: %pe\n", - ERR_PTR(ret)); - ufs_mtk_va09_pwr_ctrl(res, 1); - return ret; + + if (host->reg_avdd09) { + ret =3D regulator_disable(host->reg_avdd09); + if (ret) { + dev_err(host->hba->dev, "Failed to disable avdd09-supply: %pe\n", + ERR_PTR(ret)); + ufs_mtk_va09_pwr_ctrl(res, 1); + return ret; + } + } + + if (host->reg_avdd09_1) { + ret =3D regulator_disable(host->reg_avdd09_1); + if (ret) { + dev_err(host->hba->dev, "Failed to disable avdd09-1-supply: %pe\n", + ERR_PTR(ret)); + + ret2 =3D regulator_enable(host->reg_avdd09); + if (ret2) + dev_err(host->hba->dev, "Failed to re-enable avdd09-supply: %pe\n", + ERR_PTR(ret2)); + + ufs_mtk_va09_pwr_ctrl(res, 1); + return ret; + } } =20 return 0; @@ -535,14 +555,26 @@ static int ufs_mtk_09v_on(struct ufs_mtk_host *host) struct arm_smccc_res res; int ret; =20 - if (!host->reg_avdd09) + if (!host->reg_avdd09 && !host->reg_avdd09_1) return 0; =20 - ret =3D regulator_enable(host->reg_avdd09); - if (ret) { - dev_err(host->hba->dev, "Failed to enable avdd09-supply: %pe\n", - ERR_PTR(ret)); - return ret; + if (host->reg_avdd09) { + ret =3D regulator_enable(host->reg_avdd09); + if (ret) { + dev_err(host->hba->dev, "Failed to enable avdd09-supply: %pe\n", + ERR_PTR(ret)); + return ret; + } + } + + if (host->reg_avdd09_1) { + ret =3D regulator_enable(host->reg_avdd09_1); + if (ret) { + dev_err(host->hba->dev, "Failed to enable avdd09-1-supply: %pe\n", + ERR_PTR(ret)); + regulator_disable(host->reg_avdd09); + return ret; + } } =20 ufs_mtk_va09_pwr_ctrl(res, 1); @@ -1232,20 +1264,33 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host= *host) struct device *dev =3D host->hba->dev; const struct ufs_mtk_soc_data *data =3D of_device_get_match_data(dev); =20 - if (!data || !data->has_avdd09) + if (!data) return 0; =20 - host->reg_avdd09 =3D devm_regulator_get_optional(dev, "avdd09"); - if (IS_ERR(host->reg_avdd09)) { - if (PTR_ERR(host->reg_avdd09) =3D=3D -ENODEV) { + if (data->has_avdd09) { + host->reg_avdd09 =3D devm_regulator_get_optional(dev, "avdd09"); + if (IS_ERR(host->reg_avdd09)) { + if (PTR_ERR(host->reg_avdd09) !=3D -ENODEV) { + return dev_err_probe(dev, + PTR_ERR(host->reg_avdd09), + "Failed to get avdd09 regulator: %pe\n", + host->reg_avdd09); + } host->reg_avdd09 =3D NULL; - return 0; } + } =20 - return dev_err_probe(dev, - PTR_ERR(host->reg_avdd09), - "Failed to get avdd09 regulator: %pe\n", - host->reg_avdd09); + if (data->has_avdd09_1) { + host->reg_avdd09_1 =3D devm_regulator_get_optional(dev, "avdd09-1"); + if (IS_ERR(host->reg_avdd09_1)) { + if (PTR_ERR(host->reg_avdd09_1) !=3D -ENODEV) { + return dev_err_probe(dev, + PTR_ERR(host->reg_avdd09_1), + "Failed to get avdd09-1 regulator: %pe\n", + host->reg_avdd09_1); + } + host->reg_avdd09_1 =3D NULL; + } } =20 return 0; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index c63740b98e85..477fb9e36555 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -176,6 +176,7 @@ struct ufs_mtk_mcq_intr_info { struct ufs_mtk_host { struct phy *mphy; struct regulator *reg_avdd09; + struct regulator *reg_avdd09_1; struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS]; struct ufs_hba *hba; struct ufs_mtk_crypt_cfg *crypt; --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BDF244A3EB; Mon, 14 Sep 2026 11:39:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385967; cv=none; b=MQD7LYcDEwH740BApaY7t/UKLGUzObwmvZwSL9pt3OYNyG2njcEPr4KV2oChkZtZ/8Gg6T52bpZdHa/aDklmC6L2l/y3lPIWBHB0Fo0hDRAt1Te/fnXgz6K4Q5hN1Nt9ricNZB2XmYh5/rArcjU4SBaEOECM6KrU3zlVmiLYBBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385967; c=relaxed/simple; bh=FuNJHMb9Z+G/TLab+52xgPX/ea3DNxjrL9DsZzapMJ0=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-9-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=3160; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=qbVyf9DUj1yl0WBtYuLpa8lf0euA6P9fu1mbbWHcTyY=; b=szTeRE2PvWmd+A0XcO/R/uuh6ivndhF/blFWaC8oN9BJsg90w1HkNhjMztGBLWE9Ad4bjRf3p yMWUtCG3h4ZCXMCZ/T2/J4KhA3vX1QHOECTDWkStDPF3brwYcyeQtg6 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli Printing an error message on ENOMEM is pointless. The print will not work because there is no memory. Adding an of_match_device to the init function is pointless. Why would a different device with a different probe function ever use the same init function? Get rid of it. zero-initialising an error variable just so you can then goto a bare return statement with that error variable to signal success is also pointless, just return directly, there's no unwind being done. Reviewed-by: Peter Wang Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 43 +++++++++++++++----------------------= ---- 1 file changed, 16 insertions(+), 27 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 467fc77c90e1..2543810fcef3 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -54,18 +54,6 @@ static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = =3D { {} }; =20 -static const struct ufs_mtk_soc_data mt8183_data =3D { - .has_avdd09 =3D true, -}; - -static const struct of_device_id ufs_mtk_of_match[] =3D { - { .compatible =3D "mediatek,mt8183-ufshci", .data =3D &mt8183_data }, - { .compatible =3D "mediatek,mt8192-ufshci" }, - { .compatible =3D "mediatek,mt8195-ufshci" }, - {}, -}; -MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); - /* * Details of UIC Errors */ @@ -1308,29 +1296,19 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host= *host) */ static int ufs_mtk_init(struct ufs_hba *hba) { - const struct of_device_id *id; struct device *dev =3D hba->dev; struct ufs_mtk_host *host; struct Scsi_Host *shost =3D hba->host; - int err =3D 0; + int err; struct arm_smccc_res res; =20 host =3D devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); - if (!host) { - err =3D -ENOMEM; - dev_info(dev, "%s: no memory for mtk ufs host\n", __func__); - goto out; - } + if (!host) + return -ENOMEM; =20 host->hba =3D hba; ufshcd_set_variant(hba, host); =20 - id =3D of_match_device(ufs_mtk_of_match, dev); - if (!id) { - err =3D -EINVAL; - goto out; - } - /* Initialize host capability */ ufs_mtk_init_host_caps(hba); =20 @@ -1404,11 +1382,10 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_get_hw_ip_version(hba); =20 - goto out; + return 0; =20 out_variant_clear: ufshcd_set_variant(hba, NULL); -out: return err; } =20 @@ -2450,6 +2427,18 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_= vops =3D { .config_scsi_dev =3D ufs_mtk_config_scsi_dev, }; =20 +static const struct ufs_mtk_soc_data mt8183_data =3D { + .has_avdd09 =3D true, +}; + +static const struct of_device_id ufs_mtk_of_match[] =3D { + { .compatible =3D "mediatek,mt8183-ufshci", .data =3D &mt8183_data }, + { .compatible =3D "mediatek,mt8192-ufshci" }, + { .compatible =3D "mediatek,mt8195-ufshci" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); + /** * ufs_mtk_probe - probe routine of the driver * @pdev: pointer to Platform device handle --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0E87443C0F; Mon, 14 Sep 2026 11:39:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385969; cv=none; b=VjPZCtUzeNTjc4xqn9liqV7P0gEVbRY6pmgCTV4msjS6pVjRWuC4njVyaiBvnGy/syDCKwwaKoWXZi5+EXONCZDXWiwJQQwazv4L5kH2CW+I7xikqTCvYRB/rDjFsvagpInFqfznTsn5q+jiQ46fOk2M72jt5mxmoFDzrpYw0os= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-10-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=4293; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=QmHMe9SNsPNb3PxMp5MFOHQX7hvRU18z+upxvLaR3+o=; b=m49APqd+1CHTIki3MXV/wB46nc7hRMsv7yOZpgpsvrzJ8VXfIbJTD0EYRfVvlANvgP1gnz3s5 zuzRlMFUqfhAh3IBpZCESIU0RxJj+5NUmNNYuN6sNEqvPlI/KrpYW1m X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli I don't know whether the crypt-boost functionality as it is currently implemented is even appropriate for mainline. It might be better done in some generic way. But what I do know is that I can rework the code to make it less obtuse. Prefix the boost stuff with the appropriate vendor prefix, remove the pointless clock wrappers, and rework the function. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang (=E7=8E=8B=E4=BF=A1=E5=8F=8B) Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 89 ++++++++++++++-----------------------= ---- 1 file changed, 31 insertions(+), 58 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 2543810fcef3..4e6182d2cb6d 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -596,21 +596,6 @@ static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, = bool on) return 0; } =20 -static int ufs_mtk_get_host_clk(struct device *dev, const char *name, - struct clk **clk_out) -{ - struct clk *clk; - int err =3D 0; - - clk =3D devm_clk_get(dev, name); - if (IS_ERR(clk)) - err =3D PTR_ERR(clk); - else - *clk_out =3D clk; - - return err; -} - static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -667,65 +652,53 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, = bool boost) clk_disable_unprepare(cfg->clk_crypt_mux); } =20 -static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name, - struct clk **clk) -{ - int ret; - - ret =3D ufs_mtk_get_host_clk(hba->dev, name, clk); - if (ret) { - dev_info(hba->dev, "%s: failed to get %s: %d", __func__, - name, ret); - } - - return ret; -} - static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct ufs_mtk_crypt_cfg *cfg; struct device *dev =3D hba->dev; - struct regulator *reg; u32 volt; + int ret; =20 - host->crypt =3D devm_kzalloc(dev, sizeof(*(host->crypt)), - GFP_KERNEL); - if (!host->crypt) - goto disable_caps; + cfg =3D devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL); + if (!cfg) + return; =20 - reg =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); - if (IS_ERR(reg)) { - dev_info(dev, "failed to get dvfsrc-vcore: %ld", - PTR_ERR(reg)); - goto disable_caps; + cfg->reg_vcore =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); + if (IS_ERR(cfg->reg_vcore)) { + dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", cfg->reg_vcore); + return; } =20 - if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min", - &volt)) { - dev_info(dev, "failed to get boost-crypt-vcore-min"); - goto disable_caps; + ret =3D of_property_read_u32(dev->of_node, "mediatek,boost-crypt-vcore-mi= n", + &volt); + if (ret) { + dev_err(dev, "Failed to get mediatek,boost-crypt-vcore-min: %pe\n", + ERR_PTR(ret)); + return; } + cfg->vcore_volt =3D volt; =20 - cfg =3D host->crypt; - if (ufs_mtk_init_host_clk(hba, "crypt_mux", - &cfg->clk_crypt_mux)) - goto disable_caps; + cfg->clk_crypt_mux =3D devm_clk_get(dev, "crypt_mux"); + if (IS_ERR(cfg->clk_crypt_mux)) { + dev_err(dev, "Failed to get clock crypt_mux: %pe\n", cfg->clk_crypt_mux); + return; + } =20 - if (ufs_mtk_init_host_clk(hba, "crypt_lp", - &cfg->clk_crypt_lp)) - goto disable_caps; + cfg->clk_crypt_lp =3D devm_clk_get(dev, "crypt_lp"); + if (IS_ERR(cfg->clk_crypt_lp)) { + dev_err(dev, "Failed to get clock crypt_lp: %pe\n", cfg->clk_crypt_lp); + return; + } =20 - if (ufs_mtk_init_host_clk(hba, "crypt_perf", - &cfg->clk_crypt_perf)) - goto disable_caps; + cfg->clk_crypt_perf =3D devm_clk_get(dev, "crypt_perf"); + if (IS_ERR(cfg->clk_crypt_perf)) { + dev_err(dev, "Failed to get clock crypt_perf: %pe\n", cfg->clk_crypt_per= f); + return; + } =20 - cfg->reg_vcore =3D reg; - cfg->vcore_volt =3D volt; + host->crypt =3D cfg; host->caps |=3D UFS_MTK_CAP_BOOST_CRYPT_ENGINE; - -disable_caps: - return; } =20 static void ufs_mtk_init_host_caps(struct ufs_hba *hba) --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9573444C513; Mon, 14 Sep 2026 11:39:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385971; cv=none; b=rdfFWokmd0XGGytKtpID8tfzrwWKB+I/s8sr1djuuU43fKXpgcgLWpeyif03uznEBlnhyEOICr5rZBkhOahQ4ugLTvH4PUWjeVzz3ub1xpzQTfVHr63wO+ptETvgtVaLDcuJy/DMYudJnaSQXlfX1v37Z8Wca3dGkD0ltz1okcU= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-11-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=3082; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=TF3p9jbq2nMjNrHdI9y8GJWx1eGdMeHgZ9JSMsgxvcU=; b=qb+XKP/S0SYbg7hmTxbN1Ao8v0S9ZUAlq5KrdJAc/4sP17Q1ohTt+iLFYO69HHq3Q/IBXx/9x neG74sZhB4ZAlKFr4lv3flyAI/tS6H9Y7shOGqBfS0riAWg4nwd0yN5 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli MediaTek SoCs handled by this driver contain a per-SoC specific set of miscellaneous supplies. These feed parts of the UFS controller silicon inside the SoC, as opposed to the UFS card. Add the necessary driver code to acquire these supplies using the regulator bulk API. They should be kept on during suspend, so enable them when acquiring. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 4e6182d2cb6d..15960d7d99af 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -42,6 +42,8 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool = scale_up); struct ufs_mtk_soc_data { bool has_avdd09; bool has_avdd09_1; + u8 num_reg_names; + const char *const *reg_names; }; =20 static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] =3D { @@ -1224,10 +1226,22 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host= *host) { struct device *dev =3D host->hba->dev; const struct ufs_mtk_soc_data *data =3D of_device_get_match_data(dev); + int ret; =20 if (!data) return 0; =20 + if (data->num_reg_names) { + ret =3D devm_regulator_bulk_get_enable(dev, data->num_reg_names, + data->reg_names); + if (ret) { + dev_err_probe(dev, ret, + "Failed to get misc regulators: %pe\n", + ERR_PTR(ret)); + return ret; + } + } + if (data->has_avdd09) { host->reg_avdd09 =3D devm_regulator_get_optional(dev, "avdd09"); if (IS_ERR(host->reg_avdd09)) { @@ -2400,14 +2414,30 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk= _vops =3D { .config_scsi_dev =3D ufs_mtk_config_scsi_dev, }; =20 +static const char *const ufs_mtk_regs_avdd12_avdd18[] =3D { + "avdd12", "avdd18" +}; + +static const char *const ufs_mtk_regs_avdd12_ckbuf_avdd18[] =3D { + "avdd12", "avdd12-ckbuf", "avdd18" +}; + static const struct ufs_mtk_soc_data mt8183_data =3D { .has_avdd09 =3D true, + .reg_names =3D ufs_mtk_regs_avdd12_avdd18, + .num_reg_names =3D ARRAY_SIZE(ufs_mtk_regs_avdd12_avdd18), +}; + +static const struct ufs_mtk_soc_data mt8192_8195_data =3D { + .has_avdd09 =3D false, + .reg_names =3D ufs_mtk_regs_avdd12_ckbuf_avdd18, + .num_reg_names =3D ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf_avdd18), }; =20 static const struct of_device_id ufs_mtk_of_match[] =3D { { .compatible =3D "mediatek,mt8183-ufshci", .data =3D &mt8183_data }, - { .compatible =3D "mediatek,mt8192-ufshci" }, - { .compatible =3D "mediatek,mt8195-ufshci" }, + { .compatible =3D "mediatek,mt8192-ufshci", .data =3D &mt8192_8195_data }, + { .compatible =3D "mediatek,mt8195-ufshci", .data =3D &mt8192_8195_data }, {}, }; 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Mon, 14 Sep 2026 13:39:27 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:58 +0200 Subject: [PATCH v12 12/24] scsi: ufs: mediatek: Remove undocumented downstream reset cruft Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-12-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=2332; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=g/eawi80h53Tw7KZFt8dlxUWQY3Eq7uS+MqISAa1J18=; b=DSX8wp8bC/Y3ZCiB6NYbMTcRBphCn4WJ77ytgCQxx8jZuXtrAs9D3Vxst3ceoOJWhykQKbyiV 19IIGdQ8CqMCz+ab+1JimVwtIkLykxKqT9QBe52t1sBXdt0shJ/87IW X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli The MediaTek UFS host driver's probe function allows using a ti,syscon-reset as a reset, without going through the appropriate abstractions, or by documenting this in the binding at all. Remove this, it's downstream code and does not belong here. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Reviewed-by: Chaotian Jing Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 33 +++------------------------------ 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 15960d7d99af..3d108a092920 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -2451,38 +2451,12 @@ MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); static int ufs_mtk_probe(struct platform_device *pdev) { int err; - struct device *dev =3D &pdev->dev, *phy_dev =3D NULL; - struct device_node *reset_node, *phy_node =3D NULL; - struct platform_device *reset_pdev, *phy_pdev =3D NULL; - struct device_link *link; struct ufs_hba *hba; + struct platform_device *phy_pdev =3D NULL; + struct device *dev =3D &pdev->dev, *phy_dev =3D NULL; + struct device_node *phy_node =3D NULL; struct ufs_mtk_host *host; =20 - reset_node =3D of_find_compatible_node(NULL, NULL, - "ti,syscon-reset"); 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Mon, 14 Sep 2026 13:39:29 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:59 +0200 Subject: [PATCH v12 13/24] scsi: ufs: mediatek: Remove vendor kernel quirks cruft Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-13-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Krzysztof Kozlowski , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=3056; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=7cmTWMq9J2ZZJyalBAME0IfxrGGo6X2/e51S+qvtg4s=; b=P0AZ9J11jnkgm8EyjIym7om1BgNrFfus93vJQF5WnsfllJ2wAn6X9COIns5n7iHuibVFCQsif YwiCmQDEtTtDGUXdPvicFwQ+Z8wRulLVSsxHk2QJGuQPwn9Mvmm8L8J X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli Both ufs_mtk_vreg_fix_vcc and ufs_mtk_vreg_fix_vccqx look like they are vendor kernel hacks to work around existing downstream device trees. Mainline does not need or want them, so remove them. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 69 -------------------------------------= ---- 1 file changed, 69 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 3d108a092920..3c10a9fd09df 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1053,73 +1053,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) } } =20 -#define MAX_VCC_NAME 30 -static int ufs_mtk_vreg_fix_vcc(struct ufs_hba *hba) -{ - struct ufs_vreg_info *info =3D &hba->vreg_info; - struct device_node *np =3D hba->dev->of_node; - struct device *dev =3D hba->dev; - char vcc_name[MAX_VCC_NAME]; - struct arm_smccc_res res; - int err, ver; - - if (info->vcc) - return 0; - - if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) { - ufs_mtk_get_vcc_num(res); - if (res.a1 > UFS_VCC_NONE && res.a1 < UFS_VCC_MAX) - snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%lu", res.a1); - else - return -ENODEV; - } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) { - ver =3D (hba->dev_info.wspecversion & 0xF00) >> 8; - snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver); - } else { - return 0; - } - - err =3D ufshcd_populate_vreg(dev, vcc_name, &info->vcc, false); - if (err) - return err; - - err =3D ufshcd_get_vreg(dev, info->vcc); - if (err) - return err; - - err =3D regulator_enable(info->vcc->reg); - if (!err) { - info->vcc->enabled =3D true; - dev_info(dev, "%s: %s enabled\n", __func__, vcc_name); - } - - return err; -} - -static void ufs_mtk_vreg_fix_vccqx(struct ufs_hba *hba) -{ - struct ufs_vreg_info *info =3D &hba->vreg_info; - struct ufs_vreg **vreg_on, **vreg_off; - - if (hba->dev_info.wspecversion >=3D 0x0300) { - vreg_on =3D &info->vccq; - vreg_off =3D &info->vccq2; - } else { - vreg_on =3D &info->vccq2; - vreg_off =3D &info->vccq; - } - - if (*vreg_on) - (*vreg_on)->always_on =3D true; - - if (*vreg_off) { - regulator_disable((*vreg_off)->reg); - devm_kfree(hba->dev, (*vreg_off)->name); - devm_kfree(hba->dev, *vreg_off); - *vreg_off =3D NULL; - } -} - static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) { unsigned long flags; @@ -2040,8 +1973,6 @@ static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *= hba) host->ip_ver =3D=3D IP_VER_MT6995_B0)) hba->quirks |=3D UFSHCD_QUIRK_VCC_ON_DELAY; =20 - ufs_mtk_vreg_fix_vcc(hba); - ufs_mtk_vreg_fix_vccqx(hba); ufs_mtk_fix_ahit(hba); ufs_mtk_fix_clock_scaling(hba); } --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68AFF443E56; Mon, 14 Sep 2026 11:39:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385977; cv=none; b=GkC3YQDhpHgY5UM7Sx7PvwpWTOyll4kFNnbs7moVDbWXAY71N3Sjhfvhbi+3XWPlGDWFEEcd8WysFuABSqYLpJOTYRDxYi8pChZrokIaGGdooYGrAmPIytDGv9/c0xs0Z/5EUuqlpuWcUL94M3C8eLY6Z0hnPel5A/FFt540zhA= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-14-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=7542; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=Aoh+DU0o/8uqBdQ/QrPxSrr1YhdUqc9obDkxu9/ggr4=; b=0kJxaVCr1q8zhFgNvS0ov6aq00MS7/rXlS5+OelqDE+Q4CZQ4ACGHIQ3JXklE4WGiN8OX2FiH TJu0KzfKITJBV9DRc9RAd6HdPgUFXMGCyHmiOf++JZuBDqk+8Mcs23O X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli There is no need to reinvent the PHY framework, especially not its OF parsing. Change the code to simply use the PHY framework to acquire the device's PHY in the ufshcd init, so that it's device linked to the right device. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Reviewed-by: Chaotian Jing Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 134 +++++++++++++-----------------------= ---- drivers/ufs/host/ufs-mediatek.h | 1 - 2 files changed, 42 insertions(+), 93 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 3c10a9fd09df..538009e3b1f1 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -296,44 +296,6 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *h= ba, return 0; } =20 -static int ufs_mtk_bind_mphy(struct ufs_hba *hba) -{ - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - struct device *dev =3D hba->dev; - struct device_node *np =3D dev->of_node; - int err =3D 0; - - host->mphy =3D devm_of_phy_get_by_index(dev, np, 0); - - if (host->mphy =3D=3D ERR_PTR(-EPROBE_DEFER)) { - /* - * UFS driver might be probed before the phy driver does. - * In that case we would like to return EPROBE_DEFER code. - */ - err =3D -EPROBE_DEFER; - dev_info(dev, - "%s: required phy hasn't probed yet. err =3D %d\n", - __func__, err); - } else if (IS_ERR(host->mphy)) { - err =3D PTR_ERR(host->mphy); - if (err !=3D -ENODEV) { - dev_info(dev, "%s: PHY get failed %d\n", __func__, - err); - } - } - - if (err) - host->mphy =3D NULL; - /* - * Allow unbound mphy because not every platform needs specific - * mphy control. - */ - if (err =3D=3D -ENODEV) - err =3D 0; - - return err; -} - static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -1234,13 +1196,21 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_init_mcq_irq(hba); =20 - err =3D ufs_mtk_bind_mphy(hba); - if (err) + host->mphy =3D devm_phy_optional_get(dev, NULL); + if (IS_ERR(host->mphy)) { + err =3D dev_err_probe(dev, PTR_ERR(host->mphy), "Failed to get PHY\n"); + goto out_variant_clear; + } + + err =3D phy_init(host->mphy); + if (err) { + dev_err_probe(dev, err, "Failed to initialize PHY\n"); goto out_variant_clear; + } =20 err =3D ufs_mtk_init_reset(hba); if (err) - goto out_variant_clear; + goto out_phy_exit; =20 /* Enable runtime autosuspend */ hba->caps |=3D UFSHCD_CAP_RPM_AUTOSUSPEND; @@ -1279,7 +1249,7 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 err =3D ufs_mtk_get_supplies(host); if (err) - goto out_variant_clear; + goto out_phy_exit; =20 /* * ufshcd_vops_init() is invoked after @@ -1304,11 +1274,22 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 return 0; =20 +out_phy_exit: + phy_exit(host->mphy); out_variant_clear: ufshcd_set_variant(hba, NULL); return err; } =20 +static void ufs_mtk_exit(struct ufs_hba *hba) +{ + struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); + + ufs_mtk_mphy_power_on(hba, false); + + phy_exit(host->mphy); +} + static int ufs_mtk_negotiate_pwr_mode(struct ufs_hba *hba, const struct ufs_pa_layer_attr *dev_max_params, struct ufs_pa_layer_attr *dev_req_params) @@ -2321,6 +2302,7 @@ static void ufs_mtk_config_scsi_dev(struct scsi_devic= e *sdev) static const struct ufs_hba_variant_ops ufs_hba_mtk_vops =3D { .name =3D "mediatek.ufshci", .init =3D ufs_mtk_init, + .exit =3D ufs_mtk_exit, .get_ufs_hci_version =3D ufs_mtk_get_ufs_hci_version, .setup_clocks =3D ufs_mtk_setup_clocks, .hce_enable_notify =3D ufs_mtk_hce_enable_notify, @@ -2381,48 +2363,15 @@ MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); */ static int ufs_mtk_probe(struct platform_device *pdev) { - int err; + struct device *dev =3D &pdev->dev; struct ufs_hba *hba; - struct platform_device *phy_pdev =3D NULL; - struct device *dev =3D &pdev->dev, *phy_dev =3D NULL; - struct device_node *phy_node =3D NULL; - struct ufs_mtk_host *host; - - /* find phy node */ - phy_node =3D of_parse_phandle(dev->of_node, "phys", 0); - - if (phy_node) { - phy_pdev =3D of_find_device_by_node(phy_node); - if (!phy_pdev) - goto skip_phy; - phy_dev =3D &phy_pdev->dev; - - pm_runtime_set_active(phy_dev); - pm_runtime_enable(phy_dev); - pm_runtime_get_sync(phy_dev); - - put_device(phy_dev); - dev_info(dev, "phys node found\n"); - } else { - dev_notice(dev, "phys node not found\n"); - } + int ret; =20 -skip_phy: - /* perform generic probe */ - err =3D ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops); - if (err) { - dev_err(dev, "probe failed %d\n", err); - goto out; - } + ret =3D ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops); + if (ret) + return dev_err_probe(dev, ret, "Generic platform probe failed\n"); =20 hba =3D platform_get_drvdata(pdev); - if (!hba) - goto out; - - if (phy_node && phy_dev) { - host =3D ufshcd_get_variant(hba); - host->phy_dev =3D phy_dev; - } =20 /* * Because the default power setting of VSx (the upper layer of @@ -2431,16 +2380,12 @@ static int ufs_mtk_probe(struct platform_device *pd= ev) */ ufs_mtk_dev_vreg_set_lpm(hba, false); =20 -out: - of_node_put(phy_node); - return err; + return 0; } =20 /** * ufs_mtk_remove - set driver_data of the device to NULL * @pdev: pointer to platform device handle - * - * Always return 0 */ static void ufs_mtk_remove(struct platform_device *pdev) { @@ -2497,9 +2442,8 @@ static int ufs_mtk_system_resume(struct device *dev) static int ufs_mtk_runtime_suspend(struct device *dev) { struct ufs_hba *hba =3D dev_get_drvdata(dev); - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct arm_smccc_res res; - int ret =3D 0; + int ret; =20 ret =3D ufshcd_runtime_suspend(dev); if (ret) @@ -2510,8 +2454,11 @@ static int ufs_mtk_runtime_suspend(struct device *de= v) if (ufs_mtk_is_rtff_mtcmos(hba)) ufs_mtk_mtcmos_ctrl(false, res); =20 - if (host->phy_dev) - pm_runtime_put_sync(host->phy_dev); + ret =3D ufs_mtk_mphy_power_on(hba, false); + if (ret) { + dev_err(dev, "Failed to power off PHY: %pe\n", ERR_PTR(ret)); + return ret; + } =20 return 0; } @@ -2519,14 +2466,17 @@ static int ufs_mtk_runtime_suspend(struct device *d= ev) static int ufs_mtk_runtime_resume(struct device *dev) { struct ufs_hba *hba =3D dev_get_drvdata(dev); - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct arm_smccc_res res; + int ret; =20 if (ufs_mtk_is_rtff_mtcmos(hba)) ufs_mtk_mtcmos_ctrl(true, res); =20 - if (host->phy_dev) - pm_runtime_get_sync(host->phy_dev); + ret =3D ufs_mtk_mphy_power_on(hba, true); + if (ret) { + dev_err(dev, "Failed to power on PHY: %pe\n", ERR_PTR(ret)); + return ret; + } =20 ufs_mtk_dev_vreg_set_lpm(hba, false); =20 diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 477fb9e36555..bde2b53f5798 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -196,7 +196,6 @@ struct ufs_mtk_host { bool is_mcq_intr_enabled; int mcq_nr_intr; struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR]; - struct device *phy_dev; }; =20 /* MTK delay of autosuspend: 500 ms */ --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 611E343F8C8; Mon, 14 Sep 2026 11:39:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385979; cv=none; b=pDibWK9v+1CQEoYqDSJ4kjk6Jt8cnoY5sSdXtslzTwwqae9kaCgexsFsT0ty8/8ULM1Q34xu2OchMyLKfBgF1pFBewXU5k25ekxuzsEY9I9cOK5h1BdBCo9FHX3tCACNKntq0i/Mv8KYJYGFOfaZnqzH276kz+05dwO//RZe5tw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385979; c=relaxed/simple; bh=TLJfFKrGCdAfrDs7f3DD9z/JDqxUYjNdYN2HUNY8vUs=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-15-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=2134; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=PczjgMmcaKTNxA6z4LyX4a1OHzDCTGb37OFBfGxdudc=; b=wihNWHGsJTNgE6M7CPfE1dJeaNiBjVAIRYNZKItQBKWM7zCmPuLPcrtlSSNNit3uGjYuuWEgZ kj/MTgNpGS0BFtxHFhTenTHsuse+Uy0eQdKBTVb7IPMS7j94YUtkKhR X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli This flag property was never described in the binding, and its capability wrapper seems pointless. If one of the MediaTek SoCs needs the ufshcd quirk applied, then this can be done per-compatible, without needing to give the device tree author the option to forget to set it. Remove it and the associated capability flag wrapping code. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 5 ----- drivers/ufs/host/ufs-mediatek.h | 2 -- 2 files changed, 7 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 538009e3b1f1..8e2aeb877de8 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -691,9 +691,6 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba) if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos")) host->caps |=3D UFS_MTK_CAP_RTFF_MTCMOS; =20 - if (of_property_read_bool(np, "mediatek,ufs-broken-rtc")) - host->caps |=3D UFS_MTK_CAP_MCQ_BROKEN_RTC; - dev_info(hba->dev, "caps: 0x%x", host->caps); } =20 @@ -1234,8 +1231,6 @@ static int ufs_mtk_init(struct ufs_hba *hba) hba->quirks |=3D UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL; =20 hba->quirks |=3D UFSHCD_QUIRK_MCQ_BROKEN_INTR; - if (host->caps & UFS_MTK_CAP_MCQ_BROKEN_RTC) - hba->quirks |=3D UFSHCD_QUIRK_MCQ_BROKEN_RTC; =20 hba->vps->wb_flush_threshold =3D UFS_WB_BUF_REMAIN_PERCENT(80); =20 diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index bde2b53f5798..d97951ee1f4e 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -138,8 +138,6 @@ enum ufs_mtk_host_caps { UFS_MTK_CAP_DISABLE_MCQ =3D 1 << 8, /* Control MTCMOS with RTFF */ UFS_MTK_CAP_RTFF_MTCMOS =3D 1 << 9, - - UFS_MTK_CAP_MCQ_BROKEN_RTC =3D 1 << 10, }; =20 struct ufs_mtk_crypt_cfg { --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C4B74534BB; Mon, 14 Sep 2026 11:39:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385981; 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Mon, 14 Sep 2026 13:39:36 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:39:02 +0200 Subject: [PATCH v12 16/24] scsi: ufs: mediatek: Rework _ufs_mtk_clk_scale error paths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-16-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=3592; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=jvXLQZATgiXLw4Qin4439gnZ2vmPjomfUnBWrKcXcBE=; b=SfJeFwUBhKN17xmpJaqOdw4lnRjQZtyrWnmsGo5x7GC/7cXlZ5XE/hQO5r2VVDA1eHlsUUtME fphnoWv3Ov3DiEYMGfGquhcUFPrNKGaQdMZM1RmSsRPx/va71t/vJPs X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli Errors should be printed at the correct log level. Additionally, it looks like some "goto out"'s were omitted in the scale up case, which looks like a mistake, as the scale down branch of the code does use them. Rework the error messages to make them nicer and at the correct verbosity, and add the missing gotos. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 41 +++++++++++++++++++------------------= ---- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 8e2aeb877de8..b5b13444d27c 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -2020,16 +2020,16 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba,= bool scale_up) =20 ret =3D clk_prepare_enable(clki->clk); if (ret) { - dev_info(hba->dev, - "clk_prepare_enable() fail, ret: %d\n", ret); + dev_err(hba->dev, "%s: Failed to enable clock: %pe\n", __func__, ERR_PTR= (ret)); return; } =20 if (clk_fde_scale) { ret =3D clk_prepare_enable(fde_clki->clk); if (ret) { - dev_info(hba->dev, - "fde clk_prepare_enable() fail, ret: %d\n", ret); + dev_err(hba->dev, "%s: Failed to enable FDE clock: %pe\n", + __func__, ERR_PTR(ret)); + clk_disable_unprepare(clki->clk); return; } } @@ -2038,51 +2038,48 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba,= bool scale_up) if (clk_bind_vcore) { ret =3D regulator_set_voltage(reg, volt, INT_MAX); if (ret) { - dev_info(hba->dev, - "Failed to set vcore to %d\n", volt); + dev_err(hba->dev, "Failed to set vcore to %d\n", volt); goto out; } } =20 ret =3D clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk); if (ret) { - dev_info(hba->dev, "Failed to set clk mux, ret =3D %d\n", - ret); + dev_err(hba->dev, "%s: Failed to set clock mux: %pe\n", + __func__, ERR_PTR(ret)); + goto out; } =20 if (clk_fde_scale) { - ret =3D clk_set_parent(fde_clki->clk, - mclk->ufs_fde_max_clki->clk); + ret =3D clk_set_parent(fde_clki->clk, mclk->ufs_fde_max_clki->clk); if (ret) { - dev_info(hba->dev, - "Failed to set fde clk mux, ret =3D %d\n", - ret); + dev_err(hba->dev, "%s: Failed to set fde clock mux: %pe\n", + __func__, ERR_PTR(ret)); + goto out; } } } else { if (clk_fde_scale) { - ret =3D clk_set_parent(fde_clki->clk, - mclk->ufs_fde_min_clki->clk); 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Mon, 14 Sep 2026 13:39:37 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:39:03 +0200 Subject: [PATCH v12 17/24] scsi: ufs: mediatek: Clean up logging prints Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-17-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=9087; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=R6XUOtG+l9NxcAXb3eovE3XVvWX+L0RUpzqqexuypMY=; b=Krw9v05vCvVB66qrQF2rEGUxVx3NiaWjitiMvEtHJwZcHaeVz2gcWaLn3EXD9sPMA3kuSELre FdCj/P1UlauDEAFecBLuqo6msjO5EMGIkCpKg7tL9m3srDpi4HZaxmt X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli The Linux kernel's log buffer provides many levels of verbosity, associated with different semantic meanings. Care should be taken to only log useful information to the info level, and log errors to the error level. The MediaTek UFS driver does not do this. It freely logs verbose debug information to the info level, errors to the info level, and sometimes errors to the warning level. Adjust all the wrapped kprintf invocations to rectify this situation. Use user-friendly %pe format codes for printing errors where possible. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 92 ++++++++++++++++++-------------------= ---- 1 file changed, 41 insertions(+), 51 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index b5b13444d27c..071e81357537 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #include #include "ufshcd-pltfrm.h" @@ -194,8 +195,8 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba) =20 ufs_mtk_crypto_ctrl(res, 1); if (res.a0) { - dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n", - __func__, res.a0); + dev_err(hba->dev, "%s: crypto enable failed with error %lu, disabling\n", + __func__, res.a0); hba->caps &=3D ~UFSHCD_CAP_CRYPTO; } } @@ -576,40 +577,38 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, = bool boost) =20 ret =3D clk_prepare_enable(cfg->clk_crypt_mux); if (ret) { - dev_info(hba->dev, "clk_prepare_enable(): %d\n", - ret); + dev_err(hba->dev, "%s: Failed to enable clk_crypt_mux: %pe\n", + __func__, ERR_PTR(ret)); return; } =20 if (boost) { ret =3D regulator_set_voltage(reg, volt, INT_MAX); if (ret) { - dev_info(hba->dev, - "failed to set vcore to %d\n", volt); + dev_err(hba->dev, "%s: Failed to set vcore to %d: %pe\n", + __func__, volt, ERR_PTR(ret)); goto out; } =20 - ret =3D clk_set_parent(cfg->clk_crypt_mux, - cfg->clk_crypt_perf); + ret =3D clk_set_parent(cfg->clk_crypt_mux, cfg->clk_crypt_perf); if (ret) { - dev_info(hba->dev, - "failed to set clk_crypt_perf\n"); + dev_err(hba->dev, "%s: Failed to reparent clk_crypt_perf: %pe\n", + __func__, ERR_PTR(ret)); regulator_set_voltage(reg, 0, INT_MAX); goto out; } } else { - ret =3D clk_set_parent(cfg->clk_crypt_mux, - cfg->clk_crypt_lp); + ret =3D clk_set_parent(cfg->clk_crypt_mux, cfg->clk_crypt_lp); if (ret) { - dev_info(hba->dev, - "failed to set clk_crypt_lp\n"); + dev_err(hba->dev, "%s: Failed to reparent clk_crypt_lp: %pe\n", + __func__, ERR_PTR(ret)); goto out; } =20 ret =3D regulator_set_voltage(reg, 0, INT_MAX); if (ret) { - dev_info(hba->dev, - "failed to set vcore to MIN\n"); + dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", + __func__, ERR_PTR(ret)); } } out: @@ -799,10 +798,8 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, b= ool on, if (clk_pwr_off) { ufs_mtk_pwr_ctrl(hba, false); } else { - dev_warn(hba->dev, "Clock is not turned off, hba->ahit =3D 0x%x, AHIT = =3D 0x%x\n", - hba->ahit, - ufshcd_readl(hba, - REG_AUTO_HIBERNATE_IDLE_TIMER)); + dev_warn(hba->dev, "Clock isn't off, hba->ahit =3D 0x%x, AHIT =3D 0x%x\= n", + hba->ahit, ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER)); } ufs_mtk_mcq_disable_irq(hba); } else if (on && status =3D=3D POST_CHANGE) { @@ -846,11 +843,11 @@ static void ufs_mtk_mcq_set_irq_affinity(struct ufs_h= ba *hba, unsigned int cpu) _cpu =3D (cpu =3D=3D 0) ? 3 : cpu; ret =3D irq_set_affinity(irq, cpumask_of(_cpu)); if (ret) { - dev_err(hba->dev, "set irq %d affinity to CPU %d failed\n", + dev_err(hba->dev, "setting irq %d affinity to CPU %d failed\n", irq, _cpu); return; } - dev_info(hba->dev, "set irq %d affinity to CPU: %d\n", irq, _cpu); + dev_dbg(hba->dev, "set irq %d affinity to CPU %d\n", irq, _cpu); } =20 static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver) @@ -866,7 +863,8 @@ static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *h= ba, u32 hw_ip_ver) default: break; } - dev_info(hba->dev, "legacy IP version - 0x%x, is legacy : %d", hw_ip_ver,= is_legacy); + dev_dbg(hba->dev, "IP version 0x%x, legacy =3D %s", hw_ip_ver, + str_true_false(is_legacy)); =20 return is_legacy; } @@ -971,15 +969,12 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) } } =20 - list_for_each_entry(clki, head, list) { - dev_info(hba->dev, "clk \"%s\" present", clki->name); - } + list_for_each_entry(clki, head, list) + dev_dbg(hba->dev, "clk \"%s\" present", clki->name); =20 if (!ufs_mtk_is_clk_scale_ready(hba)) { hba->caps &=3D ~UFSHCD_CAP_CLK_SCALING; - dev_info(hba->dev, - "%s: Clk-scaling not ready. Feature disabled.", - __func__); + dev_info(hba->dev, "%s: Clock scaling unavailable", __func__); return; } =20 @@ -989,8 +984,8 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) */ reg =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); if (IS_ERR(reg)) { - dev_info(dev, "failed to get dvfsrc-vcore: %ld", - PTR_ERR(reg)); + if (PTR_ERR(reg) !=3D -ENODEV) + dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", reg); return; } =20 @@ -1004,12 +999,9 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) host->mclk.vcore_volt =3D volt; =20 /* If default boot is max gear, request vcore */ - if (reg && volt && host->clk_scale_up) { - if (regulator_set_voltage(reg, volt, INT_MAX)) { - dev_info(hba->dev, - "Failed to set vcore to %d\n", volt); - } - } + if (reg && volt && host->clk_scale_up) + if (regulator_set_voltage(reg, volt, INT_MAX)) + dev_err(hba->dev, "Failed to set vcore to %d\n", volt); } =20 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) @@ -1096,7 +1088,7 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba) } host->mcq_intr_info[i].hba =3D hba; host->mcq_intr_info[i].irq =3D irq; - dev_info(hba->dev, "get platform mcq irq: %d, %d\n", i, irq); + dev_dbg(hba->dev, "get platform mcq irq: %d, %d\n", i, irq); } =20 return; @@ -1406,10 +1398,9 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hb= a, ret =3D ufshcd_uic_change_pwr_mode(hba, FASTAUTO_MODE << 4 | FASTAUTO_MODE); =20 - if (ret) { - dev_err(hba->dev, "%s: HSG1B FASTAUTO failed ret=3D%d\n", - __func__, ret); - } + if (ret) + dev_err(hba->dev, "%s: HSG1B FASTAUTO failed: %pe\n", + __func__, ERR_PTR(ret)); } =20 /* if already configured to the requested pwr_mode, skip adapt */ @@ -1459,7 +1450,7 @@ static int ufs_mtk_auto_hibern8_disable(struct ufs_hb= a *hba) =20 out: if (ret) { - dev_warn(hba->dev, "exit h8 state fail, ret=3D%d\n", ret); + dev_err(hba->dev, "Failed to exit h8 state: %pe\n", ERR_PTR(ret)); =20 ufshcd_force_error_recovery(hba); =20 @@ -1655,12 +1646,12 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba) /* Check link state to make sure exit h8 success */ err =3D ufs_mtk_wait_idle_state(hba, 5); if (err) { - dev_warn(hba->dev, "wait idle fail, err=3D%d\n", err); + dev_err(hba->dev, "Failed to wait for idle: %pe\n", ERR_PTR(err)); return err; } err =3D ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100); if (err) { - dev_warn(hba->dev, "exit h8 state fail, err=3D%d\n", err); + dev_err(hba->dev, "Failed to wait for link to be up: %pe\n", ERR_PTR(err= )); return err; } ufshcd_set_link_active(hba); @@ -1964,20 +1955,19 @@ static void ufs_mtk_event_notify(struct ufs_hba *hb= a, =20 /* Print details of UIC Errors */ if (evt <=3D UFS_EVT_DME_ERR) { - dev_info(hba->dev, - "Host UIC Error Code (%s): %08x\n", - ufs_uic_err_str[evt], val); + dev_err(hba->dev, "Host UIC Error Code (%s): %08x\n", + ufs_uic_err_str[evt], val); reg =3D val; } =20 if (evt =3D=3D UFS_EVT_PA_ERR) { for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_pa_err_str)) - dev_info(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]); + dev_err(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]); } =20 if (evt =3D=3D UFS_EVT_DL_ERR) { for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_dl_err_str)) - dev_info(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]); + dev_err(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]); } } =20 @@ -2192,7 +2182,7 @@ static int ufs_mtk_mcq_config_resource(struct ufs_hba= *hba) =20 /* fail mcq initialization if interrupt is not filled properly */ if (!host->mcq_nr_intr) { - dev_info(hba->dev, "IRQs not ready. MCQ disabled."); + dev_err(hba->dev, "IRQs not ready. MCQ disabled."); return -EINVAL; } =20 --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F3184457AF; Mon, 14 Sep 2026 11:39:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385985; cv=none; b=HC5WusAnKXNDJgvnuYciuuTxFJ8jlzJ7NpB4FacpZZ25iqTSva7L41MerBcXcMqwTKQub60BR9es5N+Ww/iQukxcTDblQC0EJW42UO/9asBxoNmEfB+UWr7bc0DzeDzC9Y6y+ForhNyg8eUVZ/OvGqyUl8VagxW1n/8xBcGCIH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385985; c=relaxed/simple; bh=CDdzCMsyY0hbLRq251sYGR1yW3tb8Oi9E3rqzOxvS3A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fyJ981EG8etYDbNTVnu8OBujPy5nVFaCrh71KnjVL5eEeklzeGm0xdZ618F9cHeuHn6XoEf6U2ifofVw7yBqjtrBkZKaHhMj4bWtbr6gy/F6wnsBpdAQl65B9XKlZjbho1qaAVZ1p3DAu1gj7z8JKphjdeD3Klx837Y6+WIz0ZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=aMF6nVju; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="aMF6nVju" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789385981; bh=CDdzCMsyY0hbLRq251sYGR1yW3tb8Oi9E3rqzOxvS3A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=aMF6nVjuU0ISblQWTRlfacD+rzFKC8bU7/9oJCxH+XRO8/q3hMM5Vt+pz+QVn1M4K vZl6SdX4XjaGAKLy28QAXuxrlLpzVSq8/7P2Tr8bAd2lGlYQWlU5HP4dVassEGmEVQ CFu5tyjzUMvOd5oXiAciaPO6MCsHWFz+Fe2iZWYr/uszAsjoDur1qPsGTZxnnWIXQF fusYLo2xpeHH7J854WO/kVMgVHucvI3TCxSJx/eIwHz6jdtQeok9c6xOIXGQWeOUVZ kyHXz0ZHKFyO4aBGVbF5mAuT4nVLyBOsSRnqYcW8FO+50fLZdayed6k9Zu0y3qVsYa g+Si73EzsOELw== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 0F33717E07DC; Mon, 14 Sep 2026 13:39:40 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:39:04 +0200 Subject: [PATCH v12 18/24] scsi: ufs: mediatek: Rework ufs_mtk_wait_idle_state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-18-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=4343; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=ynxLXnChHF4gNItLESWr8U8gDqusMdmhPDTxRufgRJ4=; b=+ytchkoDIpFr422hk3zKxa2FvMRiLRXCzeAOig0GtFRhfBOG2aE40JA4b9ido2MiboboTF1V2 /8fW+NqrnQUAwd31zCiPX0kk1jJaVJ9ZopRKXJcucRcqMB+Fonhr1qC X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli While ufs_mtk_wait_idle state has some code smells for me (the VS_HCE_BASE early exit seems racey at best), it can still benefit from some general cleanup to make the code flow less convoluted. Use the iopoll helpers, for one, and specifically the one that sleeps and does not busy delay, as it's being done for up to 5ms. The register read is split out to a helper function that branches between new and old style flow. Every called uses the same 5ms timeout value, so there is no point in making this a parameter. Just assume a 5ms timeout in the function. Reviewed-by: Peter Wang Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 71 +++++++++++++++++--------------------= ---- 1 file changed, 30 insertions(+), 41 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 071e81357537..4a8f13e67f3f 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -384,51 +385,39 @@ static void ufs_mtk_dbg_sel(struct ufs_hba *hba) } } =20 -static int ufs_mtk_wait_idle_state(struct ufs_hba *hba, - unsigned long retry_ms) +static u32 ufs_mtk_read_state(struct ufs_hba *hba, bool old_style) { - u64 timeout, time_checked; - u32 val, sm; - bool wait_idle; - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - - /* cannot use plain ktime_get() in suspend */ - timeout =3D ktime_get_mono_fast_ns() + retry_ms * 1000000UL; - - /* wait a specific time after check base */ - udelay(10); - wait_idle =3D false; + u32 val; =20 - do { - time_checked =3D ktime_get_mono_fast_ns(); - if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) { - ufs_mtk_dbg_sel(hba); - val =3D ufshcd_readl(hba, REG_UFS_PROBE); - } else { - val =3D ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL); - val =3D val >> 16; - } + if (old_style) { + ufs_mtk_dbg_sel(hba); + val =3D ufshcd_readl(hba, REG_UFS_PROBE); + } else { + val =3D ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL) >> 16; + } =20 - sm =3D val & 0x1f; + return FIELD_GET(0x1f, val); +} =20 - /* - * if state is in H8 enter and H8 enter confirm - * wait until return to idle state. - */ - if ((sm >=3D VS_HIB_ENTER) && (sm <=3D VS_HIB_EXIT)) { - wait_idle =3D true; - udelay(50); - continue; - } else if (!wait_idle) - break; +static int ufs_mtk_wait_idle_state(struct ufs_hba *hba) +{ + struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); + bool old_style =3D (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899); + u32 val; + int ret; =20 - if (wait_idle && (sm =3D=3D VS_HCE_BASE)) - break; - } while (time_checked < timeout); + /* If the device isn't in a hibernate state after 10us, don't wait. */ + udelay(10); + val =3D ufs_mtk_read_state(hba, old_style); + if (val < VS_HIB_ENTER || val > VS_HIB_EXIT) + return 0; =20 - if (wait_idle && sm !=3D VS_HCE_BASE) { - dev_info(hba->dev, "wait idle tmo: 0x%x\n", val); - return -ETIMEDOUT; + /* Poll to wait for idle */ + ret =3D read_poll_timeout(ufs_mtk_read_state, val, (val =3D=3D VS_HCE_BAS= E), + 50, 5 * USEC_PER_MSEC, false, hba, old_style); + if (ret) { + dev_err(hba->dev, "Timed out waiting for idle state, val =3D 0x%x\n", va= l); + return ret; } =20 return 0; @@ -1442,7 +1431,7 @@ static int ufs_mtk_auto_hibern8_disable(struct ufs_hb= a *hba) ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER); =20 /* wait host return to idle state when auto-hibern8 off */ - ret =3D ufs_mtk_wait_idle_state(hba, 5); + ret =3D ufs_mtk_wait_idle_state(hba); if (ret) goto out; =20 @@ -1644,7 +1633,7 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba) return err; =20 /* Check link state to make sure exit h8 success */ - err =3D ufs_mtk_wait_idle_state(hba, 5); + err =3D ufs_mtk_wait_idle_state(hba); if (err) { dev_err(hba->dev, "Failed to wait for idle: %pe\n", ERR_PTR(err)); return err; --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81FE8456DFD; Mon, 14 Sep 2026 11:39:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385987; cv=none; b=TFwpdWpYn3nZCS737CWi6xuzdtr+ahbRNiIQbmMX95r/JFpSdZONL/01wbQdG7j9Sjw6hk/tv8kVjf13Ge76WUj10dzQudVZXDygxY6WiH0C8YEDxHhTfPIB8hvVjxXVBu1NuVK2X12tqE/89J9z2LvrO10W7OF91EsTk6JqUkA= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-19-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=7843; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=u5hsoUo2apmHj49YkhJ3H2LGdAnXHoKSFcuZGmRNLzk=; b=/4aRhR89n1PvGTjjQKKlw68pDQa29Jb8NDRCuQUjG/zKG9fRvPZZUCfH6BFKg7aNhy17xt8rh WUjhgZpiHrtAO3UggGXVLBlc3SqyXI6dKPcBRbQp+Q/McDqyeFtU/+d X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli As part of its featureset, the ufs-mediatek driver needs to play with an optional dvfsrc-vcore regulator for some of them. However, it currently does this by acquiring two different references to it in two different places, needlessly duplicating logic. Move reg_vcore to the host struct, acquire it in the same function as avdd09 is acquired, and rework the users of reg_vcore. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 60 +++++++++++++++++++------------------= ---- drivers/ufs/host/ufs-mediatek.h | 3 +-- 2 files changed, 28 insertions(+), 35 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 4a8f13e67f3f..b599e9f4624e 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -554,7 +554,6 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct ufs_mtk_crypt_cfg *cfg; - struct regulator *reg; int volt, ret; =20 if (!ufs_mtk_is_boost_crypt_enabled(hba)) @@ -562,7 +561,6 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) =20 cfg =3D host->crypt; volt =3D cfg->vcore_volt; - reg =3D cfg->reg_vcore; =20 ret =3D clk_prepare_enable(cfg->clk_crypt_mux); if (ret) { @@ -572,7 +570,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) } =20 if (boost) { - ret =3D regulator_set_voltage(reg, volt, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, volt, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to %d: %pe\n", __func__, volt, ERR_PTR(ret)); @@ -583,7 +581,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) if (ret) { dev_err(hba->dev, "%s: Failed to reparent clk_crypt_perf: %pe\n", __func__, ERR_PTR(ret)); - regulator_set_voltage(reg, 0, INT_MAX); + regulator_set_voltage(host->reg_vcore, 0, INT_MAX); goto out; } } else { @@ -594,7 +592,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) goto out; } =20 - ret =3D regulator_set_voltage(reg, 0, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, 0, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", __func__, ERR_PTR(ret)); @@ -612,15 +610,12 @@ static void ufs_mtk_init_boost_crypt(struct ufs_hba *= hba) u32 volt; int ret; =20 - cfg =3D devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL); - if (!cfg) + if (!host->reg_vcore) return; =20 - cfg->reg_vcore =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); - if (IS_ERR(cfg->reg_vcore)) { - dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", cfg->reg_vcore); + cfg =3D devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL); + if (!cfg) return; - } =20 ret =3D of_property_read_u32(dev->of_node, "mediatek,boost-crypt-vcore-mi= n", &volt); @@ -926,7 +921,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) struct list_head *head =3D &hba->clk_list_head; struct ufs_clk_info *clki, *clki_tmp; struct device *dev =3D hba->dev; - struct regulator *reg; u32 volt; =20 /* @@ -967,16 +961,8 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) return; } =20 - /* - * Default get vcore if dts have these settings. - * No matter clock scaling support or not. (may disable by customer) - */ - reg =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); - if (IS_ERR(reg)) { - if (PTR_ERR(reg) !=3D -ENODEV) - dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", reg); + if (!host->reg_vcore) return; - } =20 if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min", &volt)) { @@ -984,12 +970,11 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) return; } =20 - host->mclk.reg_vcore =3D reg; host->mclk.vcore_volt =3D volt; =20 /* If default boot is max gear, request vcore */ - if (reg && volt && host->clk_scale_up) - if (regulator_set_voltage(reg, volt, INT_MAX)) + if (volt && host->clk_scale_up) + if (regulator_set_voltage(host->reg_vcore, volt, INT_MAX)) dev_err(hba->dev, "Failed to set vcore to %d\n", volt); } =20 @@ -1101,6 +1086,17 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host = *host) const struct ufs_mtk_soc_data *data =3D of_device_get_match_data(dev); int ret; =20 + host->reg_vcore =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); + if (IS_ERR(host->reg_vcore)) { + if (PTR_ERR(host->reg_vcore) !=3D -ENODEV) { + dev_err(dev, "Failed to get dvfsrc-vcore supply: %pe\n", + host->reg_vcore); + return PTR_ERR(host->reg_vcore); + } + + host->reg_vcore =3D NULL; + } + if (!data) return 0; =20 @@ -1169,6 +1165,10 @@ static int ufs_mtk_init(struct ufs_hba *hba) host->hba =3D hba; ufshcd_set_variant(hba, host); =20 + err =3D ufs_mtk_get_supplies(host); + if (err) + goto out_variant_clear; + /* Initialize host capability */ ufs_mtk_init_host_caps(hba); =20 @@ -1223,10 +1223,6 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_init_clocks(hba); =20 - err =3D ufs_mtk_get_supplies(host); - if (err) - goto out_phy_exit; - /* * ufshcd_vops_init() is invoked after * ufshcd_setup_clock(true) in ufshcd_hba_init() thus @@ -1978,7 +1974,6 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) struct ufs_mtk_clk *mclk =3D &host->mclk; struct ufs_clk_info *clki =3D mclk->ufs_sel_clki; struct ufs_clk_info *fde_clki =3D mclk->ufs_fde_clki; - struct regulator *reg; int volt, ret =3D 0; bool clk_bind_vcore =3D false; bool clk_fde_scale =3D false; @@ -1989,9 +1984,8 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) if (!clki || !fde_clki) return; =20 - reg =3D host->mclk.reg_vcore; volt =3D host->mclk.vcore_volt; - if (reg && volt !=3D 0) + if (host->reg_vcore && volt) clk_bind_vcore =3D true; =20 if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki) @@ -2015,7 +2009,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) =20 if (scale_up) { if (clk_bind_vcore) { - ret =3D regulator_set_voltage(reg, volt, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, volt, INT_MAX); if (ret) { dev_err(hba->dev, "Failed to set vcore to %d\n", volt); goto out; @@ -2055,7 +2049,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) } =20 if (clk_bind_vcore) { - ret =3D regulator_set_voltage(reg, 0, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, 0, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", __func__, ERR_PTR(ret)); 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Mon, 14 Sep 2026 13:39:44 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:39:06 +0200 Subject: [PATCH v12 20/24] scsi: ufs: mediatek: Rework hardware version reading Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-20-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=4038; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=iMniswtHRkz52bS2IOsc2MukEzn1RAz2enUpB9VPkFo=; b=WeTrExNXCU6X8wnMjfVyVt21WlHM2Pj18MpkRDmXLGyNGcHPFpmlMeXStjWkC4oNZTFg6lwms huKGQ5wx383CI7e/oaYw6Ne+ivqL8D4ACzQ12NQOX4KWA63LpX412Zm X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli Split assignment to the host struct out from the read function, and utilise bitfield helpers to simplify the code. Also move the debug print out of the legacy version helper, which means it no longer has to take a struct ufs_hba as an input, and can be rewritten as a pure function. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 65 +++++++++++++++++++++----------------= ---- 1 file changed, 33 insertions(+), 32 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index b599e9f4624e..fc42e6baa47d 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -834,50 +834,47 @@ static void ufs_mtk_mcq_set_irq_affinity(struct ufs_h= ba *hba, unsigned int cpu) dev_dbg(hba->dev, "set irq %d affinity to CPU %d\n", irq, _cpu); } =20 -static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver) +static bool __pure ufs_mtk_is_legacy_chipset(u32 hw_ip_ver) { - bool is_legacy =3D false; - switch (hw_ip_ver) { case IP_LEGACY_VER_MT6893: case IP_LEGACY_VER_MT6781: /* can add other legacy chipset ID here accordingly */ - is_legacy =3D true; - break; - default: - break; + return true; } - dev_dbg(hba->dev, "IP version 0x%x, legacy =3D %s", hw_ip_ver, - str_true_false(is_legacy)); =20 - return is_legacy; + return false; } =20 -/* - * HW version format has been changed from 01MMmmmm to 1MMMmmmm, since - * project MT6878. In order to perform correct version comparison, - * version number is changed by SW for the following projects. - * IP_VER_MT6983 0x00360000 to 0x10360000 - * IP_VER_MT6897 0x01440000 to 0x10440000 - * IP_VER_MT6989 0x01450000 to 0x10450000 - * IP_VER_MT6991 0x01460000 to 0x10460000 +#define MTK_UFS_VER_PREFIX_M GENMASK(31, 24) + +/** + * ufs_mtk_get_hw_ip_version - read and return adjusted hardware version + * @hba: pointer to this device's &struct ufs_hba + * + * Reads, transforms and returns the hardware version. + * + * Since MT6878, the versioning scheme was changed from 01MMmmmm to 1MMMmm= mm. + * In order to support version comparisons across these different versioni= ng + * schemes, this function transforms the older style to the newer one. + * + * For example: + * MT6983 is transformed from 0x00360000 to 0x10360000 + * MT6897 is transformed from 0x01440000 to 0x10440000 + * MT6989 is transformed from 0x01450000 to 0x10450000 + * MT6991 is transformed from 0x01460000 to 0x10460000 + * + * Returns a u32 representing the hardware version. */ -static void ufs_mtk_get_hw_ip_version(struct ufs_hba *hba) +static u32 ufs_mtk_get_hw_ip_version(struct ufs_hba *hba) { - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - u32 hw_ip_ver; + u32 version =3D ufshcd_readl(hba, REG_UFS_MTK_IP_VER); + u32 prefix =3D FIELD_GET(MTK_UFS_VER_PREFIX_M, version); =20 - hw_ip_ver =3D ufshcd_readl(hba, REG_UFS_MTK_IP_VER); + if (prefix <=3D 1) + FIELD_MODIFY(MTK_UFS_VER_PREFIX_M, &version, 0x10); =20 - if (((hw_ip_ver & (0xFF << 24)) =3D=3D (0x1 << 24)) || - ((hw_ip_ver & (0xFF << 24)) =3D=3D 0)) { - hw_ip_ver &=3D ~(0xFF << 24); - hw_ip_ver |=3D (0x1 << 28); - } - - host->ip_ver =3D hw_ip_ver; - - host->legacy_ip_ver =3D ufs_mtk_is_legacy_chipset(hba, hw_ip_ver); + return version; } =20 static void ufs_mtk_get_controller_version(struct ufs_hba *hba) @@ -1242,7 +1239,11 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_setup_clocks(hba, true, POST_CHANGE); =20 - ufs_mtk_get_hw_ip_version(hba); + host->ip_ver =3D ufs_mtk_get_hw_ip_version(hba); + host->legacy_ip_ver =3D ufs_mtk_is_legacy_chipset(host->ip_ver); + + dev_dbg(hba->dev, "IP version 0x%x, legacy =3D %s", host->ip_ver, + str_true_false(host->legacy_ip_ver)); =20 return 0; =20 --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A746B4446E9; Mon, 14 Sep 2026 11:39:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385991; cv=none; b=PsEWfcEdrY9CnDBDVLnL2j6HG+kihjWdGgjCPn9R15DQCan+lZUKqp1yEarumJHb6pj/iP1UAvuJFz2kNx7HVVSvtp5RgJnwa24YQtJhVTAZl7c16q9I9MOJQc77Bjisx6GIVFRdMU/6wQRmGiyPRVctJVzirAc9qihtqXKmW/w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385991; c=relaxed/simple; bh=jzk/Hw+RMwYFWiQX14D3JvGuRlF3I6Kcci6JFjZ+Rhw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N0SOowNO+t5qwTkJxYbMR715WF/oK3mhk4NUduX9l4Y1sTxNDnl/RjMDazsOVRm+lsvFRYaBr0Ak4IS+057k0odAb5eyQRRgQOjGjsiuCQaQquPbltkBg+iLPYIjyhhG/feOia2kzISo9AAUaI2Rq+O/V45FrkUZBXgcqj+0UK8= ARC-Authentication-Results: i=1; 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Mon, 14 Sep 2026 13:39:46 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:39:07 +0200 Subject: [PATCH v12 21/24] scsi: ufs: mediatek: Back up idle timer in per-instance struct Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-21-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=2715; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=eDREcKfoNXLAMviPu/dYRbgFH1U4oQmTK8LePrPi/OU=; b=+V2pAzKnvTPRbSFBLcbv/V9Qw+vmZYTrBCuLglcudtJ9HCrbCGJGG+/p5zFhS02J2ozHJEbAZ Nzg1Jwboy+9DKdRxHWDs5rM9pEJtSzMs0HuW+NSIFHMV3xva/+X083x X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli The MediaTek UFS driver uses a function-scope static variable to back up a hardware register across a power change in the ufs_mtk_pwr_change_notify function. This is dangerous, as it's only correct if only ever one instance of the driver is loaded, which isn't true if there's more than one device on a SoC that needs it, or it otherwise gets loaded a second time. Back it up into a member of the host struct instead, as this struct is per-instance. Rework the function to not use a pointless "ret" local as well. Fixes: f5ca8d0c7a63 ("scsi: ufs: host: mediatek: Disable auto-hibern8 durin= g power mode changes") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Reviewed-by: Chaotian Jing Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 19 ++++++++----------- drivers/ufs/host/ufs-mediatek.h | 1 + 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index fc42e6baa47d..9cd852cadab5 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1451,27 +1451,24 @@ static int ufs_mtk_pwr_change_notify(struct ufs_hba= *hba, enum ufs_notify_change_status stage, struct ufs_pa_layer_attr *dev_req_params) { - int ret =3D 0; - static u32 reg; + struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); =20 switch (stage) { case PRE_CHANGE: if (ufshcd_is_auto_hibern8_supported(hba)) { - reg =3D ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); + host->ahit =3D ufshcd_readl( + hba, REG_AUTO_HIBERNATE_IDLE_TIMER); ufs_mtk_auto_hibern8_disable(hba); } - ret =3D ufs_mtk_pre_pwr_change(hba, dev_req_params); - break; + return ufs_mtk_pre_pwr_change(hba, dev_req_params); case POST_CHANGE: if (ufshcd_is_auto_hibern8_supported(hba)) - ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER); - break; - default: - ret =3D -EINVAL; - break; + ufshcd_writel(hba, host->ahit, + REG_AUTO_HIBERNATE_IDLE_TIMER); + return 0; } =20 - return ret; + return -EINVAL; } =20 static int ufs_mtk_unipro_set_lpm(struct ufs_hba *hba, bool lpm) diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 6b81c8f76201..1fa14a83e8cd 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -188,6 +188,7 @@ struct ufs_mtk_host { u16 ref_clk_gating_wait_us; u32 ip_ver; bool legacy_ip_ver; + u32 ahit; =20 bool mcq_set_intr; bool is_mcq_intr_enabled; --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A43245A2B8; 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Mon, 14 Sep 2026 13:39:48 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:39:08 +0200 Subject: [PATCH v12 22/24] scsi: ufs: mediatek: Remove ret local from link_startup_notify Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-22-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=1411; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=nvl2pTrzoEcoOiuYgn0QzQJDrspxIU1eSeChpwbZxnE=; b=1emF6kyB+Qj1bLrfbvlT4Vd+lZbfAPUyrIdQmcDSA73fZO6i3ltdylto93oswfyAW1/dsyw+p 9WOG3Id/ipDAuBhQV16UtCdqF+CllQJFI3bRBaMtI+cv0U0Mkn5qw4Y X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli Remove the "ret" local variable from ufs_mtk_link_startup_notify, as it's pointless; in all cases it is assigned, it is returned right after without being read first. Rework the code to just return directly, and get rid of the default branch while at it. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 9cd852cadab5..2ebf7a3118da 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1553,21 +1553,15 @@ static void ufs_mtk_post_link(struct ufs_hba *hba) static int ufs_mtk_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status stage) { - int ret =3D 0; - switch (stage) { case PRE_CHANGE: - ret =3D ufs_mtk_pre_link(hba); - break; + return ufs_mtk_pre_link(hba); case POST_CHANGE: ufs_mtk_post_link(hba); - break; - default: - ret =3D -EINVAL; - break; + return 0; } =20 - return ret; + return -EINVAL; } =20 static int ufs_mtk_device_reset(struct ufs_hba *hba) --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA85A45D5FF; Mon, 14 Sep 2026 11:39:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385995; cv=none; b=Gx1S+jumC+2wEWFV4gCcE7sNi2nOutmSwMtJ9Eo6D/e6hQnXSzjfV8TZ0tqi+TsWoWHtOM70KXrkUC9Gxtby6A9P+vTgU1nJPP4UO3EsrgXCWmkbJes709z2VLCGD3j1sPXk6aSzWhmUqgmkxlABPeaFCpfwTw+ktD1q7kpj7Us= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385995; c=relaxed/simple; bh=RrQ11G+Cm5hJRUq/8KCcqqo42LimhbHcdw+tJYWk+uM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gpYUs3498ZO0kJAQlQg4wDamgCDkGiqrCy0S/+RZGVp15QQn7sq8r0qJdMqttlrVdxs1DIaVRZUuL4PRJoqZ2dZZKlNs2UOBDYcZRY35tKfUarAbM0ZMlv9NiLxC0F2NB5la44I42eggfACfgFtxFgxUOXKK+gW3zNSUh0qHcYA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=b++yxDUl; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="b++yxDUl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789385991; bh=RrQ11G+Cm5hJRUq/8KCcqqo42LimhbHcdw+tJYWk+uM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=b++yxDUlX84/U3C54AKs9GyUR3i/KQyP6fQkxcipIY5imIwYcyfHfbk5i8cVKVclk AM+SuwSFeQaKsA2PS2qaoJJxyqga3MArCF/nf0Fwyct87emN2GQOf8nLOQ8j1bhPFs tPCeVtITg8UPMRd6g5EbNpIR088nSBeorEDo6ULFuhPWXDKVdZ3xevvusozkWzkU+m PSJDpgnOns3odhsdqPiaXP0nQC89LY3zbLBb1CAyQGZKuUXOzcw2tqngOdpTcluNWU yfrr5zI+8UawaHumieFTtOtsOZyIERT772KcCYp3jh2NSzckxZduoR8FGfrBy2lKvH zb0/RlLAKzlQw== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 26E3F17E091A; Mon, 14 Sep 2026 13:39:50 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:39:09 +0200 Subject: [PATCH v12 23/24] scsi: ufs: mediatek: Remove undocumented "clk-scale-up-vcore-min" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-23-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=4256; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=HyXJt2inu9adf+6l4pwYjXLkAXEg3B3Fas/K2wVfkMQ=; b=kEjseh06ExRgXJHBLBmT5Qa6t78N4c+Mwbu3bZZGsqC5cPKUWhTG08EO3dSLTIMI1d642uMF4 Ml+wD3mrWX4Csom4UC9V+ZUbToSBjHI0MnVhL5KXco5rHk9UCylfVdO X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli The MediaTek UFS driver contains support for an undocumented, non-vendor-prefixed u32 property named "clk-scale-up-vcore-min". Since it is not part of any binding, and would not pass a bindings review in its current form, remove it. To return this functionality, it needs to be resubmitted in a series that also introduces it to the binding, and justifies what it is used for. Compatibility with downstream device trees is not a valid justification for its existence. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Reviewed-by: Chaotian Jing Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 42 +------------------------------------= ---- drivers/ufs/host/ufs-mediatek.h | 1 - 2 files changed, 1 insertion(+), 42 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 2ebf7a3118da..ef8924704c90 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -917,8 +917,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct list_head *head =3D &hba->clk_list_head; struct ufs_clk_info *clki, *clki_tmp; - struct device *dev =3D hba->dev; - u32 volt; =20 /* * Find private clocks and store them in struct ufs_mtk_clk. @@ -955,24 +953,7 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) if (!ufs_mtk_is_clk_scale_ready(hba)) { hba->caps &=3D ~UFSHCD_CAP_CLK_SCALING; dev_info(hba->dev, "%s: Clock scaling unavailable", __func__); - return; - } - - if (!host->reg_vcore) - return; - - if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min", - &volt)) { - dev_info(dev, "failed to get clk-scale-up-vcore-min"); - return; } - - host->mclk.vcore_volt =3D volt; - - /* If default boot is max gear, request vcore */ - if (volt && host->clk_scale_up) - if (regulator_set_voltage(host->reg_vcore, volt, INT_MAX)) - dev_err(hba->dev, "Failed to set vcore to %d\n", volt); } =20 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) @@ -1966,8 +1947,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) struct ufs_mtk_clk *mclk =3D &host->mclk; struct ufs_clk_info *clki =3D mclk->ufs_sel_clki; struct ufs_clk_info *fde_clki =3D mclk->ufs_fde_clki; - int volt, ret =3D 0; - bool clk_bind_vcore =3D false; + int ret =3D 0; bool clk_fde_scale =3D false; =20 if (!hba->clk_scaling.is_initialized) @@ -1976,10 +1956,6 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, = bool scale_up) if (!clki || !fde_clki) return; =20 - volt =3D host->mclk.vcore_volt; - if (host->reg_vcore && volt) - clk_bind_vcore =3D true; - if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki) clk_fde_scale =3D true; =20 @@ -2000,14 +1976,6 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, = bool scale_up) } =20 if (scale_up) { - if (clk_bind_vcore) { - ret =3D regulator_set_voltage(host->reg_vcore, volt, INT_MAX); - if (ret) { - dev_err(hba->dev, "Failed to set vcore to %d\n", volt); - goto out; - } - } - ret =3D clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk); if (ret) { dev_err(hba->dev, "%s: Failed to set clock mux: %pe\n", @@ -2039,14 +2007,6 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, = bool scale_up) __func__, ERR_PTR(ret)); goto out; } - - if (clk_bind_vcore) { - ret =3D regulator_set_voltage(host->reg_vcore, 0, INT_MAX); - if (ret) { - dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", - __func__, ERR_PTR(ret)); - } - } } =20 out: diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 1fa14a83e8cd..4966aae5bd34 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -154,7 +154,6 @@ struct ufs_mtk_clk { struct ufs_clk_info *ufs_fde_clki; /* Mux */ struct ufs_clk_info *ufs_fde_max_clki; /* Max src */ struct ufs_clk_info *ufs_fde_min_clki; /* Min src */ - int vcore_volt; }; =20 struct ufs_mtk_hw_ver { --=20 2.55.0 From nobody Fri Sep 25 10:04:46 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95BE845D939; Mon, 14 Sep 2026 11:39:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385997; cv=none; b=pdmke0WXfjtsLK2barMEZpltLpg669s5HRFKolk3ZC7zUnVl+XpBbpI4e20S0YldhQUQMP+9hkBXayL8p+WFgaShmC12Vptoalt9zN06K4bSAHoDXFymnc7e/mEQppQvjP0bFGBWUVLvEez5IsMa8TpCDr/BpNZ/upKfftW0ozE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385997; c=relaxed/simple; bh=Rk+y0O0ztk10nHrAfu6DVPjZqIhRtbfOCG9WXu/Vfrk=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-mt8196-ufs-v12-24-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=2479; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=3kB+rZO2gAajRWpXhYF+u/1sOlmTFkMxKH7qtYej5DE=; b=xgcy9S5vLD0IJ2FqTQSUJTUdevhMq9VwtCLGC5u9SsFgIwrjvt+IA7rGNq5/MBnsxNq9DtmPr ImMNBTi/mQiDuHkrhHH2OmPptTcQjLUdWmIydcvjKVziFSPz/nB5WA2 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli THe MT8196's UFS controller has a new compatible. Add the necessary struct definitions to support it. Also update the copyrights and authors, without tabs following spaces to avoid checkpatch errors, to list myself as having contributed to this driver after the preceding rework patches. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index ef8924704c90..ceb52c40d266 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 MediaTek Inc. + * Copyright (C) 2026 Collabora Ltd. * Authors: - * Stanley Chu - * Peter Wang + * Stanley Chu + * Peter Wang + * Nicolas Frattaroli (Major clean= ups) */ =20 #include @@ -2252,6 +2254,10 @@ static const char *const ufs_mtk_regs_avdd12_ckbuf_a= vdd18[] =3D { "avdd12", "avdd12-ckbuf", "avdd18" }; =20 +static const char *const ufs_mtk_regs_avdd12_ckbuf[] =3D { + "avdd12", "avdd12-ckbuf" +}; + static const struct ufs_mtk_soc_data mt8183_data =3D { .has_avdd09 =3D true, .reg_names =3D ufs_mtk_regs_avdd12_avdd18, @@ -2264,10 +2270,18 @@ static const struct ufs_mtk_soc_data mt8192_8195_da= ta =3D { .num_reg_names =3D ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf_avdd18), }; =20 +static const struct ufs_mtk_soc_data mt8196_data =3D { + .has_avdd09 =3D true, + .has_avdd09_1 =3D true, + .reg_names =3D ufs_mtk_regs_avdd12_ckbuf, + .num_reg_names =3D ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf), +}; + static const struct of_device_id ufs_mtk_of_match[] =3D { { .compatible =3D "mediatek,mt8183-ufshci", .data =3D &mt8183_data }, { .compatible =3D "mediatek,mt8192-ufshci", .data =3D &mt8192_8195_data }, { .compatible =3D "mediatek,mt8195-ufshci", .data =3D &mt8192_8195_data }, + { .compatible =3D "mediatek,mt8196-ufshci", .data =3D &mt8196_data }, {}, }; MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); --=20 2.55.0