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Mon, 14 Sep 2026 07:31:08 +0000 (UTC) Received: from [127.0.1.1] (unknown [10.124.178.20]) by az2nlsmom2.o.css.fujitsu.com (Postfix) with ESMTP id C44B118002FD; Mon, 14 Sep 2026 07:31:02 +0000 (UTC) From: Itaru Kitayama Date: Mon, 14 Sep 2026 16:30:44 +0900 Subject: [PATCH v2 1/3] KVM: arm64: selftests: Support five-level stage-1 page tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-arm64-52bit-va-v2-1-3911cb9d4ad4@fujitsu.com> References: <20260914-arm64-52bit-va-v2-0-3911cb9d4ad4@fujitsu.com> In-Reply-To: <20260914-arm64-52bit-va-v2-0-3911cb9d4ad4@fujitsu.com> To: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Paolo Bonzini , Shuah Khan , Sean Christopherson Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Itaru Kitayama , Takayuki Okamoto X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789371056; l=4541; i=itaru.kitayama@fujitsu.com; s=20260825; h=from:subject:message-id; bh=mjC5aEg0jr+yXeG0sa/LeF7keN1owrxkWF90cvUI0lo=; b=7DfFUkA8aXGMtM/DD1jgfw6RcVdnLoUN1N2f+Gph7TODeSPeczCqvGITFCrwbSXP0Q82ddjs5 9kdbQI1rnOoA3MR8zsljCryu3P+Bnkrq1SgP+zofWwoU+upUoMsOOu+ X-Developer-Key: i=itaru.kitayama@fujitsu.com; a=ed25519; pk=g9bTnr9giRP7JwNSZHy+OMLQZBEUtSE9tUnXso0hH1Y= Add support for populating and walking five-level stage-1 page tables. A five-level translation starts at architectural level -1, so extend the page-table helpers and level validation accordingly. This enables the page-table infrastructure required by 52-bit VA configurations using the 4K translation granule. Signed-off-by: Itaru Kitayama Reviewed-by: Takayuki Okamoto --- .../selftests/kvm/include/arm64/processor.h | 1 + tools/testing/selftests/kvm/lib/arm64/processor.c | 45 ++++++++++++++++++= +--- 2 files changed, 41 insertions(+), 5 deletions(-) diff --git a/tools/testing/selftests/kvm/include/arm64/processor.h b/tools/= testing/selftests/kvm/include/arm64/processor.h index b8a902ba8573..7457503df956 100644 --- a/tools/testing/selftests/kvm/include/arm64/processor.h +++ b/tools/testing/selftests/kvm/include/arm64/processor.h @@ -113,6 +113,7 @@ =20 #define PTE_VALID BIT(0) #define PGD_TYPE_TABLE BIT(1) +#define P4D_TYPE_TABLE BIT(1) #define PUD_TYPE_TABLE BIT(1) #define PMD_TYPE_TABLE BIT(1) #define PTE_TYPE_PAGE BIT(1) diff --git a/tools/testing/selftests/kvm/lib/arm64/processor.c b/tools/test= ing/selftests/kvm/lib/arm64/processor.c index 01325bf4d36f..b589368bf822 100644 --- a/tools/testing/selftests/kvm/lib/arm64/processor.c +++ b/tools/testing/selftests/kvm/lib/arm64/processor.c @@ -29,13 +29,25 @@ static u64 pgd_index(struct kvm_vm *vm, gva_t gva) return (gva >> shift) & mask; } =20 +static u64 p4d_index(struct kvm_vm *vm, gva_t gva) +{ + unsigned int shift =3D 3 * (vm->page_shift - 3) + vm->page_shift; + u64 mask =3D (1UL << (vm->page_shift - 3)) - 1; + + TEST_ASSERT(vm->mmu.pgtable_levels =3D=3D 5, + "Mode %d does not have 5 page table levels", vm->mode); + + return (gva >> shift) & mask; +} + static u64 pud_index(struct kvm_vm *vm, gva_t gva) { unsigned int shift =3D 2 * (vm->page_shift - 3) + vm->page_shift; u64 mask =3D (1UL << (vm->page_shift - 3)) - 1; =20 - TEST_ASSERT(vm->mmu.pgtable_levels =3D=3D 4, - "Mode %d does not have 4 page table levels", vm->mode); + TEST_ASSERT(vm->mmu.pgtable_levels >=3D 4, + "Mode %d does not have >=3D 4 page table levels", + vm->mode); =20 return (gva >> shift) & mask; } @@ -147,6 +159,12 @@ static void _virt_pg_map(struct kvm_vm *vm, gva_t gva,= gpa_t gpa, PGD_TYPE_TABLE | PTE_VALID); =20 switch (vm->mmu.pgtable_levels) { + case 5: + ptep =3D addr_gpa2hva(vm, pte_addr(vm, *ptep)) + p4d_index(vm, gva) * 8; + if (!*ptep) + *ptep =3D addr_pte(vm, vm_alloc_page_table(vm), + P4D_TYPE_TABLE | PTE_VALID); + /* fall through */ case 4: ptep =3D addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; if (!*ptep) @@ -163,7 +181,7 @@ static void _virt_pg_map(struct kvm_vm *vm, gva_t gva, = gpa_t gpa, ptep =3D addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8; break; default: - TEST_FAIL("Page table levels must be 2, 3, or 4"); + TEST_FAIL("Page table levels must be 2, 3, 4, or 5"); } =20 pg_attr =3D PTE_AF | PTE_ATTRINDX(attr_idx) | PTE_TYPE_PAGE | PTE_VALID; @@ -182,18 +200,35 @@ void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, g= pa_t gpa) =20 u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t gva, int level) { + int start_level =3D 4 - vm->mmu.pgtable_levels; u64 *ptep; =20 + TEST_ASSERT(level >=3D start_level && level <=3D 3, + "Invalid translation level %d, valid range is %d-3", + level, start_level); + if (!vm->mmu.pgd_created) goto unmapped_gva; =20 ptep =3D addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, gva) * 8; if (!ptep) goto unmapped_gva; - if (level =3D=3D 0) + /* + * Stage-1 translation starts at level -1 for a five-level page + * table, and at levels 0, 1, or 2 for four-, three-, or two-level + * page tables, respectively. + */ + if (level =3D=3D start_level) return ptep; =20 switch (vm->mmu.pgtable_levels) { + case 5: + ptep =3D addr_gpa2hva(vm, pte_addr(vm, *ptep)) + p4d_index(vm, gva) * 8; + if (!ptep) + goto unmapped_gva; + if (level =3D=3D 0) + break; + /* fall through */ case 4: ptep =3D addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; if (!ptep) @@ -214,7 +249,7 @@ u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t= gva, int level) goto unmapped_gva; break; default: - TEST_FAIL("Page table levels must be 2, 3, or 4"); + TEST_FAIL("Page table levels must be 2, 3, 4, or 5"); } =20 return ptep; --=20 2.43.0 From nobody Fri Sep 25 10:38:23 2026 Received: from esa8.hc1455-7.c3s2.iphmx.com (esa8.hc1455-7.c3s2.iphmx.com [139.138.61.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86A173EF0AA; Mon, 14 Sep 2026 07:31:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=139.138.61.253 ARC-Seal: i=1; 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Mon, 14 Sep 2026 07:31:07 +0000 (UTC) From: Itaru Kitayama Date: Mon, 14 Sep 2026 16:30:45 +0900 Subject: [PATCH v2 2/3] KVM: arm64: selftests: Add 52-bit VA guest modes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-arm64-52bit-va-v2-2-3911cb9d4ad4@fujitsu.com> References: <20260914-arm64-52bit-va-v2-0-3911cb9d4ad4@fujitsu.com> In-Reply-To: <20260914-arm64-52bit-va-v2-0-3911cb9d4ad4@fujitsu.com> To: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Paolo Bonzini , Shuah Khan , Sean Christopherson Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Itaru Kitayama , Takayuki Okamoto X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789371056; l=7290; i=itaru.kitayama@fujitsu.com; s=20260825; h=from:subject:message-id; bh=womlNSebg8YA4nRh21CzpVYFz8+Hr298oHktq30HrIc=; b=wTuHb/dS7hr29G0OtUzlZDfl79+46Cbk0yFnl9e4puuQrjhbhmUbzlNa/yy6l6LdB6ryEMc9l 7YLLQPUCnwRCJ+gNyMBWNgdlyM+KM2lepReJ+JlYGbd6yfyiOcIfAaU X-Developer-Key: i=itaru.kitayama@fujitsu.com; a=ed25519; pk=g9bTnr9giRP7JwNSZHy+OMLQZBEUtSE9tUnXso0hH1Y= Add guest modes for 52-bit VA operation with the 4K, 16K, and 64K translation granules, using five, four, and three page-table levels, respectively. Extend the existing guest-mode capability probe to read ID_AA64MMFR2_EL1 from the same probe vCPU. Use VARange only when determining 52-bit VA support for the 64K granule. Signed-off-by: Itaru Kitayama Reviewed-by: Takayuki Okamoto --- tools/testing/selftests/kvm/include/arm64/processor.h | 2 +- tools/testing/selftests/kvm/include/kvm_util.h | 3 +++ tools/testing/selftests/kvm/lib/arm64/processor.c | 15 ++++++++++++++- tools/testing/selftests/kvm/lib/guest_modes.c | 7 +++++-- tools/testing/selftests/kvm/lib/kvm_util.c | 11 +++++++++++ 5 files changed, 34 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/include/arm64/processor.h b/tools/= testing/selftests/kvm/include/arm64/processor.h index 7457503df956..4ab00a7e6efb 100644 --- a/tools/testing/selftests/kvm/include/arm64/processor.h +++ b/tools/testing/selftests/kvm/include/arm64/processor.h @@ -169,7 +169,7 @@ enum { (v) =3D=3D VECTOR_SYNC_LOWER_32) =20 void aarch64_get_supported_page_sizes(u32 ipa, u32 *ipa4k, - u32 *ipa16k, u32 *ipa64k); + u32 *ipa16k, u32 *ipa64k, u32 *va64k); =20 void vm_init_descriptor_tables(struct kvm_vm *vm); void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu); diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing= /selftests/kvm/include/kvm_util.h index 5a7a455b5387..1c268fa994aa 100644 --- a/tools/testing/selftests/kvm/include/kvm_util.h +++ b/tools/testing/selftests/kvm/include/kvm_util.h @@ -184,6 +184,9 @@ enum vm_guest_mode { VM_MODE_P52V48_4K, VM_MODE_P52V48_16K, VM_MODE_P52V48_64K, + VM_MODE_P52V52_4K, + VM_MODE_P52V52_16K, + VM_MODE_P52V52_64K, VM_MODE_P48V48_4K, VM_MODE_P48V48_16K, VM_MODE_P48V48_64K, diff --git a/tools/testing/selftests/kvm/lib/arm64/processor.c b/tools/test= ing/selftests/kvm/lib/arm64/processor.c index b589368bf822..9915f25f0287 100644 --- a/tools/testing/selftests/kvm/lib/arm64/processor.c +++ b/tools/testing/selftests/kvm/lib/arm64/processor.c @@ -356,12 +356,14 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct= kvm_vcpu_init *init) case VM_MODE_PXXVYY_4K: TEST_FAIL("AArch64 does not support 4K sized pages " "with ANY-bit physical address ranges"); + case VM_MODE_P52V52_64K: case VM_MODE_P52V48_64K: case VM_MODE_P48V48_64K: case VM_MODE_P40V48_64K: case VM_MODE_P36V48_64K: tcr_el1 |=3D TCR_TG0_64K; break; + case VM_MODE_P52V52_16K: case VM_MODE_P52V48_16K: case VM_MODE_P48V48_16K: case VM_MODE_P40V48_16K: @@ -369,6 +371,7 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct k= vm_vcpu_init *init) case VM_MODE_P36V47_16K: tcr_el1 |=3D TCR_TG0_16K; break; + case VM_MODE_P52V52_4K: case VM_MODE_P52V48_4K: case VM_MODE_P48V48_4K: case VM_MODE_P40V48_4K: @@ -383,6 +386,9 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct k= vm_vcpu_init *init) =20 /* Configure output size */ switch (vm->mode) { + case VM_MODE_P52V52_4K: + case VM_MODE_P52V52_16K: + case VM_MODE_P52V52_64K: case VM_MODE_P52V48_4K: case VM_MODE_P52V48_16K: case VM_MODE_P52V48_64K: @@ -614,7 +620,7 @@ static u32 max_ipa_for_page_size(u32 vm_ipa, u32 gran, } =20 void aarch64_get_supported_page_sizes(u32 ipa, u32 *ipa4k, - u32 *ipa16k, u32 *ipa64k) + u32 *ipa16k, u32 *ipa64k, u32 *va64k) { struct kvm_vcpu_init preferred_init; int kvm_fd, vm_fd, vcpu_fd, err; @@ -652,6 +658,13 @@ void aarch64_get_supported_page_sizes(u32 ipa, u32 *ip= a4k, *ipa16k =3D max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN16_NI, ID_AA64MMFR0_EL1_TGRAN16_52_BIT); =20 + reg.id =3D KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR2_EL1); + err =3D ioctl(vcpu_fd, KVM_GET_ONE_REG, ®); + TEST_ASSERT(err =3D=3D 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, err)); + + *va64k =3D FIELD_GET(ID_AA64MMFR2_EL1_VARange, val) >=3D + ID_AA64MMFR2_EL1_VARange_52 ? 52 : 48; + close(vcpu_fd); close(vm_fd); close(kvm_fd); diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/= selftests/kvm/lib/guest_modes.c index 7a96c43b5704..8d2748145f8f 100644 --- a/tools/testing/selftests/kvm/lib/guest_modes.c +++ b/tools/testing/selftests/kvm/lib/guest_modes.c @@ -20,11 +20,14 @@ void guest_modes_append_default(void) #ifdef __aarch64__ { unsigned int limit =3D kvm_check_cap(KVM_CAP_ARM_VM_IPA_SIZE); - u32 ipa4k, ipa16k, ipa64k; + u32 ipa4k, ipa16k, ipa64k, va64k; int i; =20 - aarch64_get_supported_page_sizes(limit, &ipa4k, &ipa16k, &ipa64k); + aarch64_get_supported_page_sizes(limit, &ipa4k, &ipa16k, &ipa64k, &va64k= ); =20 + guest_mode_append(VM_MODE_P52V52_4K, ipa4k >=3D 52); + guest_mode_append(VM_MODE_P52V52_16K, ipa16k >=3D 52); + guest_mode_append(VM_MODE_P52V52_64K, ipa64k >=3D 52 && va64k >=3D 52); guest_mode_append(VM_MODE_P52V48_4K, ipa4k >=3D 52); guest_mode_append(VM_MODE_P52V48_16K, ipa16k >=3D 52); guest_mode_append(VM_MODE_P52V48_64K, ipa64k >=3D 52); diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/sel= ftests/kvm/lib/kvm_util.c index 9ddc047d5c27..bc3ed034e203 100644 --- a/tools/testing/selftests/kvm/lib/kvm_util.c +++ b/tools/testing/selftests/kvm/lib/kvm_util.c @@ -203,6 +203,9 @@ const char *vm_guest_mode_string(u32 i) [VM_MODE_P52V48_4K] =3D "PA-bits:52, VA-bits:48, 4K pages", [VM_MODE_P52V48_16K] =3D "PA-bits:52, VA-bits:48, 16K pages", [VM_MODE_P52V48_64K] =3D "PA-bits:52, VA-bits:48, 64K pages", + [VM_MODE_P52V52_4K] =3D "PA-bits:52, VA-bits:52, 4K pages", + [VM_MODE_P52V52_16K] =3D "PA-bits:52, VA-bits:52, 16K pages", + [VM_MODE_P52V52_64K] =3D "PA-bits:52, VA-bits:52, 64K pages", [VM_MODE_P48V48_4K] =3D "PA-bits:48, VA-bits:48, 4K pages", [VM_MODE_P48V48_16K] =3D "PA-bits:48, VA-bits:48, 16K pages", [VM_MODE_P48V48_64K] =3D "PA-bits:48, VA-bits:48, 64K pages", @@ -239,6 +242,9 @@ const struct vm_guest_mode_params vm_guest_mode_params[= ] =3D { [VM_MODE_P52V48_4K] =3D { 52, 48, 0x1000, 12 }, [VM_MODE_P52V48_16K] =3D { 52, 48, 0x4000, 14 }, [VM_MODE_P52V48_64K] =3D { 52, 48, 0x10000, 16 }, + [VM_MODE_P52V52_4K] =3D { 52, 52, 0x1000, 12 }, + [VM_MODE_P52V52_16K] =3D { 52, 52, 0x4000, 14 }, + [VM_MODE_P52V52_64K] =3D { 52, 52, 0x10000, 16 }, [VM_MODE_P48V48_4K] =3D { 48, 48, 0x1000, 12 }, [VM_MODE_P48V48_16K] =3D { 48, 48, 0x4000, 14 }, [VM_MODE_P48V48_64K] =3D { 48, 48, 0x10000, 16 }, @@ -306,10 +312,14 @@ struct kvm_vm *____vm_create(struct vm_shape shape) =20 /* Setup mode specific traits. */ switch (vm->mode) { + case VM_MODE_P52V52_4K: + vm->mmu.pgtable_levels =3D 5; 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Mon, 14 Sep 2026 07:31:19 +0000 (UTC) Received: from az2nlsmom2.o.css.fujitsu.com (unknown [10.150.26.200]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by az2nlsmgm3.fujitsu.com (Postfix) with ESMTPS id 4DA631800513; Mon, 14 Sep 2026 07:31:19 +0000 (UTC) Received: from [127.0.1.1] (unknown [10.124.178.20]) by az2nlsmom2.o.css.fujitsu.com (Postfix) with ESMTP id 90E2A180012C; Mon, 14 Sep 2026 07:31:13 +0000 (UTC) From: Itaru Kitayama Date: Mon, 14 Sep 2026 16:30:46 +0900 Subject: [PATCH v2 3/3] KVM: arm64: selftests: Test 52-bit guest virtual addresses Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260914-arm64-52bit-va-v2-3-3911cb9d4ad4@fujitsu.com> References: <20260914-arm64-52bit-va-v2-0-3911cb9d4ad4@fujitsu.com> In-Reply-To: <20260914-arm64-52bit-va-v2-0-3911cb9d4ad4@fujitsu.com> To: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Paolo Bonzini , Shuah Khan , Sean Christopherson Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Itaru Kitayama , Takayuki Okamoto X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789371056; l=4315; i=itaru.kitayama@fujitsu.com; s=20260825; h=from:subject:message-id; bh=D/w0Nd7mMBMXBwcmirCSoGgamOmcMh+0zKgJNohHTyU=; b=VA0ne9nO2NfJtWMm9NxCz3CmVr9fkGlNn8NDYp2vGUuIDTaOEeAvCHVW02A5c5d5QN+mOmvw6 P533nSEpYopCtjYRq6O4Pb1k4WBfmehGom4eFkGDD9Sp51UzYxkxnBf X-Developer-Key: i=itaru.kitayama@fujitsu.com; a=ed25519; pk=g9bTnr9giRP7JwNSZHy+OMLQZBEUtSE9tUnXso0hH1Y= Exercise reads and writes through low and high guest virtual addresses in the 52-bit VA modes with 4K, 16K and 64K pages. Verify that mappings to the same GPA share data and mappings to distinct GPAs remain independent. Signed-off-by: Itaru Kitayama Reviewed-by: Takayuki Okamoto --- tools/testing/selftests/kvm/Makefile.kvm | 1 + tools/testing/selftests/kvm/arm64/lpa_test.c | 124 +++++++++++++++++++++++= ++++ 2 files changed, 125 insertions(+) diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index 96bab7002d39..1e9d059ffb24 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -179,6 +179,7 @@ TEST_GEN_PROGS_arm64 +=3D arm64/hello_el2 TEST_GEN_PROGS_arm64 +=3D arm64/host_sve TEST_GEN_PROGS_arm64 +=3D arm64/hypercalls TEST_GEN_PROGS_arm64 +=3D arm64/external_aborts +TEST_GEN_PROGS_arm64 +=3D arm64/lpa_test TEST_GEN_PROGS_arm64 +=3D arm64/mmio_sign_ext TEST_GEN_PROGS_arm64 +=3D arm64/page_fault_test TEST_GEN_PROGS_arm64 +=3D arm64/psci_test diff --git a/tools/testing/selftests/kvm/arm64/lpa_test.c b/tools/testing/s= elftests/kvm/arm64/lpa_test.c new file mode 100644 index 000000000000..8fe6f254db28 --- /dev/null +++ b/tools/testing/selftests/kvm/arm64/lpa_test.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Higher virtual addresses read/write test + */ +#include + +#include "kvm_syscalls.h" +#include "kvm_util.h" +#include "ucall_common.h" +#include "guest_modes.h" +#include "processor.h" + +#define LOW_GVA 0xc0000000 +#define HIGH_GVA (LOW_GVA | BIT(48)) + +static void guest_code(void) +{ + u64 *low =3D (u64 *)LOW_GVA; + u64 *high =3D (u64 *)HIGH_GVA; + + WRITE_ONCE(*low, 1); + GUEST_ASSERT_EQ(READ_ONCE(*high), 1); + WRITE_ONCE(*high, 2); + GUEST_ASSERT_EQ(READ_ONCE(*low), 2); + + GUEST_SYNC(0); + + asm volatile("dsb sy\n\t" + "tlbi vmalle1is\n\t" + "dsb sy\n\t" + "isb" + : : : "memory"); + + GUEST_SYNC(1); /* Host installs HIGH_GVA -> gpa_b. */ + + asm volatile("dsb sy\n\t" + "isb\n\t" + : : : "memory"); + + /* low and high map to different GPAs. */ + WRITE_ONCE(*low, 1); + WRITE_ONCE(*high, 2); + + /* Check both after both writes to detect accidental aliasing. */ + GUEST_ASSERT_EQ(READ_ONCE(*low), 1); + GUEST_ASSERT_EQ(READ_ONCE(*high), 2); + + /* Updating the low mapping must not change the high mapping. */ + WRITE_ONCE(*low, 3); + + GUEST_ASSERT_EQ(READ_ONCE(*low), 3); + GUEST_ASSERT_EQ(READ_ONCE(*high), 2); + + GUEST_DONE(); +} + +static void run_test(enum vm_guest_mode mode, void *arg) +{ + unsigned int *nr_tests =3D arg; + struct kvm_vcpu_init init; + struct kvm_vm *vm; + struct kvm_vcpu *vcpu; + struct ucall uc; + + if (mode !=3D VM_MODE_P52V52_4K && + mode !=3D VM_MODE_P52V52_16K && + mode !=3D VM_MODE_P52V52_64K) + return; + + vm =3D __vm_create(VM_SHAPE(mode), 1, 0); + kvm_get_default_vcpu_target(vm, &init); + vcpu =3D aarch64_vcpu_add(vm, 0, &init, guest_code); + kvm_arch_vm_finalize_vcpus(vm); + + vm_init_descriptor_tables(vm); + vcpu_init_descriptor_tables(vcpu); + + u64 gpa_a =3D vm_phy_pages_alloc(vm, 1, 0, 0); + u64 gpa_b =3D vm_phy_pages_alloc(vm, 1, 0, 0); + + virt_pg_map(vm, LOW_GVA, gpa_a); + virt_pg_map(vm, HIGH_GVA, gpa_a); + + for (;;) { + vcpu_run(vcpu); + switch (get_ucall(vcpu, &uc)) { + case UCALL_DONE: + goto done; + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + break; + case UCALL_SYNC: + switch (uc.args[1]) { + case 0: + WRITE_ONCE(*virt_get_pte_hva(vm, HIGH_GVA), 0); + break; + case 1: + virt_pg_map(vm, HIGH_GVA, gpa_b); + break; + default: + TEST_FAIL("Unexpected sync stage: %lu\n", uc.args[1]); + } + /* Complete the host's PTE store before resuming the guest. */ + asm volatile("dsb sy" : : : "memory"); + break; + default: + TEST_FAIL("Unhandled ucall: %ld\n", uc.cmd); + } + } + +done: + kvm_vm_free(vm); + (*nr_tests)++; +} + +int main(int argc, char **argv) +{ + unsigned int nr_tests =3D 0; + + for_each_guest_mode(run_test, &nr_tests); + if (!nr_tests) + ksft_exit_skip("No supported 52-bit VA guest mode; skipping test\n"); + return 0; +} --=20 2.43.0