From nobody Fri Sep 25 12:34:02 2026 Received: from mout02.posteo.de (mout02.posteo.de [185.67.36.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 910D436EAA4 for ; Sat, 12 Sep 2026 20:45:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.67.36.66 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789245915; cv=none; b=DsPIFBte46kKEtLnkdFAuqZxXHM7w64mvvyc6+HhAt8v26tQyWUot5ESNyG6aZC3uDguaOmV9OBHkIa1j1vR0t65vHFttqByUUThDpGt+1n1QGFxkxyuknxq1nsO7HIFNP1m0eSPSDVCAe29b9ToKvivtvEOvpAYvPRLUFwMHQY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789245915; c=relaxed/simple; bh=Arr4R7yuKObofd2Tor2p4y08xrfyOMfz0qsf5aQA7LU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eY0dGXNz0t2GmUMRhOVtCVx/nkE5NyagTLkTC1uEDIFHn65CUzazvdYBhCypN4YTuEtn5Iwc6z4bFPk9p+dot+b6hB5G0ig2IzmLALS9LluLwaNg/pup8pxsGxva26/k38OriZ1iwvd922RCK6j9ztsmkIyhun99xMh7lLTxpfA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=posteo.net; spf=pass smtp.mailfrom=posteo.net; dkim=pass (2048-bit key) header.d=posteo.net header.i=@posteo.net header.b=ahGVWikQ; arc=none smtp.client-ip=185.67.36.66 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=posteo.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=posteo.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=posteo.net header.i=@posteo.net header.b="ahGVWikQ" Received: from submission (posteo.de [185.67.36.169]) by mout02.posteo.de (Postfix) with ESMTPS id AB81F240104 for ; Sat, 12 Sep 2026 22:45:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=posteo.net; s=1984.8680eb; t=1789245904; bh=Myy3smEvql/qodoHPfYgXGKdcJUKumaY+uFvrhTMU5M=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version: Content-Transfer-Encoding:From; b=ahGVWikQWzElFIqOcmtCZv6GyrHrNdCT13y08LejH4cvzx87/fX/9QqXntFKyrNpk QVBVvLbmhdVx06AFRD04peCv1B8VEtU7XeMtF74uBj4nCGyKv3cN1ax6NkU39CyMTT IrNeqZTvhAAqlKf3XKheadISthEvgKq2KyCyTX5mct+iBD+S8fW+XBXg7xHnCTRpJ0 Zl9BaBCywdudLwNCiirOakAFDk5uanx/aG4QO6azDnN8HUIKF9RIJPbMY0ah+7hXRG yA7MUd8FLW4pHZDtiHdPhCdXyIWr9eMIbu/qwkqwTH+Bk8AavvstpHBZPykjVdj9DJ 93rszw+rOoxLQ== Received: from customer (localhost [127.0.0.1]) by submission (posteo.de) with ESMTPSA id 4hj3M32998z9rxG; Sat, 12 Sep 2026 22:45:03 +0200 (CEST) From: Mateusz Nowicki To: alexandre.torgue@foss.st.com, mcoquelin.stm32@gmail.com Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] arm64: dts: st: add sdmmc2 node on stm32mp251 Date: Sat, 12 Sep 2026 20:45:04 +0000 Message-ID: <20260912204454.219606-2-mateusz.nowicki@posteo.net> In-Reply-To: <20260912204454.219606-1-mateusz.nowicki@posteo.net> References: <20260912204454.219606-1-mateusz.nowicki@posteo.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the SDMMC2 controller, the same PL18x/SDMMC2 block as SDMMC1 with its own delay block in SYSCFG (DLYBSD2). It is used for the eMMC on the STM32MP257F-DK and STM32MP257F-EV1 boards. Signed-off-by: Mateusz Nowicki --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 9c63fdb5a885..0d10023ec1e3 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1667,6 +1667,21 @@ sdmmc1: mmc@48220000 { status =3D "disabled"; }; =20 + sdmmc2: mmc@48230000 { + compatible =3D "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid =3D <0x00353180>; + reg =3D <0x48230000 0x400>, <0x44230800 0x8>; + interrupts =3D ; + clocks =3D <&rcc CK_KER_SDMMC2>; + clock-names =3D "apb_pclk"; + resets =3D <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency =3D <120000000>; + access-controllers =3D <&rifsc 77>; + status =3D "disabled"; + }; + ethernet1: ethernet@482c0000 { compatible =3D "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg =3D <0x482c0000 0x4000>; --=20 2.55.0 From nobody Fri Sep 25 12:34:02 2026 Received: from mout01.posteo.de (mout01.posteo.de [185.67.36.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B290348D897 for ; Sat, 12 Sep 2026 20:45:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.67.36.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789245915; cv=none; b=pdEWECSTsGU7NJ+aNm2kdr261SWPhtmpVKb03zK8qVRg23bF9gJ5xz4e0SX/Ph11xgh++yxQ/C9PwB4gIjJUKdolje+JPUp1sOuQKJ6FWdkoul+P6cAjoPLx5/U5WgpAhNoR2Ln3y1ogl3oKi0TyqBTugt1dHeRnLlg4yjGFcL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789245915; c=relaxed/simple; bh=QZX+R39YfEMz1YW0fT6go5wgSTxtL50Zgg4jwWLHrH8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T1Pnk8B7iyYIYYtswGIsq/yTZA5CelKfwMVFh8veH43YbAG8JYBujYdGyCXHF3Q7mjgA6laNiH1NVO9ZlC8VgFhw5sTuCZfZITA9B/zjQ+IhePS6pOjJ3V7ka87awl65cGZC/NWIlglkc5GbieT9nD+u3PsL15ZmLQegj3XW4ZA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=posteo.net; spf=pass smtp.mailfrom=posteo.net; dkim=pass (2048-bit key) header.d=posteo.net header.i=@posteo.net header.b=OOHWwWvQ; arc=none smtp.client-ip=185.67.36.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=posteo.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=posteo.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=posteo.net header.i=@posteo.net header.b="OOHWwWvQ" Received: from submission (posteo.de [185.67.36.169]) by mout01.posteo.de (Postfix) with ESMTPS id 889CA240027 for ; Sat, 12 Sep 2026 22:45:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=posteo.net; s=1984.8680eb; t=1789245905; bh=DQYvhd5nwDF+C0dkDYLe5yPvzGZ32GjjX1tx0SgEwRg=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version: Content-Transfer-Encoding:From; b=OOHWwWvQ1Buvm0eqMvV/4nQbi9B8c53edxOEqOM/3ScyY4XhEZFeFQIhdNqo911he Fe4bEg7+G1yAe0cM0eSL0BnXpJkkagvJzkMd/CakNaT/PuxmlTEh0AsntSQPQ304yB G0/EVTfHgoOLTyaJlCWBFXq3Npj8Nl1r2gaXk1eaG2VC4LCT55OuDZq3Hi9FlEQDYd ksdKQwrk8DFLUa60kOBGssRqGBoRZFE5UUvhBbXXdfUq+aQ8crDVXZqb/nJhT6luGe l2c37nWPCovKzTmg6OFwUkiK3xDnN8E6i286BVPJAssXXVVqaftyWVjQrPJMVlb11N K89iK6lOpa0Gg== Received: from customer (localhost [127.0.0.1]) by submission (posteo.de) with ESMTPSA id 4hj3M437p1z9rxL; Sat, 12 Sep 2026 22:45:04 +0200 (CEST) From: Mateusz Nowicki To: alexandre.torgue@foss.st.com, mcoquelin.stm32@gmail.com Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] arm64: dts: st: add sdmmc2 pins on stm32mp25 Date: Sat, 12 Sep 2026 20:45:05 +0000 Message-ID: <20260912204454.219606-3-mateusz.nowicki@posteo.net> In-Reply-To: <20260912204454.219606-1-mateusz.nowicki@posteo.net> References: <20260912204454.219606-1-mateusz.nowicki@posteo.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the 8-bit bus pin groups of SDMMC2 on port E, used by the eMMC on the STM32MP257F-DK. Signed-off-by: Mateusz Nowicki --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 456ece7f8ebc..ad55791a72fc 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -431,6 +431,75 @@ pins { }; }; =20 + /omit-if-no-ref/ + sdmmc2_b8_pins_a: sdmmc2-b8-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + , /* SDMMC2_D7 */ + ; /* SDMMC2_CMD */ + slew-rate =3D <2>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <3>; + drive-push-pull; + bias-disable; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b8_od_pins_a: sdmmc2-b8-od-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate =3D <2>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <3>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux =3D ; /* SDMMC2_CMD */ + slew-rate =3D <2>; + drive-open-drain; + bias-disable; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b8_sleep_pins_a: sdmmc2-b8-sleep-0 { + pins { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + , /* SDMMC2_D7 */ + , /* SDMMC2_CMD */ + ; /* SDMMC2_CK */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { --=20 2.55.0 From nobody Fri Sep 25 12:34:02 2026 Received: from mout01.posteo.de (mout01.posteo.de [185.67.36.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E9BE386424 for ; Sat, 12 Sep 2026 20:45:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sat, 12 Sep 2026 22:45:05 +0200 (CEST) From: Mateusz Nowicki To: alexandre.torgue@foss.st.com, mcoquelin.stm32@gmail.com Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: st: enable eMMC on stm32mp257f-dk Date: Sat, 12 Sep 2026 20:45:06 +0000 Message-ID: <20260912204454.219606-4-mateusz.nowicki@posteo.net> In-Reply-To: <20260912204454.219606-1-mateusz.nowicki@posteo.net> References: <20260912204454.219606-1-mateusz.nowicki@posteo.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the 8-Gbyte eMMC v5.1 connected to SDMMC2 with an 8-bit bus. Faster 1.8V modes are not enabled as they could not be tested yet. Signed-off-by: Mateusz Nowicki --- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp257f-dk.dts index 8daf3dfd5133..8c6aabac367e 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -21,6 +21,8 @@ / { aliases { ethernet0 =3D ðernet1; serial0 =3D &usart2; + mmc0 =3D &sdmmc1; + mmc1 =3D &sdmmc2; }; =20 chosen { @@ -231,6 +233,10 @@ scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <3300000>; }; + scmi_vddio2: regulator@1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; scmi_vddcore: regulator@11 { reg =3D ; regulator-name =3D "vddcore"; @@ -279,6 +285,21 @@ &sdmmc1 { status =3D "okay"; }; =20 +&sdmmc2 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc2_b8_pins_a>; + pinctrl-1 =3D <&sdmmc2_b8_od_pins_a>; + pinctrl-2 =3D <&sdmmc2_b8_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width =3D <8>; + status =3D "okay"; + vmmc-supply =3D <&scmi_vdd_emmc>; + vqmmc-supply =3D <&scmi_vddio2>; +}; + &usart2 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart2_pins_a>; --=20 2.55.0