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charset="utf-8" The dmaengine core assigns channel IDs in registration order. If a driver skips a hardware channel, chan_id can differ from the hardware numbering and a client cannot reliably correlate a requested channel with hardware resources. Let a driver request an exact channel ID before device registration. Reserve static IDs through the existing IDA so they remain unique, while retaining automatic IDA allocation as the default. For example, idma32 uses chan_id to select DMA_CTL_CH() and DMA_XBAR_SEL(), so it relies on ascending registration order to match chan_id with the hardware channel number. Use direction-flattened IDs for dw-edma channels. Unlike the direction-local hardware channel number, these IDs are unique within the DMA device. Suggested-by: Frank Li Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v4: - No changes. drivers/dma/dmaengine.c | 13 ++++++++----- drivers/dma/dw-edma/dw-edma-core.c | 1 + include/linux/dmaengine.h | 20 ++++++++++++++++++++ 3 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 6ffd8bd82154..cc64a4679e6f 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -1078,6 +1078,7 @@ static int __dma_async_device_channel_register(struct= dma_device *device, struct dma_chan *chan, const char *name) { + unsigned int id; int rc; =20 chan->local =3D alloc_percpu(typeof(*chan->local)); @@ -1089,11 +1090,13 @@ static int __dma_async_device_channel_register(stru= ct dma_device *device, goto err_free_local; } =20 - /* - * When the chan_id is a negative value, we are dynamically adding - * the channel. Otherwise we are static enumerating. - */ - chan->chan_id =3D ida_alloc(&device->chan_ida, GFP_KERNEL); + if (chan->chan_id & DMA_CHAN_ID_STATIC) { + id =3D chan->chan_id & ~DMA_CHAN_ID_STATIC; + chan->chan_id =3D ida_alloc_range(&device->chan_ida, id, id, + GFP_KERNEL); + } else { + chan->chan_id =3D ida_alloc(&device->chan_ida, GFP_KERNEL); + } if (chan->chan_id < 0) { pr_err("%s: unable to alloc ida for chan: %d\n", __func__, chan->chan_id); diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index 03b2c2188351..a678c70a78fe 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -988,6 +988,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u3= 2 wr_alloc, u32 rd_alloc) &dw->chip->dt_region_rd[chan->id]; =20 vchan_init(&chan->vc, dma); + dmaengine_set_static_chan_id(&chan->vc.chan, i); =20 dw_edma_core_ch_config(chan); } diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index fe33a20abc61..f669b79d7731 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -369,6 +369,26 @@ struct dma_chan { void *private; }; =20 +#define DMA_CHAN_ID_STATIC BIT(30) + +/** + * dmaengine_set_static_chan_id - request an exact DMA engine channel ID + * @chan: DMA channel + * @id: channel ID, unique within the DMA device + * + * Drivers may call this after initializing @chan and before registering i= ts + * DMA device. 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charset="utf-8" An endpoint function can reserve an endpoint-local channel while the RC programs it through an exposed register window. Such a channel must route interrupts remotely and ignore them on the endpoint. Use dma_slave_config to set per-channel interrupt routing on idle channels of a local eDMA or HDMA instance. Releasing a remote-routed channel quiesces the hardware and drains its local IRQ before restoring default routing. The eDMA quiesce may stop a complete direction. The caller must own every channel in that direction and stop remote programming first. Suggested-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v4: - Drop unnecessary READ_ONCE()/WRITE_ONCE() for irq_mode. (Frank) - Allow repeated dmaengine_slave_config() calls on idle channels when the IRQ mode is unchanged. (Sashiko) - Simplify IRQ mode handling, assuming the channel has no pending interrupt status when its mode changes. Treat racing reads by shared IRQ handlers and same-value stores on release as harmless. - Support native HDMA. drivers/dma/dw-edma/dw-edma-core.c | 136 ++++++++++++++++++++++------- include/linux/dma/edma.h | 21 +++++ 2 files changed, 125 insertions(+), 32 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index a678c70a78fe..c978da30bac5 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -177,48 +177,76 @@ dw_edma_get_default_irq_mode(struct dw_edma_chan *cha= n) DW_EDMA_CH_IRQ_REMOTE; } =20 +static int dw_edma_device_config_irq_mode(struct dw_edma_chan *chan, + enum dw_edma_ch_irq_mode mode) +{ + if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) || + (mode !=3D DW_EDMA_CH_IRQ_LOCAL && mode !=3D DW_EDMA_CH_IRQ_REMOTE)) + return -EINVAL; + + guard(spinlock_irqsave)(&chan->vc.lock); + + if (chan->status !=3D EDMA_ST_IDLE || chan->request !=3D EDMA_REQ_NONE) + return -EBUSY; + + /* IRQ routing cannot change after the initial configuration. */ + if (chan->irq_mode =3D=3D mode) + return 0; + + if (chan->configured) + return -EBUSY; + + chan->irq_mode =3D mode; + + return 0; +} + static int dw_edma_device_config(struct dma_chan *dchan, struct dma_slave_config *config) { + const struct dw_edma_chan_config *dw_config =3D config->peripheral_config; struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); - bool cfg_non_ll; - int non_ll =3D 0; - - chan->non_ll =3D false; - if (chan->dw->chip->mf =3D=3D EDMA_MF_HDMA_NATIVE) { - if (config->peripheral_config && - config->peripheral_size !=3D sizeof(int)) { - dev_err(dchan->device->dev, - "config param peripheral size mismatch\n"); + bool non_ll =3D false; + u32 flags =3D 0; + int ret; + + if (dw_config) { + if (config->peripheral_size !=3D sizeof(*dw_config) || + dw_config->flags & ~(DW_EDMA_CH_CONFIG_NON_LL | + DW_EDMA_CH_CONFIG_IRQ_MODE)) return -EINVAL; - } + flags =3D dw_config->flags; + } =20 - /* - * When there is no valid LLP base address available then the - * default DMA ops will use the non-LL mode. - * - * Cases where LL mode is enabled and client wants to use the - * non-LL mode then also client can do so via providing the - * peripheral_config param. - */ - cfg_non_ll =3D chan->dw->chip->cfg_non_ll; - if (config->peripheral_config) { - non_ll =3D *(int *)config->peripheral_config; + /* + * When there is no valid LLP base address available then the + * default DMA ops will use the non-LL mode. + * + * When LL mode is the default, clients can request non-LL mode + * through DW_EDMA_CH_CONFIG_NON_LL. + */ + non_ll =3D chan->dw->chip->mf =3D=3D EDMA_MF_HDMA_NATIVE && + chan->dw->chip->cfg_non_ll; =20 - if (cfg_non_ll && !non_ll) { - dev_err(dchan->device->dev, "invalid configuration\n"); - return -EINVAL; - } + if (flags & DW_EDMA_CH_CONFIG_NON_LL) { + if (chan->dw->chip->mf !=3D EDMA_MF_HDMA_NATIVE) + return -EINVAL; + + if (chan->dw->chip->cfg_non_ll && !dw_config->non_ll) { + dev_err(dchan->device->dev, "invalid configuration\n"); + return -EINVAL; } =20 - if (cfg_non_ll || non_ll) - chan->non_ll =3D true; - } else if (config->peripheral_config) { - dev_err(dchan->device->dev, - "peripheral config param applicable only for HDMA\n"); - return -EINVAL; + non_ll =3D dw_config->non_ll; + } + + if (flags & DW_EDMA_CH_CONFIG_IRQ_MODE) { + ret =3D dw_edma_device_config_irq_mode(chan, dw_config->irq_mode); + if (ret) + return ret; } =20 + chan->non_ll =3D non_ll; memcpy(&chan->config, config, sizeof(*config)); chan->configured =3D true; =20 @@ -890,11 +918,53 @@ static void dw_edma_wait_termination(struct dma_chan = *dchan) "timeout waiting for channel termination\n"); } =20 +static void dw_edma_synchronize_chan_irq(struct dw_edma_chan *chan) +{ + struct dw_edma *dw =3D chan->dw; + unsigned long *mask; + int i; + + /* + * A shared handler may retain this channel's status across quiesce. + * With nr_irqs =3D=3D 1, it scans both directions even if routing and + * delegation are direction-wide. Drain it before allowing a routing chan= ge. + */ + for (i =3D 0; i < dw->nr_irqs; i++) { + mask =3D chan->dir =3D=3D EDMA_DIR_WRITE ? dw->irq[i].wr_mask : + dw->irq[i].rd_mask; + if (!test_bit(chan->id, mask)) + continue; + + synchronize_irq(dw->chip->ops->irq_vector(dw->chip->dev, i)); + return; + } +} + static void dw_edma_device_synchronize(struct dma_chan *dchan) { struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); + bool remote; + + /* + * irq_mode is fixed after initial configuration. The free path + * restores it only after synchronization. + */ + remote =3D chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL && + chan->irq_mode =3D=3D DW_EDMA_CH_IRQ_REMOTE; + + /* + * Peer-driven transfers bypass local descriptor tracking, so quiesce + * the hardware explicitly. + */ + if (remote && dw_edma_core_ch_quiesce(chan)) + dev_warn(chan->dw->chip->dev, + "failed to quiesce remote-routed %s channel %u\n", + chan->dir =3D=3D EDMA_DIR_WRITE ? "write" : "read", + chan->id); =20 dw_edma_wait_termination(dchan); + if (remote) + dw_edma_synchronize_chan_irq(chan); cancel_work_sync(&chan->irq_work); atomic_set(&chan->irq_pending, 0); vchan_synchronize(&chan->vc); @@ -907,8 +977,10 @@ static void dw_edma_free_chan_resources(struct dma_cha= n *dchan) dw_edma_device_terminate_all(dchan); dw_edma_device_synchronize(dchan); =20 - scoped_guard(spinlock_irqsave, &chan->vc.lock) + scoped_guard(spinlock_irqsave, &chan->vc.lock) { chan->configured =3D false; + chan->irq_mode =3D dw_edma_get_default_irq_mode(chan); + } =20 vchan_free_chan_resources(&chan->vc); } diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 3c8e2ef9dee0..43831fa57357 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -101,6 +101,27 @@ enum dw_edma_ch_irq_mode { DW_EDMA_CH_IRQ_REMOTE, }; =20 +#define DW_EDMA_CH_CONFIG_NON_LL BIT(0) +#define DW_EDMA_CH_CONFIG_IRQ_MODE BIT(1) + +/** + * struct dw_edma_chan_config - dw-edma channel configuration + * @flags: fields selected by DW_EDMA_CH_CONFIG_* + * @non_ll: use HDMA non-linked-list mode + * @irq_mode: interrupt routing mode + * + * Pass this structure through dma_slave_config.peripheral_config. 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charset="utf-8" get_cached_msi_msg() returns the base message shared by a multi-MSI descriptor. dw-edma currently derives per-channel data from its local IRQ index and does not adjust a common IRQ at all. Both assume eDMA starts at the descriptor's first vector. That is not true when eDMA receives a tail subset. Compose each message from the IRQ offset relative to the descriptor base in both paths. While at it, avoid reading PCI MSI attributes from descriptors owned by non-PCI devices. Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v4: - No changes. drivers/dma/dw-edma/dw-edma-core.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index c978da30bac5..1e6fbe0922a9 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -1106,12 +1107,23 @@ static inline void dw_edma_dec_irq_alloc(int *nr_ir= qs, u32 *alloc, u16 cnt) } } =20 +static void dw_edma_compose_msi(int irq, struct msi_msg *msi) +{ + struct msi_desc *desc =3D irq_get_msi_desc(irq); + + if (!desc) + return; + + get_cached_msi_msg(irq, msi); + if (dev_is_pci(desc->dev) && !desc->pci.msi_attrib.is_msix) + msi->data +=3D irq - desc->irq; +} + static int dw_edma_irq_request(struct dw_edma *dw, u32 *wr_alloc, u32 *rd_alloc) { struct dw_edma_chip *chip =3D dw->chip; struct device *dev =3D dw->chip->dev; - struct msi_desc *msi_desc; int i, err =3D 0; u32 ch_cnt; int irq; @@ -1136,8 +1148,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, return err; } =20 - if (irq_get_msi_desc(irq)) - get_cached_msi_msg(irq, &dw->irq[0].msi); + dw_edma_compose_msi(irq, &dw->irq[0].msi); =20 dw->nr_irqs =3D 1; } else { @@ -1160,12 +1171,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, &dw->irq[i]); if (err) goto err_irq_free; - msi_desc =3D irq_get_msi_desc(irq); - if (msi_desc) { - get_cached_msi_msg(irq, &dw->irq[i].msi); - if (!msi_desc->pci.msi_attrib.is_msix) - dw->irq[i].msi.data =3D dw->irq[0].msi.data + i; - } + dw_edma_compose_msi(irq, &dw->irq[i].msi); } =20 dw->nr_irqs =3D i; --=20 2.51.0