From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3499D417BD2; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; cv=none; b=nPA0fRefJQjS9yu4b2XsHABjzbJy/FTXXOqUe7tdM88XTDtdOvQKWdCno6ms/ZrBUA7MLfq9bMPFKOQkznqxhn356RNeAMlb9vevfQFqfnbgjiM9dgQOK3Dvg9Bx6MpBfO6rMJcY9C/eItxHE5iEKUzcsmZxSO4Q/vMp0aB8xrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; c=relaxed/simple; bh=o2VSyHTxUfSGM5eyyNwP4XWCmgbVTwqPS8NmK4uo3Bc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FZXM2WPkfS14PeyMbHAiG3UcV9OdzXFx79u4xkOR1y4pTJmtWT9YqJoO3KrQOzuKpYe//A+zgLU3/Q8QC4fi2Twj1OKoB8DpfrbohjgbRnAWwW1KVd6MDUseXTR9jX/Q3iU4XnbanFpkeiW6zWD6JWE+OZ/l8vGWrkBthnUHinI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dwQ/BcLz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dwQ/BcLz" Received: by smtp.kernel.org (Postfix) with ESMTPS id D4A0BC2BCFB; Sat, 12 Sep 2026 08:39:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202357; bh=o2VSyHTxUfSGM5eyyNwP4XWCmgbVTwqPS8NmK4uo3Bc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dwQ/BcLzXWFkdM15bclsJMKmhmWZ7gBJuPTMFjzL00PkHbQyFKxck5qE5s5MLBIZp ZYRj6SecHwRq9iyVozMuh/93BEPbxO/vQjEeNBBPWtVVqK/Dw5q7qEwk8ECSosyfdN 3R/8FIQdc3h+5PwKHcPaaZq06InIQEtrg6PN4A0sEKLI2CaGTJv+NUvW/b0NkjzZYl OVEhz83G1O05luAN+qsAALnLKiAnw5N6H7Z+gosO6wE4K2b71VngMkcA4FJRYZpUNM 2nV8Umv28rjgUXnNpgVLR5i1uydvKQysyzlNsTbb65JyXHXOij7D6c+HYzqLY4Rb/t 9P3IfZHGbpVYA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD128C88E53; Sat, 12 Sep 2026 08:39:17 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:10 +0300 Subject: [PATCH RFC 01/20] dt-bindings: clock: qcom: Add MSM8952 global clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-1-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=9903; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=QFdtS+4ir8qozpzsMSNO2DZzGZTmEOtu2UKFZZesD/A=; b=at0BTMV+Mfb/LXDsg/wLvnABIQbu0yGFesjX58+sXobrtx8rbp6hCarwipA5XkEmdRV/p+OmT 3riFANHlGYPCzBWsxZ2s9lF3S/GbxJ1MbgyI43AJtUSYOlbJnAc2JQO X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add a device tree binding to describe clocks, resets and power domains provided by the global clock controller on MSM8952 SoC. Signed-off-by: Muzaffer Kadir --- .../bindings/clock/qcom,gcc-msm8952.yaml | 56 ++++++ include/dt-bindings/clock/qcom,gcc-msm8952.h | 219 +++++++++++++++++= ++++ 2 files changed, 275 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8952.yaml = b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8952.yaml new file mode 100644 index 000000000000..274dde633e17 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8952.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8952.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8952 + +maintainers: + - Muzaffer Kadir + +description: | + Qualcomm global clock control module provides the clocks, resets and pow= er + domains on MSM8952. + + See also:: + include/dt-bindings/clock/qcom,gcc-msm8952.h + +properties: + compatible: + enum: + - qcom,gcc-msm8952 + + clocks: + items: + - description: XO source + - description: Always-on XO source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + + clock-names: + items: + - const: xo + - const: xo_a + - const: dsi0pll + - const: dsi0pllbyte + +required: + - compatible + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8952"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + reg =3D <0x01800000 0x80000>; + }; +... diff --git a/include/dt-bindings/clock/qcom,gcc-msm8952.h b/include/dt-bind= ings/clock/qcom,gcc-msm8952.h new file mode 100644 index 000000000000..1ae241614d3c --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8952.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Linaro Limited + * Copyright 2026 Muzaffer Kadir + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8952_H +#define _DT_BINDINGS_CLK_MSM_GCC_8952_H + +#define GPLL0 0 +#define GPLL0_VOTE 1 +#define GPLL3 2 +#define GPLL3_EARLY 3 +#define GPLL4 4 +#define GPLL4_VOTE 5 +#define GPLL6 6 +#define GPLL6_VOTE 7 +#define CAMSS_TOP_AHB_CLK_SRC 8 +#define APSS_AHB_CLK_SRC 9 +#define CSI0_CLK_SRC 10 +#define CSI1_CLK_SRC 11 +#define GFX3D_CLK_SRC 12 +#define VFE0_CLK_SRC 13 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 14 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 15 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 16 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 17 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 18 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 19 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 20 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 21 +#define BLSP1_UART1_APPS_CLK_SRC 22 +#define BLSP1_UART2_APPS_CLK_SRC 23 +#define CCI_CLK_SRC 24 +#define CAMSS_GP0_CLK_SRC 25 +#define CAMSS_GP1_CLK_SRC 26 +#define JPEG0_CLK_SRC 27 +#define MCLK0_CLK_SRC 28 +#define MCLK1_CLK_SRC 29 +#define CSI0PHYTIMER_CLK_SRC 30 +#define CSI1PHYTIMER_CLK_SRC 31 +#define CPP_CLK_SRC 32 +#define CRYPTO_CLK_SRC 33 +#define GP1_CLK_SRC 34 +#define GP2_CLK_SRC 35 +#define GP3_CLK_SRC 36 +#define BYTE0_CLK_SRC 37 +#define ESC0_CLK_SRC 38 +#define MDP_CLK_SRC 39 +#define PCLK0_CLK_SRC 40 +#define VSYNC_CLK_SRC 41 +#define PDM2_CLK_SRC 42 +#define SDCC1_APPS_CLK_SRC 43 +#define SDCC2_APPS_CLK_SRC 44 +#define USB_HS_SYSTEM_CLK_SRC 45 +#define VCODEC0_CLK_SRC 46 +#define GCC_BLSP1_AHB_CLK 47 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 48 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 49 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 50 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 51 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 52 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 53 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 54 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 55 +#define GCC_BLSP1_UART1_APPS_CLK 56 +#define GCC_BLSP1_UART2_APPS_CLK 57 +#define GCC_BOOT_ROM_AHB_CLK 58 +#define GCC_CAMSS_CCI_AHB_CLK 59 +#define GCC_CAMSS_CCI_CLK 60 +#define GCC_CAMSS_CSI0_AHB_CLK 61 +#define GCC_CAMSS_CSI0_CLK 62 +#define GCC_CAMSS_CSI0PHY_CLK 63 +#define GCC_CAMSS_CSI0PIX_CLK 64 +#define GCC_CAMSS_CSI0RDI_CLK 65 +#define GCC_CAMSS_CSI1_AHB_CLK 66 +#define GCC_CAMSS_CSI1_CLK 67 +#define GCC_CAMSS_CSI1PHY_CLK 68 +#define GCC_CAMSS_CSI1PIX_CLK 69 +#define GCC_CAMSS_CSI1RDI_CLK 70 +#define GCC_CAMSS_CSI_VFE0_CLK 71 +#define GCC_CAMSS_GP0_CLK 72 +#define GCC_CAMSS_GP1_CLK 73 +#define GCC_CAMSS_ISPIF_AHB_CLK 74 +#define GCC_CAMSS_JPEG0_CLK 75 +#define GCC_CAMSS_JPEG_AHB_CLK 76 +#define GCC_CAMSS_JPEG_AXI_CLK 77 +#define GCC_CAMSS_MCLK0_CLK 78 +#define GCC_CAMSS_MCLK1_CLK 79 +#define GCC_CAMSS_MICRO_AHB_CLK 80 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 81 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 82 +#define GCC_CAMSS_AHB_CLK 83 +#define GCC_CAMSS_TOP_AHB_CLK 84 +#define GCC_CAMSS_CPP_AHB_CLK 85 +#define GCC_CAMSS_CPP_CLK 86 +#define GCC_CAMSS_VFE0_CLK 87 +#define GCC_CAMSS_VFE_AHB_CLK 88 +#define GCC_CAMSS_VFE_AXI_CLK 89 +#define GCC_CRYPTO_AHB_CLK 90 +#define GCC_CRYPTO_AXI_CLK 91 +#define GCC_CRYPTO_CLK 92 +#define GCC_OXILI_GMEM_CLK 93 +#define GCC_GP1_CLK 94 +#define GCC_GP2_CLK 95 +#define GCC_GP3_CLK 96 +#define GCC_MDSS_AHB_CLK 97 +#define GCC_MDSS_AXI_CLK 98 +#define GCC_MDSS_BYTE0_CLK 99 +#define GCC_MDSS_ESC0_CLK 100 +#define GCC_MDSS_MDP_CLK 101 +#define GCC_MDSS_PCLK0_CLK 102 +#define GCC_MDSS_VSYNC_CLK 103 +#define GCC_MSS_CFG_AHB_CLK 104 +#define GCC_OXILI_AHB_CLK 105 +#define GCC_OXILI_GFX3D_CLK 106 +#define GCC_PDM2_CLK 107 +#define GCC_PDM_AHB_CLK 108 +#define GCC_PRNG_AHB_CLK 109 +#define GCC_SDCC1_AHB_CLK 110 +#define GCC_SDCC1_APPS_CLK 111 +#define GCC_SDCC2_AHB_CLK 112 +#define GCC_SDCC2_APPS_CLK 113 +#define GCC_GTCU_AHB_CLK 114 +#define GCC_JPEG_TBU_CLK 115 +#define GCC_MDP_TBU_CLK 116 +#define GCC_SMMU_CFG_CLK 117 +#define GCC_VENUS_TBU_CLK 118 +#define GCC_VFE_TBU_CLK 119 +#define GCC_USB2A_PHY_SLEEP_CLK 120 +#define GCC_USB_HS_AHB_CLK 121 +#define GCC_USB_HS_SYSTEM_CLK 122 +#define GCC_VENUS0_AHB_CLK 123 +#define GCC_VENUS0_AXI_CLK 124 +#define GCC_VENUS0_VCODEC0_CLK 125 +#define GCC_APSS_TCU_CLK 126 +#define GCC_GFX_TCU_CLK 127 +#define GCC_BIMC_GFX_CLK 128 +#define GCC_BIMC_GPU_CLK 129 +#define GCC_MSS_Q6_BIMC_AXI_CLK 130 +#define GCC_GFX_TBU_CLK 131 +#define GCC_CPP_TBU_CLK 132 +#define USB_FS_SYSTEM_CLK_SRC 133 +#define USB_FS_IC_CLK_SRC 134 +#define GCC_USB_FS_AHB_CLK 135 +#define GCC_USB_FS_IC_CLK 136 +#define GCC_USB_FS_SYSTEM_CLK 137 +#define GCC_VENUS0_CORE0_VCODEC0_CLK 138 +#define GCC_VENUS0_CORE1_VCODEC0_CLK 139 +#define GCC_OXILI_TIMER_CLK 140 +#define GCC_USB_HS_PHY_CFG_AHB_CLK 141 +#define CSI2_CLK_SRC 142 +#define GCC_CAMSS_CSI2_AHB_CLK 143 +#define GCC_CAMSS_CSI2_CLK 144 +#define GCC_CAMSS_CSI2PHY_CLK 145 +#define GCC_CAMSS_CSI2PIX_CLK 146 +#define GCC_CAMSS_CSI2RDI_CLK 147 +#define SDCC1_ICE_CORE_CLK_SRC 148 +#define GCC_SDCC1_ICE_CORE_CLK 149 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 150 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 151 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 152 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 153 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 154 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 155 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 156 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 157 +#define BLSP2_UART1_APPS_CLK_SRC 158 +#define BLSP2_UART2_APPS_CLK_SRC 159 +#define GCC_BLSP2_AHB_CLK 160 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 161 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 162 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 163 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 164 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 165 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 166 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 167 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 168 +#define GCC_BLSP2_UART1_APPS_CLK 169 +#define GCC_BLSP2_UART2_APPS_CLK 170 +#define VFE1_CLK_SRC 171 +#define GCC_CAMSS_VFE1_CLK 172 +#define GCC_CAMSS_VFE1_AHB_CLK 173 +#define GCC_CAMSS_VFE1_AXI_CLK 174 +#define GCC_CAMSS_CSI_VFE1_CLK 175 +#define MCLK2_CLK_SRC 176 +#define GCC_CAMSS_MCLK2_CLK 177 +#define GCC_VFE1_TBU_CLK 178 +#define GCC_IPA_TBU_CLK 179 +#define GCC_CAMSS_CPP_AXI_CLK 180 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2026 08:39:17 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:11 +0300 Subject: [PATCH RFC 02/20] clk: qcom: Add global clock controller driver for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-2-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=100158; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=7WR0OwcYW8xxxGTh5D3tOzMUgqbxLxEiKMAhDORw92E=; b=plAmjYlyrZy11qj/0mcrd9XEzvd73TJwArU+oLEXxKPYApflXusgeYrGgkm3qBFVBi6ah23eN Ej5iK8NNdL9Ci/HB6k8bOsZiWSnjv1IB69LdxqG6dXhh7Z/ctU6ESzn X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir This driver provides clocks, resets and power domains needed for various components of the MSM8952. Some downstreams merge MSM8952 to MSM8917 and MSM8937. But upstreamed GCC driver for 8917 series has different pll structure and ported from different GCC driver. Downstream Reference: [1] [1] https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-wea= r-7.0.0_r0.3/drivers/clk/qcom/clock-gcc-8952.c Signed-off-by: Muzaffer Kadir --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-msm8952.c | 3576 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 3587 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6ef083f5d9e2..7577d87c05ec 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -778,6 +778,16 @@ config MSM_GCC_8939 Say Y if you want to use devices such as UART, SPI i2c, USB, SD/eMMC, display, graphics, camera etc. =20 +config MSM_GCC_8952 + tristate "MSM8952 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + default ARCH_QCOM + help + Support for the global clock controller on msm8952 devices. + Say Y if you want to use devices such as UART, SPI i2c, USB, + SD/eMMC, display, graphics, camera etc. + config MSM_GCC_8960 tristate "APQ8064/MSM8960 Global Clock Controller" depends on ARM || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index a6c676f68b79..3c3f27dcc68d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_MSM_GCC_8909) +=3D gcc-msm8909.o obj-$(CONFIG_MSM_GCC_8916) +=3D gcc-msm8916.o obj-$(CONFIG_MSM_GCC_8917) +=3D gcc-msm8917.o obj-$(CONFIG_MSM_GCC_8939) +=3D gcc-msm8939.o +obj-$(CONFIG_MSM_GCC_8952) +=3D gcc-msm8952.o obj-$(CONFIG_MSM_GCC_8953) +=3D gcc-msm8953.o obj-$(CONFIG_MSM_GCC_8960) +=3D gcc-msm8960.o obj-$(CONFIG_MSM_GCC_8974) +=3D gcc-msm8974.o diff --git a/drivers/clk/qcom/gcc-msm8952.c b/drivers/clk/qcom/gcc-msm8952.c new file mode 100644 index 000000000000..e75bf51ad408 --- /dev/null +++ b/drivers/clk/qcom/gcc-msm8952.c @@ -0,0 +1,3576 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Linaro Limited + * Copyright 2026 Muzaffer Kadir + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-alpha-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "reset.h" +#include "gdsc.h" + +enum { + P_XO, + P_XO_A, + P_GPLL0, + P_GPLL0_OUT_MAIN, + P_GPLL0_AUX, + P_GPLL3, + P_GPLL4, + P_GPLL6, + P_GPLL6_AUX, + P_GPLL6_OUT_MAIN, + P_DSI0_PHYPLL_BYTE, + P_DSI0_PHYPLL_DSI, +}; + +static struct clk_pll gpll0 =3D { + .l_reg =3D 0x21004, + .m_reg =3D 0x21008, + .n_reg =3D 0x2100c, + .config_reg =3D 0x21014, + .mode_reg =3D 0x21000, + .status_reg =3D 0x2101c, + .status_bit =3D 17, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xo", + }, + .num_parents =3D 1, + .ops =3D &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll0_vote =3D { + .enable_reg =3D 0x45000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll0_vote", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + /* This clock is required for other ones to function. */ + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_pll_vote_ops, + }, +}; + +static const struct pll_vco gpll3_p_vco[] =3D { + { 700000000, 1400000000, 0 }, +}; + +static const struct alpha_pll_config gpll3_early_config =3D { + .l =3D 63, + .config_ctl_val =3D 0x4001055b, + .main_output_mask =3D BIT(0), + .test_ctl_val =3D 0x0, + .test_ctl_mask =3D GENMASK(31, 0), + .test_ctl_hi_val =3D 0x40000600, + .test_ctl_hi_mask =3D GENMASK(31, 0), + .alpha_en_mask =3D BIT(24), + .post_div_val =3D BIT(8), + .post_div_mask =3D GENMASK(11, 8), +}; + +static struct clk_alpha_pll gpll3_early =3D { + .offset =3D 0x22000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .vco_table =3D gpll3_p_vco, + .num_vco =3D ARRAY_SIZE(gpll3_p_vco), + .flags =3D SUPPORTS_DYNAMIC_UPDATE, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll3_early", + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xo", + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + }, +}; + +static struct clk_alpha_pll_postdiv gpll3 =3D { + .offset =3D 0x22000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll3", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll3_early.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_pll gpll4 =3D { + .l_reg =3D 0x24004, + .m_reg =3D 0x24008, + .n_reg =3D 0x2400c, + .config_reg =3D 0x24018, + .mode_reg =3D 0x24000, + .status_reg =3D 0x24000, + .status_bit =3D 30, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll4", + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xo", + }, + .num_parents =3D 1, + .ops =3D &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll4_vote =3D { + .enable_reg =3D 0x45000, + .enable_mask =3D BIT(5), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll4_vote", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll4.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_pll_vote_ops, + }, +}; + +static struct clk_pll gpll6 =3D { + .l_reg =3D 0x37004, + .m_reg =3D 0x37008, + .n_reg =3D 0x3700c, + .config_reg =3D 0x37014, + .mode_reg =3D 0x37000, + .status_reg =3D 0x3701c, + .status_bit =3D 17, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll6", + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xo", + }, + .num_parents =3D 1, + .ops =3D &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll6_vote =3D { + .enable_reg =3D 0x45000, + .enable_mask =3D BIT(7), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll6_vote", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll6.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_pll_vote_ops, + }, +}; + +static const struct parent_map gcc_xo_gpll0_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 1 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_parent_data[] =3D { + { .fw_name =3D "xo" }, + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_out_main_map[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_out_main_parent_data[] = =3D { + { .fw_name =3D "xo" }, + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct parent_map gcc_xo_a_gpll0_map[] =3D { + { P_XO_A, 0 }, + { P_GPLL0, 1 }, +}; + +static const struct clk_parent_data gcc_xo_a_gpll0_parent_data[] =3D { + { .fw_name =3D "xo_a" }, + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll3_gpll6a_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL3, 2 }, + { P_GPLL6_AUX, 3 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll3_gpll6a_parent_data[= ] =3D { + { .fw_name =3D "xo" }, + { .hw =3D &gpll0_vote.hw }, + { .hw =3D &gpll3.clkr.hw }, + { .hw =3D &gpll6_vote.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll4_parent_data[] =3D { + { .fw_name =3D "xo" }, + { .hw =3D &gpll0_vote.hw }, + { .hw =3D &gpll4_vote.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll6_map[] =3D { + { P_XO, 0 }, + { P_GPLL6, 2 }, + { P_GPLL0, 1 }, +}; + +static const struct parent_map gcc_xo_gpll6_out_main_map[] =3D { + { P_XO, 0 }, + { P_GPLL6_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll6_parent_data[] =3D { + { .fw_name =3D "xo" }, + { .hw =3D &gpll6_vote.hw }, + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct parent_map gcc_xo_gpll0a_map[] =3D { + { P_XO, 0 }, + { P_GPLL0_AUX, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] =3D { + { .fw_name =3D "xo" }, + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct clk_parent_data gcc_gpll0_parent_data[] =3D { + { .hw =3D &gpll0_vote.hw }, +}; + +static const struct parent_map gcc_gpll0_map[] =3D { + { P_GPLL0, 1 }, +}; + +static const struct parent_map gcc_xo_map[] =3D { + { P_XO, 0, }, +}; + +static const struct clk_parent_data gcc_xo_parent_data[] =3D { + { .fw_name =3D "xo" }, +}; + +static const struct parent_map gcc_xo_dsibyte_map[] =3D { + { P_XO, 0 }, + { P_DSI0_PHYPLL_BYTE, 1 }, +}; + +static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] =3D { + { .fw_name =3D "xo" }, + { .fw_name =3D "dsi0pllbyte", .name =3D "dsi0pllbyte" }, +}; + +static const struct parent_map gcc_xo_dsiphy_map[] =3D { + { P_XO, 0 }, + { P_DSI0_PHYPLL_DSI, 1 }, +}; + +static const struct clk_parent_data gcc_xo_dsiphy_parent_data[] =3D { + { .fw_name =3D "xo" }, + { .fw_name =3D "dsi0pll", .name =3D "dsi0pll" }, +}; + +static const struct parent_map gcc_xo_gpll0_dsiphy_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_DSI0_PHYPLL_DSI, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_dsiphy_parent_data[] =3D { + { .fw_name =3D "xo" }, + { .hw =3D &gpll0_vote.hw }, + { .fw_name =3D "dsi0pll", .name =3D "dsi0pll" }, +}; + +static const struct clk_parent_data gcc_xo_gpll6_out_main_parent_data[] = =3D { + { .fw_name =3D "xo" }, + { .hw =3D &gpll6_vote.hw }, +}; + +static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] =3D { + F(40000000, P_GPLL0, 10, 1, 2), + F(61540000, P_GPLL0, 13, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + { } +}; + +static struct clk_rcg2 camss_top_ahb_clk_src =3D { + .cmd_rcgr =3D 0x5a000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_top_ahb_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "camss_top_ahb_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_apss_ahb_clk[] =3D { + F(19200000, P_XO_A, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(133330000, P_GPLL0, 6, 0, 0), + { } +}; + +static struct clk_rcg2 apss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x46000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_a_gpll0_map, + .freq_tbl =3D ftbl_apss_ahb_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "apss_ahb_clk_src", + .parent_data =3D gcc_xo_a_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_a_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + /* + * This clock allows the CPUs to communicate with + * the rest of the SoC. Without it, the brain will + * operate without the rest of the body. + */ + .flags =3D CLK_IS_CRITICAL, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csi0_1_2_clk[] =3D { + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 csi0_clk_src =3D { + .cmd_rcgr =3D 0x4e020, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_csi0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "csi0_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi1_clk_src =3D { + .cmd_rcgr =3D 0x4f020, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_csi0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "csi1_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi2_clk_src =3D { + .cmd_rcgr =3D 0x3c020, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_csi0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "csi2_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(228570000, P_GPLL0, 3.5, 0, 0), + F(240000000, P_GPLL6_AUX, 4.5, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(400000000, P_GPLL0, 2, 0, 0), + F(465000000, P_GPLL3, 1, 0, 0), + F(500000000, P_GPLL3, 1, 0, 0), + F(550000000, P_GPLL3, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gfx3d_clk_src =3D { + .cmd_rcgr =3D 0x59000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll3_gpll6a_map, + .freq_tbl =3D ftbl_gcc_oxili_gfx3d_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gfx3d_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll3_gpll6a_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll3_gpll6a_parent_data), + .ops =3D &clk_rcg2_ops, + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] =3D { + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(133330000, P_GPLL0, 6, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(177780000, P_GPLL0, 4.5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(308570000, P_GPLL6, 3.5, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + F(360000000, P_GPLL6, 3, 0, 0), + { } +}; + +static struct clk_rcg2 vfe0_clk_src =3D { + .cmd_rcgr =3D 0x58000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_vfe0_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "vfe0_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 vfe1_clk_src =3D { + .cmd_rcgr =3D 0x58054, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_vfe0_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "vfe1_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x0200c, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup1_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] =3D { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(16000000, P_GPLL0, 10, 1, 5), + F(19200000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0, 16, 1, 2), + F(50000000, P_GPLL0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x02024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup1_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x03000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup2_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x03014, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup2_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x04000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup3_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x04024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup3_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x05000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup4_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x05024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup4_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] =3D { + F(3686400, P_GPLL0, 1, 72, 15625), + F(7372800, P_GPLL0, 1, 144, 15625), + F(14745600, P_GPLL0, 1, 288, 15625), + F(16000000, P_GPLL0, 10, 1, 5), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 1, 3, 100), + F(25000000, P_GPLL0, 16, 1, 2), + F(32000000, P_GPLL0, 1, 1, 25), + F(40000000, P_GPLL0, 1, 1, 20), + F(46400000, P_GPLL0, 1, 29, 500), + F(48000000, P_GPLL0, 1, 3, 50), + F(51200000, P_GPLL0, 1, 8, 125), + F(56000000, P_GPLL0, 1, 7, 100), + F(58982400, P_GPLL0, 1, 1152, 15625), + F(60000000, P_GPLL0, 1, 3, 40), + { } +}; + +static struct clk_rcg2 blsp1_uart1_apps_clk_src =3D { + .cmd_rcgr =3D 0x02044, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_uart1_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart2_apps_clk_src =3D { + .cmd_rcgr =3D 0x03034, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_uart2_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x0c00c, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup1_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x0c024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup1_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x0d000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup2_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x0d014, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup2_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x0f000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup3_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x0f024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup3_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x18000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup4_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x18024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_qup1_6_spi_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup4_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_uart1_apps_clk_src =3D { + .cmd_rcgr =3D 0x0c044, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_uart1_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp2_uart2_apps_clk_src =3D { + .cmd_rcgr =3D 0x0d034, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_blsp1_uart1_6_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_uart2_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_cci_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + F(37500000, P_GPLL0_AUX, 1, 3, 64), + { } +}; + +static struct clk_rcg2 cci_clk_src =3D { + .cmd_rcgr =3D 0x51000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0a_map, + .freq_tbl =3D ftbl_gcc_camss_cci_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "cci_clk_src", + .parent_data =3D gcc_xo_gpll0a_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0a_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_camss_gp0_1_clk_src[] =3D { + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 camss_gp0_clk_src =3D { + .cmd_rcgr =3D 0x54000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_gpll0_map, + .freq_tbl =3D ftbl_camss_gp0_1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "camss_gp0_clk_src", + .parent_data =3D gcc_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 camss_gp1_clk_src =3D { + .cmd_rcgr =3D 0x55000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_gpll0_map, + .freq_tbl =3D ftbl_camss_gp0_1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "camss_gp1_clk_src", + .parent_data =3D gcc_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] =3D { + F(133330000, P_GPLL0, 6, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 jpeg0_clk_src =3D { + .cmd_rcgr =3D 0x57000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_jpeg0_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "jpeg0_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_mclk0_1_2_clk[] =3D { + F(6150000, P_GPLL0, 1, 1, 130), + F(8000000, P_GPLL0, 1, 1, 100), + F(24000000, P_GPLL6, 1, 1, 45), + F(66670000, P_GPLL0, 12, 0, 0), + { } +}; + +static struct clk_rcg2 mclk0_clk_src =3D { + .cmd_rcgr =3D 0x52000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_mclk0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "mclk0_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 mclk1_clk_src =3D { + .cmd_rcgr =3D 0x53000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_mclk0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "mclk1_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 mclk2_clk_src =3D { + .cmd_rcgr =3D 0x5c000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_mclk0_1_2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "mclk2_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] =3D { + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 csi0phytimer_clk_src =3D { + .cmd_rcgr =3D 0x4e000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_csi0_1phytimer_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "csi0phytimer_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi1phytimer_clk_src =3D { + .cmd_rcgr =3D 0x4f000, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_camss_csi0_1phytimer_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "csi1phytimer_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] =3D { + F(133330000, P_GPLL0, 6, 0, 0), + F(180000000, P_GPLL6, 6, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(308570000, P_GPLL6, 3.5, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cpp_clk_src =3D { + .cmd_rcgr =3D 0x58018, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_camss_cpp_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "cpp_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_crypto_clk[] =3D { + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + { } +}; + +static struct clk_rcg2 crypto_clk_src =3D { + .cmd_rcgr =3D 0x16004, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_crypto_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "crypto_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +/* + * This is a frequency table for "General Purpose" clocks. + * These clocks can be muxed to the SoC pins and may be used by + * external devices. They're often used as PWM source. + * + * Please note that MND divider must be enabled for duty-cycle + * control to be possible. (M !=3D N) Also since D register is configured + * with a value multiplied by 2, and duty cycle is calculated as + * (2 * D) % 2^W + * DutyCycle =3D ---------------- + * 2 * (N % 2^W) + * (where W =3D .mnd_width) + * N must be half or less than maximum value for the register. + * Otherwise duty-cycle control would be limited. + * (e.g. for 8-bit NMD N should be less than 128) + */ +static const struct freq_tbl ftbl_gcc_gp1_3_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gp1_clk_src =3D { + .cmd_rcgr =3D 0x08004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_gpll0_map, + .freq_tbl =3D ftbl_gcc_gp1_3_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gp1_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_vote.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gp2_clk_src =3D { + .cmd_rcgr =3D 0x09004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_gpll0_map, + .freq_tbl =3D ftbl_gcc_gp1_3_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gp2_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_vote.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gp3_clk_src =3D { + .cmd_rcgr =3D 0x0a004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_gpll0_map, + .freq_tbl =3D ftbl_gcc_gp1_3_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gp3_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_vote.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 byte0_clk_src =3D { + .cmd_rcgr =3D 0x4d044, + .hid_width =3D 5, + .parent_map =3D gcc_xo_dsibyte_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "byte0_clk_src", + .parent_data =3D gcc_xo_dsibyte_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_dsibyte_parent_data), + .ops =3D &clk_byte2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 esc0_clk_src =3D { + .cmd_rcgr =3D 0x4d05c, + .hid_width =3D 5, + .parent_map =3D gcc_xo_map, + .freq_tbl =3D ftbl_gcc_mdss_esc_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "esc0_clk_src", + .parent_data =3D gcc_xo_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] =3D { + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(145450000, P_GPLL0, 5.5, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(177780000, P_GPLL0, 4.5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 mdp_clk_src =3D { + .cmd_rcgr =3D 0x4d014, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_dsiphy_map, + .freq_tbl =3D ftbl_gcc_mdss_mdp_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "mdp_clk_src", + .parent_data =3D gcc_xo_gpll0_dsiphy_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_dsiphy_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 pclk0_clk_src =3D { + .cmd_rcgr =3D 0x4d000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_dsiphy_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "pclk0_clk_src", + .parent_data =3D gcc_xo_dsiphy_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_dsiphy_parent_data), + .ops =3D &clk_pixel_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] =3D { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 vsync_clk_src =3D { + .cmd_rcgr =3D 0x4d02c, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0a_map, + .freq_tbl =3D ftbl_gcc_mdss_vsync_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "vsync_clk_src", + .parent_data =3D gcc_xo_gpll0a_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0a_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk[] =3D { + F(64000000, P_GPLL0, 12.5, 0, 0), + { } +}; + +static struct clk_rcg2 pdm2_clk_src =3D { + .cmd_rcgr =3D 0x44010, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_pdm2_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "pdm2_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] =3D { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_GPLL0, 10, 1, 4), + F(25000000, P_GPLL0, 16, 1, 2), + F(50000000, P_GPLL0, 16, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(177770000, P_GPLL0, 4.5, 0, 0), + F(192000000, P_GPLL4, 6, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(384000000, P_GPLL4, 3, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x42004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll4_map, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "sdcc1_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll4_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll4_parent_data), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] =3D { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_GPLL0, 10, 1, 4), + F(25000000, P_GPLL0, 16, 1, 2), + F(50000000, P_GPLL0, 16, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(177770000, P_GPLL0, 4.5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc2_apps_clk_src =3D { + .cmd_rcgr =3D 0x43004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_sdcc2_apps_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "sdcc2_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk[] =3D { + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x5d000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_out_main_map, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "sdcc1_ice_core_clk_src", + .parent_data =3D gcc_xo_gpll0_out_main_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_out_main_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0x5d014, + .clkr =3D { + .enable_reg =3D 0x5d014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] =3D { + F(57140000, P_GPLL0, 14, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(133330000, P_GPLL0, 6, 0, 0), + F(177780000, P_GPLL0, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 usb_hs_system_clk_src =3D { + .cmd_rcgr =3D 0x41010, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_map, + .freq_tbl =3D ftbl_gcc_usb_hs_system_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "usb_hs_system_clk_src", + .parent_data =3D gcc_xo_gpll0_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] =3D { + F(64000000, P_GPLL0_AUX, 12.5, 0, 0), + { } +}; + +static struct clk_rcg2 usb_fs_system_clk_src =3D { + .cmd_rcgr =3D 0x3f010, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0a_map, + .freq_tbl =3D ftbl_gcc_usb_fs_system_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "usb_fs_system_clk_src", + .parent_data =3D gcc_xo_gpll0a_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0a_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] =3D { + F(60000000, P_GPLL6_OUT_MAIN, 9, 1, 2), + { } +}; + +static struct clk_rcg2 usb_fs_ic_clk_src =3D { + .cmd_rcgr =3D 0x3f034, + .hid_width =3D 5, + .mnd_width =3D 8, + .parent_map =3D gcc_xo_gpll6_out_main_map, + .freq_tbl =3D ftbl_gcc_usb_fs_ic_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "usb_fs_ic_clk_src", + .parent_data =3D gcc_xo_gpll6_out_main_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll6_out_main_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] =3D { + F(133330000, P_GPLL0, 6, 0, 0), + F(180000000, P_GPLL6, 6, 0, 0), + F(228570000, P_GPLL0, 3.5, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(308570000, P_GPLL6, 3.5, 0, 0), + { } +}; + +static struct clk_rcg2 vcodec0_clk_src =3D { + .cmd_rcgr =3D 0x4C000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_xo_gpll0_gpll6_map, + .freq_tbl =3D ftbl_gcc_venus0_vcodec0_clk, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "vcodec0_clk_src", + .parent_data =3D gcc_xo_gpll0_gpll6_parent_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_gpll6_parent_data), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_blsp1_ahb_clk =3D { + .halt_reg =3D 0x01008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(10), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk =3D { + .halt_reg =3D 0x02008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x02008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup1_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk =3D { + .halt_reg =3D 0x02004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x02004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup1_spi_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup1_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk =3D { + .halt_reg =3D 0x03010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x03010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup2_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk =3D { + .halt_reg =3D 0x0300c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0300c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup2_spi_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup2_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk =3D { + .halt_reg =3D 0x04020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x04020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup3_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk =3D { + .halt_reg =3D 0x0401c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0401c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup3_spi_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup3_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk =3D { + .halt_reg =3D 0x05020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x05020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup4_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk =3D { + .halt_reg =3D 0x0501c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0501c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup4_spi_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup4_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart1_apps_clk =3D { + .halt_reg =3D 0x0203c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0203c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_uart1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_uart1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart2_apps_clk =3D { + .halt_reg =3D 0x0302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_uart2_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_uart2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_ahb_clk =3D { + .halt_reg =3D 0x0b008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(20), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk =3D { + .halt_reg =3D 0x0c008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0c008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup1_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup1_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup1_spi_apps_clk =3D { + .halt_reg =3D 0x0c004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0c004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup1_spi_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup1_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_uart1_apps_clk =3D { + .halt_reg =3D 0x0c03c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0c03c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_uart1_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_uart1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk =3D { + .halt_reg =3D 0x0d010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0d010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup2_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup2_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup2_spi_apps_clk =3D { + .halt_reg =3D 0x0d00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0d00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup2_spi_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup2_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_uart2_apps_clk =3D { + .halt_reg =3D 0x0d02c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0d02c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_uart2_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_uart2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk =3D { + .halt_reg =3D 0x0f020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0f020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup3_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup3_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup3_spi_apps_clk =3D { + .halt_reg =3D 0x0f01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x0f01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup3_spi_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup3_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk =3D { + .halt_reg =3D 0x18020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x18020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup4_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup4_spi_apps_clk =3D { + .halt_reg =3D 0x1801c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1801c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup4_spi_apps_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &blsp2_qup4_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x1300c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(7), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cci_ahb_clk =3D { + .halt_reg =3D 0x5101c, + .clkr =3D { + .enable_reg =3D 0x5101c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_cci_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cci_clk =3D { + .halt_reg =3D 0x51018, + .clkr =3D { + .enable_reg =3D 0x51018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_cci_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &cci_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0_ahb_clk =3D { + .halt_reg =3D 0x4e040, + .clkr =3D { + .enable_reg =3D 0x4e040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0_clk =3D { + .halt_reg =3D 0x4e03c, + .clkr =3D { + .enable_reg =3D 0x4e03c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0phy_clk =3D { + .halt_reg =3D 0x4e048, + .clkr =3D { + .enable_reg =3D 0x4e048, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0phy_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0pix_clk =3D { + .halt_reg =3D 0x4e058, + .clkr =3D { + .enable_reg =3D 0x4e058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0pix_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0rdi_clk =3D { + .halt_reg =3D 0x4e050, + .clkr =3D { + .enable_reg =3D 0x4e050, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0rdi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1_ahb_clk =3D { + .halt_reg =3D 0x4f040, + .clkr =3D { + .enable_reg =3D 0x4f040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1_clk =3D { + .halt_reg =3D 0x4f03c, + .clkr =3D { + .enable_reg =3D 0x4f03c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1phy_clk =3D { + .halt_reg =3D 0x4f048, + .clkr =3D { + .enable_reg =3D 0x4f048, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1phy_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1pix_clk =3D { + .halt_reg =3D 0x4f058, + .clkr =3D { + .enable_reg =3D 0x4f058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1pix_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1rdi_clk =3D { + .halt_reg =3D 0x4f050, + .clkr =3D { + .enable_reg =3D 0x4f050, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1rdi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2_ahb_clk =3D { + .halt_reg =3D 0x3c040, + .clkr =3D { + .enable_reg =3D 0x3c040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi2_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2_clk =3D { + .halt_reg =3D 0x3c03c, + .clkr =3D { + .enable_reg =3D 0x3c03c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2phy_clk =3D { + .halt_reg =3D 0x3c048, + .clkr =3D { + .enable_reg =3D 0x3c048, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi2phy_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2pix_clk =3D { + .halt_reg =3D 0x3c058, + .clkr =3D { + .enable_reg =3D 0x3c058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi2pix_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2rdi_clk =3D { + .halt_reg =3D 0x3c050, + .clkr =3D { + .enable_reg =3D 0x3c050, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi2rdi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk2_clk =3D { + .halt_reg =3D 0x5c018, + .clkr =3D { + .enable_reg =3D 0x5c018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_mclk2_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &mclk2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi_vfe0_clk =3D { + .halt_reg =3D 0x58050, + .clkr =3D { + .enable_reg =3D 0x58050, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi_vfe0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vfe0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_gp0_clk =3D { + .halt_reg =3D 0x54018, + .clkr =3D { + .enable_reg =3D 0x54018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_gp0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_gp0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_gp1_clk =3D { + .halt_reg =3D 0x55018, + .clkr =3D { + .enable_reg =3D 0x55018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_ispif_ahb_clk =3D { + .halt_reg =3D 0x50004, + .clkr =3D { + .enable_reg =3D 0x50004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_ispif_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg0_clk =3D { + .halt_reg =3D 0x57020, + .clkr =3D { + .enable_reg =3D 0x57020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_jpeg0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &jpeg0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg_ahb_clk =3D { + .halt_reg =3D 0x57024, + .clkr =3D { + .enable_reg =3D 0x57024, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_jpeg_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg_axi_clk =3D { + .halt_reg =3D 0x57028, + .clkr =3D { + .enable_reg =3D 0x57028, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_jpeg_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk0_clk =3D { + .halt_reg =3D 0x52018, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_mclk0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &mclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk1_clk =3D { + .halt_reg =3D 0x53018, + .clkr =3D { + .enable_reg =3D 0x53018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_mclk1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &mclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_micro_ahb_clk =3D { + .halt_reg =3D 0x5600c, + .clkr =3D { + .enable_reg =3D 0x5600c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_micro_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0phytimer_clk =3D { + .halt_reg =3D 0x4e01c, + .clkr =3D { + .enable_reg =3D 0x4e01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi0phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi0phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1phytimer_clk =3D { + .halt_reg =3D 0x4f01c, + .clkr =3D { + .enable_reg =3D 0x4f01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi1phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &csi1phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_ahb_clk =3D { + .halt_reg =3D 0x56004, + .clkr =3D { + .enable_reg =3D 0x56004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_top_ahb_clk =3D { + .halt_reg =3D 0x5a014, + .clkr =3D { + .enable_reg =3D 0x5a014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_top_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe0_ahb_clk =3D { + .halt_reg =3D 0x58044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x58044, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data) { + .name =3D "gcc_camss_vfe0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + .flags =3D CLK_SET_RATE_PARENT, + } + } +}; + +static struct clk_branch gcc_camss_vfe0_axi_clk =3D { + .halt_reg =3D 0x58048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x58048, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data) { + .name =3D "gcc_camss_vfe0_axi_clk", + .ops =3D &clk_branch2_ops, + } + } +}; + +static struct clk_branch gcc_camss_cpp_ahb_clk =3D { + .halt_reg =3D 0x58040, + .clkr =3D { + .enable_reg =3D 0x58040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_cpp_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_clk =3D { + .halt_reg =3D 0x5803c, + .clkr =3D { + .enable_reg =3D 0x5803c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_cpp_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &cpp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe0_clk =3D { + .halt_reg =3D 0x58038, + .clkr =3D { + .enable_reg =3D 0x58038, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_vfe0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vfe0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe_ahb_clk =3D { + .halt_reg =3D 0x58044, + .clkr =3D { + .enable_reg =3D 0x58044, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_vfe_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe_axi_clk =3D { + .halt_reg =3D 0x58048, + .clkr =3D { + .enable_reg =3D 0x58048, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_vfe_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_axi_clk =3D { + .halt_reg =3D 0x58064, + .clkr =3D { + .enable_reg =3D 0x58064, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_cpp_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_ahb_clk =3D { + .halt_reg =3D 0x16024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_crypto_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_axi_clk =3D { + .halt_reg =3D 0x16020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(1), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_crypto_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_clk =3D { + .halt_reg =3D 0x1601c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(2), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &crypto_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_oxili_gmem_clk =3D { + .halt_reg =3D 0x59024, + .clkr =3D { + .enable_reg =3D 0x59024, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_oxili_gmem_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x08000, + .clkr =3D { + .enable_reg =3D 0x08000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x09000, + .clkr =3D { + .enable_reg =3D 0x09000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x0a000, + .clkr =3D { + .enable_reg =3D 0x0a000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_ahb_clk =3D { + .halt_reg =3D 0x4d07c, + .clkr =3D { + .enable_reg =3D 0x4d07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_axi_clk =3D { + .halt_reg =3D 0x4d080, + .clkr =3D { + .enable_reg =3D 0x4d080, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_byte0_clk =3D { + .halt_reg =3D 0x4d094, + .clkr =3D { + .enable_reg =3D 0x4d094, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_esc0_clk =3D { + .halt_reg =3D 0x4d098, + .clkr =3D { + .enable_reg =3D 0x4d098, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_mdp_clk =3D { + .halt_reg =3D 0x4D088, + .clkr =3D { + .enable_reg =3D 0x4D088, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x4d084, + .clkr =3D { + .enable_reg =3D 0x4d084, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdss_vsync_clk =3D { + .halt_reg =3D 0x4d090, + .clkr =3D { + .enable_reg =3D 0x4d090, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_cfg_ahb_clk =3D { + .halt_reg =3D 0x49000, + .clkr =3D { + .enable_reg =3D 0x49000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mss_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_q6_bimc_axi_clk =3D { + .halt_reg =3D 0x49004, + .clkr =3D { + .enable_reg =3D 0x49004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mss_q6_bimc_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_oxili_ahb_clk =3D { + .halt_reg =3D 0x59028, + .clkr =3D { + .enable_reg =3D 0x59028, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_oxili_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_oxili_gfx3d_clk =3D { + .halt_reg =3D 0x59020, + .clkr =3D { + .enable_reg =3D 0x59020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_oxili_gfx3d_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x4400c, + .clkr =3D { + .enable_reg =3D 0x4400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x44004, + .clkr =3D { + .enable_reg =3D 0x44004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk =3D { + .halt_reg =3D 0x13004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x45004, + .enable_mask =3D BIT(8), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_prng_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x4201c, + .clkr =3D { + .enable_reg =3D 0x4201c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x42018, + .clkr =3D { + .enable_reg =3D 0x42018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk =3D { + .halt_reg =3D 0x4301c, + .clkr =3D { + .enable_reg =3D 0x4301c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk =3D { + .halt_reg =3D 0x43018, + .clkr =3D { + .enable_reg =3D 0x43018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_apss_tcu_clk =3D { + .halt_reg =3D 0x12018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(1), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_apss_tcu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gfx_tcu_clk =3D { + .halt_reg =3D 0x12020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(2), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gfx_tcu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gfx_tbu_clk =3D { + .halt_reg =3D 0x12010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(3), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gfx_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdp_tbu_clk =3D { + .halt_reg =3D 0x1201c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(4), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdp_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus_tbu_clk =3D { + .halt_reg =3D 0x12014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(5), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi_vfe1_clk =3D { + .halt_reg =3D 0x58074, + .clkr =3D { + .enable_reg =3D 0x58074, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_csi_vfe1_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &vfe1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_clk =3D { + .halt_reg =3D 0x5805c, + .clkr =3D { + .enable_reg =3D 0x5805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_vfe1_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &vfe1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_ahb_clk =3D { + .halt_reg =3D 0x58060, + .clkr =3D { + .enable_reg =3D 0x58060, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_vfe1_ahb_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &camss_top_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_axi_clk =3D { + .halt_reg =3D 0x58068, + .clkr =3D { + .enable_reg =3D 0x58068, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camss_vfe1_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vfe_tbu_clk =3D { + .halt_reg =3D 0x1203c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(9), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_vfe_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_jpeg_tbu_clk =3D { + .halt_reg =3D 0x12034, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(10), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_jpeg_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_smmu_cfg_clk =3D { + .halt_reg =3D 0x12038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(12), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_smmu_cfg_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gtcu_ahb_clk =3D { + .halt_reg =3D 0x12044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(13), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gtcu_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpp_tbu_clk =3D { + .halt_reg =3D 0x12040, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(14), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpp_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vfe1_tbu_clk =3D { + .halt_reg =3D 0x12090, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(17), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_vfe1_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ipa_tbu_clk =3D { + .halt_reg =3D 0x120a0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4500c, + .enable_mask =3D BIT(16), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ipa_tbu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gfx_clk =3D { + .halt_reg =3D 0x59034, + .clkr =3D { + .enable_reg =3D 0x59034, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_bimc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gpu_clk =3D { + .halt_reg =3D 0x59030, + .clkr =3D { + .enable_reg =3D 0x59030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_bimc_gpu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2a_phy_sleep_clk =3D { + .halt_reg =3D 0x4102c, + .clkr =3D { + .enable_reg =3D 0x4102c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb2a_phy_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_fs_ahb_clk =3D { + .halt_reg =3D 0x3f008, + .clkr =3D { + .enable_reg =3D 0x3f008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_fs_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk =3D { + .halt_reg =3D 0x41030, + .clkr =3D { + .enable_reg =3D 0x41030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_hs_phy_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_fs_ic_clk =3D { + .halt_reg =3D 0x3f030, + .clkr =3D { + .enable_reg =3D 0x3f030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_fs_ic_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &usb_fs_ic_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_fs_system_clk =3D { + .halt_reg =3D 0x3f004, + .clkr =3D { + .enable_reg =3D 0x3f004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_fs_system_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &usb_fs_system_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_hs_ahb_clk =3D { + .halt_reg =3D 0x41008, + .clkr =3D { + .enable_reg =3D 0x41008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_hs_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_hs_system_clk =3D { + .halt_reg =3D 0x41004, + .clkr =3D { + .enable_reg =3D 0x41004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb_hs_system_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &usb_hs_system_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus0_ahb_clk =3D { + .halt_reg =3D 0x4c020, + .clkr =3D { + .enable_reg =3D 0x4c020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus0_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus0_axi_clk =3D { + .halt_reg =3D 0x4c024, + .clkr =3D { + .enable_reg =3D 0x4c024, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus0_vcodec0_clk =3D { + .halt_reg =3D 0x4c01c, + .clkr =3D { + .enable_reg =3D 0x4c01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus0_vcodec0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vcodec0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus0_core0_vcodec0_clk =3D { + .halt_reg =3D 0x4c02c, + .clkr =3D { + .enable_reg =3D 0x4c02c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus0_core0_vcodec0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vcodec0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus0_core1_vcodec0_clk =3D { + .halt_reg =3D 0x4c034, + .clkr =3D { + .enable_reg =3D 0x4c034, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_venus0_core1_vcodec0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &vcodec0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_oxili_timer_clk =3D { + .halt_reg =3D 0x59040, + .clkr =3D { + .enable_reg =3D 0x59040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_oxili_timer_clk", + .parent_data =3D &(const struct clk_parent_data){ + .fw_name =3D "xo", + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc venus_gdsc =3D { + .gdscr =3D 0x4c018, + .cxcs =3D (unsigned int []){ 0x4c024, 0x4c01c }, + .cxc_count =3D 2, + .pd =3D { + .name =3D "venus_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc mdss_gdsc =3D { + .gdscr =3D 0x4d078, + .cxcs =3D (unsigned int []){ 0x4d080, 0x4d088 }, + .cxc_count =3D 2, + .pd =3D { + .name =3D "mdss_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc jpeg_gdsc =3D { + .gdscr =3D 0x5701c, + .cxcs =3D (unsigned int []){ 0x57020, 0x57028 }, + .cxc_count =3D 2, + .pd =3D { + .name =3D "jpeg_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc vfe0_gdsc =3D { + .gdscr =3D 0x58034, + .cxcs =3D (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 }, + .cxc_count =3D 4, + .pd =3D { + .name =3D "vfe0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc vfe1_gdsc =3D { + .gdscr =3D 0x5806c, + .cxcs =3D (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 }, + .cxc_count =3D 4, + .pd =3D { + .name =3D "vfe1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc cpp_gdsc =3D { + .gdscr =3D 0x58078, + .cxcs =3D (unsigned int []){ 0x5803c, 0x58064 }, + .cxc_count =3D 2, + .pd =3D { + .name =3D "cpp_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc oxili_gx_gdsc =3D { + .gdscr =3D 0x5901c, + .cxcs =3D (unsigned int []){ 0x59000, 0x59024 }, + .cxc_count =3D 2, + .pd =3D { + .name =3D "oxili_gx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc venus_core0_gdsc =3D { + .gdscr =3D 0x4c028, + .cxcs =3D (unsigned int []){ 0x4c02c }, + .cxc_count =3D 1, + .pd =3D { + .name =3D "venus_core0_gdsc", + }, + .flags =3D HW_CTRL_TRIGGER, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc venus_core1_gdsc =3D { + .gdscr =3D 0x4c030, + .cxcs =3D (unsigned int []){ 0x4c034 }, + .cxc_count =3D 1, + .pd =3D { + .name =3D "venus_core1_gdsc", + }, + .flags =3D HW_CTRL_TRIGGER, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct clk_regmap *gcc_msm8952_clocks[] =3D { + [GPLL0] =3D &gpll0.clkr, + [GPLL0_VOTE] =3D &gpll0_vote, + [CAMSS_TOP_AHB_CLK_SRC] =3D &camss_top_ahb_clk_src.clkr, + [APSS_AHB_CLK_SRC] =3D &apss_ahb_clk_src.clkr, + [CSI0_CLK_SRC] =3D &csi0_clk_src.clkr, + [CSI1_CLK_SRC] =3D &csi1_clk_src.clkr, + [CSI2_CLK_SRC] =3D &csi2_clk_src.clkr, + [GFX3D_CLK_SRC] =3D &gfx3d_clk_src.clkr, + [VFE0_CLK_SRC] =3D &vfe0_clk_src.clkr, + [BLSP1_QUP1_I2C_APPS_CLK_SRC] =3D &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] =3D &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] =3D &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] =3D &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] =3D &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] =3D &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] =3D &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] =3D &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] =3D &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] =3D &blsp1_uart2_apps_clk_src.clkr, + [CCI_CLK_SRC] =3D &cci_clk_src.clkr, + [CAMSS_GP0_CLK_SRC] =3D &camss_gp0_clk_src.clkr, + [CAMSS_GP1_CLK_SRC] =3D &camss_gp1_clk_src.clkr, + [JPEG0_CLK_SRC] =3D &jpeg0_clk_src.clkr, + [MCLK0_CLK_SRC] =3D &mclk0_clk_src.clkr, + [MCLK1_CLK_SRC] =3D &mclk1_clk_src.clkr, + [CSI0PHYTIMER_CLK_SRC] =3D &csi0phytimer_clk_src.clkr, + [CSI1PHYTIMER_CLK_SRC] =3D &csi1phytimer_clk_src.clkr, + [CPP_CLK_SRC] =3D &cpp_clk_src.clkr, + [CRYPTO_CLK_SRC] =3D &crypto_clk_src.clkr, + [GP1_CLK_SRC] =3D &gp1_clk_src.clkr, + [GP2_CLK_SRC] =3D &gp2_clk_src.clkr, + [GP3_CLK_SRC] =3D &gp3_clk_src.clkr, + [BYTE0_CLK_SRC] =3D &byte0_clk_src.clkr, + [ESC0_CLK_SRC] =3D &esc0_clk_src.clkr, + [MDP_CLK_SRC] =3D &mdp_clk_src.clkr, + [PCLK0_CLK_SRC] =3D &pclk0_clk_src.clkr, + [VSYNC_CLK_SRC] =3D &vsync_clk_src.clkr, + [PDM2_CLK_SRC] =3D &pdm2_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] =3D &sdcc1_apps_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] =3D &sdcc2_apps_clk_src.clkr, + [SDCC1_ICE_CORE_CLK_SRC] =3D &sdcc1_ice_core_clk_src.clkr, + [USB_HS_SYSTEM_CLK_SRC] =3D &usb_hs_system_clk_src.clkr, + [VCODEC0_CLK_SRC] =3D &vcodec0_clk_src.clkr, + [GCC_BLSP1_AHB_CLK] =3D &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] =3D &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] =3D &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] =3D &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] =3D &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] =3D &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] =3D &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] =3D &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] =3D &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] =3D &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] =3D &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMSS_CCI_AHB_CLK] =3D &gcc_camss_cci_ahb_clk.clkr, + [GCC_CAMSS_CCI_CLK] =3D &gcc_camss_cci_clk.clkr, + [GCC_CAMSS_CSI0_AHB_CLK] =3D &gcc_camss_csi0_ahb_clk.clkr, + [GCC_CAMSS_CSI0_CLK] =3D &gcc_camss_csi0_clk.clkr, + [GCC_CAMSS_CSI0PHY_CLK] =3D &gcc_camss_csi0phy_clk.clkr, + [GCC_CAMSS_CSI0PIX_CLK] =3D &gcc_camss_csi0pix_clk.clkr, + [GCC_CAMSS_CSI0RDI_CLK] =3D &gcc_camss_csi0rdi_clk.clkr, + [GCC_CAMSS_CSI1_AHB_CLK] =3D &gcc_camss_csi1_ahb_clk.clkr, + [GCC_CAMSS_CSI1_CLK] =3D &gcc_camss_csi1_clk.clkr, + [GCC_CAMSS_CSI1PHY_CLK] =3D &gcc_camss_csi1phy_clk.clkr, + [GCC_CAMSS_CSI1PIX_CLK] =3D &gcc_camss_csi1pix_clk.clkr, + [GCC_CAMSS_CSI1RDI_CLK] =3D &gcc_camss_csi1rdi_clk.clkr, + [GCC_CAMSS_CSI2_AHB_CLK] =3D &gcc_camss_csi2_ahb_clk.clkr, + [GCC_CAMSS_CSI2_CLK] =3D &gcc_camss_csi2_clk.clkr, + [GCC_CAMSS_CSI2PHY_CLK] =3D &gcc_camss_csi2phy_clk.clkr, + [GCC_CAMSS_CSI2PIX_CLK] =3D &gcc_camss_csi2pix_clk.clkr, + [GCC_CAMSS_CSI2RDI_CLK] =3D &gcc_camss_csi2rdi_clk.clkr, + [GCC_CAMSS_CSI_VFE0_CLK] =3D &gcc_camss_csi_vfe0_clk.clkr, + [GCC_CAMSS_GP0_CLK] =3D &gcc_camss_gp0_clk.clkr, + [GCC_CAMSS_GP1_CLK] =3D &gcc_camss_gp1_clk.clkr, + [GCC_CAMSS_ISPIF_AHB_CLK] =3D &gcc_camss_ispif_ahb_clk.clkr, + [GCC_CAMSS_JPEG0_CLK] =3D &gcc_camss_jpeg0_clk.clkr, + [GCC_CAMSS_JPEG_AHB_CLK] =3D &gcc_camss_jpeg_ahb_clk.clkr, + [GCC_CAMSS_JPEG_AXI_CLK] =3D &gcc_camss_jpeg_axi_clk.clkr, + [GCC_CAMSS_MCLK0_CLK] =3D &gcc_camss_mclk0_clk.clkr, + [GCC_CAMSS_MCLK1_CLK] =3D &gcc_camss_mclk1_clk.clkr, + [GCC_CAMSS_MICRO_AHB_CLK] =3D &gcc_camss_micro_ahb_clk.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK] =3D &gcc_camss_csi0phytimer_clk.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK] =3D &gcc_camss_csi1phytimer_clk.clkr, + [GCC_CAMSS_AHB_CLK] =3D &gcc_camss_ahb_clk.clkr, + [GCC_CAMSS_TOP_AHB_CLK] =3D &gcc_camss_top_ahb_clk.clkr, + [GCC_CAMSS_VFE0_AHB_CLK] =3D &gcc_camss_vfe0_ahb_clk.clkr, + [GCC_CAMSS_VFE0_AXI_CLK] =3D &gcc_camss_vfe0_axi_clk.clkr, + [GCC_CAMSS_CPP_AHB_CLK] =3D &gcc_camss_cpp_ahb_clk.clkr, + [GCC_CAMSS_CPP_CLK] =3D &gcc_camss_cpp_clk.clkr, + [GCC_CAMSS_VFE0_CLK] =3D &gcc_camss_vfe0_clk.clkr, + [GCC_CAMSS_VFE_AHB_CLK] =3D &gcc_camss_vfe_ahb_clk.clkr, + [GCC_CAMSS_VFE_AXI_CLK] =3D &gcc_camss_vfe_axi_clk.clkr, + [GCC_CRYPTO_AHB_CLK] =3D &gcc_crypto_ahb_clk.clkr, + [GCC_CRYPTO_AXI_CLK] =3D &gcc_crypto_axi_clk.clkr, + [GCC_CRYPTO_CLK] =3D &gcc_crypto_clk.clkr, + [GCC_OXILI_GMEM_CLK] =3D &gcc_oxili_gmem_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_MDSS_AHB_CLK] =3D &gcc_mdss_ahb_clk.clkr, + [GCC_MDSS_AXI_CLK] =3D &gcc_mdss_axi_clk.clkr, + [GCC_MDSS_BYTE0_CLK] =3D &gcc_mdss_byte0_clk.clkr, + [GCC_MDSS_ESC0_CLK] =3D &gcc_mdss_esc0_clk.clkr, + [GCC_MDSS_MDP_CLK] =3D &gcc_mdss_mdp_clk.clkr, + [GCC_MDSS_PCLK0_CLK] =3D &gcc_mdss_pclk0_clk.clkr, + [GCC_MDSS_VSYNC_CLK] =3D &gcc_mdss_vsync_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] =3D &gcc_mss_cfg_ahb_clk.clkr, + [GCC_OXILI_AHB_CLK] =3D &gcc_oxili_ahb_clk.clkr, + [GCC_OXILI_GFX3D_CLK] =3D &gcc_oxili_gfx3d_clk.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PRNG_AHB_CLK] =3D &gcc_prng_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, + [GCC_GTCU_AHB_CLK] =3D &gcc_gtcu_ahb_clk.clkr, + [GCC_JPEG_TBU_CLK] =3D &gcc_jpeg_tbu_clk.clkr, + [GCC_MDP_TBU_CLK] =3D &gcc_mdp_tbu_clk.clkr, + [GCC_SMMU_CFG_CLK] =3D &gcc_smmu_cfg_clk.clkr, + [GCC_VENUS_TBU_CLK] =3D &gcc_venus_tbu_clk.clkr, + [GCC_VFE_TBU_CLK] =3D &gcc_vfe_tbu_clk.clkr, + [GCC_USB2A_PHY_SLEEP_CLK] =3D &gcc_usb2a_phy_sleep_clk.clkr, + [GCC_USB_HS_AHB_CLK] =3D &gcc_usb_hs_ahb_clk.clkr, + [GCC_USB_HS_SYSTEM_CLK] =3D &gcc_usb_hs_system_clk.clkr, + [GCC_VENUS0_AHB_CLK] =3D &gcc_venus0_ahb_clk.clkr, + [GCC_VENUS0_AXI_CLK] =3D &gcc_venus0_axi_clk.clkr, + [GCC_VENUS0_VCODEC0_CLK] =3D &gcc_venus0_vcodec0_clk.clkr, + [GCC_APSS_TCU_CLK] =3D &gcc_apss_tcu_clk.clkr, + [GCC_GFX_TCU_CLK] =3D &gcc_gfx_tcu_clk.clkr, + [GCC_BIMC_GFX_CLK] =3D &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_GPU_CLK] =3D &gcc_bimc_gpu_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] =3D &gcc_mss_q6_bimc_axi_clk.clkr, + [GPLL3] =3D &gpll3.clkr, + [GPLL3_EARLY] =3D &gpll3_early.clkr, + [GPLL4] =3D &gpll4.clkr, + [GPLL4_VOTE] =3D &gpll4_vote, + [GPLL6] =3D &gpll6.clkr, + [GPLL6_VOTE] =3D &gpll6_vote, + [GCC_GFX_TBU_CLK] =3D &gcc_gfx_tbu_clk.clkr, + [GCC_CPP_TBU_CLK] =3D &gcc_cpp_tbu_clk.clkr, + [USB_FS_SYSTEM_CLK_SRC] =3D &usb_fs_system_clk_src.clkr, + [USB_FS_IC_CLK_SRC] =3D &usb_fs_ic_clk_src.clkr, + [GCC_USB_FS_AHB_CLK] =3D &gcc_usb_fs_ahb_clk.clkr, + [GCC_USB_HS_PHY_CFG_AHB_CLK] =3D &gcc_usb_hs_phy_cfg_ahb_clk.clkr, + [GCC_USB_FS_IC_CLK] =3D &gcc_usb_fs_ic_clk.clkr, + [GCC_USB_FS_SYSTEM_CLK] =3D &gcc_usb_fs_system_clk.clkr, + [GCC_VENUS0_CORE0_VCODEC0_CLK] =3D &gcc_venus0_core0_vcodec0_clk.clkr, + [GCC_VENUS0_CORE1_VCODEC0_CLK] =3D &gcc_venus0_core1_vcodec0_clk.clkr, + [GCC_OXILI_TIMER_CLK] =3D &gcc_oxili_timer_clk.clkr, + [BLSP2_QUP1_I2C_APPS_CLK_SRC] =3D &blsp2_qup1_i2c_apps_clk_src.clkr, + [BLSP2_QUP1_SPI_APPS_CLK_SRC] =3D &blsp2_qup1_spi_apps_clk_src.clkr, + [BLSP2_QUP2_I2C_APPS_CLK_SRC] =3D &blsp2_qup2_i2c_apps_clk_src.clkr, + [BLSP2_QUP2_SPI_APPS_CLK_SRC] =3D &blsp2_qup2_spi_apps_clk_src.clkr, + [BLSP2_QUP3_I2C_APPS_CLK_SRC] =3D &blsp2_qup3_i2c_apps_clk_src.clkr, + [BLSP2_QUP3_SPI_APPS_CLK_SRC] =3D &blsp2_qup3_spi_apps_clk_src.clkr, + [BLSP2_QUP4_I2C_APPS_CLK_SRC] =3D &blsp2_qup4_i2c_apps_clk_src.clkr, + [BLSP2_QUP4_SPI_APPS_CLK_SRC] =3D &blsp2_qup4_spi_apps_clk_src.clkr, + [BLSP2_UART1_APPS_CLK_SRC] =3D &blsp2_uart1_apps_clk_src.clkr, + [BLSP2_UART2_APPS_CLK_SRC] =3D &blsp2_uart2_apps_clk_src.clkr, + [GCC_BLSP2_AHB_CLK] =3D &gcc_blsp2_ahb_clk.clkr, + [GCC_BLSP2_QUP1_I2C_APPS_CLK] =3D &gcc_blsp2_qup1_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP1_SPI_APPS_CLK] =3D &gcc_blsp2_qup1_spi_apps_clk.clkr, + [GCC_BLSP2_QUP2_I2C_APPS_CLK] =3D &gcc_blsp2_qup2_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP2_SPI_APPS_CLK] =3D &gcc_blsp2_qup2_spi_apps_clk.clkr, + [GCC_BLSP2_QUP3_I2C_APPS_CLK] =3D &gcc_blsp2_qup3_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP3_SPI_APPS_CLK] =3D &gcc_blsp2_qup3_spi_apps_clk.clkr, + [GCC_BLSP2_QUP4_I2C_APPS_CLK] =3D &gcc_blsp2_qup4_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP4_SPI_APPS_CLK] =3D &gcc_blsp2_qup4_spi_apps_clk.clkr, + [GCC_BLSP2_UART1_APPS_CLK] =3D &gcc_blsp2_uart1_apps_clk.clkr, + [GCC_BLSP2_UART2_APPS_CLK] =3D &gcc_blsp2_uart2_apps_clk.clkr, + [VFE1_CLK_SRC] =3D &vfe1_clk_src.clkr, + [GCC_CAMSS_VFE1_CLK] =3D &gcc_camss_vfe1_clk.clkr, + [GCC_CAMSS_VFE1_AHB_CLK] =3D &gcc_camss_vfe1_ahb_clk.clkr, + [GCC_CAMSS_VFE1_AXI_CLK] =3D &gcc_camss_vfe1_axi_clk.clkr, + [GCC_CAMSS_CSI_VFE1_CLK] =3D &gcc_camss_csi_vfe1_clk.clkr, + [MCLK2_CLK_SRC] =3D &mclk2_clk_src.clkr, + [GCC_CAMSS_MCLK2_CLK] =3D &gcc_camss_mclk2_clk.clkr, + [GCC_VFE1_TBU_CLK] =3D &gcc_vfe1_tbu_clk.clkr, + [GCC_IPA_TBU_CLK] =3D &gcc_ipa_tbu_clk.clkr, + [GCC_CAMSS_CPP_AXI_CLK] =3D &gcc_camss_cpp_axi_clk.clkr, +}; + +static struct gdsc *gcc_msm8952_gdscs[] =3D { + [CPP_GDSC] =3D &cpp_gdsc, + [VENUS_GDSC] =3D &venus_gdsc, + [MDSS_GDSC] =3D &mdss_gdsc, + [JPEG_GDSC] =3D &jpeg_gdsc, + [VFE0_GDSC] =3D &vfe0_gdsc, + [VFE1_GDSC] =3D &vfe1_gdsc, + [OXILI_GX_GDSC] =3D &oxili_gx_gdsc, + [VENUS_CORE0_GDSC] =3D &venus_core0_gdsc, + [VENUS_CORE1_GDSC] =3D &venus_core1_gdsc, +}; + +static const struct qcom_reset_map gcc_msm8952_resets[] =3D { + [RST_CAMSS_MICRO_BCR] =3D { 0x56008 }, + [RST_USB_HS_BCR] =3D { 0x41000 }, + [RST_QUSB2_PHY_BCR] =3D { 0x4103c }, + [RST_USB_HS_PHY_CFG_AHB_CBCR] =3D { 0x41030 }, + [RST_USB2_HS_PHY_ONLY_BCR] =3D { 0x41034 }, + [RST_USB_FS_BCR] =3D { 0x3f000 }, + [RST_CAMSS_CSI1PIX_CBCR] =3D { 0x4f058 }, + [RST_CAMSS_CSI_VFE1_CBCR] =3D { 0x58074 }, + [RST_CAMSS_VFE1_CBCR] =3D { 0x5805c }, + [RST_CAMSS_CPP_CBCR] =3D { 0x5803c }, + [RST_MSS_BCR] =3D { 0x71000 }, + [RST_MDSS_BCR] =3D { 0x4d074 }, +}; + +static const struct regmap_config gcc_msm8952_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x80000, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gcc_msm8952_desc =3D { + .config =3D &gcc_msm8952_regmap_config, + .clks =3D gcc_msm8952_clocks, + .num_clks =3D ARRAY_SIZE(gcc_msm8952_clocks), + .resets =3D gcc_msm8952_resets, + .num_resets =3D ARRAY_SIZE(gcc_msm8952_resets), + .gdscs =3D gcc_msm8952_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_msm8952_gdscs), +}; + +static const struct of_device_id gcc_msm8952_match_table[] =3D { + { .compatible =3D "qcom,gcc-msm8952" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_msm8952_match_table); + +static int gcc_msm8952_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap =3D qcom_cc_map(pdev, &gcc_msm8952_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Set Sleep and Wakeup cycles to 0 for GMEM clock */ + ret =3D regmap_update_bits(regmap, gcc_oxili_gmem_clk.clkr.enable_reg, 0x= ff0, 0); + if (ret) + return ret; + + /* Disable GMEM HW Dynamic, Without this write, GMEM can't get enabled */ + ret =3D regmap_write(regmap, 0x7E004, 0x1); + if (ret) + return ret; + + clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config); + + return qcom_cc_really_probe(&pdev->dev, &gcc_msm8952_desc, regmap); +} + +static struct platform_driver gcc_msm8952_driver =3D { + .probe =3D gcc_msm8952_probe, + .driver =3D { + .name =3D "gcc-msm8952", + .of_match_table =3D gcc_msm8952_match_table, + }, +}; + +static int __init gcc_msm8952_init(void) +{ + return platform_driver_register(&gcc_msm8952_driver); +} +core_initcall(gcc_msm8952_init); + +static void __exit gcc_msm8952_exit(void) +{ + platform_driver_unregister(&gcc_msm8952_driver); +} +module_exit(gcc_msm8952_exit); + +MODULE_DESCRIPTION("Qualcomm GCC MSM8952 Driver"); +MODULE_LICENSE("GPL"); --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7793C41A4EE; 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Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:12 +0300 Subject: [PATCH RFC 03/20] dt-bindings: nvmem: Add compatible for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-3-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=797; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=KPWh3nm9PQmseVb7i0DEMou+AXydIuwF+UdhOvlk108=; b=XMWmcJJQTiOZvONwNP2Fc0z27vfW2XM7BgryKDkrLcGwWYCxhIbNgNlTvKN27uEkFjmQ7W0F4 gyTaFBnj1YiBP1X78V44RhU1VmeSq1RtlZp3MrUSbQfBjLbcrloNpx2 X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the QFPROM block found on MSM8952. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Doc= umentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 566304ed4c78..646f2e8dcf4d 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -37,6 +37,7 @@ properties: - qcom,msm8916-qfprom - qcom,msm8917-qfprom - qcom,msm8937-qfprom + - qcom,msm8952-qfprom - qcom,msm8960-qfprom - qcom,msm8974-qfprom - qcom,msm8976-qfprom --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F2A041A508; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; cv=none; b=BVRu9gmHDds36/ahuXF1IwCnzjk/IXNJzgBSCGXOib5peN9L0yHiX3MDL17/4uQb/uB4ZTDtdjT5DKTRVJBhgMkAtYB4xhi5DFZq+0FOnQwi0KZAeWR13L8FxYlmo2YiK/Y+FxlsrUk6our3w8QV5CWl9ah0Qbtx/TonUgNqy44= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; c=relaxed/simple; bh=WqyeewKom7P7COh88TTOK1qoXNFMd40eFyYNGK/7f3M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VSJcCu8IK9T1Ut0coDqRwtPlcHPvi60qQiW2agquKEWIH93YPkAPGugqTGVizlTqRawwciz29E6bXJFW8WnZEhyqlQv/7e3SRV6ZgZib9l3dK3Hr0zo2stc0Vdbg30psJbxBGn2OWqcnqo4Qxm3a8E2ZgpoJAhB3KHQ0tZmWq+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KYFNi8rp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KYFNi8rp" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1735CC4AF1A; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202358; bh=WqyeewKom7P7COh88TTOK1qoXNFMd40eFyYNGK/7f3M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=KYFNi8rpdaBuE5Rk5sEKltTtnr8LUL1b/rzSaOPU7xPGXavKGJUzb5ECBGhK4lf52 R0TgDun12TYO5Nu7kCw3P4hkQqTZTitA6ELUbRhswrlRmORR4Hzkx4j31X13rI3vZw aqHZqIz/znpyXMHy1Kl9ql0f7nML936js4W+zvrOXNRdmQ2CWd1A1iB39puFOCq9FZ yx7NVWrSn+pVAXczEiLGfU+0M25rdQK6xrbiKZFmBb6xtB7vYaI9wQmSLa1s9ukgL2 U16M4npOBW0FZuCMyYNZgqsnWjiWeFreD8bZXXiPh6RbT7zmL6t6dJRjYRU50h46lH 6KOimrKYSe0jQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F235FC88E56; Sat, 12 Sep 2026 08:39:17 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:13 +0300 Subject: [PATCH RFC 04/20] dt-bindings: power: rpmpd: Add MSM8952 power domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-4-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=754; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=6ZI51ceEaOIY/u/VVB+l7JnsBp7inUEcGIBHgiYAiBE=; b=dztDjXymTNo98gMcgzcAM1ZlmGVG6mQv95qqYW9EttJLlaVnbTxsMMBF33je4lABvOJ+nHxUo gFM1b8UvYs5BFp5RzBbSVzQruiYPNmdITMMrXf0e6F6EM7uMpa5ttXT X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the compatible for the rpmpd found on MSM8952. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Docu= mentation/devicetree/bindings/power/qcom,rpmpd.yaml index a70bfacbc5d1..8ee1c25a7c9d 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -76,6 +76,7 @@ properties: - items: - enum: - qcom,msm8937-rpmpd + - qcom,msm8952-rpmpd - const: qcom,msm8917-rpmpd - items: - enum: --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96B9141A79C; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; cv=none; b=Hlm51BVQAcAhuu5Xu4cIZ7z/8SgAB0VxVvXzEQ/q62WuVnzVAgtmt5nVZZmP21HozproFbwi8gUcRSFLckbqhQ4peYzUrhziO4vM67YwCaNvTC2sY2Vc7Rt+ySJ6vh/vzkx1uHQHx5Zo9sf1QNZIXgJtF6N8q8+gFMTqALZvhII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; c=relaxed/simple; bh=pYcFE5374oIVVn03ajNnY96fsnJeNt1jxuuyEUBwheE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QODVb5Xpc6ir19G5FshJpLKXQEi9VFG2gLvSiC8dC3fCtS2i/tFOqQzFJ2UesPOJhNZE8Pfn31WoOYlB4xECh1+uvmBAO2rjuOveg9oQN4Gxfg6Ccam2/pKdy6jg7Meo9n24NXNInrRnf29IFCdzWQwzmnFYlLuhj9fVBTlFhkk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FBALDT8k; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FBALDT8k" Received: by smtp.kernel.org (Postfix) with ESMTPS id 281D8C32782; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202358; bh=pYcFE5374oIVVn03ajNnY96fsnJeNt1jxuuyEUBwheE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=FBALDT8kAHRCsX0ehCbvyYrzBGput6puHmkm6sUqqBzQ4/w9zjjdzuAGUtOl6AneL AF4o1694FBZsh2nXG6HQKWXnQEwDjFmF7qlYqwTrhxmBiEwt5TwjhX44Mav6y5DqSx Yz+6j3F+dOzJiBwxmJaDHTZqNtVKQkj+jk6PUJVfra+5QMr6qkc6/STJ0FX9sf/ffU Dy6jL3Kp/++TvlaneU+sHb1OuiKF4zDEwyhPkirH0C2boqC3OCweXC0webtrhDK2H6 WiAVR+iDTEw96XeZ+qto1xVgCwHNgszmuU/gNEI+4kF7ZtefFyTIT1ihxizQg2FyRp zrp7alRIuJaLg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12536C88E5D; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:14 +0300 Subject: [PATCH RFC 05/20] dt-bindings: mmc: sdhci-msm: Add MSM8952 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-5-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=861; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=i5JYnHiSTI2FsDfkaSc7QQm0T2uZHX+0vDTSQH293vs=; b=rjKT3vKCGe+tuI8MU/z1XGpbuQVv/ke+KNZMWn+sOLwz+aMBrDn6Valk9bYaifasRV15rtB6N dn/v6Dz6be2BZg1MvcsdUFgQyAMQa2giIzKk6qWaaWtpvS+mB8rBHZo X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the compatible string for the SDHCI controller on the msm8952 platform. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Do= cumentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml index 69bd44e65ad7..9d4409c958fa 100644 --- a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml @@ -26,6 +26,7 @@ properties: - qcom,ipq4019-sdhci - qcom,ipq8074-sdhci - qcom,msm8226-sdhci + - qcom,msm8952-sdhci - qcom,msm8953-sdhci - qcom,msm8974-sdhci - qcom,msm8976-sdhci --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B489241B8CD; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; cv=none; b=URSMHHcHp6cRwdm9ytSz16lEI+TRmUtLuv0XPTo6xcvTux6/CBn8QGHc/oxiQVxY0u2OOpbBV4l7TaaYUlm73z67sOETtfUuIDkGfcDYbqxI37gEIUOWcM+DSqtBn1dfKOYDSwHfNbSAjP1tERH44Y2EOVFv4OZ7hr+E6Y7WdWk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; c=relaxed/simple; bh=6aztPucHhwcfvtH05KLuWDZknFBinjt+ASMvoTJAUkM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=An8RhrkvmlHK9Xuql7kUajNMHsbkna1/PAIMdkimn2Cy2PFJo7alSsUX0Tk4toueRg7ehClbEaFFK+hCWfgksCyki8eEGeL7SFZ6oeO8tYK6T3veU9h8JehfUxKevA3wEyKncY3+N89/xhZ36SknsKbBcOlqWD/BeoaeEyA9l8c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lXczFAQz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lXczFAQz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3D353C4DDE4; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202358; bh=6aztPucHhwcfvtH05KLuWDZknFBinjt+ASMvoTJAUkM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lXczFAQzzArIIxIdFVmrzdQnBgfrhXhQ4M7zUP1N2uZkVth/gPkXGf1LQSDL10OrO zLpLXnLS5b/w8fAcK+cx/u/Jto0/5+jN0mm2uBSmSGEjhuCNmfPd4XMRrqxOSOFlaJ algO7oov0sL0GyMmOMmJiy12TXYOro/Z+Nf64Lh/VrEF/lpdnuBv/0Xa0xKaPded03 Y4o/52c2f1TeFoPWw8nhTO53Kdzo4MmYviIs5CkMlnBy9AKtxyHBinB1txAfYnb6M6 hrwyYjpjbCABWXTGmyyjPXXnFcizBFXKRtR1s3ANhSjgQt7eSlHouVudutQ6krG4MJ pp8a1Cm6yBxPw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25014C79FB6; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:15 +0300 Subject: [PATCH RFC 06/20] dt-bindings: vendor-prefixes: Add General Mobile Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-6-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=851; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=r3ZLJrtM9n2VHMSFrmIfF7hLeBB7OX3rKnjug6/4v2s=; b=HjCW1YfrhClV6QDEqd2tMP79zA2T3UvNy9/heINjnpQPnPG7PQc2eI2U55+9ASYNYWq4IOEeJ LSKyO0FajxVDp2KCf3ltIwZ+8Kt4jK55TaAd8XZ0d0yyGzrlScJmi3l X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add vendor prefix for General Mobile. Link: https://www.generalmobile.com Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index ba2002969373..37f991d9352c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -662,6 +662,8 @@ patternProperties: description: Gemei Digital Technology Co., Ltd. "^gemtek,.*": description: Gemtek Technology Co., Ltd. + "^generalmobile,.*": + description: General Mobile Fzc. "^genesys,.*": description: Genesys Logic, Inc. "^genexis,.*": --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC81841D11C; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; cv=none; b=kezDllgttt3CuxuBgqMrICZMZ7MsArqC+c3QO17j/WS2my7drPdmW01gXx9ZUGi/2yGEgcWK+rCmHI5GUWsc7zFT6iGIJzmhL0u6i6e045PukBlzjCg8UGhPf1+6sLgvyumgbpLg/7TXQwcfXWskD/yp4oP/TO4hI8Jjs3VT4e0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; c=relaxed/simple; bh=Dhsv6jxnEgsYdsiLMg7sI/bMzu9qrqEvPc9vujb6Tf0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=agQBg0yaJ8gp3getcR0TmUKnFgruTdKKBbalOL7gu1tWEzA5gNK0v6fTbc5yJsKQUU6V9Hc3XSdWdkmsvueISMvqM3L2N6CiYSDSB5TLkT5tu+6dpQD0OOt3ERDD/rtNMAT5S7j6QM+e/1J/R0vlPoauPhp8sASh/JMiGfR9KG8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b1Gi9VSU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b1Gi9VSU" Received: by smtp.kernel.org (Postfix) with ESMTPS id 53E09C4DDFB; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202358; bh=Dhsv6jxnEgsYdsiLMg7sI/bMzu9qrqEvPc9vujb6Tf0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=b1Gi9VSU9idVc827MqX6kLoFg9VNAzESDJIv9U1mZrG9KhfZGrq4MIrAI/2kLHs16 rdfcBcxZQjFJPbzdk74L057ztylAvztcNP6lon/yjcOM43QM6e5n9IHa+cO9zBzBrH Jgk3NSad80vqCeLeMKyTHUJiY1XWoVEQ0qdjA9gXaWVSTPGnBI1tkQ4DnbX90KeqSM Wu/b/UkFTEjJuITKuabOE+5NOV6LnorFUHc8jvi0ruU0/3Hs+fZbjSPqj5nnGxwBoj SACL1f3r6YZNZcwg/IaohHnifnQ0ZbbsRjdD7QTpchQNFlEYpGxbinimXls3/c2XYi pJYEG/qv4Vi2g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BA91C88E53; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:16 +0300 Subject: [PATCH RFC 07/20] dt-bindings: arm: qcom: Document MSM8952 SoC binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-7-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=1049; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=IrdfYEEL5OvimAfTCyeFYw0PIvJN61JxPWVoerUdBaQ=; b=TVDUf5Go9nCED2Okfn9stCy1gKxseubk7rRPG7eRimzVN0gejMhc6hCu4pFtrUyI0Uslg/Ya4 VPwmtAtA7pXD0Aw4A/czbxaOPQH1CbIOR2S6I6E6/7cZjIo/eWXc6qe X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the MSM8952 and add General Mobile shamrock to it. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index eddf87fbd0cc..b611ad40f537 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -296,6 +296,11 @@ properties: - wingtech,wt82918hdhw39 - const: qcom,msm8939 =20 + - items: + - enum: + - generalmobile,shamrock + - const: qcom,msm8952 + - items: - enum: - flipkart,rimob @@ -1341,6 +1346,7 @@ allOf: - qcom,msm8917 - qcom,msm8937 - qcom,msm8939 + - qcom,msm8952 - qcom,msm8953 - qcom,msm8956 - qcom,msm8992 --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBA7F41D135; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; cv=none; b=ERcwSKa5v5VZzyZD/wudOSvZJg3colgUVYFLB1o+sgV1QjqPnyTCzfRKqEQzmz8GpUI6AzmlJu1YVw0Kdlc+JsQ+xoVR/IfdXuG5JPhzJsDdWf0GK7FYEwfflZuTFzbdVnlrqKCdAbXX9jh8a5XT8tbW3nYxo1+lcCmRF1qjBz8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202358; c=relaxed/simple; bh=Y2tYpAAcz6nz7Pdv5HgsCC9rwT95/7ljDoBRHQCON3s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HjAScdD2Ca6ZNEAEBZgsQDExrxH2UdPVdZGSMRQmCzVsf6Jyhy3hM3WxGeJwIqkrJcqJsqLI4nuJfOWO2zojjSISN0nHjb9IzWudOvObTe+WdKJO1wLLBt9cBal+mJIE2/TdWZEl4+MpMjq6gu0CLMQdLmqKoc/6ONOIwlnzNRg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RrP3E5Qe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RrP3E5Qe" Received: by smtp.kernel.org (Postfix) with ESMTPS id 61F55C2BCF4; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202358; bh=Y2tYpAAcz6nz7Pdv5HgsCC9rwT95/7ljDoBRHQCON3s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=RrP3E5Qe+mIh+TW3RNi1DPrd2NFS9gsO65yrHAwNu9JZSBXjGGJAU2K+ezZf75J2V sygQiS7VPAmtoqdWXrqAeqXAjmTjcZTEhEQqhXh7l6v/X9/jWqXcuRAJJLMhOIgQxX oYh2f43BdBCXrxw/rMdaXipXbJ00XRLmoRtSC4ImjsO3a/A8fppJPdugrG3rGj4X6C voh49xdGNbw7HUEgHUP9v6twf0jQnZ6d/NB6U57uiKdo4d5d9/umJgzY0s3QRW/9KU /Y/VoMlllRpeHPKFDoxI4twzG3KspnE0dSyVqgjLPYDZ4nR62460hm2YmEP19NMB1h l29+IJWCg3mEw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DB6EC88E5C; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:17 +0300 Subject: [PATCH RFC 08/20] dt-bindings: iommu: qcom,iommu: Add MSM8952 IOMMU to SMMUv2 compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-8-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=899; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=nfAz99So67UR0eyTBCJCXrrz8ldqx9jhB2u8iWLdXd0=; b=Z9hBQwW3JsQ/kODJPQLSBFfYBWzo5BSslJ1ZlFBgCfDDIIvFSV6QYaiyA8hAixG4n8CEQ0H97 lu8pLX6n+dIAYy8WRvqKolnULsJ2gwy3uzmOfmCipsoIk4FyamxGpNQ X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add MSM8952 compatible string with "qcom,msm-iommu-v2" as fallback for the MSM8952 IOMMU which is compatible with Qualcomm's secure fw "SMMU v2" implementation. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Docu= mentation/devicetree/bindings/iommu/qcom,iommu.yaml index 93a489025317..9952b9da9a6a 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml @@ -27,6 +27,7 @@ properties: - const: qcom,msm-iommu-v1 - items: - enum: + - qcom,msm8952-iommu - qcom,msm8953-iommu - qcom,msm8976-iommu - const: qcom,msm-iommu-v2 --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECD4A41D23C; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; cv=none; b=sjxgJV5QemCfOLrirp77eeD9R4DzYdCagRFVCnIok2TwyxLefH9sy/cC8eGWJLkyw8u6KIQpbk5hCsL0Up2/140GrtVuTkm8d038rY6P6HF9vke+CxWWJbO+jLIh1HYPjTHZNyCA33Fb2gR1sC6vhtpJdhGnI48I08JW4Ff5tcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; c=relaxed/simple; bh=SGxzZ78zMyAPGfHj+Y/wCCSvNMOZMOTutYr6UmYwbww=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kEUmYs/BKFvGDfHi7+gOkYRjrqxg7hUljRkVyNgTNVJiAPG1jrOXaWIBNOP2zqBBrjMrOkSaJ+l/oeLR3NrM0YvR4ywRP8MjgGngTyPDP4uSCZLkIdWISGhSovCxW2C8Bob5UMCasFVUlN44zDuPU7NJcbbtEU3OOyh07raa/nM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZcJnV4hP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZcJnV4hP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 75F95C4DDFD; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202358; bh=SGxzZ78zMyAPGfHj+Y/wCCSvNMOZMOTutYr6UmYwbww=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZcJnV4hPZoEUmcUBY/h2oY1NvRUJR5RWSS9wgTbIdLMdL4g1NrWP0mxzIOTDjoMLj C8CbWXqMBxN7xCVsK80tt0ZYqTAS2CqIQMHRkFB2iXId69nKVhqdiZS3YAs/GdhX9e +wJui2cKScV8dIpRdFWfBfPmVSL/Gg8kt/Xz0nmBr5RpogyDA+QQ0S9NLa60BB25LO ntvZNW7LTAZsjscuRGMDDyGRG0ZWHUtEwrbmhVhCgYRQ483qY5RTmOQ4rODqpbfisc nzfetBOZsMhqi9gbcKTAqtFFZEKZOedNqVlLbWZ6I9E9DjD4y8dYQcO3Xx3Jsnk6CG uSULsEW3v8z1A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 601E2C88E56; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:18 +0300 Subject: [PATCH RFC 09/20] dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-9-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=762; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=UXP5FYqQk5LMDz6EEMbHWLm1DRZQe1v+vfaQe/3iLkY=; b=bcHzWWSzSSuWF4BYSsHbZbr+ya6y+s5LZoYdg2J+JMsAsGE366QxlPkofMHX7ybS6T0YLyukt C+QxDSlhHGiDdpzNwyoI6z7n6RVeKBhIKN5DtMTOMl/6SSn2Qf2sdtk X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the qcom,tcsr-msm8952 compatible. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documen= tation/devicetree/bindings/mfd/qcom,tcsr.yaml index c3889f974ed3..a021e4dea486 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -60,6 +60,7 @@ properties: - qcom,tcsr-msm8916 - qcom,tcsr-msm8917 - qcom,tcsr-msm8937 + - qcom,tcsr-msm8952 - qcom,tcsr-msm8953 - qcom,tcsr-msm8960 - qcom,tcsr-msm8974 --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 081A341D648; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; cv=none; b=JbCEgI3eSeTbjddYjXGeeCo35AbXC+JvJo4QxoaohNcQ03idzBAEJeBSa/+p1fMe4SBZfs1vXyWkAI3TErDwHXiYDmHfY16jKhXALUuM+DTqpsmCg7lbPpB7YT7SRXrsmvTG8h0KJcKnIsiFwX5E+fTHI80mNbOEqd8l3Hy+X8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; c=relaxed/simple; bh=nEETZd30ihFYodF7S3ZnHo54IVYKqjEmYVA7vkPl+28=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Iky+4R02saavdIuH6iS1Si0Uo6ni0Y15vMfIgej+IpWu2XraP0EoIQxwzLxfjEmVssu/AcqG6XzyIlF/Al4U0zw8KmnmpB4WVE/XzZXg+4b4xquMIu45R7oPQK6vFA4GR1kR44re8OBFL1tXaVvVYEFgK3Fi7vhbi9PzSlc76+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mCV6Y+Mo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mCV6Y+Mo" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8B91CC4AF4D; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202358; bh=nEETZd30ihFYodF7S3ZnHo54IVYKqjEmYVA7vkPl+28=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mCV6Y+Mo58DTk67vE3fZ9dL4AK3y9rNvaCoX+oMgXDUwRd9frtLOHRJcC/AukKiAy V1E0LroiqxvQfohhicmTGF1176vYsOHSh+vX9f7tBAih+afucY42CWDZicvZcoGUaG 6um0DCCt9fISSOKncYysiilrSEE7+I9t5ts6N/KNpdh1chKo509/E8UjNABef1Ea9N hmhLPqZXamDdfstm9h7yrBhKakH0F2BaIlmtueuvoOW/FR4NxKuOm/xOSrJyMQLszW 5q3egLMp6zon4DYeazMqOEABxS96U6ZUcBoXxyZN5LW0H2Jw0L5TPgCRO1fzxrkuPc 4S8hW0I/vXMlw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 734BAC88E4D; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:19 +0300 Subject: [PATCH RFC 10/20] dt-bindings: display/msm: qcom, mdp5: Add MSM8952 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-10-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=837; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=cXfQWRfr0HZxeGRc0NvaHMBSXgmQUJGS4sxKDd4qU2Q=; b=YrF7YAJj2jR94ChJAFzftyyXleyxH9bz8s2O/DIeDlx9GetLx56VZAvspoBkn2FlSNCmAZsQv axnMNSBg6FYAz5/1f4d4cmKotxTlxO+58jL1SAHiVLwv/LOL/MmhMov X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add the compatible for the MDP5 found on MSM8952. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml b= /Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml index 2735c78b0b67..2f0a32a3f586 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml @@ -26,6 +26,7 @@ properties: - qcom,msm8916-mdp5 - qcom,msm8917-mdp5 - qcom,msm8937-mdp5 + - qcom,msm8952-mdp5 - qcom,msm8953-mdp5 - qcom,msm8974-mdp5 - qcom,msm8976-mdp5 --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3938A41F349; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; cv=none; b=rg18GpeZqtdfjgV/50SL3hyGKr/ESj31UkJc8VY1M5eR02/GIoyFcbTA9gFd2AZcJkjQdpRUUpex9xDj+nTA8KQPH1inZgEM3bKDNUEuCGnfuR2nCgQsr78r/TP99izGVZuQplBAvXgAHkJ5lx14RgRpiReox0J8X7j84nhmi0o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; c=relaxed/simple; bh=jjBzcU+PWB563ItVa5qUSj175U7LXox6DD+MRq2sB74=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gJy4dk1ZObVhELVOEstvW/gwaSMgHvNGa8wEjxigez1bhbhywVlD4liZe55VuCBJm8oblVVx09Xfew/2Y1HAgm41dETVbLVpLADodg1v86zIDXF0hh7kDyTuaQR4MWg+AXxIXOOu2Lpju/JLJ9qEaHLNz3TgplRpXuJxq2iSkc4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JlYD6aMy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JlYD6aMy" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9B726C4DE1D; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202358; bh=jjBzcU+PWB563ItVa5qUSj175U7LXox6DD+MRq2sB74=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JlYD6aMy8W11leAmX4XpwGdNrBKVFVq11ykvvYdnR/zoSBUySa3RsuydCwJ6L+ScW mLyY6MtzgCCrhw7VrxGcQ1PgqBWw3/nLaYoH3VNY7TU8R/+dODSg1ILKd5iSG6aDQP LyRLVJicoI+SgtM1Cy/9exnLD0G1/QY1A8nOX+4lI1YUPF/oLUewEUjMIjMDrJvZPi TOAlPi1YurIiMsQObXrusHC1PGtNdCLTc3jiSU/FQ1ai9X4qxXGFJ88VoMCRp3hfX4 kRoWN6oGGsL5z8RnKRjDRLSeV8K9PIxPW4vzeBBClAL+9eQwXLDx0+sujXxjJEOmL+ fcRPmD417L24Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8608AC88E62; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:20 +0300 Subject: [PATCH RFC 11/20] dt-bindings: firmware: qcom,scm: Document MSM8952 SCM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-11-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=1326; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=y9z+BmiJWSSl0cHCd04a2j09/dawogbBu+CncXJroZE=; b=jED5d9jA1E9k+qYhTSIWrvjNI0LnSmE4aVay8EjQTIze1BX7RZ/XWWGSYQ2Bv0n4VFxpeR75r tuGtBofQQnMA6ncpzlOky/XF2GOE+CYtvfsYmHngrQmNeIiOwXAEkdC X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the scm compatible for msm8952 SoC. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index ecee5aef65a7..40a267c54b00 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -45,6 +45,7 @@ properties: - qcom,scm-msm8660 - qcom,scm-msm8916 - qcom,scm-msm8937 + - qcom,scm-msm8952 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -153,6 +154,7 @@ allOf: - qcom,scm-msm8660 - qcom,scm-msm8916 - qcom,scm-msm8937 + - qcom,scm-msm8952 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -199,6 +201,7 @@ allOf: - qcom,scm-msm8226 - qcom,scm-msm8916 - qcom,scm-msm8937 + - qcom,scm-msm8952 - qcom,scm-msm8953 - qcom,scm-msm8974 - qcom,scm-msm8976 --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40F1341F379; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; cv=none; b=rtpWp+lev/+2dWpB366CbmnwgCpCDH+AmyZVWjXuNojDpsgaTiKfs7RnUIA1o5SM/EDuISlGSv+7FeXeum0xO3O/JY/VkS9djo+4m+tLQtygihrz951fTSgw8ucuKf6ctNJ+ewsc8d72YhE4wN+PA9/JChpu2KgbgFe/6hP1nbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; c=relaxed/simple; bh=wo5rvcgpiDR2tWdJaWVv8550ALi5urbFQa8p/WD73j4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Qek9s97JhfywdLGMl6IlUPgxXalSxu/5klgp6KMGO4uCDfFg82cBEHLVOySQxNUdsoGLc8y8Fr1NVMdrpmzvupWphNAXXOCmEXnyHpUCRRKzqlb350+B0I6BbpmURuG8nmc5q5GvzxJM7QU7phD7jL2YedD+dPlXB3Mv5zOdquU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U8hCsUnb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U8hCsUnb" Received: by smtp.kernel.org (Postfix) with ESMTPS id BBF02C4E68E; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202358; bh=wo5rvcgpiDR2tWdJaWVv8550ALi5urbFQa8p/WD73j4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=U8hCsUnbIvPGTLUU8bGGhgo6CBWjcPgR9eqJP5gry7uURqui1lUs111uELS8rGjuN cgn66cB5s/ZWGdVg14m5ImqoQUeGEDJkRph9ps+RuqcwvckQqC6SQ7IRi9haz57eU4 A9hT7u7N4DEEotmSIGI85W4SE1JbzbT8VPBqOG/D2VOG4dIXt5AZ63T6FpgGh0/QiP rlGDSfEB2a35Ou7TWoyx+pzzFIVAmWplWJXCTWwfhCnXoXfgU5LUizwVoMkOa5TpOk lJcpOWRaQXCTwfLeaQrWFOTzvS6vtvn/i0apg10CM8ZKFCmw1QPxdN7vUAz53U2xi4 e9pDNsESTGlew== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A68CC88E5D; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:21 +0300 Subject: [PATCH RFC 12/20] dt-bindings: clock: qcom,rpmcc: Add MSM8952 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-12-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=1095; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=RjoJbvQY6DTtuLDZ5TP0oZiQtiyl85vhqU0L6uvEo40=; b=pcRaa0ZTvYkfbl+BsShmjQWmwODB4ZJDeAyLKhVRHL0xmSF18K3ztVbIsuT78yBj0Vys2iYkw nyq7g0GOjpBBYcwa6YVmOnON71GKl7fv8Tyn0qvKac5nQklOJ6BfjCU X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Document the rpmcc found on MSM8952. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Docu= mentation/devicetree/bindings/clock/qcom,rpmcc.yaml index 17332aa55886..4532d2b6c1fd 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml @@ -36,6 +36,7 @@ properties: - qcom,rpmcc-msm8936 - qcom,rpmcc-msm8937 - qcom,rpmcc-msm8940 + - qcom,rpmcc-msm8952 - qcom,rpmcc-msm8953 - qcom,rpmcc-msm8974 - qcom,rpmcc-msm8976 @@ -121,6 +122,7 @@ allOf: - qcom,rpmcc-msm8936 - qcom,rpmcc-msm8937 - qcom,rpmcc-msm8940 + - qcom,rpmcc-msm8952 - qcom,rpmcc-msm8953 - qcom,rpmcc-msm8974 - qcom,rpmcc-msm8976 --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58E2A41F7D4; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; cv=none; b=GAjluYoh0LUCU2fozmYYpXfOce+ItoBlzV96wjr1diP2I/nG1ET2IK/kKXwp5z7wD6TPrm0c6yuOAR2O0F9KnXl5rpObom8dLidKjcxewJ05+/wKFd4Dj4NDo1iGyhtAYOowTEME01vDgdwP6KKJkw2Ak/vmW+sfi0+ttM3pWZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; c=relaxed/simple; bh=N4cJ+1neKZ1MgK8R9M1x2BOiA+d5mi3obLJN2Tvd7kU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=O50akAVLxHqLeXgad/pnZUHGtnxbZuGbnbhIbuD3yg/5H9grKhAC+0kHKADkabB79WSZ+PE3mZjBXh+j0hx/91HVONdNsntYZoo+mBriq5cvsIY4EXP9SSnkd1cqLunYm+z8rawewnU6oGScyB+90RKfTFoGVwGTVynBOw4qs28= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DR5HBNmE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DR5HBNmE" Received: by smtp.kernel.org (Postfix) with ESMTPS id C2FC7C4E698; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202358; bh=N4cJ+1neKZ1MgK8R9M1x2BOiA+d5mi3obLJN2Tvd7kU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DR5HBNmEyxqjZNsG1H7AEARg553o4OK15OySMWTHAy5nQ8OtafNQkPbGY/nprkrRa Dq9jLzgW1En6W3WyWBigcfGReBM+VhGAQYxDzDWcffau5oLhy9QmGvJWNcM98NSefV Lc2pt2T/DusrU1Ih1V9dTYXw1YD8ojz9ZaZIbGVzovd7n0w9eT3x0jO76a0pYCaouU edoPpEsrGJxeJ/kqpGtz7GKZAruZujgwknRNaRbpEBxck9SLM4svB9bhVY0KFMF2qf V8zpbTA3HmUleWIqY/nMX1anrUMnE/8Ycu7f998xLv1D98An3l9xxnOIvj2H5+Iz1P cjFU6m/K2DuBg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD3B8C79FB6; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:22 +0300 Subject: [PATCH RFC 13/20] clk: qcom: smd-rpm: Add clocks for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-13-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=2526; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=+fbbxQznzh0EAsRYoXyBD9lf98TEt7urc9Q1WfJgNWo=; b=QkA6CKY/iZxxVumpyHBKti6xBNNNjPEOZTgP8ktL+4FuOcB5mh12Wqar04/gVtSyc72YdRvRx gSHRBLEIIbIA6XL7tN/dseny4/Qk+50P2Nv+Mii5/RLCKH790m8lR7Z X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir MSM8952 has same clocks with MSM8976 and MSM8940. Signed-off-by: Muzaffer Kadir --- drivers/clk/qcom/clk-smd-rpm.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 487d715ed5d2..4ed08cbfa8a2 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -740,6 +740,34 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8940 = =3D { .num_icc_clks =3D ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), }; =20 +static struct clk_smd_rpm *msm8952_clks[] =3D { + [RPM_SMD_XO_CLK_SRC] =3D &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] =3D &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_QDSS_CLK] =3D &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] =3D &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_BB_CLK1] =3D &clk_smd_rpm_bb_clk1, + [RPM_SMD_BB_CLK1_A] =3D &clk_smd_rpm_bb_clk1_a, + [RPM_SMD_BB_CLK2] =3D &clk_smd_rpm_bb_clk2, + [RPM_SMD_BB_CLK2_A] =3D &clk_smd_rpm_bb_clk2_a, + [RPM_SMD_RF_CLK2] =3D &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] =3D &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_BB_CLK1_PIN] =3D &clk_smd_rpm_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] =3D &clk_smd_rpm_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] =3D &clk_smd_rpm_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] =3D &clk_smd_rpm_bb_clk2_a_pin, + [RPM_SMD_DIV_CLK2] =3D &clk_smd_rpm_div_clk2, + [RPM_SMD_DIV_A_CLK2] =3D &clk_smd_rpm_div_clk2_a, + [RPM_SMD_IPA_CLK] =3D &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] =3D &clk_smd_rpm_ipa_a_clk, +}; + +static const struct rpm_smd_clk_desc rpm_clk_msm8952 =3D { + .clks =3D msm8952_clks, + .num_clks =3D ARRAY_SIZE(msm8952_clks), + .icc_clks =3D bimc_pcnoc_snoc_smmnoc_icc_clks, + .num_icc_clks =3D ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), +}; + static struct clk_smd_rpm *msm8974_clks[] =3D { [RPM_SMD_XO_CLK_SRC] =3D &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] =3D &clk_smd_rpm_branch_bi_tcxo_a, @@ -1292,6 +1320,7 @@ static const struct of_device_id rpm_smd_clk_match_ta= ble[] =3D { { .compatible =3D "qcom,rpmcc-msm8936", .data =3D &rpm_clk_msm8936 }, { .compatible =3D "qcom,rpmcc-msm8937", .data =3D &rpm_clk_msm8937 }, { .compatible =3D "qcom,rpmcc-msm8940", .data =3D &rpm_clk_msm8940 }, + { .compatible =3D "qcom,rpmcc-msm8952", .data =3D &rpm_clk_msm8952 }, { .compatible =3D "qcom,rpmcc-msm8953", .data =3D &rpm_clk_msm8953 }, { .compatible =3D "qcom,rpmcc-msm8974", .data =3D &rpm_clk_msm8974 }, { .compatible =3D "qcom,rpmcc-msm8976", .data =3D &rpm_clk_msm8976 }, --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61BFE420482; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-14-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=2908; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=tN86AwIVz+/4z2KwlUplPpbsNM+e16O69T3qlIbXC0E=; b=D+Mx3bXoA7Gp2aJrzbakliBWsehboQQCDHUiAE6mtMMsP3Rz+XXR7XoC9JCqMmHP/BbvAqRJb pM6YBmDSDrSC8nbOgefdBSyahFuqo9ikgTtGT80P59kglzet9qZyeZz X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add the mdp5_cfg_hw entry for MDP5 version v1.12 found on MSM8952. Signed-off-by: Muzaffer Kadir --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 81 ++++++++++++++++++++++++++++= ++++ 1 file changed, 81 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm= /disp/mdp5/mdp5_cfg.c index 7c91fc1915f3..d34c94d6f7e2 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -744,6 +744,86 @@ static const struct mdp5_cfg_hw msm8x76_config =3D { .max_clk =3D 360000000, }; =20 +static const struct mdp5_cfg_hw msm8952_config =3D { + .name =3D "msm8952", + .mdp =3D { + .count =3D 1, + .base =3D { 0x0 }, + .caps =3D MDP_CAP_SMP | + 0, + }, + .smp =3D { + .mmb_count =3D 8, + .mmb_size =3D 8192, + .clients =3D { + [SSPP_VIG0] =3D 1, [SSPP_DMA0] =3D 4, + [SSPP_RGB0] =3D 7, [SSPP_RGB1] =3D 8, + }, + }, + .ctl =3D { + .count =3D 3, + .base =3D { 0x01000, 0x01200, 0x01400 }, + .flush_hw_mask =3D 0xffffffff, + }, + .pipe_vig =3D { + .count =3D 1, + .base =3D { 0x04000 }, + .caps =3D MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | + MDP_PIPE_CAP_DECIMATION, + }, + .pipe_rgb =3D { + .count =3D 2, + .base =3D { 0x14000, 0x16000 }, + .caps =3D MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_DECIMATION, + }, + .pipe_dma =3D { + .count =3D 1, + .base =3D { 0x24000 }, + .caps =3D MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, + }, + .pipe_cursor =3D { + .count =3D 1, + .base =3D { 0x440DC }, + .caps =3D MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SW_PIX_EXT | + MDP_PIPE_CAP_CURSOR | + 0, + }, + .lm =3D { + .count =3D 2, + .base =3D { 0x44000, 0x47000 }, + .instances =3D { + { .id =3D 0, .pp =3D 0, .dspp =3D 0, + .caps =3D MDP_LM_CAP_DISPLAY, }, + { .id =3D 3, .pp =3D -1, .dspp =3D -1, + .caps =3D MDP_LM_CAP_WB }, + }, + .nb_stages =3D 8, + .max_width =3D 2048, + .max_height =3D 0xFFFF, + }, + .dspp =3D { + .count =3D 1, + .base =3D { 0x54000 }, + + }, + .pp =3D { + .count =3D 3, + .base =3D { 0x70000, 0x70800, 0x72000 }, + }, + .intf =3D { + .base =3D { 0x00000, 0x6a800 }, + .connect =3D { + [0] =3D INTF_DISABLED, + [1] =3D INTF_DSI, + }, + }, + .max_clk =3D 320000000, +}; + static const struct mdp5_cfg_hw msm8x53_config =3D { .name =3D "msm8x53", .mdp =3D { @@ -1017,6 +1097,7 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[= ] =3D { { .revision =3D 9, .config =3D { .hw =3D &msm8x94_config } }, { .revision =3D 7, .config =3D { .hw =3D &msm8x96_config } }, { .revision =3D 11, .config =3D { .hw =3D &msm8x76_config } }, + { .revision =3D 12, .config =3D { .hw =3D &msm8952_config } }, { .revision =3D 14, .config =3D { .hw =3D &msm8937_config } }, { .revision =3D 15, .config =3D { .hw =3D &msm8917_config } }, { .revision =3D 16, .config =3D { .hw =3D &msm8x53_config } }, --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70B39420E8F; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-15-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=932; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=skwIjxkrl7U33MIrHcZ89NbRfjE7bPXAcmofXi9BbYM=; b=QSHsJj7/vHWLcjnNVscnJ/gGyO7FHTOR1kVfDAfCo5wB3CWXS9770w3VqpF+uwlvHODfeTlsk CriGqM9bLadByD66M3rOK+Ae2KwoD1bd+Wri0Qn1UgfLewtf+i8HiP7 X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir MSM8952 uses Adreno 405 and predates ubwc just like MSM8939. Signed-off-by: Muzaffer Kadir Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/soc/qcom/ubwc_config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 36c90f72943f..53c1df3ca641 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -130,6 +130,7 @@ static const struct of_device_id qcom_ubwc_configs[] __= maybe_unused =3D { { .compatible =3D "qcom,msm8937", .data =3D &ubwc_1_0_hbb14 }, { .compatible =3D "qcom,msm8929", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8939", .data =3D &no_ubwc_data }, + { .compatible =3D "qcom,msm8952", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8953", .data =3D &ubwc_1_0_hbb14 }, { .compatible =3D "qcom,msm8956", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8974", .data =3D &no_ubwc_data }, --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B770421231; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; cv=none; b=FnKW6YU3bM74UXJrVuQf7wJsuJuBAjr5MtCFmZrYdwKrvt3EaroAdfo5an9bi+2vsvZxeuLoIDmni5VqojZeWJtfKaeg6DRdqaoUB+DhiZtgtFHPTcZ0pSMyg2dc4Xajb90FaFahz+tyhEus8Tebocnjw09agt0hlS/1Iv5Z/R4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; c=relaxed/simple; bh=M03YYE4QzuecWse/3jF90R8u21tAuUCseoussBmT+ZI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Rpn4Z3EC67AjmccUgAHnGheLWdLL4kyubfe+1skxyqHm7EJi5AAheCcWx9vA52ZFlsqly02PKF2oqqfn7bMaVVWjbGDm5t3wMtl18u8kWoNF0kKekUJ0JYsYiv+s+g/RI7lIo5yJLbn5yVKvAHsqoiS3yALN+9Om7LhrKDaD6R0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gVb8wGC/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gVb8wGC/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0BF51C4AF0C; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202359; bh=M03YYE4QzuecWse/3jF90R8u21tAuUCseoussBmT+ZI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gVb8wGC/Or9QEo+wj8L2awv6GMSx7YRKiUKPUTcm/VlkFSbGiQwmEcUdEnmMJjOgC zn+ICdxatcjlBLp1kvI+OGEGqiGsB/wA9Ed+yNCqyf2tzitPbI4EjTXBZiFTMvh3Qq XKGbMpg8vA1OgolwEd4yIS1djwYopFL/YFVvzQxut74aIAbs7cQLY34h9aLWTngsLY PCJwtBppqYdv4A0leCT3hgY1lqWJxJ5wKV4kFZmZm8m+reI/2SrWuieLJWNuu/7x7f hJ58j8LC4jrdLQv+98h+lu0xXG0aXWG5uXs3AEu7kWLqQjGELzU+ur2gudvRv8P4OI Cql4S+9kxIy6g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7F5DC88E5C; Sat, 12 Sep 2026 08:39:18 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:25 +0300 Subject: [PATCH RFC 16/20] dt-bindings: thermal: tsens: Add MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-16-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=797; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=SHQrlXrOKfClSSRN67nbliq/vzHPWzLada9e+lrsFjk=; b=6PA6NmEgUQ0+HVxnxKIS1Rps1nE6jluEZqKw0B9t6fZK/k8tUGG/aqh5ETyWK0HE8R1OS6mTS vmKKlI3zzAJAx5HjDMNyrJM829WeCzGX14kOv3rZ0gjr7eQCdkhmj/G X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add compatible string for tsens block found in MSM8952. Signed-off-by: Muzaffer Kadir --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Do= cumentation/devicetree/bindings/thermal/qcom-tsens.yaml index 5a8f7673e730..c78074fbcecf 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -46,6 +46,7 @@ properties: items: - enum: - qcom,msm8937-tsens + - qcom,msm8952-tsens - qcom,msm8956-tsens - qcom,msm8976-tsens - qcom,qcs404-tsens --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B883421233; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; cv=none; b=uI3xR6doN0jv9mx1Aqvskyie64WDvwLHom5CZn20u9YJNIj+OrWYLxrGzNJVBVqvZmaONkQdx3/X0anzzFsnadBzoxM0vJhvop4UXIY611dFQkNLUTC0vcqrmMkfDGKfstUupb/CRwdHlRTGc7oe8xcBttoelb8Q2/DWiSOuHy0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; c=relaxed/simple; bh=JJRJhySTsLtcFd8GQW981z7R0SglGrCnEEAhSveaKRc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rxGH+nDDNpLJYvVDtPwXGwHvpXSDq5ZnMdsUocKKZ4Zz8OyNArlqSXPYr0fD0HwFyip1b7LlnX834udzRMlrvIEHXO0MNMLjhWALcIrIs64wdhtBCFAJruwtmk5vvV9XlAuTM1iWot2dHiHxxDNLIYnoUlEz7vHWNrXAGNVRmtg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BU/5eFnx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BU/5eFnx" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1ADEFC4AF67; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202359; bh=JJRJhySTsLtcFd8GQW981z7R0SglGrCnEEAhSveaKRc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BU/5eFnxpuoqCYjnzZhrz7hlpOYJI1RobJPIZ9JZtppVJ/LLYphGeg77vQfLXiESx H3zoBgcPA2yk5Z9/IJY9kT1W1coke7MicjZgHBP76xClPccJy5yTkKhpUudfA6zMS4 3dfipeT1jKGKiPIB7LgDzYDFA0VHlh0veaLsLwrGW0M9OwVeX/MNfp9cYhNncYqBiQ 1We0i6YGYGjGDjg9VFeOOnQ8qddnXWkfhUVY1T0iLJVMtcf2YWWDwT0ZMw/f8lrm1Y 9i8lQ3nhJgYdy9G7RATuYqneg/nc9uOTK0VQHoPSu/rvrcTATg7tfxinGkA6AK7rgm vrpPMqbMJ3oRw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06B5AC88E53; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:26 +0300 Subject: [PATCH RFC 17/20] thermal: qcom: tsens: Add support for MSM8952 tsens Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-17-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=3766; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=NwE63NVSkM7PuI6TKSkbUbPMowTu/Nb0hrYPBEBZEM8=; b=qif+Ybig1msGLGYO1mBqVUwMj+daZ4OeXh4dt1RlzYrgo2xguH8VvfynZ721wMKjqbX2/e427 NPprsdgOQobCRixKnAlaaA1Ir6qZmLLmI3FeBuGTIQZ451psQ7CRNPt X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add MSM8952 support for tsens. Downstream does a lot of advanced things with calculations. But seems like using tsens-v1 directly works too. Downstream reference: [1] [1] https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-wea= r-7.0.0_r0.3/drivers/thermal/msm-tsens.c#1621 Signed-off-by: Muzaffer Kadir --- drivers/thermal/qcom/tsens-v1.c | 44 +++++++++++++++++++++++++++++++++++++= ++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v= 1.c index faa5d00788ca..f4201748ea29 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -145,6 +145,37 @@ static const struct reg_field tsens_v1_regfields[MAX_R= EGFIELDS] =3D { [TRDY] =3D REG_FIELD(TM_TRDY_OFF, 0, 0), }; =20 +static int __init init_8952(struct tsens_priv *priv) +{ + for (int i =3D 0; i < priv->num_sensors; ++i) + priv->sensor[i].slope =3D 3200; + + priv->sensor[0].p1_calib_offset =3D 2; + priv->sensor[0].p2_calib_offset =3D -1; + priv->sensor[1].p1_calib_offset =3D -4; + priv->sensor[1].p2_calib_offset =3D -4; + priv->sensor[2].p1_calib_offset =3D 4; + priv->sensor[2].p2_calib_offset =3D 5; + priv->sensor[3].p1_calib_offset =3D 1; + priv->sensor[3].p2_calib_offset =3D 1; + priv->sensor[4].p1_calib_offset =3D 2; + priv->sensor[4].p2_calib_offset =3D 3; + priv->sensor[5].p1_calib_offset =3D -1; + priv->sensor[5].p2_calib_offset =3D -1; + priv->sensor[6].p1_calib_offset =3D 0; + priv->sensor[6].p2_calib_offset =3D -1; + priv->sensor[7].p1_calib_offset =3D 3; + priv->sensor[7].p2_calib_offset =3D 4; + priv->sensor[8].p1_calib_offset =3D 2; + priv->sensor[8].p2_calib_offset =3D 4; + priv->sensor[9].p1_calib_offset =3D 0; + priv->sensor[9].p2_calib_offset =3D 0; + priv->sensor[10].p1_calib_offset =3D -3; + priv->sensor[10].p2_calib_offset =3D -2; + + return init_common(priv); +} + static int __init init_8956(struct tsens_priv *priv) { priv->sensor[0].slope =3D 3313; priv->sensor[1].slope =3D 3275; @@ -223,6 +254,19 @@ struct tsens_plat_data data_8937 =3D { .fields =3D tsens_v1_regfields, }; =20 +static const struct tsens_ops ops_8952 =3D { + .init =3D init_8952, + .calibrate =3D tsens_calibrate_common, + .get_temp =3D get_temp_tsens_valid, +}; + +struct tsens_plat_data data_8952 =3D { + .num_sensors =3D 11, + .ops =3D &ops_8952, + .feat =3D &tsens_v1_feat, + .fields =3D tsens_v1_regfields, +}; + static const struct tsens_ops ops_8956 =3D { .init =3D init_8956, .calibrate =3D tsens_calibrate_common, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b5ec70201e2f..4d7013fc79d6 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -1191,6 +1191,9 @@ static const struct of_device_id tsens_table[] =3D { }, { .compatible =3D "qcom,msm8939-tsens", .data =3D &data_8939, + }, { + .compatible =3D "qcom,msm8952-tsens", + .data =3D &data_8952, }, { .compatible =3D "qcom,msm8956-tsens", .data =3D &data_8956, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index e8376accdff3..a35b15312961 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -669,7 +669,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, = data_8974, data_9607; =20 /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_89= 56; +extern struct tsens_plat_data data_tsens_v1, data_8937, data_8952, data_89= 76, data_8956; =20 /* TSENS v1 with no RPM targets */ extern const struct tsens_plat_data data_ipq5018; --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9129A4229C6; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; cv=none; b=LSpmcIGlZ7u1mKQPgMzwbn8I7YnrVPOjeOD3+P5TZAMY4P1u7bUXW9fnBg0IfT2VSumKT98k8SqqJCk7jMZdFG94ryfGLnMpctYHZmk9PI3L9qWXvLJPv24JCQ8WRrwXAwVszg3WLskiwlvFo76ZV4axWTw+I4Ab4OCtjzCExqc= ARC-Message-Signature: i=1; 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b=D+3PQMqpV26jjo2wy6LQArBecfr5zyU+Sb/6NVd2Tqho2Gm1YIeOCLxQRH8hSvCbp Gc3W1cS2ZRS7DjSwaLxYorpXLsFtFSLqGTRwNc39A3JDyvKdIZmUoGge+UH8IFBWVI kr+ESjIRkSClc96oXxKoaMvm9S6clbMAyBGN4mVT1Q6V936Pq4N+fBsHAptHxc/bds JMmBSeJ9Dlwk+pUWwuhu2CyL+hcZfhgFg1Qxkrd/FWFHwhALRnfZboB8rgAWq5ybYI Sen9IhiaesGzWjLercgt/JwtVO5ZV3H+hHw/ixsKnDnsIb22n/TKF4rRZh6QdGggi4 0SwJ1zVZVpfnA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EA8AC88E5D; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:27 +0300 Subject: [PATCH RFC 18/20] arm64: dts: qcom: Add initial support for MSM8952 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-18-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=54079; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=Q6cP0oC+rZuALc3TpqdF9n3yDX2oC+4FO0MtksYYSAs=; b=PfKaXPo6n0mq6AkTggKSBUfNyJ8e+H2WHH/ztdJCeUX2XkqKVf5mzYQgaqUmqCrUdrvlfAwba bBTvu8Ie9isDNwTHmZl2exGcK0yLpfgKBgfReiacdiOqP9Gru70xzDH X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add initial support for MSM8952 SoC. AI help is used for calculating qfprom nodes. Downstream reference for port is [1] which is very lightly modified version of [2]. Downstream reference used to calculate qfprom: [3] Currently supported features in this port: - Internal Storage support - MDSS - Basic Adsp remote proc support - Blsp 1 and 2 with i2c exists on shamrock device - Tsens support - USB - RPM with mpm (not fully wired) and master-stats support [1] https://github.com/Asderdd/android_kernel_generalmobile_shamrock/blob/c= m-14.1/arch/arm/boot/dts/qcom/msm8952.dtsi [2] https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-wea= r-7.0.0_r0.3/arch/arm/boot/dts/qcom/msm8952.dtsi [3] https://android.googlesource.com/kernel/msm.git/+/refs/tags/android-wea= r-7.0.0_r0.3/drivers/thermal/msm-tsens.c#1621 Assisted-By: LLM Signed-off-by: Muzaffer Kadir --- arch/arm64/boot/dts/qcom/msm8952.dtsi | 2257 +++++++++++++++++++++++++++++= ++++ 1 file changed, 2257 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8952.dtsi b/arch/arm64/boot/dts/qc= om/msm8952.dtsi new file mode 100644 index 000000000000..8b7fa84e7986 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8952.dtsi @@ -0,0 +1,2257 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Dang Huynh + * Copyright (C) 2026 Muzaffer Kadir + * Author: Muzaffer Kadir + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + qcom,acc =3D <&acc0>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x40000>; + cache-unified; + }; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + qcom,acc =3D <&acc1>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + qcom,acc =3D <&acc2>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + qcom,acc =3D <&acc3>; + clocks =3D <&apcs0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@100 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x100>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + qcom,acc =3D <&acc4>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + clocks =3D <&apcs1>; + #cooling-cells =3D <2>; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-unified; + }; + }; + + cpu5: cpu@101 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x101>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + qcom,acc =3D <&acc5>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + clocks =3D <&apcs1>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@102 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x102>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + qcom,acc =3D <&acc6>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + clocks =3D <&apcs1>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@103 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x103>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + qcom,acc =3D <&acc7>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + clocks =3D <&apcs1>; + #cooling-cells =3D <2>; + }; + + cpu-map { + /* Little Cores */ + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + /* Big Cores */ + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-msm8952", "qcom,scm"; + clocks =3D <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names =3D "core", + "bus", + "iface"; + #reset-cells =3D <1>; + + qcom,dload-mode =3D <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0x80000000 0 0>; + device_type =3D "memory"; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + qseecom_mem: reserved@85b00000 { + reg =3D <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg =3D <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + mpss_mem: mpss@86c00000 { + reg =3D <0x0 0x86c00000 0x0 0x5600000>; + no-map; + }; + + lpass_mem: lpass@8c200000 { + reg =3D <0x0 0x8c200000 0x0 0x1700000>; + no-map; + }; + + rmtfs_mem: rmtfs { + compatible =3D "qcom,rmtfs-mem"; + + size =3D <0x0 0x200000>; + alloc-ranges =3D <0x0 0xa0000000 0x0 0x2000000>; + no-map; + + qcom,client-id =3D <1>; + }; + + adsp_mem: adsp { + size =3D <0x0 0x400000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + + ramoops_mem: ramoops@dffc0000 { + compatible =3D "ramoops"; + reg =3D <0x0 0xdffc0000 0x0 0x40000>; + + record-size =3D <0x10000>; + console-size =3D <0x10000>; + pmsg-size =3D <0x20000>; + + status =3D "disabled"; + }; + + mba_mem: mba { + size =3D <0x0 0x100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + + wcnss_mem: wcnss { + size =3D <0x0 0x700000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + + venus_mem: venus { + size =3D <0x0 0x500000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + + status =3D "disabled"; + }; + }; + + cpu_opp_table_c0: opp-table-c0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz =3D /bits/ 64 <403200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + }; + + cpu_opp_table_c1: opp-table-c1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + }; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000>; + }; + + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + }; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + rpm: remoteproc { + compatible =3D "qcom,msm8952-rpm-proc", "qcom,rpm-proc"; + + master-stats { + compatible =3D "qcom,rpm-master-stats"; + qcom,rpm-msg-ram =3D <&apss_master_stats>, + <&mpss_master_stats>, + <&pronto_master_stats>, + <&tz_master_stats>, + <&lpass_master_stats>; + qcom,master-names =3D "APSS", "MPSS", "PRONTO", "TZ", "LPASS"; + }; + + smd-edge { + interrupts =3D ; + qcom,ipc =3D <&apcs1 8 0>; + qcom,smd-edge =3D <15>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-msm8952", "qcom,smd-rpm"; + qcom,smd-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-msm8952", "qcom,rpmcc"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmpd: power-controller { + compatible =3D "qcom,msm8952-rpmpd", "qcom,msm8917-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level =3D ; + }; + }; + }; + }; + }; + + mpm: interrupt-controller { + compatible =3D "qcom,mpm"; + qcom,rpm-msg-ram =3D <&apss_mpm>; + interrupts =3D ; + mboxes =3D <&apcs1 1>; + interrupt-controller; + #interrupt-cells =3D <2>; + #power-domain-cells =3D <0>; + interrupt-parent =3D <&intc>; + qcom,mpm-pin-count =3D <64>; + qcom,mpm-pin-map =3D <2 216>, /* TSENS UPLOW */ + <49 172>, /* USB ASYNC */ + <53 104>, /* MDSS */ + <58 166>, /* USB */ + <62 222>; /* SPMI */ + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + + interrupts =3D ; + + mboxes =3D <&apcs1 10>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + + interrupts =3D ; + + mboxes =3D <&apcs1 14>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-wcnss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <451>, <431>; + + interrupts =3D ; + + mboxes =3D <&apcs1 18>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smsm { + compatible =3D "qcom,smsm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + mboxes =3D <0>, <&apcs1 13>, <&apcs1 9>, <&apcs1 19>; + + apps_smsm: apps@0 { + reg =3D <0>; + + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smsm: hexagon@1 { + reg =3D <1>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wcnss_smsm: wcnss@6 { + reg =3D <6>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0xffffffff>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + rng@22000 { + compatible =3D "qcom,prng"; + reg =3D <0x00022000 0x140>; + clocks =3D <&gcc GCC_PRNG_AHB_CLK>; + clock-names =3D "core"; + }; + + qfprom: qfprom@5c000 { + compatible =3D "qcom,msm8952-qfprom", "qcom,qfprom"; + reg =3D <0x0005c000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tsens_base0: base0@a0 { + reg =3D <0xa0 0x1>; + bits =3D <0 8>; + }; + + tsens_s5_p1: s5-p1@a1 { + reg =3D <0xa1 0x1>; + bits =3D <0 6>; + }; + tsens_s5_p2: s5-p2@a1 { + reg =3D <0xa1 0x2>; + bits =3D <6 6>; + }; + + tsens_s6_p1: s6-p1@a2 { + reg =3D <0xa2 0x2>; + bits =3D <4 6>; + }; + tsens_s6_p2: s6-p2@a3 { + reg =3D <0xa3 0x1>; + bits =3D <2 6>; + }; + + tsens_s7_p1: s7-p1@a4 { + reg =3D <0xa4 0x1>; + bits =3D <0 6>; + }; + tsens_s7_p2: s7-p2@a4 { + reg =3D <0xa4 0x2>; + bits =3D <6 6>; + }; + + tsens_s8_p1: s8-p1@a5 { + reg =3D <0xa5 0x2>; + bits =3D <4 6>; + }; + tsens_s8_p2: s8-p2@a6 { + reg =3D <0xa6 0x1>; + bits =3D <2 6>; + }; + + tsens_base1: base1@a7 { + reg =3D <0xa7 0x1>; + bits =3D <0 8>; + }; + + tsens_mode: mode@d0 { + reg =3D <0xd0 0x1>; + bits =3D <0 3>; + }; + tsens_s0_p1: s0-p1@d0 { + reg =3D <0xd0 0x2>; + bits =3D <3 6>; + }; + + tsens_s0_p2: s0-p2@d1 { + reg =3D <0xd1 0x1>; + bits =3D <1 6>; + }; + tsens_s1_p1: s1-p1@d1 { + reg =3D <0xd1 0x2>; + bits =3D <7 6>; + }; + + tsens_s1_p2: s1-p2@d2 { + reg =3D <0xd2 0x2>; + bits =3D <5 6>; + }; + + tsens_s2_p1: s2-p1@d3 { + reg =3D <0xd3 0x2>; + bits =3D <3 6>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg =3D <0xd4 0x1>; + bits =3D <1 6>; + }; + tsens_s3_p1: s3-p1@d4 { + reg =3D <0xd4 0x2>; + bits =3D <7 6>; + }; + + tsens_s3_p2: s3-p2@d5 { + reg =3D <0xd5 0x2>; + bits =3D <5 6>; + }; + + tsens_s4_p1: s4-p1@d6 { + reg =3D <0xd6 0x2>; + bits =3D <3 6>; + }; + tsens_s4_p2: s4-p2@d7 { + reg =3D <0xd7 0x1>; + bits =3D <1 6>; + }; + + tsens_s9_p1: s9-p1@f0 { + reg =3D <0xf0 0x1>; + bits =3D <0 6>; + }; + tsens_s9_p2: s9-p2@f0 { + reg =3D <0xf0 0x2>; + bits =3D <6 6>; + }; + + tsens_s10_p1: s10-p1@f1 { + reg =3D <0xf1 0x2>; + bits =3D <4 6>; + }; + tsens_s10_p2: s10-p2@f2 { + reg =3D <0xf2 0x1>; + bits =3D <2 6>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible =3D "qcom,rpm-msg-ram"; + reg =3D <0x00060000 0x8000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x00060000 0x8000>; + + apss_master_stats: sram@150 { + reg =3D <0x150 0x14>; + }; + + apss_mpm: sram@1d0 { + reg =3D <0x1d0 0x64>; + }; + + mpss_master_stats: sram@1150 { + reg =3D <0x1150 0x14>; + }; + + pronto_master_stats: sram@2550 { + reg =3D <0x2550 0x14>; + }; + + tz_master_stats: sram@3550 { + reg =3D <0x3550 0x14>; + }; + + lpass_master_stats: sram@4550 { + reg =3D <0x4550 0x14>; + }; + }; + + usb_hs_phy: phy@6c000 { + compatible =3D "qcom,usb-hs-28nm-femtophy"; + reg =3D <0x0006c000 0x200>; + #phy-cells =3D <0>; + clocks =3D <&xo_board>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names =3D "ref", "ahb", "sleep"; + resets =3D <&gcc RST_QUSB2_PHY_BCR>, + <&gcc RST_USB2_HS_PHY_ONLY_BCR>; + reset-names =3D "phy", "por"; + + status =3D "disabled"; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,msm8952-tsens", "qcom,tsens-v1"; + reg =3D <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells =3D <&tsens_mode>, + <&tsens_base0>, <&tsens_base1>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names =3D "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; + interrupts =3D ; + interrupt-names =3D "uplow"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <11>; + }; + + restart@4ab000 { + compatible =3D "qcom,pshold"; + reg =3D <0x004ab000 0x4>; + }; + crypto_dma: dma-controller@704000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x00704000 0x20000>; + interrupts =3D ; + #dma-cells =3D <1>; + qcom,ee =3D <1>; + qcom,num-ees =3D <4>; + num-channels =3D <16>; + qcom,controlled-remotely; + }; + + crypto: crypto@73a000 { + compatible =3D "qcom,crypto-v5.4"; + reg =3D <0x0073a000 0x6000>; + clocks =3D <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names =3D "iface", "bus", "core"; + dmas =3D <&crypto_dma 2>, <&crypto_dma 3>; + dma-names =3D "rx", "tx"; + }; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8952-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 134>; + wakeup-parent =3D <&mpm>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + blsp_spi1_default: spi1-default-state { + spi-pins { + pins =3D "gpio0", "gpio1", "gpio3"; + function =3D "blsp_spi1"; + drive-strength =3D <12>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio2"; + function =3D "blsp_spi1"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + blsp_spi1_sleep: spi1-sleep-state { + spi-pins { + pins =3D "gpio0", "gpio1", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cs-pins { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "blsp_uart1"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + + blsp1_uart1_console_default: blsp-uart1-console-default-state { + tx-pins { + pins =3D "gpio0"; + function =3D "blsp_uart1"; + drive-strength =3D <16>; + bias-disable; + bootph-all; + }; + + rx-pins { + pins =3D "gpio1"; + function =3D "blsp_uart1"; + drive-strength =3D <16>; + bias-pull-up; + bootph-all; + }; + }; + + blsp1_uart1_console_sleep: blsp-uart1-console-sleep-state { + pins =3D "gpio0", "gpio1"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "blsp_uart2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "blsp_i2c2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins =3D "gpio6", "gpio7"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins =3D "gpio10", "gpio11"; + function =3D "blsp_i2c3"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { + pins =3D "gpio10", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + + blsp2_i2c1_default: blsp2-i2c1-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "blsp_i2c5"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { + pins =3D "gpio18", "gpio19"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c4_default: blsp2-i2c4-default-state { + pins =3D "gpio98", "gpio99"; + function =3D "blsp_i2c8"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { + pins =3D "gpio98", "gpio99"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc1_clk_on: sdc1-clk-on-state { + pins =3D "sdc1_clk"; + bias-disable; + drive-strength =3D <16>; + }; + + sdc1_clk_off: sdc1-clk-off-state { + pins =3D "sdc1_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc1_cmd_on: sdc1-cmd-on-state { + pins =3D "sdc1_cmd"; + bias-disable; + drive-strength =3D <10>; + }; + + sdc1_cmd_off: sdc1-cmd-off-state { + pins =3D "sdc1_cmd"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc1_data_on: sdc1-data-on-state { + pins =3D "sdc1_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc1_data_off: sdc1-data-off-state { + pins =3D "sdc1_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + + sdc1_rclk_on: sdc1-rclk-on-state { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + + sdc1_rclk_off: sdc1-rclk-off-state { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + + sdc2_clk_on: sdc2-clk-on-state { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + sdc2_clk_off: sdc2-clk-off-state { + pins =3D "sdc2_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <2>; + }; + + sdc2_data_on: sdc2-data-on-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc2_data_off: sdc2-data-off-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + + sdc2_cd_on: cd-on-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sdc2_cd_off: cd-off-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8952"; + reg =3D <0x01800000 0x80000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; + clock-names =3D "xo", + "xo_a", + "dsi0pll", + "dsi0pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01905000 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1937000 { + compatible =3D "qcom,tcsr-msm8952", "syscon"; + reg =3D <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible =3D "qcom,mdss"; + reg =3D <0x01a00000 0x1000>, + <0x01ac8000 0x3000>; + reg-names =3D "mdss_phys", "vbif_phys"; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "vsync"; + + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <1>; + + resets =3D <&gcc RST_MDSS_BCR>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@1a01000 { + compatible =3D "qcom,msm8952-mdp5", "qcom,mdp5"; + reg =3D <0x01a01000 0x89000>; + reg-names =3D "mdp_phys"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&gcc MDSS_GDSC>; + + iommus =3D <&apps_iommu 0x17>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_mdp_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-266670000 { + opp-hz =3D /bits/ 64 <266670000>; + required-opps =3D <&rpmpd_opp_svs_plus>; + }; + + opp-320000000 { + opp-hz =3D /bits/ 64 <320000000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@1a98000 { + compatible =3D "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x01a98000 0x25c>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + assigned-clocks =3D <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys =3D <&mdss_dsi0_phy>; + + operating-points-v2 =3D <&dsi0_opp_table>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&mdss_mdp_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-120000000 { + opp-hz =3D /bits/ 64 <120000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a98300 { + compatible =3D "qcom,dsi-phy-28nm-lp"; + reg =3D <0x01a98300 0xd4>, + <0x01a98500 0x280>, + <0x01a98780 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + }; + + gpu: gpu@1c00000 { + compatible =3D "qcom,adreno-405.0", "qcom,adreno"; + reg =3D <0x01c00000 0x10000>; + reg-names =3D "kgsl_3d0_reg_memory"; + interrupts =3D ; + interrupt-names =3D "kgsl_3d0_irq"; + clock-names =3D "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d", + "rbbmtimer"; + clocks =3D <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>, + <&gcc GCC_OXILI_TIMER_CLK>; + power-domains =3D <&gcc OXILI_GX_GDSC>; + operating-points-v2 =3D <&opp_table>; + iommus =3D <&gpu_iommu 0>, <&gpu_iommu 1>; + #cooling-cells =3D <2>; + + status =3D "disabled"; + + opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-550000000 { + opp-hz =3D /bits/ 64 <550000000>; + required-opps =3D <&rpmpd_opp_turbo>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmpd_opp_nom_plus>; + }; + + opp-465000000 { + opp-hz =3D /bits/ 64 <465000000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + required-opps =3D <&rpmpd_opp_svs_plus>; + }; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmpd_opp_min_svs>; + }; + }; + }; + + apps_iommu: iommu@1e20000 { + compatible =3D "qcom,msm8952-iommu", "qcom,msm-iommu-v2"; + ranges =3D <0 0x01e20000 0x20000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names =3D "iface", "bus"; + + qcom,iommu-secure-id =3D <17>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + + /* CPP */ + iommu-ctx@13000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x13000 0x1000>; + interrupts =3D ; + }; + + /* JPEG ENC0 */ + iommu-ctx@14000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x14000 0x1000>; + interrupts =3D ; + }; + + /* VFE */ + iommu-ctx@15000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x15000 0x1000>; + interrupts =3D ; + }; + + /* VENUS NS */ + iommu-ctx@16000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x16000 0x1000>; + interrupts =3D ; + }; + + /* MDP0 */ + iommu-ctx@17000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x17000 0x1000>; + interrupts =3D ; + }; + + /* PRONTO */ + iommu-ctx@18000 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x18000 0x1000>; + interrupts =3D ; + }; + + }; + + gpu_iommu: iommu@1f08000 { + compatible =3D "qcom,msm8952-iommu", "qcom,msm-iommu-v2"; + ranges =3D <0 0x01f08000 0x10000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names =3D "iface", "bus"; + + qcom,iommu-secure-id =3D <18>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + + /* gfx3d user */ + iommu-ctx@0 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x0 0x1000>; + qcom,ctx-asid =3D <0>; + interrupts =3D ; + }; + + /* gfx3d secure */ + iommu-ctx@1000 { + compatible =3D "qcom,msm-iommu-v2-sec"; + reg =3D <0x1000 0x1000>; + qcom,ctx-asid =3D <2>; + interrupts =3D ; + }; + + /* gfx3d priv */ + iommu-ctx@3000 { + compatible =3D "qcom,msm-iommu-v2-sec"; + reg =3D <0x3000 0x1000>; + qcom,ctx-asid =3D <1>; + interrupts =3D ; + }; + }; + + spmi_bus: spmi@200f000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts =3D ; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x04044000 0x19000>; + interrupts =3D ; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + + num-channels =3D <6>; + qcom,num-ees =3D <1>; + qcom,powered-remotely; + + status =3D "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible =3D "qcom,msm8952-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07824900 0x500>, <0x07824000 0x800>, <0x7824e00 0x200>; + reg-names =3D "hc", "core", "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "core", "xo"; + + pinctrl-0 =3D <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 =3D <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_of= f>; + pinctrl-names =3D "default", "sleep"; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + mmc-hs400-1_8v; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + bus-width =3D <8>; + non-removable; + + status =3D "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible =3D "qcom,msm8952-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "core", "xo"; + + pinctrl-0 =3D <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 =3D <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-names =3D "default", "sleep"; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + + bus-width =3D <4>; + + status =3D "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07884000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <12>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp1_uart1: serial@78af000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078af000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_uart1_console_default>; + pinctrl-1 =3D <&blsp1_uart1_console_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078b0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_uart2_default>; + pinctrl-1 =3D <&blsp1_uart2_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "disabled"; + }; + + blsp1_spi1: spi@78b5000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b5000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp_spi1_default>; + pinctrl-1 =3D <&blsp_spi1_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b6000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_i2c2_default>; + pinctrl-1 =3D <&blsp1_i2c2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp1_i2c3: i2c@78b7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_i2c3_default>; + pinctrl-1 =3D <&blsp1_i2c3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_dma: dma-controller@78c4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x078c4000 0x17000>; + interrupts =3D ; + #dma-cells =3D <1>; + num-channels =3D <4>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + qcom,controlled-remotely; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07ac4000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + qcom,controlled-remotely; + }; + + blsp2_i2c1: i2c@7af5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_i2c1_default>; + pinctrl-1 =3D <&blsp2_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp2_i2c4: i2c@7af8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af8000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp2_i2c4_default>; + pinctrl-1 =3D <&blsp2_i2c4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + usb: usb@78db000 { + compatible =3D "qcom,ci-hdrc"; + reg =3D <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts =3D , + ; + clocks =3D <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names =3D "iface", "core"; + assigned-clocks =3D <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates =3D <80000000>; + resets =3D <&gcc RST_USB_HS_BCR>; + reset-names =3D "core"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config =3D <0>; + dr_mode =3D "otg"; + phy_type =3D "ulpi"; + phy-names =3D "usb-phy"; + phys =3D <&usb_hs_phy>; + #reset-cells =3D <1>; + + status =3D "disabled"; + }; + + imem: sram@8600000 { + compatible =3D "qcom,msm8976-imem", "syscon", "simple-mfd"; + reg =3D <0x08600000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0 0x08600000 0x1000>; + + pil-reloc@94c { + compatible =3D "qcom,pil-reloc-info"; + reg =3D <0x94c 0xc8>; + }; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + apcs1: mailbox@b011000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b011000 0x1000>; + #mbox-cells =3D <1>; + clocks =3D <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", "aux", "ref"; + #clock-cells =3D <0>; + }; + + a53pll_c1: clock@b016000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b016000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + operating-points-v2 =3D <&pll_opp_table_c1>; + + pll_opp_table_c1: opp-table { + compatible =3D "operating-points-v2"; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + }; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000>; + }; + + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + }; + }; + }; + + watchdog@b017000 { + compatible =3D "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg =3D <0x0b017000 0x1000>; + interrupts =3D , + ; + clocks =3D <&sleep_clk>; + }; + + acc4: clock-controller@b088000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b088000 0x1000>; + }; + + acc5: clock-controller@b098000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b098000 0x1000>; + }; + + acc6: clock-controller@b0a8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b0a8000 0x1000>; + }; + + acc7: clock-controller@b0b8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b0b8000 0x1000>; + }; + + apcs0: mailbox@b111000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b111000 0x1000>; + #mbox-cells =3D <1>; + clocks =3D <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", "aux", "ref"; + #clock-cells =3D <0>; + }; + + a53pll_c0: clock@b116000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b116000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + operating-points-v2 =3D <&pll_opp_table_c0>; + + pll_opp_table_c0: opp-table { + compatible =3D "operating-points-v2"; + + opp-403200000 { + opp-hz =3D /bits/ 64 <403200000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + + }; + }; + + acc0: clock-controller@b188000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b188000 0x1000>; + }; + + acc1: clock-controller@b198000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b198000 0x1000>; + }; + + acc2: clock-controller@b1a8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b1a8000 0x1000>; + }; + + acc3: clock-controller@b1b8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b1b8000 0x1000>; + }; + + timer@b120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0b120000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + clock-frequency =3D <19200000>; + + frame@b121000 { + reg =3D <0x0b121000 0x1000>, <0x0b122000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@b123000 { + reg =3D <0x0b123000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@b124000 { + reg =3D <0x0b124000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@b125000 { + reg =3D <0x0b125000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@b126000 { + reg =3D <0x0b126000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@b127000 { + reg =3D <0x0b127000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@b128000 { + reg =3D <0x0b128000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + + a53pll_cci: clock@b1d0000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b1d0000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + }; + + apcs2: mailbox@b1d1000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b1d1000 0x1000>; + clocks =3D <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC= >; + clock-names =3D "pll", "aux", "ref"; + #clock-cells =3D <0>; + #mbox-cells =3D <1>; + }; + + adsp: remoteproc@c200000 { + compatible =3D "qcom,msm8996-adsp-pil"; + reg =3D <0x0c200000 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks =3D <&rpmcc RPM_SMD_BB_CLK1>; + clock-names =3D "xo"; + + power-domains =3D <&rpmpd RPMPD_VDDCX>; + power-domain-names =3D "cx"; + + qcom,smem-states =3D <&adsp_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + memory-region =3D <&lpass_mem>; + + status =3D "disabled"; + + smd-edge { + interrupts =3D ; + + mboxes =3D <&apcs1 8>; + + qcom,smd-edge =3D <1>; + qcom,remote-pid =3D <2>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 1>; + trips { + modem_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + qdsp-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 2>; + trips { + qdsp_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + l2-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 4>; + + trips { + l2_alert0: trip-point0 { + temperature =3D <50000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + l2_alert1: trip-point1 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + l2_crit: l2-crit { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 5>; + + cooling-maps { + map0 { + trip =3D <&cpu4_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu4_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu4_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 6>; + + cooling-maps { + map0 { + trip =3D <&cpu5_alert1>; + cooling-device =3D <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu5_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu5_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 7>; + + cooling-maps { + map0 { + trip =3D <&cpu6_alert1>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu6_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu6_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 8>; + + cooling-maps { + map0 { + trip =3D <&cpu7_alert1>; + cooling-device =3D <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu7_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu7_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu0-3-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 9>; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu0_crit: cpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 10>; + + trips { + gpu_crit: gpu-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; + + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <19200000>; + }; +}; + --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A937D423EB7; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; cv=none; b=e85nQNxIhSmxqj1P/R85FI+ql61Wnepsh3AU8n+Mn2Z3u9bqLTP+S6P26kot/EfInfbHV9NIwJoLAPT+OedggHOQPb/8LflOYKAnuPv0R4KPciSPWV2WPzHi1igq+gtGrxDmpgOYDj4evoOb8iFct0kPuSGCUY4EjePDNMywI8E= ARC-Message-Signature: i=1; a=rsa-sha256; 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b=bQP7qEAKHeRMUl1hH0MDC7J7a9cCAh8NKn/od9sIQW3Qqur7s9MIoLz49zM1K9lED wk2WyoQsBEmExpBPmQSFL6zcMYW93eBNhgINqZnD+eO5keVyH0fZrs8mkPo0d+vbmR hYmPmhDM+tSHIqPmOxxEaRB7T6+lnlcgBV1Eg1a9bspGZDBBcEllathXWgWBR1Tn7p d9ZAr39TWKRa7tK32TmUJN0XVOAjxH5LhUacvjl91WrtCFV6r91kvX/nyj5XcomssG k+/ybWKw7jotEbXa+l6k4pT6Mr7cjX43L3pvqeq+VkChPBvmRj5rvgdfuc1RrRva6T bddc3dSaEMpgA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32B5DC88E60; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:28 +0300 Subject: [PATCH RFC 19/20] dt-bindings: input: touchscreen: goodix: Add binding for GT970 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-19-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=1586; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=Qoy33EJn3v6X56PtrYhm3G9p9Sahcex0RkQOCVhpJ3w=; b=bdZyKcCT7IdWUsls580MpK+jGBXtthmOOQm6HNiFHMVSEF6gRr/EocPv5cO4TZRwkV2Y2986M ppD+uWM839hCCUX+1HyoRAqVC0StePZL2tApZJf9FJXPIhcPKJU2fmt X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir GT970 works with GT911 driver, document it to be used with GT911 compatible. Signed-off-by: Muzaffer Kadir --- .../bindings/input/touchscreen/goodix.yaml | 35 ++++++++++++------= ---- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.yam= l b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml index a26a54d63a1c..4be2c137abd7 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml @@ -14,21 +14,26 @@ allOf: =20 properties: compatible: - enum: - - goodix,gt1151 - - goodix,gt1158 - - goodix,gt5663 - - goodix,gt5688 - - goodix,gt911 - - goodix,gt9110 - - goodix,gt912 - - goodix,gt9147 - - goodix,gt917s - - goodix,gt927 - - goodix,gt9271 - - goodix,gt928 - - goodix,gt9286 - - goodix,gt967 + oneOf: + - enum: + - goodix,gt1151 + - goodix,gt1158 + - goodix,gt5663 + - goodix,gt5688 + - goodix,gt911 + - goodix,gt9110 + - goodix,gt912 + - goodix,gt9147 + - goodix,gt917s + - goodix,gt927 + - goodix,gt9271 + - goodix,gt928 + - goodix,gt9286 + - goodix,gt967 + - items: + - enum: + - goodix,gt970 + - const: goodix,gt911 =20 reg: enum: [ 0x5d, 0x14 ] --=20 2.54.0 From nobody Fri Sep 25 12:34:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC003424646; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; cv=none; b=lpf3LQwxmk5CNcWgtE58aAco0XmDXl9L/BNyZ9TtxySAhKD4b4bumncGJXvul+o65Rrqq5AyplWj3ZNrESpgqcG2upz2a/d8k1X62qCChnPVWl8QzgkxLsq9XfZkJXmo63O1xHkgcMXlVjWcEf+7PZyVxeg5UM/ULTdtyrnpSKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789202359; c=relaxed/simple; bh=nD48Rbf55h4sWLzi95Et5X6Uny5CPQdhvbqLqn3l11k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=exBiwRgQpoMvZLB7RoFZRnxzroXtixULf2q3t7NpGhjh4Bl64GSuiQpntThiqfDg3TosU0kHO4JnrZWo5WlJPKxDEhndbRLfACiNe2n9fiEV8mJWa/1KX71Mpml0XRoFFdJXKP004FoDB/Ks6xlTDuD9aP/XRhjhZYhPWAuSE7U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bT1sqa0h; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bT1sqa0h" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5D824C4DE1F; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789202359; bh=nD48Rbf55h4sWLzi95Et5X6Uny5CPQdhvbqLqn3l11k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bT1sqa0hSGWxijxsD54/aO6BDrpuRy+MxLRrG5tOfAD8q8EpAyYc33EA5brcRokHR 7uFpyX80f99Sqe6aKg/E5khnG4etc1rXSCgxDMPRAt4OYse7WIW0zfrFnljLBglgDA 0WDeGWVh6sttWTOCF24oKB0aqLNG+SHTuAYpo6effFXUabtI1FJ4lns7r5iE+XfSeW VH98QwrLEccIaERW1NCaYFTP8WdgrWby0TTeD1puR6bYgIFxChC+xWxrNzAy0W2CxT uEjqjAMkH+eXKreYbLpoNrjA2lElF6GXtaYfDdifAxFRQVbe5J8bqzLMr1QjFuDaq+ ZCp1pMm8+50fA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4781AC88E56; Sat, 12 Sep 2026 08:39:19 +0000 (UTC) From: Muzaffer Kadir via B4 Relay Date: Sat, 12 Sep 2026 11:39:29 +0300 Subject: [PATCH RFC 20/20] arm64: dts: qcom: generalmobile-shamrock: new device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260912-msm8952-initial-support-v1-20-0e742578b524@mainlining.org> References: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> In-Reply-To: <20260912-msm8952-initial-support-v1-0-0e742578b524@mainlining.org> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Ulf Hansson , Konrad Dybcio , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Lee Jones , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Robert Marko , Guru Das Srinagesh , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , Dang Huynh , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, iommu@lists.linux.dev, mfd@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-input@vger.kernel.org, Muzaffer Kadir X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789202354; l=11139; i=muzafferkadir@mainlining.org; s=20260816; h=from:subject:message-id; bh=LCzevTgTqTbZMUx77r9xIrvOtg8agw+pOgdFFe2F8OI=; b=Zt9U45CXeRUso7gHItINI29ZBZOM5SeFnBW3fRl0fEdvMHnCzOsLAFiDs/Z9UjEJN+i3gnO7N 59fC6iGHvgLDg0IJ5VExg/sBHEA0CYPCjzIh29kQVHT7ldOlVDmeTqM X-Developer-Key: i=muzafferkadir@mainlining.org; a=ed25519; pk=4zkv4suQ3cYcO4Z7CrV8JSSjEGLBGepUtvQCFjgnYIU= X-Endpoint-Received: by B4 Relay for muzafferkadir@mainlining.org/20260816 with auth_id=954 X-Original-From: Muzaffer Kadir Reply-To: muzafferkadir@mainlining.org From: Muzaffer Kadir Add General Mobile Shamrock (GM 5 Plus). Shamrock is designed similar to L9300. Downstream reference is [1]. [1] https://github.com/Asderdd/android_kernel_generalmobile_shamrock/blob/c= m-14.1/arch/arm/boot/dts/qcom/msm8952-l9300.dtsi Signed-off-by: Muzaffer Kadir --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/msm8952-generalmobile-shamrock.dts | 426 +++++++++++++++++= ++++ 2 files changed, 427 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index d6547fb18edf..3cc2dfb09116 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -125,6 +125,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-samsung-a7.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-wingtech-wt82918.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-wingtech-wt82918hd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D msm8952-generalmobile-shamrock.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-flipkart-rimob.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-xiaomi-daisy.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8952-generalmobile-shamrock.dts b/= arch/arm64/boot/dts/qcom/msm8952-generalmobile-shamrock.dts new file mode 100644 index 000000000000..22723b62d3d6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8952-generalmobile-shamrock.dts @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8952.dtsi" +#include "pm8950.dtsi" +#include "pmi8950.dtsi" +#include +#include + +/ { + model =3D "General Mobile GM 5 Plus (shamrock)"; + compatible =3D "generalmobile,shamrock", "qcom,msm8952"; + qcom,msm-id =3D ; + qcom,board-id =3D ; + chassis-type =3D "handset"; + + aliases { + mmc0 =3D &sdhc_1; /* SDC1 eMMC slot */ + mmc1 =3D &sdhc_2; /* SDC2 SD card slot */ + serial0 =3D &blsp1_uart2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + + framebuffer { + compatible =3D "simple-framebuffer"; + memory-region =3D <&cont_splash_mem>; + + width =3D <1080>; + height =3D <1920>; + stride =3D <(1080 * 3)>; + format =3D "r8g8b8"; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + reserved-memory { + cont_splash_mem: cont-splash@83200000 { + reg =3D <0x0 0x83200000 0x0 (1080 * 1920 * 3)>; + no-map; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&gpio_hall_sensor_default>, <&gpio_keys_default>; + pinctrl-names =3D "default"; + + event-hall-sensor { + label =3D "Hall Effect Sensor"; + gpios =3D <&tlmm 46 GPIO_ACTIVE_LOW>; + linux,input-type =3D ; + linux,code =3D ; + linux,can-disable; + wakeup-source; + }; + + button-volume-up { + label =3D "Volume Up"; + gpios =3D <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code =3D ; + debounce-interval =3D <15>; + wakeup-source; + }; + }; + + /* Front Flash */ + flash-led-controller { + compatible =3D "sgmicro,sgm3140"; + + enable-gpios =3D <&tlmm 33 GPIO_ACTIVE_HIGH>; + flash-gpios =3D <&tlmm 128 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&front_flash_default>; + pinctrl-names =3D "default"; + + front_flash_led: led { + function =3D LED_FUNCTION_FLASH; + color =3D ; + flash-max-microamp =3D <1000000>; + led-max-microamp =3D <625000>; + flash-max-timeout-us =3D <1280000>; + }; + }; + + battery: battery { + compatible =3D "simple-battery"; + + charge-term-current-microamp =3D <100000>; + charge-full-design-microamp-hours =3D <3100000>; + constant-charge-current-max-microamp =3D <3000000>; + constant-charge-voltage-max-microvolt =3D <4400000>; + voltage-min-design-microvolt =3D <3400000>; + voltage-max-design-microvolt =3D <4400000>; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph-pwr"; + regulator-always-on; + regulator-boot-on; + }; + + multi-led { + compatible =3D "leds-group-multicolor"; + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + leds =3D <&red_status>, <&green_status>, <&blue_status>; + }; + +}; + +&blsp2_i2c1 { + status =3D "okay"; + + /* FUSB301 @25 USB-C Controller */ + + tpa6130a2: tpa6130a2@60 { + compatible =3D "ti,tpa6130a2"; + pinctrl-0 =3D <&tpa6130a2_default>; + pinctrl-names =3D "default"; + reg =3D <0x60>; + power-gpios =3D <&tlmm 61 GPIO_ACTIVE_HIGH>; + Vdd-supply =3D <&pm8950_l22>; + }; + + tusb320: tusb320@67 { + compatible =3D "ti,tusb320"; + reg =3D <0x67>; + interrupts-extended =3D <&tlmm 45 IRQ_TYPE_EDGE_RISING>; + }; + + led-controller@68 { + compatible =3D "si-en,sn3193"; + reg =3D <0x68>; + + shutdown-gpios =3D <&tlmm 68 GPIO_ACTIVE_HIGH>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + red_status: led@1 { + reg =3D <1>; + label =3D "red:status"; + led-max-microamp =3D <17500>; + }; + + green_status: led@2 { + reg =3D <2>; + label =3D "green:status"; + led-max-microamp =3D <17500>; + }; + + blue_status: led@3 { + reg =3D <3>; + label =3D "blue:status"; + led-max-microamp =3D <17500>; + }; + }; +}; + +&blsp1_i2c2 { + status =3D "okay"; + /* SMB1351 @1d charger */ + /* wsa881x-i2c @e @44 @f @45 audio amplifier */ +}; + +&blsp1_i2c3 { + status =3D "okay"; + + /* himax,852x@48 Touchscreen */ + + touchscreen@5d { + compatible =3D "goodix,gt970", "goodix,gt911"; + reg =3D <0x5d>; + interrupts-extended =3D <&tlmm 65 IRQ_TYPE_EDGE_FALLING>; + irq-gpios =3D <&tlmm 65 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&tlmm 64 GPIO_ACTIVE_HIGH>; + AVDD28-supply =3D <&pm8950_l10>; + VDDIO-supply =3D <&pm8950_l6>; + + pinctrl-0 =3D <&touchscreen_default>; + pinctrl-names =3D "default"; + + touchscreen-size-x =3D <1080>; + touchscreen-size-y =3D <1920>; + }; +}; + +&pm8950_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&sdhc_1 { + vmmc-supply =3D <&pm8950_l8>; + vqmmc-supply =3D <&pm8950_l5>; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; + vmmc-supply =3D <&pm8950_l11>; + vqmmc-supply =3D <&pm8950_l12>; + + status =3D "okay"; +}; + +&sdc2_cd_on { + /delete-property/ bias-pull-up; + bias-disable; +}; + +&pmi8950_wled { + qcom,enabled-strings =3D <0 1>; + qcom,current-limit-microamp =3D <30000>; + qcom,ovp-millivolt =3D <29500>; + qcom,external-pfet; + + status =3D "okay"; +}; + +&ramoops_mem { + status =3D "okay"; +}; + +&adsp { + status =3D "okay"; +}; + +&lpass_mem { + status =3D "okay"; +}; + +&pm8950_spmi_regulators { + // PM8950 S5 + S6 =3D VDD_APC supply + pm8950_s5: s5 { + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1350000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&rpm_requests { + pm8950_rpm_regulators: regulators { + compatible =3D "qcom,rpm-pm8950-regulators"; + vdd_s1-supply =3D <&vph_pwr>; + vdd_s2-supply =3D <&vph_pwr>; + vdd_s3-supply =3D <&vph_pwr>; + vdd_s4-supply =3D <&vph_pwr>; + vdd_s6-supply =3D <&vph_pwr>; + vdd_l1_l19-supply =3D <&pm8950_s3>; + vdd_l2_l23-supply =3D <&pm8950_s3>; + vdd_l3-supply =3D <&pm8950_s3>; + vdd_l5_l6_l7_l16-supply =3D <&pm8950_s4>; + vdd_l8_l11_l12_l17_l22-supply =3D <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply =3D <&vph_pwr>; + + pm8950_s1: s1 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1225000>; + }; + + pm8950_s3: s3 { + regulator-min-microvolt =3D <1300000>; + regulator-max-microvolt =3D <1300000>; + }; + pm8950_s4: s4 { + regulator-min-microvolt =3D <2050000>; + regulator-max-microvolt =3D <2050000>; + }; + + pm8950_l2: l2 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + /* pm8950_l3 is managed by rpmpd (RPMPD_VDDMX) */ + + pm8950_l5: l5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l6: l6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l7: l7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l8: l8 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8950_l9: l9 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l10: l10 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8950_l11: l11 { + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <2950000>; + regulator-allow-set-load; + regulator-system-load =3D <200000>; + }; + + pm8950_l12: l12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8950_l13: l13 { + regulator-min-microvolt =3D <3075000>; + regulator-max-microvolt =3D <3075000>; + }; + + pm8950_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l17: l17 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2850000>; + }; + + pm8950_l19: l19 { + regulator-min-microvolt =3D <1225000>; + regulator-max-microvolt =3D <1350000>; + }; + + pm8950_l22: l22 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8950_l23: l23 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <20 4>; // Downstream doesn't use 21,22,23. 24 i= s mdss_te + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins =3D "gpio46"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + front_flash_default: front-flash-default-state { + pins =3D "gpio33", "gpio128"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + gpio_keys_default: gpio-keys-default-state { + pins =3D "gpio85"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + touchscreen_default: touchscreen-default-state { + pins =3D "gpio65", "gpio64"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + tpa6130a2_default: tpa6130a2-default-state { + pins =3D "gpio61"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + output-low; + }; +}; + +&sleep_clk { + clock-frequency =3D <32768>; +}; + +&xo_board { + clock-frequency =3D <19200000>; +}; --=20 2.54.0