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[144.49.247.25]) by smtp-relay.gmail.com with ESMTPS id 956f58d0204a3-67125b7d75asm134565d50.2.2026.09.11.16.35.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2026 16:35:49 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-9308eafb465so329415685a.2 for ; Fri, 11 Sep 2026 16:35:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1789169748; x=1789774548; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=b2fm0ws0RI4s9RoRTTFvcpWCb6oGc74Nxq3EnwLBIAc=; b=agyq7AaoAhnxpaxQe5nJqFpQRS/b4NutoFP+BL7ljaM9Fbm2gvkxGafMrARpQorFt5 JEZv0NhnNw5ohiu2xz39LO4nxm+lHg3+zEEEMDmg/kKZBm5uA6jRTLwnDszPhcbPGxj9 sFqobIOK58AELPbOzAaBqtCJlbbfCRaJt0HLA= X-Forwarded-Encrypted: i=1; AKwUvByKIryfPGkw3G65qfylRiwSKK4mOscQo/zEeMEDMUBFGmPEOoLWmYQRblZ3IIrCD0CvdOsa98o8ZCK09wU=@vger.kernel.org X-Received: by 2002:a05:620a:2982:b0:939:d5f4:ab5d with SMTP id af79cd13be357-93a038b94d6mr83404885a.33.1789169748381; Fri, 11 Sep 2026 16:35:48 -0700 (PDT) X-Received: by 2002:a05:620a:2982:b0:939:d5f4:ab5d with SMTP id af79cd13be357-93a038b94d6mr83401085a.33.1789169747922; Fri, 11 Sep 2026 16:35:47 -0700 (PDT) Received: from stband-bld-1.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9120f45ab71sm31717326d6.12.2026.09.11.16.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 16:35:47 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 01/13] PCI: brcmstb: Remove redundant const specifier for struct fields Date: Fri, 11 Sep 2026 19:35:26 -0400 Message-Id: <20260911233541.1650895-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260911233541.1650895-1-james.quinlan@broadcom.com> References: <20260911233541.1650895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" All of the variables using this particular structure are declared as const. There is no reason to declare its individual fields as being const. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 8a0c353d2abf..89aaa19d508a 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -288,9 +288,9 @@ struct inbound_win { =20 struct pcie_cfg_data { const int *offsets; - const enum pcie_soc_base soc_base; - const bool has_phy; - const u32 quirks; + enum pcie_soc_base soc_base; + bool has_phy; + u32 quirks; u8 num_inbound_wins; int (*perst_set)(struct brcm_pcie *pcie, u32 val); int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); --=20 2.34.1 From nobody Fri Sep 25 13:16:52 2026 Received: from mail-pl1-f227.google.com (mail-pl1-f227.google.com [209.85.214.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2CE440E8CD for ; Fri, 11 Sep 2026 23:35:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.227 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789169754; cv=none; b=L7MmUX3C6q8MziELfOMnFVF2OiRONu90EnzA7/HIXuCdm2UdGPGTWy1YuU10DMZ0+cK0QIxiLwHS/N2GPDCTvORMsprdGcQB7xESyWbhO3H0s96CXk5i1NtBibHFGdH59imJY4okWgIK1/6h03iLkA6xchyMZFLGHsKg6W0qU5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789169754; c=relaxed/simple; bh=//3ALQS3wymbFPv6KJPwmFP6Ogw6mcd5PsWWglFfL6w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ibSt+uQE0PvyGzfGpKl8woHQX76RCTouBQcVpFRkSNqKRy96QroMnupVxw89FUi4Th1d1xH43lVgpqHLqsBGSlVuRHEu65OJuFBlERVw6Pu2r/nJZA7VLi9CcZdPvddVuy7vgs6ewKaUW1/9t9Mus3j4ELi4GDkn+PWZy7VsJbE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=WPMO/+ms; arc=none smtp.client-ip=209.85.214.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="WPMO/+ms" Received: by mail-pl1-f227.google.com with SMTP id d9443c01a7336-2d6efd73032so25475335ad.0 for ; Fri, 11 Sep 2026 16:35:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1789169752; x=1789774552; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=dY9ozb5KV1VBJo3Z3p+RlJyXkFICluMij+wCeI97mXA=; b=JebI7vS6u9FtnD2L8qagugQGWly95qAEBmf5pOx3m1SZwurelmNhwvFzme9zDdtyjR MthQwTuhlgJLwLmi+o7S6fVTneiWMr/DrusbUFpy58IqbIk2U7SS0d2Y0m3bry49WtE4 VlzKAYe8LI0WkwHndCnn7zQY+cWmyypJlZ8/lI/sciBrgJJgk8bU2iHmDKqTxGu2kiVd 4UCe5o7sPWbrG2QqTvx6/0HSW/0HkjB8MJmcy/rV75mEpGB4srA8DY54go6SlXVEmFmz +1vsyvt/cr80nNTaONEn//OGamH6xKvRhOkm5G0/aplcdP/Bn7iYsW+jDwtQIjZ1eJxJ qG8Q== X-Forwarded-Encrypted: i=1; AKwUvBzldzncFFGNfcWBot3WE1ItZ68tjdosVFm75I53VIHC3/R1565J5AlYUqG8dJaaQaQg/CLGcpJsMrhooO4=@vger.kernel.org X-Gm-Message-State: AFuF++nSf7RE0wmj1Dr9YPYZpM058e7rha/7t1U1UwXGv4xraFp8IyHE kpiXnVYb2m/YW8540AP5afb+ndeleeEX3yhLAqTKIo9Wq4A71tcAxz68jkEsWwwBd/7ZMD9+L8c 1O63JMfHnmErbN6XrgfWM41rrZWXsiajkw3HWtyaZDJAZNUw8O3zA2KM444lMcSvVg6IYEPc7+7 /4s+KuFXUTnhcXc+RhCfwxwixucl/fh/F8S2XyrHrlZQ2NGZKo5NSvLR2HkmaScDcCx3pGWtQPq 0Mca1b8tngEC4XHiZam X-Gm-Gg: AYBFou0vz5CCm5aZ1eoQXvOfsa2lMSWIGWlXUn2YmR3M2BmipkaWpx6DGLmh4Umgf9l XdQJoMIpVdVtgBuFIEJJNns++AWggrHz3HbxSvcjGGOCTFLx/PGMEZIEX6V2+5qCYM2w6hjdYw0 +wrQC8uQw2X0EatdmcajqyckQWav8R2orxwT0OLe7qnOQ4lIpBZBrSSGsBYHyfRaIcguwPV+hrH isUEZ8anCqR0poWAoHT+4c16zEherY7WW8D9W+1srFfAt7g5noxmoSCrdNK8FSDFvZzRv+UmskN C0w5l+Vwq+IjoQgBf2RZc5VCJUZDgejopFxedUrPelLEZKXH/USf0XMDBYTQx2YF8HQ6jvQqF4o NsrKltV8tI7s7vkmtUYdYxCqFNmlwFOP+jtT1dGvEy8WfIPyspb7pxrmob2b9kPAuf5xgmfFkvB jQsbkIVSO6wUDLHdnilG8omJ4T1gQbZqLRFCDn X-Received: by 2002:a17:90b:35c7:b0:395:8124:ac53 with SMTP id 98e67ed59e1d1-39d97eeba04mr5843076a91.6.1789169752275; Fri, 11 Sep 2026 16:35:52 -0700 (PDT) Received: from smtp-us-east1-p01-i01-si01.dlp.protect.broadcom.com (address-144-49-247-25.dlp.protect.broadcom.com. [144.49.247.25]) by smtp-relay.gmail.com with ESMTPS id 98e67ed59e1d1-39daa7a9f85sm1140335a91.8.2026.09.11.16.35.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2026 16:35:52 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-91055aae7f4so47615046d6.1 for ; Fri, 11 Sep 2026 16:35:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1789169750; x=1789774550; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=dY9ozb5KV1VBJo3Z3p+RlJyXkFICluMij+wCeI97mXA=; b=WPMO/+ms+I+7rbiJZOfRQ8IyMJPpdiGcJccvrfGEqXa5ERsKR9tNTr34MmSY50gm0d 61PgVL/BitWRlY9Pu2HGtMTN7sI+4dbN+8A0J5jUyN7+PaIVJFm7HAAPYFx0m9/qNLUi /bJvbSOOf35K5lNV9thX0LVeaYFaClixglyXc= X-Forwarded-Encrypted: i=1; AKwUvBxL1J+hfFcGlqJH/APBt1y79/4YGH4q9rsMGY3i8zqY3I7kwP2fk4pHFFOAxF6yqdgf4MQiW0kJTYQAjBk=@vger.kernel.org X-Received: by 2002:ad4:5965:0:b0:910:42f3:958e with SMTP id 6a1803df08f44-912029a2a01mr144987276d6.27.1789169749959; Fri, 11 Sep 2026 16:35:49 -0700 (PDT) X-Received: by 2002:ad4:5965:0:b0:910:42f3:958e with SMTP id 6a1803df08f44-912029a2a01mr144987016d6.27.1789169749543; Fri, 11 Sep 2026 16:35:49 -0700 (PDT) Received: from stband-bld-1.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9120f45ab71sm31717326d6.12.2026.09.11.16.35.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 16:35:49 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 02/13] PCI: brcmstb: Use flags u32 instead of bools Date: Fri, 11 Sep 2026 19:35:27 -0400 Message-Id: <20260911233541.1650895-3-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260911233541.1650895-1-james.quinlan@broadcom.com> References: <20260911233541.1650895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Instead of having separate 'bool' fields for each SoC configuration, use a small bitvector (u32). Doing this uses less memory and provides a uniform method to assign flags for a specific SoC. The expectation is that more flags will be added as we replace conditions like "if (chipA || chipB)" with "if (behavior_X)". A helper macro "BFLAG()" is used to shorten the determination of the flag value. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 89aaa19d508a..47862569937e 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -286,16 +286,24 @@ struct inbound_win { */ #define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN BIT(0) =20 +/* FLAGS */ +#define BFLAG(pcie, flag) ((pcie)->cfg->flags & CFG_FLG_ ## flag) + +/* The PCIe HW registers have phy control of a "RESCAL" reset block */ +#define CFG_FLG_HAS_PHY BIT(0) +/* The SoC PCIe HW can dump to the console PCIe error info */ +#define CFG_FLG_HAS_ERR_REPORT BIT(1) + + struct pcie_cfg_data { const int *offsets; enum pcie_soc_base soc_base; - bool has_phy; + u32 flags; u32 quirks; u8 num_inbound_wins; int (*perst_set)(struct brcm_pcie *pcie, u32 val); int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); int (*post_setup)(struct brcm_pcie *pcie); - bool has_err_report; }; =20 struct subdev_regulators { @@ -356,14 +364,14 @@ static int brcm_pcie_bridge_sw_init_set(struct brcm_p= cie *pcie, u32 val) unsigned long flags; int ret; =20 - if (pcie->cfg->has_err_report) + if (BFLAG(pcie, HAS_ERR_REPORT)) spin_lock_irqsave(&pcie->bridge_lock, flags); =20 ret =3D pcie->cfg->bridge_sw_init_set(pcie, val); /* If we fail, assume the bridge is in reset (off) */ pcie->bridge_in_reset =3D ret ? true : val; =20 - if (pcie->cfg->has_err_report) + if (BFLAG(pcie, HAS_ERR_REPORT)) spin_unlock_irqrestore(&pcie->bridge_lock, flags); =20 return ret; @@ -1589,12 +1597,12 @@ static int brcm_phy_cntl(struct brcm_pcie *pcie, co= nst int start) =20 static inline int brcm_phy_start(struct brcm_pcie *pcie) { - return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 1) : 0; + return BFLAG(pcie, HAS_PHY) ? brcm_phy_cntl(pcie, 1) : 0; } =20 static inline int brcm_phy_stop(struct brcm_pcie *pcie) { - return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 0) : 0; + return BFLAG(pcie, HAS_PHY) ? brcm_phy_cntl(pcie, 0) : 0; } =20 static int brcm_pcie_turn_off(struct brcm_pcie *pcie) @@ -1898,7 +1906,7 @@ static void brcm_pcie_remove(struct platform_device *= pdev) pci_stop_root_bus(bridge->bus); pci_remove_root_bus(bridge->bus); pci_unlock_rescan_remove(); - if (pcie->cfg->has_err_report) + if (BFLAG(pcie, HAS_ERR_REPORT)) brcm_unregister_die_notifiers(pcie); =20 __brcm_pcie_remove(pcie); @@ -1999,9 +2007,8 @@ static const struct pcie_cfg_data bcm7216_cfg =3D { .soc_base =3D BCM7278, .perst_set =3D brcm_pcie_perst_set_7278, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, - .has_phy =3D true, + .flags =3D CFG_FLG_HAS_PHY | CFG_FLG_HAS_ERR_REPORT, .num_inbound_wins =3D 3, - .has_err_report =3D true, }; =20 static const struct pcie_cfg_data bcm7712_cfg =3D { @@ -2179,7 +2186,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) return ret; } =20 - if (pcie->cfg->has_err_report) { + if (BFLAG(pcie, HAS_ERR_REPORT)) { spin_lock_init(&pcie->bridge_lock); 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[144.49.247.25]) by smtp-relay.gmail.com with ESMTPS id d2e1a72fcca58-86b27dc0f73sm1001319b3a.5.2026.09.11.16.35.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2026 16:35:57 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-939d6c515deso258070385a.3 for ; Fri, 11 Sep 2026 16:35:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1789169756; x=1789774556; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ArH91frdffOdQcxWygxWviJhRnyFFFtxyckVO+/C0bo=; b=dCvy9JHNCgDuDdq2QGRIzPDZha80q+mHVC58ZUudGIHMCwZvGhZ/fIFdSJWnyzlNBf 06Io73X97Q0b7N+n6ckzg1/s1CBq/VRJlSpI7Zf6OHiP72kQnmv6FqMCayvgeSCFv/Fa sZKMwd7uhXvRqQ6Qi8PrluT/D/QI9F/VrFtow= X-Forwarded-Encrypted: i=1; AKwUvBwJKGo+inoaauFOZC9s63xeLEZmxSTDR2fiFwCKPH8dpK5w34A0yMCMEelElwuTUHppbmclp7Nf9dvLeTc=@vger.kernel.org X-Received: by 2002:a05:622a:164b:b0:530:b2e2:9038 with SMTP id d75a77b69052e-530c87b2e6amr91266261cf.56.1789169756363; Fri, 11 Sep 2026 16:35:56 -0700 (PDT) X-Received: by 2002:a05:622a:164b:b0:530:b2e2:9038 with SMTP id d75a77b69052e-530c87b2e6amr91262541cf.56.1789169751039; Fri, 11 Sep 2026 16:35:51 -0700 (PDT) Received: from stband-bld-1.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9120f45ab71sm31717326d6.12.2026.09.11.16.35.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 16:35:50 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 03/13] PCI: brcmstb: Add Broadcom quirks macro Date: Fri, 11 Sep 2026 19:35:28 -0400 Message-Id: <20260911233541.1650895-4-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260911233541.1650895-1-james.quinlan@broadcom.com> References: <20260911233541.1650895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Introduce a 'BQUIRK()' macro to shorten the calculation of a specific quirk's value. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 47862569937e..bf002bcf6bd5 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -277,6 +277,9 @@ struct inbound_win { u64 cpu_addr; }; =20 +/* QUIRKS */ +#define BQUIRK(pcie, quirk) ((pcie)->cfg->quirks & CFG_QUIRK_ ## quirk) + /* * The RESCAL block is tied to PCIe controller #1, regardless of the numbe= r of * controllers, and turning off PCIe controller #1 prevents access to the = RESCAL @@ -1627,7 +1630,7 @@ static int brcm_pcie_turn_off(struct brcm_pcie *pcie) u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MAS= K); writel(tmp, base + HARD_DEBUG(pcie)); =20 - if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN)) + if (!(BQUIRK(pcie, AVOID_BRIDGE_SHUTDOWN))) /* Shutdown PCIe bridge */ ret =3D brcm_pcie_bridge_sw_init_set(pcie, 1); =20 --=20 2.34.1 From nobody Fri Sep 25 13:16:52 2026 Received: from mail-ot1-f98.google.com (mail-ot1-f98.google.com [209.85.210.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D91441F7EE for ; Fri, 11 Sep 2026 23:35:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.98 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789169756; cv=none; b=UOFvIKCuD0yIDqvwqbHUZ1Cdy/agzRcmkoDTD3NcOrPqa8ih1ulAWYzonCP5wlA8hMMa2FDYxfERRvSL0aSHF6c16eJLK/YFt80ysLgKBUNL3/QkTMcAJosH1iznLYSHnr0JmsybvHLJ4yCCJUYG6D5l9zMxBUYKNNyo6Ng/Vhw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789169756; c=relaxed/simple; bh=nttleM8Tx0cIVF/OubkghUhIrwkhO7hXwcPPrF0zhrg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jl6DGUDqK4ERcV0jrmRZnse6m6vb8VZtwVJXhG5A7C6um/Sg0lKoVckOH0rm2MDf5Bs/my+Dd/EKtJSH1fOoRJwQTkuTQeJ3iQeNlG96sEoloP5cgApagCxPfVQNBR4GTo0QFHNPdIFqEVfO3VWeOZkavD753NoTM335hX9HpoE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=gZIQPoqd; arc=none smtp.client-ip=209.85.210.98 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="gZIQPoqd" Received: by mail-ot1-f98.google.com with SMTP id 46e09a7af769-7f5934ba2a5so810384a34.3 for ; Fri, 11 Sep 2026 16:35:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1789169754; x=1789774554; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=TL/+G3e3u5ILLrluIyCPB8J12Dl41Ws69Qu/dHBTdLE=; b=rt1G/TZjGlotEls+3SnkvRxnoVyajjOmel4YNiAUN2BBe+khpzDbEgy5KlOccq/qAe +9x2W5F9AaixDAeVJyxg7KVjAzoAHnQi8NPZYCBJPxmg1OI/OSowopH4FHO/glhHU7gy x5MUEookClAPXejwlg5EgUQ8SB46+kAbBqpB79II/pCHBK6yqXPaxLQpSVaioKPlSM5E TY3pM7ZW3qJR4s/KKvHOfX13WI/C6ROKOe6c999xvO5ajXwa0wq/1i/3iqXmuzqFZ8Tf bk9/xI+cKbcbIVOHfuOvHka6V5B3/BRD7T5r4aISpWjwnLF6zv7wknMqBVVXg3TnH/An bemQ== X-Forwarded-Encrypted: i=1; AKwUvBw/iaeZ4NtJiEmf9h1sr2Pd1lcdEK+HTwaIPTmncK0Ax3+lGpRI92c9FUu35b4+jTYEFDBjHmgskBsX5MU=@vger.kernel.org X-Gm-Message-State: AFuF++nqNXZ6o/E7SR1wfGSE/TnoqtCoRUyW2UjtOpfgzZBjrzEC+PdN fEVr9wu5+12JrmnoKs+ED4srRg8mjYR5aGmXgb8ATByTbqEOmpKCeqMuqmYi+SK+biWFH/b5QmR KZdKyXTi95WOZbum4M1VAIZdi5ZgVnG2ZwJzhUeFu1xYISAEajIVppfFCTYjAcclAR7WMdNI7Jg Yu1d5rRvPGp7X/hrURIscGEX1u8T7MhUDQUXfHSxeRJAsRWXskeWWJg8PgzqW3etN390no9HW+C Ua8/lTXkdo+0WtKfx8T X-Gm-Gg: AYBFou1rliqbnhYS+ylO7BBRtGpflvxzflgjfTDmfBlAb58kEpLRsUqOiS9hWB6vXOx v1ldGeepoREpkIvZ20ZPnKyDnCFQJhKZD8bzpQVcvb2SuIzCmhiz0Fq6HlkRAqqYA1MISpY1H2q EIb/8KQZAnWsn3HLf8NoU1jg3aSFHqzn/vkZ4us9X0vYE6bP8KSek15BkKTZCvrhBvQ7R6F8/4E BLiWJkiv3tNNdIPnx5/32GMLsYdcH7LSttnw4jPaBrW3qKMXCpLlWm1ERPYMlgSqRXuOOlnZFX3 HwBZIeSCkPcFVNbBEYZB2vV+ABBLBPpXUmzHDxQwrPETEDOUofWsEmiQFCFws9KlMPJN6rfGRt5 uSTcoJICv/2hLavxX8r5ywVXExD/uLebCy2VzpY9uTRsw4n6Hgn86SH9sZntdxINLDowpqfnHY9 0xMYLTqC4QsfIcSqHGDCzcP4rtHClj04FJAP/q X-Received: by 2002:a05:6830:4c0e:b0:7f6:705b:fff6 with SMTP id 46e09a7af769-8059e8508d4mr450538a34.3.1789169754190; Fri, 11 Sep 2026 16:35:54 -0700 (PDT) Received: from smtp-us-east1-p01-i01-si01.dlp.protect.broadcom.com (address-144-49-247-25.dlp.protect.broadcom.com. [144.49.247.25]) by smtp-relay.gmail.com with ESMTPS id 46e09a7af769-803f5df7d05sm1925055a34.6.2026.09.11.16.35.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2026 16:35:54 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-53013dc2330so29725151cf.0 for ; Fri, 11 Sep 2026 16:35:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1789169753; x=1789774553; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=TL/+G3e3u5ILLrluIyCPB8J12Dl41Ws69Qu/dHBTdLE=; b=gZIQPoqdAAqhb5huqkn97h2zkxhCXrW65TjzrfniLxZLzqQjNMQqSULXslpNfugxqt +QURE23PufRHEySGKH+0aej0yvL8kT1wZx8yZhdd4rd6E67PbP6+uIt/EcaBnG5aIKDa INA5KTzuadk9yIYiNZ1CKahdNygL7h9dAEYi4= X-Forwarded-Encrypted: i=1; AKwUvBwyfa3pvjsO5nhgUZiW/2LWtz7kmOfkVtI9z2hyxCiLhlZ9jvpiQ7Tch4s0ZBKAgGC12cp22pbN0BrEduE=@vger.kernel.org X-Received: by 2002:ac8:6903:0:b0:530:cbf7:6bb7 with SMTP id d75a77b69052e-530e81f5bdamr6175151cf.49.1789169753254; Fri, 11 Sep 2026 16:35:53 -0700 (PDT) X-Received: by 2002:ac8:6903:0:b0:530:cbf7:6bb7 with SMTP id d75a77b69052e-530e81f5bdamr6174881cf.49.1789169752856; Fri, 11 Sep 2026 16:35:52 -0700 (PDT) Received: from stband-bld-1.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9120f45ab71sm31717326d6.12.2026.09.11.16.35.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 16:35:52 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 04/13] PCI: brcmstb: Declare and assign quirk OB_WIN_32BIT_ADDR Date: Fri, 11 Sep 2026 19:35:29 -0400 Message-Id: <20260911233541.1650895-5-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260911233541.1650895-1-james.quinlan@broadcom.com> References: <20260911233541.1650895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Even though only BMIPs chips have this quirk, it is more uniform and readable to define this specific quirk in which the outbound region must reside in the lower 4GB region. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index bf002bcf6bd5..71ddd8a760af 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -288,6 +288,8 @@ struct inbound_win { * or a hang (AXI). */ #define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN BIT(0) +/* The outbound windows must be within the 0-4GB region */ +#define CFG_QUIRK_OB_WIN_32BIT_ADDR BIT(1) =20 /* FLAGS */ #define BFLAG(pcie, flag) ((pcie)->cfg->flags & CFG_FLG_ ## flag) @@ -519,7 +521,7 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie= *pcie, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK); writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); =20 - if (is_bmips(pcie)) + if (BQUIRK(pcie, OB_WIN_32BIT_ADDR)) return; =20 /* Write the cpu & limit addr upper bits */ @@ -1995,6 +1997,7 @@ static const struct pcie_cfg_data bcm7425_cfg =3D { .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, + .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR, }; =20 static const struct pcie_cfg_data bcm7435_cfg =3D { @@ -2003,6 +2006,7 @@ static const struct pcie_cfg_data bcm7435_cfg =3D { .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, + .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR, }; =20 static const struct pcie_cfg_data bcm7216_cfg =3D { --=20 2.34.1 From nobody Fri Sep 25 13:16:52 2026 Received: from mail-pg1-f225.google.com (mail-pg1-f225.google.com [209.85.215.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7268642901F for ; Fri, 11 Sep 2026 23:35:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789169760; cv=none; b=IjbbFjH2dADyzYv4OMdCEpTZ/g+4iiZVbWagRPw3B39xP5g1CvMIHbcDMDe3xu2A0DB4D4ZayldVqE0+9eRXDaFBzsjt4YDiQQaSj2K5WR0YvcfhcKOUpl6tIteFgGgZc5u8xuNGVvpxBrkuSD/PeQY+RTXigR/vkLKadCguynA= ARC-Message-Signature: i=1; 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[144.49.247.14]) by smtp-relay.gmail.com with ESMTPS id 41be03b00d2f7-cc4c62a4114sm1417010a12.1.2026.09.11.16.35.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2026 16:35:57 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-91054f537f9so36982726d6.0 for ; Fri, 11 Sep 2026 16:35:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1789169756; x=1789774556; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=VUDYRA+elxh8m3+YuX4zLBX8SlbUvqG/ZGp7B+YZHjQ=; b=N4hHzScjuki7aapQCdjclzeyqCcdPamMy5TmK5lkZur8ahKA1BnQGyipfFGx38/+cJ Hfo9Hkl3vDT1P6TV/zObHZ2jLc1jk1byQk31FG0FcuirVuX3qZebcfPpgGHu6xxp3wB/ YIIdErnPSJWn8CtB6JGPHFKb4jFESwXPcQXrs= X-Forwarded-Encrypted: i=1; AKwUvBxY6mH1SOUKyBE1z1/sP96l+3HRJsIptvMtKTZDr0EI/sLxxLnNclUkY/W0xfqW5t/Dmb7/iyYxvrJsvMY=@vger.kernel.org X-Received: by 2002:a05:6214:2b09:b0:8e9:51b7:2d49 with SMTP id 6a1803df08f44-912028a08bdmr150317586d6.2.1789169756309; Fri, 11 Sep 2026 16:35:56 -0700 (PDT) X-Received: by 2002:a05:6214:2b09:b0:8e9:51b7:2d49 with SMTP id 6a1803df08f44-912028a08bdmr150317256d6.2.1789169755927; Fri, 11 Sep 2026 16:35:55 -0700 (PDT) Received: from stband-bld-1.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9120f45ab71sm31717326d6.12.2026.09.11.16.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 16:35:54 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 05/13] PCI: brcmstb: Declare and assign quirk OB_WIN_MAXSZ_128MB Date: Fri, 11 Sep 2026 19:35:30 -0400 Message-Id: <20260911233541.1650895-6-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260911233541.1650895-1-james.quinlan@broadcom.com> References: <20260911233541.1650895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Even though only BMIPs chips have this quirk, it is more uniform and readable to define this specific quirk where each outbound window is must be <=3D SZ_128M. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 71ddd8a760af..401898d04d52 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -290,6 +290,8 @@ struct inbound_win { #define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN BIT(0) /* The outbound windows must be within the 0-4GB region */ #define CFG_QUIRK_OB_WIN_32BIT_ADDR BIT(1) +/* Each of the outbound windows size must be <=3D SZ_128M */ +#define CFG_QUIRK_OB_WIN_MAXSZ_128MB BIT(2) =20 /* FLAGS */ #define BFLAG(pcie, flag) ((pcie)->cfg->flags & CFG_FLG_ ## flag) @@ -1294,11 +1296,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return -EINVAL; } =20 - if (is_bmips(pcie)) { + if (BQUIRK(pcie, OB_WIN_MAXSZ_128MB)) { u64 start =3D res->start; unsigned int j, nwins =3D resource_size(res) / SZ_128M; =20 - /* bmips PCIe outbound windows have a 128MB max size */ + /* PCIe outbound windows have a 128MB max size */ if (nwins > BRCM_NUM_PCIE_OUT_WINS) nwins =3D BRCM_NUM_PCIE_OUT_WINS; for (j =3D 0; j < nwins; j++, start +=3D SZ_128M) @@ -1997,7 +1999,8 @@ static const struct pcie_cfg_data bcm7425_cfg =3D { .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, - .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR, + .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR + | CFG_QUIRK_OB_WIN_MAXSZ_128MB, }; =20 static const struct pcie_cfg_data bcm7435_cfg =3D { @@ -2006,7 +2009,8 @@ static const struct pcie_cfg_data bcm7435_cfg =3D { .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, - .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR, + .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR + | CFG_QUIRK_OB_WIN_MAXSZ_128MB, }; =20 static const struct pcie_cfg_data bcm7216_cfg =3D { --=20 2.34.1 From nobody Fri Sep 25 13:16:52 2026 Received: from mail-pg1-f226.google.com (mail-pg1-f226.google.com [209.85.215.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42835415B6E for ; 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Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 401898d04d52..8927d1d97f4a 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -300,7 +300,8 @@ struct inbound_win { #define CFG_FLG_HAS_PHY BIT(0) /* The SoC PCIe HW can dump to the console PCIe error info */ #define CFG_FLG_HAS_ERR_REPORT BIT(1) - +/* SoC uses a Broadcom variant of the MIPS-1 ISA */ +#define CFG_FLG_IS_BMIPS BIT(2) =20 struct pcie_cfg_data { const int *offsets; @@ -361,11 +362,6 @@ struct brcm_pcie { spinlock_t bridge_lock; }; =20 -static inline bool is_bmips(const struct brcm_pcie *pcie) -{ - return pcie->cfg->soc_base =3D=3D BCM7435 || pcie->cfg->soc_base =3D=3D B= CM7425; -} - static int brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) { unsigned long flags; @@ -1176,7 +1172,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return ret; =20 tmp =3D readl(base + HARD_DEBUG(pcie)); - if (is_bmips(pcie)) + if (BFLAG(pcie, IS_BMIPS)) tmp &=3D ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; else tmp &=3D ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; @@ -1189,7 +1185,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) * is encoded as 0=3D128, 1=3D256, 2=3D512, 3=3DRsvd, for BCM7278 it * is encoded as 0=3DRsvd, 1=3D128, 2=3D256, 3=3D512. */ - if (is_bmips(pcie)) + if (BFLAG(pcie, IS_BMIPS)) burst =3D 0x1; /* 256 bytes */ else if (pcie->cfg->soc_base =3D=3D BCM2711) burst =3D 0x0; /* 128 bytes */ @@ -2001,6 +1997,7 @@ static const struct pcie_cfg_data bcm7425_cfg =3D { .num_inbound_wins =3D 3, .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR | CFG_QUIRK_OB_WIN_MAXSZ_128MB, + .flags =3D CFG_FLG_IS_BMIPS, }; =20 static const struct pcie_cfg_data bcm7435_cfg =3D { @@ -2011,6 +2008,7 @@ static const struct pcie_cfg_data bcm7435_cfg =3D { .num_inbound_wins =3D 3, .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR | CFG_QUIRK_OB_WIN_MAXSZ_128MB, + .flags =3D CFG_FLG_IS_BMIPS, }; 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Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 8927d1d97f4a..be414d346855 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -292,6 +292,8 @@ struct inbound_win { #define CFG_QUIRK_OB_WIN_32BIT_ADDR BIT(1) /* Each of the outbound windows size must be <=3D SZ_128M */ #define CFG_QUIRK_OB_WIN_MAXSZ_128MB BIT(2) +/* PCIe HW can only access config space with 32bit R/W */ +#define CFG_QUIRK_32BIT_PCI_OPS BIT(3) =20 /* FLAGS */ #define BFLAG(pcie, flag) ((pcie)->cfg->flags & CFG_FLG_ ## flag) @@ -1996,7 +1998,7 @@ static const struct pcie_cfg_data bcm7425_cfg =3D { .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR - | CFG_QUIRK_OB_WIN_MAXSZ_128MB, + | CFG_QUIRK_OB_WIN_MAXSZ_128MB | CFG_QUIRK_32BIT_PCI_OPS, .flags =3D CFG_FLG_IS_BMIPS, }; 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Fri, 11 Sep 2026 16:36:01 -0700 (PDT) Received: from stband-bld-1.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9120f45ab71sm31717326d6.12.2026.09.11.16.35.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 16:36:01 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 08/13] PCI: brcmstb: Declare and assign quirk NO_RGR1_TIMER Date: Fri, 11 Sep 2026 19:35:33 -0400 Message-Id: <20260911233541.1650895-9-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260911233541.1650895-1-james.quinlan@broadcom.com> References: <20260911233541.1650895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Very few SoCs do not have an internal bus timer whose timeout value may be adusted for L1SS operation. Declare this as a quirk and assign it accordingly. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index be414d346855..e2284e114241 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -294,6 +294,8 @@ struct inbound_win { #define CFG_QUIRK_OB_WIN_MAXSZ_128MB BIT(2) /* PCIe HW can only access config space with 32bit R/W */ #define CFG_QUIRK_32BIT_PCI_OPS BIT(3) +/* PCIe HW does not have an internal bus timer */ +#define CFG_QUIRK_NO_RGR1_TIMER BIT(4) =20 /* FLAGS */ #define BFLAG(pcie, flag) ((pcie)->cfg->flags & CFG_FLG_ ## flag) @@ -1339,8 +1341,8 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie= *pcie) const unsigned int REG_OFFSET =3D PCIE_RGR1_SW_INIT_1(pcie) - 8; u32 timeout_us =3D 4000000; /* 4 seconds, our setting for L1SS */ =20 - /* 7712 does not have this (RGR1) timer */ - if (pcie->cfg->soc_base =3D=3D BCM7712) + /* Don't do access if there is no timer */ + if (BQUIRK(pcie, NO_RGR1_TIMER)) return; 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[144.49.247.25]) by smtp-relay.gmail.com with ESMTPS id af79cd13be357-939e810de2esm41658785a.1.2026.09.11.16.36.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2026 16:36:04 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-91219341db7so15339946d6.1 for ; Fri, 11 Sep 2026 16:36:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1789169764; x=1789774564; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=/JrxdF8t+QTOTmJ7fVNc0ZXDeEsvlNdyHKnTguJqLTM=; b=DFTE4iLy7PzPnI/CkY1LZhtN7NzKoI/0ynlgqfJJfZYuekzyF7X4sjY9qqeuKYQZ7Z 8vW2Y0sMGGBr6NKTKtk8rHIT32Kj6+X9GXNkbG/vxdAZQHij92nI/fw4/mQPIG/zBl9C CgoTgVxLlWXEhnaKMeOGRyl7AEx6g83aB7sqg= X-Forwarded-Encrypted: i=1; AKwUvBwR2nQiKLl/HNEPjj1c+CeafcQBHQgm3ek7UuJmn5NhZCzleQdeHvFaekXmWWLyLXYFwGWIJAKnzeze9Kg=@vger.kernel.org X-Received: by 2002:a05:6214:ca8:b0:8ef:e0d0:9fae with SMTP id 6a1803df08f44-9121d8f1169mr10166846d6.14.1789169764081; Fri, 11 Sep 2026 16:36:04 -0700 (PDT) X-Received: by 2002:a05:6214:ca8:b0:8ef:e0d0:9fae with SMTP id 6a1803df08f44-9121d8f1169mr10166536d6.14.1789169763636; Fri, 11 Sep 2026 16:36:03 -0700 (PDT) Received: from stband-bld-1.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9120f45ab71sm31717326d6.12.2026.09.11.16.36.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 16:36:02 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 09/13] PCI: brcmstb: Declare and assign quirk EARLY_PERST_ASSERT Date: Fri, 11 Sep 2026 19:35:34 -0400 Message-Id: <20260911233541.1650895-10-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260911233541.1650895-1-james.quinlan@broadcom.com> References: <20260911233541.1650895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Declare and assign a quirk where PERST# must be asserted prior to an internal bus being turned on. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index e2284e114241..dfd703571091 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -296,6 +296,8 @@ struct inbound_win { #define CFG_QUIRK_32BIT_PCI_OPS BIT(3) /* PCIe HW does not have an internal bus timer */ #define CFG_QUIRK_NO_RGR1_TIMER BIT(4) +/* PCIe PERST# must be asserted before internal bridge turned on */ +#define CFG_QUIRK_EARLY_PERST_ASSERT BIT(5) =20 /* FLAGS */ #define BFLAG(pcie, flag) ((pcie)->cfg->flags & CFG_FLG_ ## flag) @@ -1159,8 +1161,8 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) if (ret) return ret; =20 - /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->cfg->soc_base =3D=3D BCM2711) { + if (BQUIRK(pcie, EARLY_PERST_ASSERT)) { + /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ ret =3D pcie->cfg->perst_set(pcie, 1); if (ret) { pcie->cfg->bridge_sw_init_set(pcie, 0); @@ -1965,6 +1967,7 @@ static const struct pcie_cfg_data bcm2711_cfg =3D { .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, + .quirks =3D CFG_QUIRK_EARLY_PERST_ASSERT, }; =20 static const struct pcie_cfg_data bcm2712_cfg =3D { --=20 2.34.1 From nobody Fri Sep 25 13:16:52 2026 Received: from mail-pl1-f225.google.com (mail-pl1-f225.google.com [209.85.214.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B28F7443302 for ; Fri, 11 Sep 2026 23:36:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789169769; cv=none; b=IkORCG4XT1JLt+AsCv7CqIUO7Z/wMzhP9nhsYPvO/5AZTV7wIfSAEriq/St52+aAIjN5cdVoEhhXWMQYSQmTjzPwOz74imzswDXkFW2R8S6p0F+0TgeDUySdbW0huKwJ3oWRRfhE9pXPkW+4HV0AWLiXJRtlXnbM7NedPG9RHEA= ARC-Message-Signature: i=1; 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[144.49.247.14]) by smtp-relay.gmail.com with ESMTPS id 41be03b00d2f7-cc4c65b1a04sm1331178a12.6.2026.09.11.16.36.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2026 16:36:07 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-90e8135d7eeso23262596d6.1 for ; Fri, 11 Sep 2026 16:36:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1789169765; x=1789774565; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=RexkG3EFmXpE/deY9AEDz2v/2Wt3PCylK3Bm+blW8Y0=; b=MbuqxYFnmYe3Te8IRrICDYE9Aqwcjv7x1MPEer0MV1y4BT5EYhJJriuGC4EvUFe/dp kl6l6TsDAhMvTEZRWsKmT/BBDLBAWZeWShbAoZQtPr0nSn8+k6wb0sfXQuOhJ1E5nluS 3Pg2J0jzkoGD7e+jwcVINK4Ig4YkoCWFXjT3I= X-Forwarded-Encrypted: i=1; AKwUvBxCKuGzYHb6LqYUb8x7vjoeZmWGIA/YeE7iWl1ARbnpgVG+njsOOrz7Y3R4fU9NuhXiGBdSRpUzuT6kwic=@vger.kernel.org X-Received: by 2002:a05:6214:3218:b0:910:63c3:5c70 with SMTP id 6a1803df08f44-912120f1bdcmr91745236d6.19.1789169765664; Fri, 11 Sep 2026 16:36:05 -0700 (PDT) X-Received: by 2002:a05:6214:3218:b0:910:63c3:5c70 with SMTP id 6a1803df08f44-912120f1bdcmr91744836d6.19.1789169765178; Fri, 11 Sep 2026 16:36:05 -0700 (PDT) Received: from stband-bld-1.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9120f45ab71sm31717326d6.12.2026.09.11.16.36.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 16:36:04 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 10/13] PCI: brcmstb: Declare and assign quirk PERST_PCIE_REV_CUTOFF Date: Fri, 11 Sep 2026 19:35:35 -0400 Message-Id: <20260911233541.1650895-11-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260911233541.1650895-1-james.quinlan@broadcom.com> References: <20260911233541.1650895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" The SW behavior for asserting PERST# for some SoCs only works up to a specific PCIe HW version. Declare this as a quirk and assign it accordingly. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index dfd703571091..047783e33ae4 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -298,6 +298,8 @@ struct inbound_win { #define CFG_QUIRK_NO_RGR1_TIMER BIT(4) /* PCIe PERST# must be asserted before internal bridge turned on */ #define CFG_QUIRK_EARLY_PERST_ASSERT BIT(5) +/* PCIe SW PERST behavior only works up to a specific HW version */ +#define CFG_QUIRK_PERST_PCIE_REV_CUTOFF BIT(6) =20 /* FLAGS */ #define BFLAG(pcie, flag) ((pcie)->cfg->flags & CFG_FLG_ ## flag) @@ -1987,6 +1989,7 @@ static const struct pcie_cfg_data bcm4908_cfg =3D { .perst_set =3D brcm_pcie_perst_set_4908, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, + .quirks =3D CFG_QUIRK_PERST_PCIE_REV_CUTOFF, }; =20 static const struct pcie_cfg_data bcm7278_cfg =3D { @@ -2168,7 +2171,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) goto fail; =20 pcie->hw_rev =3D readl(pcie->base + PCIE_MISC_REVISION); - if (pcie->cfg->soc_base =3D=3D BCM4908 && + if (BQUIRK(pcie, PERST_PCIE_REV_CUTOFF) && pcie->hw_rev >=3D BRCM_PCIE_HW_REV_3_20) { dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); ret =3D -ENODEV; --=20 2.34.1 From nobody Fri Sep 25 13:16:52 2026 Received: from mail-oi1-f225.google.com (mail-oi1-f225.google.com [209.85.167.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BBA1425CF0 for ; Fri, 11 Sep 2026 23:36:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789169776; cv=none; b=Fwj0PdZVphwfmFK1lrxvc1u19JVG7Js6eq/K8Fj3ucsnS8yIGWUGJv4uB0vLA4os4lyAAm8LNe1YfM3D6UrNs5oHUGAMJS/c+LE4UMxkjnEd2mrFApu5xeSXGns1TZKPB0EjhFtE8sS3nLEqzCfATsR2uJrN8Rfk9N2ajR+bWck= ARC-Message-Signature: i=1; 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[144.49.247.14]) by smtp-relay.gmail.com with ESMTPS id 46e09a7af769-803f56d4b3fsm1837813a34.3.2026.09.11.16.36.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2026 16:36:13 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-90ceabcd64aso27581126d6.3 for ; Fri, 11 Sep 2026 16:36:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1789169772; x=1789774572; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=XvxeiUifxpfQFpLPlhrwkJPg9MEHvf8vpcauDPPob84=; b=hoq3W9NiGhcMviPnYOAqdjmDWZWB0CK0aJunu7/QAEtToC/qJOHJBMVEckqPrMz584 SmqDkxxI8l2kCebcaNby2584Z4H2elUur2llp5juw9sTyzDJu2cxq8KqEBU+EjY9cTqQ Dyv6E5GqYc6RqqWfoX38ZUtuBbQlzN0l7ea7Y= X-Forwarded-Encrypted: i=1; AKwUvBydC7GqZAz6GTs89aUCyqBTKBeP/AKZtWLLEAlhd4Cg980AtYq+wV2DT1SXWGRcMqh3J03Z0sQnF1DLx7Q=@vger.kernel.org X-Received: by 2002:a05:6214:3d08:b0:910:3453:505e with SMTP id 6a1803df08f44-9121dae180fmr10670866d6.32.1789169772221; Fri, 11 Sep 2026 16:36:12 -0700 (PDT) X-Received: by 2002:a05:6214:3d08:b0:910:3453:505e with SMTP id 6a1803df08f44-9121dae180fmr10665916d6.32.1789169767016; Fri, 11 Sep 2026 16:36:07 -0700 (PDT) Received: from stband-bld-1.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9120f45ab71sm31717326d6.12.2026.09.11.16.36.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 16:36:06 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 11/13] PCI: brcmstb: Put max_burst_size setting in cfg_data Date: Fri, 11 Sep 2026 19:35:36 -0400 Message-Id: <20260911233541.1650895-12-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260911233541.1650895-1-james.quinlan@broadcom.com> References: <20260911233541.1650895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Rather than ascertaining the max_burst_size setting by comparing different SoC IDs, specify the setting in the config_data structure for each SoC. Also add a comment on each SoC's encoding of this field. Note: Previously, the max burst setting used for the 4908 Soc was 2. However, it appears that the setting of 2 is illegal for this chip. Set it to 0 as (a) this is the safest (smallest) choice and (b) the 2 was probably interpreted by the HW as a 0 anyway. Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 29 ++++++++++++--------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 047783e33ae4..8bca98e6f5fa 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -317,6 +317,7 @@ struct pcie_cfg_data { u32 flags; u32 quirks; u8 num_inbound_wins; + u8 burst_setting; int (*perst_set)(struct brcm_pcie *pcie, u32 val); int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); int (*post_setup)(struct brcm_pcie *pcie); @@ -1153,7 +1154,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) void __iomem *base =3D pcie->base; struct pci_host_bridge *bridge; struct resource_entry *entry; - u32 tmp, burst, num_lanes, num_lanes_cap; + u32 tmp, num_lanes, num_lanes_cap; u8 num_out_wins =3D 0; int num_inbound_wins =3D 0; int memc, ret; @@ -1188,20 +1189,6 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) /* Wait for SerDes to be stable */ usleep_range(100, 200); =20 - /* - * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it - * is encoded as 0=3D128, 1=3D256, 2=3D512, 3=3DRsvd, for BCM7278 it - * is encoded as 0=3DRsvd, 1=3D128, 2=3D256, 3=3D512. - */ - if (BFLAG(pcie, IS_BMIPS)) - burst =3D 0x1; /* 256 bytes */ - else if (pcie->cfg->soc_base =3D=3D BCM2711) - burst =3D 0x0; /* 128 bytes */ - else if (pcie->cfg->soc_base =3D=3D BCM7278) - burst =3D 0x3; /* 512 bytes */ - else - burst =3D 0x2; /* 512 bytes */ - /* * Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN, * RCB_MPS_MODE, RCB_64B_MODE @@ -1209,7 +1196,8 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) tmp =3D readl(base + PCIE_MISC_MISC_CTRL); u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); - u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); + u32p_replace_bits(&tmp, pcie->cfg->burst_setting, + PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK); u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK); writel(tmp, base + PCIE_MISC_MISC_CTRL); @@ -1961,6 +1949,7 @@ static const struct pcie_cfg_data generic_cfg =3D { .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, + .burst_setting =3D 0x2, /* 0=3D128B, 1=3D256B, 2=3D512B, 3=3DRsvd */ }; =20 static const struct pcie_cfg_data bcm2711_cfg =3D { @@ -1970,6 +1959,7 @@ static const struct pcie_cfg_data bcm2711_cfg =3D { .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, .quirks =3D CFG_QUIRK_EARLY_PERST_ASSERT, + .burst_setting =3D 0x0, /* 0=3D128B, 1=3D256B, 2=3D512B, 3=3DRsvd */ }; =20 static const struct pcie_cfg_data bcm2712_cfg =3D { @@ -1981,6 +1971,7 @@ static const struct pcie_cfg_data bcm2712_cfg =3D { .quirks =3D CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN | CFG_QUIRK_NO_RGR1_TIMER, .num_inbound_wins =3D 10, + .burst_setting =3D 0x2, /* 0=3D64B, 1=3D128B, 2=3D256B, 3=3DRsvd */ }; =20 static const struct pcie_cfg_data bcm4908_cfg =3D { @@ -1990,6 +1981,7 @@ static const struct pcie_cfg_data bcm4908_cfg =3D { .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, .quirks =3D CFG_QUIRK_PERST_PCIE_REV_CUTOFF, + .burst_setting =3D 0x0, /* 0=3D64B, 1=3D128B, 2=3DRsvd, 3=3DRsvd */ }; =20 static const struct pcie_cfg_data bcm7278_cfg =3D { @@ -1998,6 +1990,7 @@ static const struct pcie_cfg_data bcm7278_cfg =3D { .perst_set =3D brcm_pcie_perst_set_7278, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, .num_inbound_wins =3D 3, + .burst_setting =3D 0x3, /* 0=3DResv, 1=3D128B, 2=3D256B, 3=3D512B */ }; =20 static const struct pcie_cfg_data bcm7425_cfg =3D { @@ -2009,6 +2002,7 @@ static const struct pcie_cfg_data bcm7425_cfg =3D { .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR | CFG_QUIRK_OB_WIN_MAXSZ_128MB | CFG_QUIRK_32BIT_PCI_OPS, .flags =3D CFG_FLG_IS_BMIPS, + .burst_setting =3D 1, /* 0=3D128B, 1=3D256B, 2=3DRsvd, 3=3DRsvd */ }; =20 static const struct pcie_cfg_data bcm7435_cfg =3D { @@ -2020,6 +2014,7 @@ static const struct pcie_cfg_data bcm7435_cfg =3D { .quirks =3D CFG_QUIRK_OB_WIN_32BIT_ADDR | CFG_QUIRK_OB_WIN_MAXSZ_128MB, .flags =3D CFG_FLG_IS_BMIPS, + .burst_setting =3D 1, /* 0=3D128B, 1=3D256B, 2=3DRsvd, 3=3DRsvd */ }; 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The code followed this nomenclature by not using the 0th element of the inbound array. Undo this approach and use order-0 indexing. Also use a struct pointer variable in two functions instead of array indexing. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 49 ++++++++++++--------------- 1 file changed, 21 insertions(+), 28 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 8bca98e6f5fa..53984cfa2c96 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -954,8 +954,8 @@ static void add_inbound_win(struct inbound_win *b, u8 *= count, u64 size, (*count)++; } =20 -static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, - struct inbound_win inbound_wins[]) +static int brcm_pcie_get_ib_wins(struct brcm_pcie *pcie, + struct inbound_win *ib_win) { struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(pcie); u64 pci_offset, cpu_addr, size =3D 0, tot_size =3D 0; @@ -965,13 +965,6 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie= *pcie, int ret, i =3D 0; u8 n =3D 0; =20 - /* - * The HW registers (and PCIe) use order-1 numbering for BARs. As such, - * we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1]. - */ - struct inbound_win *b_begin =3D &inbound_wins[1]; - struct inbound_win *b =3D b_begin; - /* * STB chips beside 7712 disable the first inbound window default. * Rather being mapped to system memory it is mapped to the @@ -980,7 +973,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie = *pcie, * SoCs. */ if (pcie->cfg->soc_base !=3D BCM7712) - add_inbound_win(b++, &n, 0, 0, 0); + add_inbound_win(ib_win++, &n, 0, 0, 0); =20 resource_list_for_each_entry(entry, &bridge->dma_ranges) { u64 pcie_start =3D entry->res->start - entry->offset; @@ -997,7 +990,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie = *pcie, * two. */ if (pcie->cfg->soc_base =3D=3D BCM7712) - add_inbound_win(b++, &n, size, cpu_start, pcie_start); + add_inbound_win(ib_win++, &n, size, cpu_start, pcie_start); =20 if (n > pcie->cfg->num_inbound_wins) break; @@ -1081,44 +1074,44 @@ static int brcm_pcie_get_inbound_wins(struct brcm_p= cie *pcie, } =20 /* Enable inbound window 2, the main inbound window for STB chips */ - add_inbound_win(b++, &n, size, cpu_addr, pci_offset); + add_inbound_win(ib_win++, &n, size, cpu_addr, pci_offset); =20 /* * Disable inbound window 3. On some chips presents the same * window as #2 but the data appears in a settable endianness. */ - add_inbound_win(b++, &n, 0, 0, 0); + add_inbound_win(ib_win++, &n, 0, 0, 0); =20 return n; } =20 static u32 brcm_bar_reg_offset(int bar) { - if (bar <=3D 3) - return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); + if (bar <=3D 2) + return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * bar; else - return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); + return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 3); } =20 static u32 brcm_ubus_reg_offset(int bar) { - if (bar <=3D 3) - return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); + if (bar <=3D 2) + return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * bar; else - return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 4); + return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 3); } =20 -static void set_inbound_win_registers(struct brcm_pcie *pcie, - const struct inbound_win *inbound_wins, - u8 num_inbound_wins) +static void brcm_pcie_set_ib_win_registers(struct brcm_pcie *pcie, + const struct inbound_win *ib_win, + u8 num_inbound_wins) { void __iomem *base =3D pcie->base; int i; =20 - for (i =3D 1; i <=3D num_inbound_wins; i++) { - u64 pci_offset =3D inbound_wins[i].pci_offset; - u64 cpu_addr =3D inbound_wins[i].cpu_addr; - u64 size =3D inbound_wins[i].size; + for (i =3D 0; i < num_inbound_wins; i++, ib_win++) { + u64 pci_offset =3D ib_win->pci_offset; + u64 cpu_addr =3D ib_win->cpu_addr; + u64 size =3D ib_win->size; u32 reg_offset =3D brcm_bar_reg_offset(i); u32 tmp =3D lower_32_bits(pci_offset); =20 @@ -1202,11 +1195,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK); writel(tmp, base + PCIE_MISC_MISC_CTRL); =20 - num_inbound_wins =3D brcm_pcie_get_inbound_wins(pcie, inbound_wins); + num_inbound_wins =3D brcm_pcie_get_ib_wins(pcie, inbound_wins); if (num_inbound_wins < 0) return num_inbound_wins; =20 - set_inbound_win_registers(pcie, inbound_wins, num_inbound_wins); + brcm_pcie_set_ib_win_registers(pcie, inbound_wins, num_inbound_wins); =20 if (!brcm_pcie_rc_mode(pcie)) { dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); 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charset="utf-8" The function brcm_pcie_get_inbound_wins() is abstruse. Most of its code is used exclusively by older chips, where the PCIe HW employed a baroque internal inbound window mapping scheme which was an artifact for when the PCIe would be configured as an endpoint. Create two variants of this function, one for the newer chips and one for the older chips, and assign them using the config_data structures. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 105 +++++++++++++++++--------- 1 file changed, 68 insertions(+), 37 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 53984cfa2c96..45e8a9e030d4 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -321,6 +321,9 @@ struct pcie_cfg_data { int (*perst_set)(struct brcm_pcie *pcie, u32 val); int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); int (*post_setup)(struct brcm_pcie *pcie); + int (*get_ib_wins)(struct brcm_pcie *pcie, struct inbound_win + *inbound_wins); + }; =20 struct subdev_regulators { @@ -954,8 +957,58 @@ static void add_inbound_win(struct inbound_win *b, u8 = *count, u64 size, (*count)++; } =20 +/* + * This is used by newer SoCs. It configures the inbound mapping windows + * in accordance to the values of the dma-ranges properties. + */ static int brcm_pcie_get_ib_wins(struct brcm_pcie *pcie, struct inbound_win *ib_win) +{ + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(pcie); + struct resource_entry *entry; + u64 size; + u8 n =3D 0; + + resource_list_for_each_entry(entry, &bridge->dma_ranges) { + u64 pcie_start =3D entry->res->start - entry->offset; + u64 cpu_start =3D entry->res->start; + + size =3D resource_size(entry->res); + add_inbound_win(ib_win++, &n, size, cpu_start, pcie_start); + if (n > pcie->cfg->num_inbound_wins) + break; + } + + if (!n) { + dev_err(pcie->dev, "DT node has no dma-ranges\n"); + return -EINVAL; + } + + return n; +} + +/* + * Originally, the Broadcom STB PCIe HW played the endpoint (EP) role. As + * an EP, one of its goals was to present system memory as a single + * contigous PCIe BAR. So if there was two regions of system memory, say + * 1GB@0GB and 2GB@2GB, these two regions would be presented as a + * contiguous BAR that was 3GB in size and started at a PCIe offset that + * was configured by SW. + * + * Then the same PCIe HW was modified to also play the Root Complex (RC) + * role and the same internal mapping strategy was employed. For any SoC + * that uses this scheme, each "BAR" is an inbound window and the PCIe HW + * is internally mapped and hard-wired to system memory regions. Even + * though the code of the function below uses the dma-ranges properties, it + * is unable to configure the CPU region that is covered, but it can set + * the size and offset of the PCIe side of the window. + * + * Newer SoCs use the brcm_pcie_get_ib_wins() function have the freedom to + * configure mapping windows from any CPU region to any PCIe region, + * provided they follow the rules on offset alignment and size. + */ +static int brcm_pcie_get_ib_wins_internal_map(struct brcm_pcie *pcie, + struct inbound_win *ib_win) { struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(pcie); u64 pci_offset, cpu_addr, size =3D 0, tot_size =3D 0; @@ -965,33 +1018,15 @@ static int brcm_pcie_get_ib_wins(struct brcm_pcie *p= cie, int ret, i =3D 0; u8 n =3D 0; =20 - /* - * STB chips beside 7712 disable the first inbound window default. - * Rather being mapped to system memory it is mapped to the - * internal registers of the SoC. This feature is deprecated, has - * security considerations, and is not implemented in our modern - * SoCs. - */ - if (pcie->cfg->soc_base !=3D BCM7712) - add_inbound_win(ib_win++, &n, 0, 0, 0); + /* By default, disable the first inbound window */ + add_inbound_win(ib_win++, &n, 0, 0, 0); =20 resource_list_for_each_entry(entry, &bridge->dma_ranges) { u64 pcie_start =3D entry->res->start - entry->offset; - u64 cpu_start =3D entry->res->start; =20 - size =3D resource_size(entry->res); - tot_size +=3D size; + tot_size +=3D resource_size(entry->res); if (pcie_start < lowest_pcie_addr) lowest_pcie_addr =3D pcie_start; - /* - * 7712 and newer chips may have many BARs, with each - * offering a non-overlapping viewport to system memory. - * That being said, each BARs size must still be a power of - * two. - */ - if (pcie->cfg->soc_base =3D=3D BCM7712) - add_inbound_win(ib_win++, &n, size, cpu_start, pcie_start); - if (n > pcie->cfg->num_inbound_wins) break; } @@ -1001,14 +1036,6 @@ static int brcm_pcie_get_ib_wins(struct brcm_pcie *p= cie, return -EINVAL; } =20 - /* - * 7712 and newer chips do not have an internal memory mapping system - * that enables multiple memory controllers. As such, it can return - * now w/o doing special configuration. - */ - if (pcie->cfg->soc_base =3D=3D BCM7712) - return n; - ret =3D of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", p= cie->memc_size, 1, PCIE_BRCM_MAX_MEMC); if (ret <=3D 0) { @@ -1123,13 +1150,8 @@ static void brcm_pcie_set_ib_win_registers(struct br= cm_pcie *pcie, /* Write high */ writel_relaxed(upper_32_bits(pci_offset), base + reg_offset + 4); =20 - /* - * Most STB chips: - * Do nothing. - * 7712: - * All of their BARs need to be set. - */ - if (pcie->cfg->soc_base =3D=3D BCM7712) { + /* SoCs w/o fixed internal mapping can remap the cpu_addr */ + if (pcie->cfg->get_ib_wins =3D=3D brcm_pcie_get_ib_wins) { /* BUS remap register settings */ reg_offset =3D brcm_ubus_reg_offset(i); tmp =3D lower_32_bits(cpu_addr) & ~0xfff; @@ -1195,7 +1217,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK); writel(tmp, base + PCIE_MISC_MISC_CTRL); =20 - num_inbound_wins =3D brcm_pcie_get_ib_wins(pcie, inbound_wins); + num_inbound_wins =3D pcie->cfg->get_ib_wins(pcie, inbound_wins); if (num_inbound_wins < 0) return num_inbound_wins; =20 @@ -1943,6 +1965,7 @@ static const struct pcie_cfg_data generic_cfg =3D { .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, .burst_setting =3D 0x2, /* 0=3D128B, 1=3D256B, 2=3D512B, 3=3DRsvd */ + .get_ib_wins =3D brcm_pcie_get_ib_wins_internal_map, }; =20 static const struct pcie_cfg_data bcm2711_cfg =3D { @@ -1953,6 +1976,7 @@ static const struct pcie_cfg_data bcm2711_cfg =3D { .num_inbound_wins =3D 3, .quirks =3D CFG_QUIRK_EARLY_PERST_ASSERT, .burst_setting =3D 0x0, /* 0=3D128B, 1=3D256B, 2=3D512B, 3=3DRsvd */ + .get_ib_wins =3D brcm_pcie_get_ib_wins_internal_map, }; =20 static const struct pcie_cfg_data bcm2712_cfg =3D { @@ -1965,6 +1989,7 @@ static const struct pcie_cfg_data bcm2712_cfg =3D { CFG_QUIRK_NO_RGR1_TIMER, .num_inbound_wins =3D 10, .burst_setting =3D 0x2, /* 0=3D64B, 1=3D128B, 2=3D256B, 3=3DRsvd */ + .get_ib_wins =3D brcm_pcie_get_ib_wins, }; =20 static const struct pcie_cfg_data bcm4908_cfg =3D { @@ -1975,6 +2000,7 @@ static const struct pcie_cfg_data bcm4908_cfg =3D { .num_inbound_wins =3D 3, .quirks =3D CFG_QUIRK_PERST_PCIE_REV_CUTOFF, .burst_setting =3D 0x0, /* 0=3D64B, 1=3D128B, 2=3DRsvd, 3=3DRsvd */ + .get_ib_wins =3D brcm_pcie_get_ib_wins_internal_map, }; =20 static const struct pcie_cfg_data bcm7278_cfg =3D { @@ -1984,6 +2010,7 @@ static const struct pcie_cfg_data bcm7278_cfg =3D { .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, .num_inbound_wins =3D 3, .burst_setting =3D 0x3, /* 0=3DResv, 1=3D128B, 2=3D256B, 3=3D512B */ + .get_ib_wins =3D brcm_pcie_get_ib_wins_internal_map, }; =20 static const struct pcie_cfg_data bcm7425_cfg =3D { @@ -1996,6 +2023,7 @@ static const struct pcie_cfg_data bcm7425_cfg =3D { | CFG_QUIRK_OB_WIN_MAXSZ_128MB | CFG_QUIRK_32BIT_PCI_OPS, .flags =3D CFG_FLG_IS_BMIPS, .burst_setting =3D 1, /* 0=3D128B, 1=3D256B, 2=3DRsvd, 3=3DRsvd */ + .get_ib_wins =3D brcm_pcie_get_ib_wins_internal_map, }; =20 static const struct pcie_cfg_data bcm7435_cfg =3D { @@ -2008,6 +2036,7 @@ static const struct pcie_cfg_data bcm7435_cfg =3D { | CFG_QUIRK_OB_WIN_MAXSZ_128MB, .flags =3D CFG_FLG_IS_BMIPS, .burst_setting =3D 1, /* 0=3D128B, 1=3D256B, 2=3DRsvd, 3=3DRsvd */ + .get_ib_wins =3D brcm_pcie_get_ib_wins_internal_map, }; =20 static const struct pcie_cfg_data bcm7216_cfg =3D { @@ -2018,6 +2047,7 @@ static const struct pcie_cfg_data bcm7216_cfg =3D { .flags =3D CFG_FLG_HAS_PHY | CFG_FLG_HAS_ERR_REPORT, .num_inbound_wins =3D 3, .burst_setting =3D 0x3, /* 0=3DResv, 1=3D128B, 2=3D256B, 3=3D512B */ + .get_ib_wins =3D brcm_pcie_get_ib_wins_internal_map, }; =20 static const struct pcie_cfg_data bcm7712_cfg =3D { @@ -2028,6 +2058,7 @@ static const struct pcie_cfg_data bcm7712_cfg =3D { .num_inbound_wins =3D 10, .quirks =3D CFG_QUIRK_NO_RGR1_TIMER, .burst_setting =3D 0x2, /* 0=3D64B, 1=3D128B, 2=3D256B, 3=3DResv */ + .get_ib_wins =3D brcm_pcie_get_ib_wins, }; =20 static const struct of_device_id brcm_pcie_match[] =3D { --=20 2.34.1