From nobody Fri Sep 25 14:30:58 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2132.outbound.protection.partner.outlook.cn [139.219.17.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F09C14334C9; Fri, 11 Sep 2026 10:24:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.17.132 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789122271; cv=fail; b=pODFmfusbCtRb/VlOcf9IbM57q7XcXq0QOjQlMwt+5ZGrP/5PFidtfcyzVzjP8vqL5BBeDaURdoTK5LlzJCPdF17ZNkWUqdXy4ehySyo4puoutoEBz15Or66T+MHyU1U74UqzfCYid7E9XWP0bVoeJsbhSZKUVo702rnjUpFX3U= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789122271; c=relaxed/simple; bh=yt+1nhelVuAVzHS2JHV4ZCl/uJc32y61yUlPnQ6oAc0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=Eao/PBZXkOh12b4MrO3psE6AxxkX2vIgGKwetdBW/h86qwnVqSmGgfYBYsA549EpvnAJ8UDkDXPQggF/zgY0W22z4LFPL9JcGydIzHVJHTnlAVZXg0FGk9Ktlf/vAFUk/2bhloDhK5FGKoP/ClshOAYmph2/BsK9RKiAqCgBxOI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.17.132 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hwEKyRUXCpc+N48+8JEXThxGvzBMtdXDY2Uft/UurWdmQccj/iTkLdUyLIvMNgVIaixNAHL6Az2cTAhW85uAkhJ/JnTar8ZYI5wa3GtU4vQhlwCkp/B6BLiD9Rr5kRtU7DWOCUpJZgLqyoIZa8YxhIOJc6B7bexqQ6zhfyQnCFcyRcR69XLeET1B8ErVYmM+FqcmfLhY5mWyAawuRXQQUqIxC0bdaYjH00l08eaIT+/WUABNoTtdSy4UiNT7kHLy1KdyEb2pF0rzvRT1WKt1gViyy6IYubiomgX/4LC9BC6ktfI3Ii5GD09VuJDqR7ik2fK6LG7yxc2KuKfy0fyP0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9QrYqNz7vYwFjKRNPlRAWfsUJTdhpmpB/T9S6p39ROg=; b=Wdg3e6JeTIEsRfWo9FLjp8z+F5n24V9ncPGh6nrL0Y8hOioJEZofQUy8DbH+0e/tslToKTBv68QUPVT29yBSUOwLdB5uMifPGTg41BC4Yorn815GbSC6HnjkruuD49Axo4FTfxk1IBqRb/86WmI0cZ9y3/U5uRreDcEMVAPXHVYYZh69qn+2Kdpdxs1aeO0nVDMBccKa84OWzH+U+kXCVi4e1yJwVxNcA2LCelc5uJL2WB1tbOMFK0vS40wifr9ddH+lTt5KMQEjMTwxAv3lMnUlCGU96bLW6jwiflTb3E45KmIRjI/Nzy/bi+l3txL01A1gcwNdMEVfkIASN6UkAw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) by SHXPR01MB0573.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.18; Fri, 11 Sep 2026 10:24:12 +0000 Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::9b99:12dc:a115:b90f]) by SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::9b99:12dc:a115:b90f%4]) with mapi id 15.21.0339.017; Fri, 11 Sep 2026 10:24:12 +0000 From: Minda Chen To: Alim Akhtar , Avri Altman , Bart Van Assche , Sai Krishna Potthuri , Ajay Neeli , "James E . J . Bottomley" , "Martin K . Petersen" , Arnd Bergmann , AngeloGioacchino Del Regno , Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-scsi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Minda Chen Subject: [PATCH v3 1/3] scsi: ufs: dt-bindings: starfive: Add UFS Host Controller for JHB100 soc Date: Fri, 11 Sep 2026 18:23:57 +0800 Message-Id: <20260911102359.83288-2-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260911102359.83288-1-minda.chen@starfivetech.com> References: <20260911102359.83288-1-minda.chen@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0016.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::28) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_|SHXPR01MB0573:EE_ X-MS-Office365-Filtering-Correlation-Id: 7bfc42fc-ab8d-4285-2630-08df0feed2c0 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|52116014|376014|366016|23010399003|1800799024|38350700014|921020|3023799007|10067099003|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: dBWx5PUx/6V5zMzrcl+/IV9A64q3xNYOX5/BmIiSQUpJux4gGeiirQnslmhus8z2QYbgdsTdJS9AtUaXMmA4NeXIXkdKe+oZRYCrwaAs79Ohkkbs+6LNvvDDnaamVC//Ch3BS7jUYnPRec6oiCtzyNcy/32pQqaXkbg3PsdB7TG2FsH9g8oqOYbJWq7V+tLSNZrdAjJJzLfIyTDJKKpAhlisL5xVbw7pg6aoN6gxunrfHSZshE8EQDbUFwyTOCY/iJQHTafn6In3zPtgJ90XwOMlVm2gZNgBxmRfn96BsNZtUQisNngID7FImtIbhpOrYSI3pDzYNb89W6M1LYFfT4eBGCAcJcskMQMuhGbBoW1L+lhz5L/flxNngPM0i0YEA6gCNRIXyDRjU7C/0s8qtEI+EctEy71pplegTjQmH0meTy799qXeTs1NmOKZLEc8A64ekLlMIG5+lwlkXRbjyeba2NFDET78FgJMOWdcv0ODlCbClznFA0erkvFI2AuYWDq3APFFmTg6FJrZeDszp+QDCxpDtGBf6yf5EKoxOy6vwDWsmLiQZCDjwKzRVSglkG3yaeDm2kq7qOyQ/Rp5WA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230040)(7416014)(52116014)(376014)(366016)(23010399003)(1800799024)(38350700014)(921020)(3023799007)(10067099003)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?h5pYUZVLzdlC+1SMgB+7/JiX8xTZnRlnfjWP9UI6eirZJonvKb3vJQcoSNb8?= =?us-ascii?Q?n4X0SLYZUB+EE9YxTS8a5obIFYOuPzVZgp9j8wAXr/wCxtoW4gpfogxxSMBQ?= =?us-ascii?Q?xUrkh9+zUyvcADl7G2VwXvaYN5pS3GLy1ivqzNrNxAzw7NRZ8gxCZ6pjmgxP?= =?us-ascii?Q?vaw5WfFxB/61CFueoGEzqPG2ZdbTx7YPBPGq/1d0v/3LwT7YW5sh+l3QxXPf?= =?us-ascii?Q?nEKvuKkCq1BINgOQX5u5Pjf/pQViz6DhbNr9ozTFuFj4Bj+P9UgAGu+UjeVe?= =?us-ascii?Q?LlULk/0akc600f6iEPxRTHH+HtN1PYjI+cOEYz2kfqhnMHrVK+d0AjVJwB+P?= =?us-ascii?Q?AkniwfxUx+4V16x0mID1rfSYZCX+TjTzDjw56TKi7AgH5pQ/3dZ6HjMWdFGi?= =?us-ascii?Q?ZWT3fNFx9XVughVhYB6SogxybXrSsu7ijO8NET4Rlxdb+zKWsQ/MSSU5f3jB?= =?us-ascii?Q?o4gp+ukafjHgMpn3JZ97ejtvn/FlaJ/fc0X3eTn5JtcuNbCSIAMj4qm/tKUn?= =?us-ascii?Q?5aeTMG9yBGhwOfdUnwCRkneEyDX43Xt+B5DKfFTVWFHlBacd6liq86McmSXN?= =?us-ascii?Q?CD2zJkVaTVkDtjX9E/J+Fa+7GseL09+6JIjC0pkH5jVeorYItLKqkfvZjk0e?= =?us-ascii?Q?Vtk4u5hbBa1//wr3F7cEX/TWWuYrm7gJzOvK3mqlb0Opu80gyZ/E7lGRBX07?= =?us-ascii?Q?bZz1aD1i7NTTvnf6Xo1tXBq4Y5c4xLj9EtwL2x1veHApLaWBJfQUrZ9GL3tK?= =?us-ascii?Q?8jdEuQXW50GTYBMWJQz5zQxQFHBzIn3yc/U6ggbfwohwlswMJ8o6lXKPPxv+?= =?us-ascii?Q?vaaMeLDN1HoNhrE1AzX6A4JzRQW7q/EYNJPz9M9d/wH9ytF2Z+FXQOgMBbU5?= =?us-ascii?Q?zjB6dWYgeIZm0cRLEblkx70Lo7yisk5HiyMk0hIWyUV2pcjXQbZezSNmNfHc?= =?us-ascii?Q?xmDGfw1Wyewwd6dWk98RyOV8B3wj3VxW5cgGviUO/Cn7t8Fi2opFWWNjkbo+?= =?us-ascii?Q?vtACDEwUdRFsPR6c1n6t1xhlYeLYLAfh+O2uFpeYIU1w2ANA92UgSj51sA9F?= =?us-ascii?Q?9PHN050P1y60kiGxm21PxMvsxIpjqs05MMMZLQXgkRRiFy+gnH1V3PrOY65M?= =?us-ascii?Q?OJEeOqtlHZj/EuTNL3qOsLEPU6yBYHzTmLEIhMe+6k2TzS2quBtGkIA3tHzf?= =?us-ascii?Q?Rc1uoazHxpLWdbY7qTO6zdq5Pg9NIqs6YcWxw+QiGUt4RHXmMGfSax4f3rYt?= =?us-ascii?Q?VzvhCd9ygzQStBVFxu0WUBT9M+pmZdRw/+CVdT6kYv08bh2FwJQZpXMZYulJ?= =?us-ascii?Q?jr/0NMK7CUKbq2S2fl2ElrbVccTpsM7wMX6afftW6OmpTAsFeJfw19tXpADO?= =?us-ascii?Q?j43Y2BZrl1SndXPueWTtn79FAaPLkFR1fmfyYbFWVAxy77G3S7eT6xJCJVST?= =?us-ascii?Q?s4scNM0kGVbjvSGmOAvY63Hq0IJUtYQvazaR1EpwsIxeZIq8DRko9ImeOwJc?= =?us-ascii?Q?kksFfR7cy1BYLwR7vDf9cxcJuxicX/Z5j9Gi3EBBK7T7vtUYsw7m23TYzpMb?= =?us-ascii?Q?5hTMOSOgO34eBcJex1785xG3U28Tmdxy3Z7PpO1vNNXgVOwLoU94ych8vv8N?= =?us-ascii?Q?JGgph1hY8Fct2YsnZng338pOmYEe7HvFMPQUw3BP08wsL2MI7Elgb2ilA0qe?= =?us-ascii?Q?HLXc8pmHSpgyl+ShZxr18naR0r87xSLGGWFuSBU0ggJbuDBWGguXSxWsKhXg?= =?us-ascii?Q?tuzPB/svZj7DqUeT5PwJLMNtxAv63/U=3D?= X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7bfc42fc-ab8d-4285-2630-08df0feed2c0 X-MS-Exchange-CrossTenant-AuthSource: SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2026 10:24:12.3970 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DmkmrXPwgQuIzoNMv5Cwji9BY6Pr+x7StJ1YXgI8tFXZ3IUZ/5dTCGYUDBykV3AjWFcHphdIW83CG/J9u+VEDkgHcltWKrAp7Jd0tehE4ds= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0573 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree document for UFS Host Controller StarFive JHB100 SoC. The UFS controller is based on the Synopsys DesignWare UFS controller. Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- .../bindings/ufs/starfive,jhb100-ufs.yaml | 71 +++++++++++++++++++ MAINTAINERS | 5 ++ 2 files changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/starfive,jhb100-u= fs.yaml diff --git a/Documentation/devicetree/bindings/ufs/starfive,jhb100-ufs.yaml= b/Documentation/devicetree/bindings/ufs/starfive,jhb100-ufs.yaml new file mode 100644 index 000000000000..a65cc9455a85 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/starfive,jhb100-ufs.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/starfive,jhb100-ufs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Starfive Universal Flash Storage (UFS) Controller + +maintainers: + - Minda Chen + +allOf: + - $ref: ufs-common.yaml + +properties: + compatible: + const: starfive,jhb100-ufs + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: main + + resets: + items: + - description: UFS main reset + - description: UFS PHY reset + + reset-names: + items: + - const: main + - const: phy + + interrupts: + maxItems: 1 + + starfive,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to System Register Controller syscon node. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - interrupts + - starfive,syscon + +unevaluatedProperties: false + +examples: + - | + ufs@11b10000 { + compatible =3D "starfive,jhb100-ufs"; + reg =3D <0x11b10000 0x20000>; + interrupts =3D <105>; + clocks =3D <&syscrg 4>; + clock-names =3D "main"; + resets =3D <&syscrg 10>, + <&syscrg 7>; + reset-names =3D "main", "phy"; + starfive,syscon =3D <&syscon>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index fc320b373656..10b0d0839ca4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -28095,6 +28095,11 @@ L: linux-scsi@vger.kernel.org S: Maintained F: drivers/ufs/host/ufs-renesas.c =20 +UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER STARFIVE +M: Minda Chen +S: Maintained +F: Documentation/devicetree/bindings/ufs/starfive,jhb100-ufs.yaml + UNIWILL LAPTOP DRIVER M: Armin Wolf L: platform-driver-x86@vger.kernel.org --=20 2.17.1 From nobody Fri Sep 25 14:30:58 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2132.outbound.protection.partner.outlook.cn [139.219.17.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADEE243A7E7; Fri, 11 Sep 2026 10:24:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.17.132 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789122274; cv=fail; b=VzeIjoj9Nu/avOq+f9b9RCD0TjjzyxB6106aHOqUPD6p2CBMFCk8sXITVroysDsEgFMmWnQtIUgbeaStXz+QB3b4Hcm4l0tBQLXVQ1XSP99Y844Pe8sC9hCwY5UM90Bw+C88s7Q7R9wjJSk4y07WvYAgeRG5rboXOV0b46QgwKM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789122274; c=relaxed/simple; bh=1md+k+jdnycV06xXtdR04WxvTvNMX+vKJAZTCLB4NRI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=gr9BolA4fBW5OvYpg67w0x6wmEMPRK9xp5Qa6GTrgj0D2kTNp7ftPnhBN0Ufu0LA+QVvg80Ip/w2ZYtme/f3BueGVcbz/1doRF9w9rEjKTS04R2KL3/AMJjfciEEZn6UTHh7FGcbSSPlp6Fo8mLkR/YElepOvjfv+4LmrndVImE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.17.132 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nTjne+I3lsKqs4RIwAvH8ETK4+rdmt52PdkfgLgRC9pB46pvuyJLBtw4ztOxB80y0YE2SwfF1hBcgS8hGj0jiBa+Kp55+VIr78MMSrCEpQlHJLCemj1zLXDX4XxX875J37/z6YlkJMFieKMisFJq1bS0RBR1dsevVZ49BgznaB/vx5d7FnHO3fB+e5dXH1jeqvSDVXGDh9NJ1cC6W5dcGO4oHfeL6cZUia23qY8eF5AvMYsXBrG4gGVDjNrbOBPaLi/h3oKQ732soFc2Daya7+cuWRLZC6qQPwr/i0s+2XxxmUq5mtiGOXYlqLkCmV7RxASgpTuTs596yaJ4y2aX5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=W4EzxHFUTu9WVBH+v0tR9P7XybMLoPk/e0NVjTM3rnA=; b=O7wwDtF1Twe9QW8sJKwudCC57VOCUaAOuMFVFx8JY+hxi8i4X/Zi//8byUa+BBvZMu4433h8G+wA5OYo6KGZ+iE5N3/01ExMVQgp9ypOJzst5uHeSLOOaIlU3Q/CzVBHQdctSE8VXZX/liV3wpiMPE7P52B2UUL6jOepfB5uYgbFmGqLz3gErX+Uxxfz0/ybrWdSwolVpq5bhnRA2LCWfiI9pT3//G8MOXMQm/HPQXEGMXukclBT7xG7RGY+5/1bcE/ScGKtD3UDNQKRqSV4zWMlXTIA71R/0lOnLs9ZycVt7ryoozMziXaK9PdX3MqYQx/n0oW7TzGV3R1QJXu13g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) by SHXPR01MB0573.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.18; Fri, 11 Sep 2026 10:24:13 +0000 Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::9b99:12dc:a115:b90f]) by SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::9b99:12dc:a115:b90f%4]) with mapi id 15.21.0339.017; Fri, 11 Sep 2026 10:24:13 +0000 From: Minda Chen To: Alim Akhtar , Avri Altman , Bart Van Assche , Sai Krishna Potthuri , Ajay Neeli , "James E . J . Bottomley" , "Martin K . Petersen" , Arnd Bergmann , AngeloGioacchino Del Regno , Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-scsi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Minda Chen Subject: [PATCH v3 2/3] scsi: ufs: dwc: Rename amd-versal2 read/write PHY API and move to dwc common file Date: Fri, 11 Sep 2026 18:23:58 +0800 Message-Id: <20260911102359.83288-3-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260911102359.83288-1-minda.chen@starfivetech.com> References: <20260911102359.83288-1-minda.chen@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0016.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::28) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_|SHXPR01MB0573:EE_ X-MS-Office365-Filtering-Correlation-Id: 155ebce1-d236-4e7b-384c-08df0feed39e X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|52116014|376014|366016|23010399003|1800799024|38350700014|921020|6133799003|3023799007|10067099003|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: p1RApmtTnxFrpxuCU3dhWxG2E+l4KhVfzHEHOtN+sbZpFJcMAHCp4KKINYFL1IckOApvD5cbQvQJ+muRP23NxJopdlAMfHbdjCVFpAGeuPD+ZbpYM9XnLXQ/Xs7DIqdYaTEqgtLmKcHzWfAQD1DjeMVLWNazPO2mdSMpZhI81AuOAErtpPv5gi0SLZcErvcdxj5h/nfxRAdbce4V4kBxxYYl2JFVm2Xb4tNcUnIbTBboJmCKYy94t9OeptAxo0TSH5u2sQrM34+GkBBVwNPPMIue0T6XG1c2B1HQf7V74xH0FKOlhTm2GVauAFjRSVQDRh9OEiiAwDdh79261C53H/fm6T6HcoqoGJZ7WZ22FOfblxT5Bps6zLepheBbvOnkabu/hYApE9UaoehU+1WcO0JaSQDrcWHVEUioVdz6FN7SSXHOZrbcTRsZsY10yzZ+/Pryturtz7JCIpqD1B2C0jQ6obXS+1HZKrcuJ7sshaPYNKORHB/NXs2y0yt7UqBKoE2QR3NrDt2A6nJysPflxaA6iq5rVvbmNTDWXV5f6LAO1n08hcinYnNs5dgqhllx/YxsIj3sEKljYI1nW+yl9w== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230040)(7416014)(52116014)(376014)(366016)(23010399003)(1800799024)(38350700014)(921020)(6133799003)(3023799007)(10067099003)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?xBtmAdIp/ARrO9tBhXqKAunPxSRMHqxSfyKzzNjaYBHVxz8RwBfahPNXPbiV?= =?us-ascii?Q?tZepUhvLOY+hVsl6gkWjbaUSlYX2eoQMRdYAONaG8llrLb6M/8kp/Nt5J4IB?= =?us-ascii?Q?EgTG0VupH8FCYTB2Nt2FoDIkDSa3M7EloyRszgBqgyBvX84RDyHrRGxUXuH1?= =?us-ascii?Q?vOrx05pxuzeVA+f1rJLNrUCU0qeTw3CZzSIQdwMq6j0R0JBoiddNCVwznubU?= =?us-ascii?Q?9XrvIMT5Aytl4a4jaHMyGr5N6mpwTQ6ABV1s6luVOEQrWbTPdOhEImmjAKPr?= =?us-ascii?Q?h/6UCXhdINn6NYYJQuQhdlG+y/2r0TuJxWf/bCl7WdCxWrdCdieORgg83aZn?= =?us-ascii?Q?PtIyfJghn4DlR7cMAy0YX8oTMhSY+xltHgwQB3WuI4Qyx7uL5K18eCbX4taV?= =?us-ascii?Q?yDfAMS7n9fdZFO3Id1e1xH4HgwPjY2Xe9OutNowmXbYgmzUA4M0TYm1mHh8c?= =?us-ascii?Q?q99LlxKPz8gHxCAm81eJ1e9b1gJvyI/t31D7HFVsnnpS/On3NgDbWin8iSE4?= =?us-ascii?Q?1BA/qA2EzMLIeKpfrQ4s8P2Tn+LxFcJwdesyw/NDMuxzAViCXjYHD0NNtHav?= =?us-ascii?Q?SENPg9VDj5VS5VJhzUEHklXVvFYV36v3ppJK4IaQGCBE0hXWRgaLkhxT7tZg?= =?us-ascii?Q?cpsD4HS0HRxaf8J+lIfV+tpNibCtfZSl9TtaWspn2aGi1fdCj4ywd87Jsk3w?= =?us-ascii?Q?m51X97NKTbEK0W9Z/KnSNnc6syyUOr6LFJjjZkgdQvSnL4ryHCIKgaITtPLR?= =?us-ascii?Q?5nWTMfafyOaOfk1kxip1rMfZH58ZSlnUp9/myJ+CzMkzNoSsCQJT2qNyXP0/?= =?us-ascii?Q?WJR0VvN3yVOO2PVhmJAhdq0QvJAKSj07kwC4ANGHFkPcNfkwG8Ul0pTv07qt?= =?us-ascii?Q?/dPdwE7/FYDfrJ7aF/hES/KHRIux/bTqejAMDcZuSY9ECgr3YDwlS7RwERbD?= =?us-ascii?Q?tFvhFciBgK0M4Y0aP0yyTQRHdNF0epZiJw3yyNhcPPduENs/MTU4JgZd/zXg?= =?us-ascii?Q?Gevatwm6sxMqesIJw9nwGBon9nJKDls5PiU0UcPaqp8kQZZ9am5RIQoNja56?= =?us-ascii?Q?3PURFreV4dHcXdZgS7BNZnPNQp1nefVDGvz5QLs+QUhcBaANqtR9s4eL2qxU?= =?us-ascii?Q?JNTlocaa+85eMGh0H0s+ErUggjkFichGt/Nn+48OEaEMaokijxNjMw0BORkD?= =?us-ascii?Q?dn+jEnSGXWHJHxaPxsSrj53Ouubtkf07IYYGBrrqk0Otto5QySRg0XgR0N9K?= =?us-ascii?Q?+Q+3oF9U1DnoTPJPUDoiNcztMkHv2MkMDUEijFTxXBYwqmdNIy6MjkI9Nski?= =?us-ascii?Q?tfHGlePpj2LL+Qnuegvr0hSLD/DUY+tTo2vSfv774fRsV7iCUUAjKNw8oVQY?= =?us-ascii?Q?NtuOA7nLpzJ3N2VBuBe+5BCbTPaZ8JRnaIlvMc6Ju1JZzSiYpEyTNN+07YLP?= =?us-ascii?Q?M0pziTV0GxpX/XD3yoe8Z2fPSJp+S/3ETd9F4rvtxr2aknX9LtYtHXQ8pt4+?= =?us-ascii?Q?03yo/QqT4hp0MfE2t9Ke/zSKZdv3oCo25xjQeWV9+uJ4zTREFTI7Lv2W6uAS?= =?us-ascii?Q?5xdosYL/Zj100bdVNIbumkamd9B5Ajq0RikPQIedPj/8Nc72pzJ5OLQAPwjv?= =?us-ascii?Q?xEL4GeTjH5YuREalCX1/YY5kHU8f3B+CiFteH3rtv3voREj2TaNTUBqu7uDo?= =?us-ascii?Q?hRIx13xpHk6pepV2me/bE2igUJVO2wAF9t++zYU88+Fop4ntclEBPRgrVkQn?= =?us-ascii?Q?82vZ4CYp3kOIak4eAlOkqLHzAxkBFHU=3D?= X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 155ebce1-d236-4e7b-384c-08df0feed39e X-MS-Exchange-CrossTenant-AuthSource: SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2026 10:24:13.8089 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5ejDjXlfEQ82PfN/AkU5VvjcJP1kzQz0NOsFYz+R4B6JXEtCCrsF2B/jVm8VZQiYd4ftV4d/xI8cO+4uP0l9qn3Q5Uoj8f3i0WzG00wmYSA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0573 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AMD versal2 UFS using designware ufs mipi PHY. The read/write PHY register API are common functions for designware ufs PHY. For other vendors reuse the code, move to common ufshcd-dwc.c file. Signed-off-by: Minda Chen --- drivers/ufs/host/ufs-amd-versal2.c | 85 ++++++------------------------ drivers/ufs/host/ufshcd-dwc.c | 53 +++++++++++++++++++ drivers/ufs/host/ufshcd-dwc.h | 2 + 3 files changed, 72 insertions(+), 68 deletions(-) diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-= versal2.c index 2154d6286817..2e671881e7ae 100644 --- a/drivers/ufs/host/ufs-amd-versal2.c +++ b/drivers/ufs/host/ufs-amd-versal2.c @@ -43,57 +43,6 @@ struct ufs_versal2_host { u8 ctlecompval1; }; =20 -static int ufs_versal2_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 va= l) -{ - static struct ufshcd_dme_attr_val phy_write_attrs[] =3D { - { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, - { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } - }; - - phy_write_attrs[0].mib_val =3D (u8)addr; - phy_write_attrs[1].mib_val =3D (u8)(addr >> 8); - phy_write_attrs[2].mib_val =3D (u8)val; - phy_write_attrs[3].mib_val =3D (u8)(val >> 8); - - return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_writ= e_attrs)); -} - -static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *va= l) -{ - u32 mib_val; - int ret; - static struct ufshcd_dme_attr_val phy_read_attrs[] =3D { - { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, - { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } - }; - - phy_read_attrs[0].mib_val =3D (u8)addr; - phy_read_attrs[1].mib_val =3D (u8)(addr >> 8); - - ret =3D ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read= _attrs)); - if (ret) - return ret; - - ret =3D ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); - if (ret) - return ret; - - *val =3D mib_val; - ret =3D ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); - if (ret) - return ret; - - *val |=3D (mib_val << 8); - - return 0; -} - static int ufs_versal2_enable_phy(struct ufs_hba *hba) { u32 offset, reg; @@ -162,64 +111,64 @@ static int ufs_versal2_setup_phy(struct ufs_hba *hba) u32 reg; =20 /* Bypass RX-AFE offset calibrations (ATT/CTLE) */ - ret =3D ufs_versal2_phy_reg_read(hba, FAST_FLAGS(0), ®); + ret =3D ufs_dwc_phy_reg_read(hba, FAST_FLAGS(0), ®); if (ret) return ret; =20 reg |=3D MPHY_FAST_RX_AFE_CAL; - ret =3D ufs_versal2_phy_reg_write(hba, FAST_FLAGS(0), reg); + ret =3D ufs_dwc_phy_reg_write(hba, FAST_FLAGS(0), reg); if (ret) return ret; =20 - ret =3D ufs_versal2_phy_reg_read(hba, FAST_FLAGS(1), ®); + ret =3D ufs_dwc_phy_reg_read(hba, FAST_FLAGS(1), ®); if (ret) return ret; =20 reg |=3D MPHY_FAST_RX_AFE_CAL; - ret =3D ufs_versal2_phy_reg_write(hba, FAST_FLAGS(1), reg); + ret =3D ufs_dwc_phy_reg_write(hba, FAST_FLAGS(1), reg); if (ret) return ret; =20 /* Program ATT and CTLE compensation values */ if (host->attcompval0) { - ret =3D ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcomp= val0); + ret =3D ufs_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0= ); if (ret) return ret; } =20 if (host->attcompval1) { - ret =3D ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcomp= val1); + ret =3D ufs_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1= ); if (ret) return ret; } =20 if (host->ctlecompval0) { - ret =3D ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctleco= mpval0); + ret =3D ufs_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompva= l0); if (ret) return ret; } =20 if (host->ctlecompval1) { - ret =3D ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctleco= mpval1); + ret =3D ufs_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompva= l1); if (ret) return ret; } =20 - ret =3D ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); + ret =3D ufs_dwc_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); if (ret) return ret; =20 reg |=3D MPHY_FW_CALIB_CFG_VAL; - ret =3D ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); + ret =3D ufs_dwc_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); if (ret) return ret; =20 - ret =3D ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); + ret =3D ufs_dwc_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); if (ret) return ret; =20 reg |=3D MPHY_FW_CALIB_CFG_VAL; - return ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); + return ufs_dwc_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); } =20 static int ufs_versal2_phy_init(struct ufs_hba *hba) @@ -406,7 +355,7 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba,= u32 activelanes, u32 rx_ =20 for (lane =3D 0; lane < activelanes; lane++) { time_left =3D TIMEOUT_MICROSEC; - ret =3D ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); + ret =3D ufs_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); if (ret) return ret; =20 @@ -416,12 +365,12 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hb= a, u32 activelanes, u32 rx_ else reg &=3D ~MPHY_RX_OVRD_VAL; =20 - ret =3D ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); + ret =3D ufs_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); if (ret) return ret; =20 do { - ret =3D ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), ®); + ret =3D ufs_dwc_phy_reg_read(hba, RX_PCS_OUT(lane), ®); if (ret) return ret; =20 @@ -483,12 +432,12 @@ static int ufs_versal2_pwr_change_notify(struct ufs_h= ba *hba, enum ufs_notify_ch =20 /* Remove rx_req override */ for (lane =3D 0; lane < dev_req_params->lane_tx; lane++) { - ret =3D ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); + ret =3D ufs_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); if (ret) return ret; =20 reg &=3D ~MPHY_RX_OVRD_EN; - ret =3D ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); + ret =3D ufs_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); if (ret) return ret; } diff --git a/drivers/ufs/host/ufshcd-dwc.c b/drivers/ufs/host/ufshcd-dwc.c index 21b1cf912dcc..b057a78e151c 100644 --- a/drivers/ufs/host/ufshcd-dwc.c +++ b/drivers/ufs/host/ufshcd-dwc.c @@ -15,6 +15,59 @@ #include "ufshcd-dwc.h" #include "ufshci-dwc.h" =20 +int ufs_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val) +{ + static struct ufshcd_dme_attr_val phy_write_attrs[] =3D { + { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + phy_write_attrs[0].mib_val =3D (u8)addr; + phy_write_attrs[1].mib_val =3D (u8)(addr >> 8); + phy_write_attrs[2].mib_val =3D (u8)val; + phy_write_attrs[3].mib_val =3D (u8)(val >> 8); + + return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_writ= e_attrs)); +} +EXPORT_SYMBOL(ufs_dwc_phy_reg_write); + +int ufs_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) +{ + u32 mib_val; + int ret; + static struct ufshcd_dme_attr_val phy_read_attrs[] =3D { + { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + phy_read_attrs[0].mib_val =3D (u8)addr; + phy_read_attrs[1].mib_val =3D (u8)(addr >> 8); + + ret =3D ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read= _attrs)); + if (ret) + return ret; + + ret =3D ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); + if (ret) + return ret; + + *val =3D mib_val; + ret =3D ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); + if (ret) + return ret; + + *val |=3D (mib_val << 8); + + return 0; +} +EXPORT_SYMBOL(ufs_dwc_phy_reg_read); + int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, const struct ufshcd_dme_attr_val *v, int n) { diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h index c618bb914904..8091f186a9b3 100644 --- a/drivers/ufs/host/ufshcd-dwc.h +++ b/drivers/ufs/host/ufshcd-dwc.h @@ -68,4 +68,6 @@ int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status status); int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, const struct ufshcd_dme_attr_val *v, int n); +int ufs_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val); +int ufs_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val); #endif /* End of Header */ --=20 2.17.1 From nobody Fri Sep 25 14:30:58 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2132.outbound.protection.partner.outlook.cn [139.219.17.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F123430309; Fri, 11 Sep 2026 10:24:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.17.132 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789122277; cv=fail; b=JAUPWXoDqa7j4z9Fat/dL7Mn/Vd7t+zWq/PjQabjPLKdUhTAY7UwzsX5jIYq96WypV4DxuHnHNOTGiyz9PUcmjNxoEh7NwpJd7ACC7YnMi2X4KE9h4WArDZU5uyyjZFsRA6fPmC0s+MzhRr77cZJFwdT6JkpnHs2+s8oNOh4FxI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789122277; c=relaxed/simple; bh=7jXBIchFoQhZdYUX+FMUwr2OOE+Gk47R3gLg9n8TWTA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=B1HcrvyVPelSa0reYkOUwRt0BUtuHWdb5L+7pQbaGe/W812nT6zHmMRubqZ22mINwT4z7xPB6fe4M44YWN5Xu/ci7M6M8Zkb6dymzG5I0NqdJ6Q8o9mAHvA6SC5WbGWzuYAiP/O/gwgunBkK8jw4UIkgkyQxTNbvJ5Ywc32UPzo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.17.132 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=W83k7nl88Xfq+moD0wixGv73JC3/Rm3WDSq3DjNE3JQySeqUh4xJPohRHOLmytXltK7rvjXzlXL+9LDVoprQjUQjDn07RPmOPzVVVlujgxbpYtTpxxPkBMZW7y6MjTe3b7JK3wPHsUQ5DzYDHLS+UVP1Y6U495SBmLTOm0uauntAWH2fE1cbllJva1V3lzPinrLRcJ8aTttPJes7HzneSf9/DNORVGpjrp+HkP79Z01MJkM9BnUctB1xjaNi7hfdME09mEegc1jo5VGl3FRy7OztzKWohNhEFzxUa2HbXrDyqYUe8fubOojBxxLylATf2jnDEmhIg2ZEqS5/NMRcKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=l7pFBtxc8vj5Rn3u0QX5IrAI42XcfMuWLWiuVSrhHNo=; b=V2fOm6gUMQiXhq5o1gNWKlC2VX9Th6/yl+ir5ejcb3yngbOZSLIjftUaXkNKWlUORXaFJnzIn5GQaLqmC8PQXyxT1/7CHp0EDnEw/FwO9sGYIfxF+xsIR4pHnh8Z1tZKJ0AcHuq6BMRrJniciOvdmU8H5s3O7GPLFk9IzCPrmEcwYWVJQRCpowSn3LYfGYJqHk1wEPrIFqEK7bSa757kzX71TQZFRJNmMeVHM7j2CuvRMkmZLWIVnp+4DNexn5qQq3VMu26Ebbfx9wk8xvTKlsncV7HExVEZEhY02psRN/HumVuDC8pzu59fyaJ8OkeRk5vuWDYHZzPWW5RzlZQnKw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) by SHXPR01MB0573.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.18; Fri, 11 Sep 2026 10:24:15 +0000 Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::9b99:12dc:a115:b90f]) by SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::9b99:12dc:a115:b90f%4]) with mapi id 15.21.0339.017; Fri, 11 Sep 2026 10:24:15 +0000 From: Minda Chen To: Alim Akhtar , Avri Altman , Bart Van Assche , Sai Krishna Potthuri , Ajay Neeli , "James E . J . Bottomley" , "Martin K . Petersen" , Arnd Bergmann , AngeloGioacchino Del Regno , Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-scsi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Minda Chen Subject: [PATCH v3 3/3] scsi: ufs: starfive: Add UFS support for StarFive JHB100 SoC Date: Fri, 11 Sep 2026 18:23:59 +0800 Message-Id: <20260911102359.83288-4-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260911102359.83288-1-minda.chen@starfivetech.com> References: <20260911102359.83288-1-minda.chen@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0016.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::28) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_|SHXPR01MB0573:EE_ X-MS-Office365-Filtering-Correlation-Id: 5576a1a5-3d87-4390-7687-08df0feed476 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|52116014|376014|366016|23010399003|1800799024|38350700014|921020|6133799003|10067099003|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: ofXG+xTi5AfQrheXm4KO67wnVzHMRWIFn6KC8IWUAieFDbUvhvZBMzei4DUgcyT8nNaBBBZ0oxRwVIm3y/uy5G5s9d3cCDjXixYqKXQaSvlPYYY3s6n8QOg4+gBghwGv5nDZIPA+MEMPtlunvsc6En95cDBS/Hyg+vWqwaQ+B4Qy4GLCR2hbl8BY1zH11k/Q09q0WYLcjz2oitI0dA3bQfslHXi6KajkrkUUdL1s8bZ2IvGqazmOCUtzprMAaqiSSDGhahTaPPb4fgWHdmyOwI0rMYu8QLx1qME632HB1DnPH5p8bhnsygzyODPtDiTH2bhplrVMfSigxHxn8kcJc4SKYBHvMA0IeOU9KzxwV491KCtntVDH6+N3RiYwHLizWqWLvyelk6xbHMLtY4eCcpdstnY+EzubIVl/9oO89Ea3Z9I8Od8tqdbVjgkjh1p/lE9YmG1telJFA2uv1lrYR5nUDgJikkQlcaGb0DYoFk9fGC13a4esINfL3dEZB9PUyqNNB5b5puIbs5ngw2RnSWqNRiPo3iUd1cwBaGofLSSvupttvJSgTmGbcmuvcwY8xbEUZLTW1v0qq073DK8J5g== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230040)(7416014)(52116014)(376014)(366016)(23010399003)(1800799024)(38350700014)(921020)(6133799003)(10067099003)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?E4vUZ14ViIT94A8GaPnI6N9ffBDpPqVsGvBZ5VBe9KY5Dv7P7ACVirAK4APt?= =?us-ascii?Q?rgJFswEamIdjXsBw3IN8MW1sMI4Fl9u0KEYuyOj2qP5BvvWVqxmReMmQxNZp?= =?us-ascii?Q?8OcIJPFy4fMfl1+NUQotSzVi0tt1RZtlEnTLIj/8cO1yvd3DQdbLg/jgFQtK?= =?us-ascii?Q?GZpatC5V1ul9wqqkJ7vI0wFvpa12t8iAtGAJdLXfK9HFwHKMvgCFsjLMPfRT?= =?us-ascii?Q?1k/nhDhD/2+xm7DZ6d1MOUji543QtTApfuNtyhVfHT0IyHQ4hUQhtPL4lHAl?= =?us-ascii?Q?Y6jjGZHyqViBhx10XFDEHpLnaTAvRZ7vygif1suWN9eNaDc4zJd3/iWn3GL9?= =?us-ascii?Q?YUHGNOSvW15p4Pu2V0QZC4V7GU3BsM8aRw/qlhZrrqifDtNpbWeS21229lsd?= =?us-ascii?Q?xY2idfKcjLDlZe/56i39SMlh1LJDbeXa3BCffaEL21PxklFYpsXN6pWNiNDd?= =?us-ascii?Q?5zvSbH+e+jQQ7hCLPoSSK2jZkS+PkfXzWki9kKCnNDHgiNb5t2Pl7jbqTcJF?= =?us-ascii?Q?REsjfGtioWrvn9yB1C0qaoJAnARj/XS/q8i0ZpcRp3AQW77MUYKiKe7mhtyN?= =?us-ascii?Q?w9d0Qz3L67yZJ2nyH4eXEAWcm6Eq2zVGk4TxksCuneWAZRh8CWgw0P8Y/bh3?= =?us-ascii?Q?JAHMGXDNhiWCe508vOy2hUMODDKk3fj3NXrD2dsMwq/Z7PiskgxvATPvTfcK?= =?us-ascii?Q?itUn7QaGZHLdrTgzfZnUNmGZqDcmcfmbXglBBTnbInhkI1wOOaImC2n1wAcl?= =?us-ascii?Q?TcrHPyG60VPkGxdsWCHsJCx4Snbonga/A/lQRQyBP2S+qn41ixt/tVLHRtZY?= =?us-ascii?Q?9TTjKVsC9565Ly/nSD7UYJK+0uJldLzjD7V3BGRgTQLW/oDlh6a3qQhIWP8l?= =?us-ascii?Q?ioAu4N1MrlqOyBUri0mJMghFtns0hxjZinIWF5UxgEOWyNqtkj9e3mkEacua?= =?us-ascii?Q?CT5XuMh1WPHpLxV5d53eBDuoIz1w63CkcpxZh6bQjKmfkL3b2emMnb1ncjiA?= =?us-ascii?Q?n/P+z1JULZC1bRZAdYN0XAwCrBSQX6VBrxS8Eb4p7Mwi++c/q3nKdpMB2l4V?= =?us-ascii?Q?CXOGzfiGHNHSy3Yg4ILeQsnFAdBD40NFgVT8XNzwcZfvLTI7QglFYfmVIx4v?= =?us-ascii?Q?sw/HSHx77KriY21qtxuwdRFl28nn/d/pI0KrqC8dV2I4ayYzmAVrtSmLVnA6?= =?us-ascii?Q?XSTyH/nDIok/dSPmeBqXYcVSTOctGIBKPJlEYKvgN0IasJdkekjfGvIq2UKz?= =?us-ascii?Q?1Hs+zZo2Mzcl3mMNFhQFQ+s4HVYf+dSCQp9pPIgJLichkzN6FBGnyKGH6uDr?= =?us-ascii?Q?3Jf+S4p2BUEbwKnsiLQSvBK4nl54uqW49LyZ24vyTPOBWo2YRU+ZjDcFZ2cd?= =?us-ascii?Q?rsw0LoO6B4ALdKimUNp8lcCtzviX5Z8u6+bG7ycuyZSuHmsbCJhR94Lpdixz?= =?us-ascii?Q?x+/wPQKHNGppU5qm/3NVLfbAhdJ6dWz8mrPQZyXV12KNtumMlQUgqgSvsZV9?= =?us-ascii?Q?cPESbXq9EfqYSMIM2PKi3V32iF3v4SS2trxF02KemSDo44itqXJ2CPD3cyzI?= =?us-ascii?Q?Bm7pc76bZFgPRcjkjpgB61fntsxbpibZS/vlTpLwOJQebFJpBN4yH99qBlRX?= =?us-ascii?Q?XnEpAxt0y7Ocd0dxLidLKdoQvuaeUlIz9wtXGRbb/vGrFrYq2ASiHn1Tun85?= =?us-ascii?Q?SbeHt8TWUZX2MXaz/zx+k0w5SA0Cv7LpFQC8peMJpHYL2MHvZQCngB/ReUFq?= =?us-ascii?Q?K/CEYrJrIDoHAA/Y2jiv0Pq6Bm+Mcu8=3D?= X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5576a1a5-3d87-4390-7687-08df0feed476 X-MS-Exchange-CrossTenant-AuthSource: SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2026 10:24:15.2332 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 56drpEQxeyA5enW5RjKF2i65yHVqkVZbIXc5xw1fLIPo4iC7g5zkEXMeYNMsEYutQqr2R9yyiUcV6uxXmfxtxZP6mRmfh+oN36reRNKzixU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0573 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the UFS host controller on JHB100 SoC, built on the Synopsys DWC UFS controller and using UFSHCD platform driver. This controller requires specific configurations like M-PHY/RMMI/UniPro Signed-off-by: Minda Chen --- MAINTAINERS | 1 + drivers/ufs/host/Kconfig | 13 ++ drivers/ufs/host/Makefile | 1 + drivers/ufs/host/ufs-starfive.c | 297 ++++++++++++++++++++++++++++++++ drivers/ufs/host/ufshcd-dwc.h | 18 ++ 5 files changed, 330 insertions(+) create mode 100644 drivers/ufs/host/ufs-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index 10b0d0839ca4..de81bd15f3bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -28099,6 +28099,7 @@ UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER STAR= FIVE M: Minda Chen S: Maintained F: Documentation/devicetree/bindings/ufs/starfive,jhb100-ufs.yaml +F: drivers/ufs/host/ufs-starfive.c =20 UNIWILL LAPTOP DRIVER M: Armin Wolf diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig index ff170c0b6da0..9d96f5bb92ef 100644 --- a/drivers/ufs/host/Kconfig +++ b/drivers/ufs/host/Kconfig @@ -168,3 +168,16 @@ config SCSI_UFS_AMD_VERSAL2 =20 Select this if you have UFS controller on AMD Versal Gen 2 SoC. If unsure, say N. + +config SCSI_UFS_STARFIVE + tristate "Starfive UFS controller platform driver" + depends on OF && SCSI_UFSHCD_PLATFORM + depends on ARCH_STARFIVE || COMPILE_TEST + help + This selects the StarFive specific additions to UFSHCD platform driver. + UFS host on StarFive needs some vendor specific configuration before + accessing the hardware which includes PHY configuration and vendor + specific registers. + + Select this if you have UFS controller on StarFive chipset. + If unsure, say N. diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile index 7d8db67eb23c..9c6c2897692d 100644 --- a/drivers/ufs/host/Makefile +++ b/drivers/ufs/host/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_SCSI_UFS_ROCKCHIP) +=3D ufs-rockchip.o obj-$(CONFIG_SCSI_UFS_SPRD) +=3D ufs-sprd.o obj-$(CONFIG_SCSI_UFS_TI_J721E) +=3D ti-j721e-ufs.o obj-$(CONFIG_SCSI_UFS_AMD_VERSAL2) +=3D ufs-amd-versal2.o ufshcd-dwc.o +obj-$(CONFIG_SCSI_UFS_STARFIVE) +=3D ufs-starfive.o ufshcd-dwc.o diff --git a/drivers/ufs/host/ufs-starfive.c b/drivers/ufs/host/ufs-starfiv= e.c new file mode 100644 index 000000000000..fab65da0507e --- /dev/null +++ b/drivers/ufs/host/ufs-starfive.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Starfive UFS host platform driver + * + * Copyright (C) 2026 Starfive, Inc. + * + * Authors: Minda Chen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ufshcd-pltfrm.h" +#include "ufshcd-dwc.h" +#include "ufshci-dwc.h" + +struct ufs_starfive_host { + struct ufs_hba *hba; + struct regmap *syscon; + struct reset_control *core_reset; + struct reset_control *phy_reset; + struct clk *ufs_clk; + bool phy_init; +}; + +#define SRAM_STATUS 0x38 +#define SRAM_EXT_LD_DONE BIT(1) +#define SRAM_INIT_DONE BIT(2) +#define UFS_REFCLK 0x3c +#define REFCLK_OEN BIT(8) +#define RESET_I BIT(9) +#define RESET_OEN BIT(10) + +#define MPHY_POLL_INTERVAL_US 100 +#define MPHY_POLL_TIMEOUT_US 10000 + +static int ufs_starfive_phy_config(struct ufs_hba *hba, struct ufs_starfiv= e_host *host) +{ + static struct ufs_dwc_phy_pair_data phy_data[] =3D { + { RAWAONLANEN_DIG_MPLLA_COARSE_TUNE, 0x51}, + { MPLL_SKIPCAL_COARSE_TUNE, 0x51}, + { RX_AFE_ATT_IDAC(0), 0x8a}, + { RX_AFE_ATT_IDAC(1), 0xc2}, + { RX_AFE_CTLE_IDAC(0), 0x8e}, + { RX_AFE_CTLE_IDAC(1), 0x8b}, + { FAST_FLAGS(0), 0x0004 }, + { FAST_FLAGS(1), 0x0004 }, + { RX_ADAPT_DFE(0), 0xa00}, + { RX_ADAPT_DFE(1), 0xa00}, + }; + struct ufs_dwc_phy_pair_data *data; + int ret, i; + + for (i =3D 0; i < ARRAY_SIZE(phy_data); i++) { + data =3D &phy_data[i]; + ret =3D ufs_dwc_phy_reg_write(hba, data->addr, data->value); + if (ret) + return ret; + } + + ret =3D ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYDISABLE), 0); + if (ret) + return ret; + + ret =3D ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1); + if (ret) + return ret; + + return 0; +} + +static int ufs_starfive_phy_init(struct ufs_hba *hba) +{ + struct ufs_starfive_host *host =3D ufshcd_get_variant(hba); + static struct ufshcd_dme_attr_val rmmi_config[] =3D { + { UIC_ARG_MIB(CBRATESEL), 0x1, + DME_LOCAL }, + { UIC_ARG_MIB(CBREFCLKCTRL2), CBREFREFCLK_GATE_OVR_EN, + DME_LOCAL }, + { UIC_ARG_MIB_SEL(RXSQCONTROL, SELIND_LN0_RX), 0x01, + DME_LOCAL }, + { UIC_ARG_MIB_SEL(RXRHOLDCTRLOPT, SELIND_LN0_RX), 0x02, + DME_LOCAL }, + { UIC_ARG_MIB_SEL(RXSQCONTROL, SELIND_LN1_RX), 0x01, + DME_LOCAL }, + { UIC_ARG_MIB_SEL(RXRHOLDCTRLOPT, SELIND_LN1_RX), 0x02, + DME_LOCAL }, + { UIC_ARG_MIB(EXT_COARSE_TUNE_RATEA), 0x25, + DME_LOCAL }, + { UIC_ARG_MIB(EXT_COARSE_TUNE_RATEB), 0x51, + DME_LOCAL }, + { UIC_ARG_MIB(CBCRCTRL), 0x01, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x1, + DME_LOCAL }, + }; + int ret, val; + + if (host->phy_init) + return 0; + + ret =3D ufshcd_dwc_dme_set_attrs(hba, rmmi_config, + ARRAY_SIZE(rmmi_config)); + if (ret) { + dev_err(hba->dev, "set rmmi config failed\n"); + return ret; + } + + ret =3D reset_control_deassert(host->phy_reset); + if (ret) { + dev_err(hba->dev, "Failed to reset phy\n"); + return ret; + } + + ret =3D regmap_read_poll_timeout(host->syscon, + SRAM_STATUS, val, + (val & SRAM_INIT_DONE), + MPHY_POLL_INTERVAL_US, + MPHY_POLL_TIMEOUT_US); + if (ret) { + dev_err(hba->dev, "wait sram init done timeout\n"); + return ret; + } + + regmap_update_bits(host->syscon, SRAM_STATUS, + SRAM_EXT_LD_DONE, SRAM_EXT_LD_DONE); + + ret =3D ufs_starfive_phy_config(hba, host); + if (ret) { + dev_err(hba->dev, "configure phy failed\n"); + return ret; + } + + host->phy_init =3D 1; + + return 0; +} + +static int ufs_starfive_init(struct ufs_hba *hba) +{ + struct ufs_starfive_host *host; + struct device *dev =3D hba->dev; + struct platform_device *pdev; + int ret; + + pdev =3D container_of(dev, struct platform_device, dev); + host =3D devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); + if (!host) + return dev_err_probe(dev, -ENOMEM, + "no memory for starfive ufs host\n"); + + host->syscon =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "starfive,syscon"); + + if (IS_ERR(host->syscon)) + return dev_err_probe(dev, PTR_ERR(host->syscon), "getting the regmap fai= led\n"); + + host->core_reset =3D devm_reset_control_get_exclusive(hba->dev, "main"); + if (IS_ERR(host->core_reset)) + return dev_err_probe(dev, PTR_ERR(host->core_reset), + "Failed to get core clock resets"); + + host->phy_reset =3D devm_reset_control_get_exclusive(hba->dev, "phy"); + if (IS_ERR(host->phy_reset)) + return dev_err_probe(dev, PTR_ERR(host->phy_reset), + "Failed to get phy clk reset\n"); + + host->ufs_clk =3D devm_clk_get_enabled(&pdev->dev, "main"); + if (IS_ERR(host->ufs_clk)) + return dev_err_probe(dev, PTR_ERR(host->ufs_clk), + "Failed to get ufs clock\n"); + + regmap_update_bits(host->syscon, UFS_REFCLK, + REFCLK_OEN | RESET_OEN, 0); + udelay(10); + regmap_update_bits(host->syscon, UFS_REFCLK, RESET_I, RESET_I); + + ret =3D reset_control_deassert(host->core_reset); + if (ret) + return dev_err_probe(dev, ret, + "Failed to reset core clock"); + + host->hba =3D hba; + ufshcd_set_variant(hba, host); + hba->caps |=3D UFSHCD_CAP_WB_EN; + + return 0; +} + +static void ufs_starfive_exit(struct ufs_hba *hba) +{ + struct ufs_starfive_host *host =3D ufshcd_get_variant(hba); + + if (host->phy_init) { + reset_control_assert(host->phy_reset); + host->phy_init =3D 0; + } + clk_disable_unprepare(host->ufs_clk); + + reset_control_assert(host->core_reset); +} + +static int ufs_starfive_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + int ret; + + if (status =3D=3D PRE_CHANGE) { + ret =3D ufshcd_vops_phy_initialization(hba); + if (ret) { + dev_err(hba->dev, "Phy setup failed (%d)\n", ret); + return ret; + } + } else { /* POST_CHANGE */ + return ufshcd_dwc_link_startup_notify(hba, status); + } + + return 0; +} + +static int ufs_starfive_hce_enable_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + u32 val; + + if (status !=3D POST_CHANGE) + return 0; + + /* Disable Gating clock. Auto hibernation quirk */ + val =3D ufshcd_readl(hba, REG_BUSTHRTL); + val &=3D ~(LP_AH8_POWER_GATING_EN + | LP_POWER_GATING_EN + | CLK_GATING_EN); + ufshcd_writel(hba, val, REG_BUSTHRTL); + + return 0; +} + +static struct ufs_hba_variant_ops ufs_hba_vops =3D { + .name =3D "ufs_starfive_platform", + .init =3D ufs_starfive_init, + .exit =3D ufs_starfive_exit, + .link_startup_notify =3D ufs_starfive_link_startup_notify, + .phy_initialization =3D ufs_starfive_phy_init, + .hce_enable_notify =3D ufs_starfive_hce_enable_notify, +}; + +static int ufs_starfive_probe(struct platform_device *pdev) +{ + int err; + + /* Perform generic probe */ + err =3D ufshcd_pltfrm_init(pdev, &ufs_hba_vops); + if (err) + dev_err(&pdev->dev, "ufshcd_pltfrm_init() failed %d\n", err); + + return err; +} + +static void ufs_starfive_remove(struct platform_device *pdev) +{ + ufshcd_pltfrm_remove(pdev); +} + +static const struct dev_pm_ops ufs_starfive_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) + SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) +}; + +static const struct of_device_id ufs_starfive_pltfm_match[] =3D { + { .compatible =3D "starfive,jhb100-ufs", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ufs_starfive_pltfm_match); + +static struct platform_driver ufs_starfive_driver =3D { + .probe =3D ufs_starfive_probe, + .remove =3D ufs_starfive_remove, + .driver =3D { + .name =3D "ufs-starfive", + .pm =3D pm_ptr(&ufs_starfive_pm_ops), + .of_match_table =3D of_match_ptr(ufs_starfive_pltfm_match), + }, +}; + +module_platform_driver(ufs_starfive_driver); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:ufs-starfive"); +MODULE_DESCRIPTION("Starfive UFS host platform glue driver"); diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h index 8091f186a9b3..71a60ede6805 100644 --- a/drivers/ufs/host/ufshcd-dwc.h +++ b/drivers/ufs/host/ufshcd-dwc.h @@ -12,7 +12,15 @@ =20 #include =20 +/* ufshcd vendor specific register */ +#define REG_BUSTHRTL 0xc0 +#define LP_AH8_POWER_GATING_EN BIT(17) +#define LP_POWER_GATING_EN BIT(16) +#define CLK_GATING_EN BIT(12) + /* RMMI Attributes */ +#define RXSQCONTROL 0x8009 +#define RXRHOLDCTRLOPT 0x8013 #define CBREFCLKCTRL2 0x8132 #define CBCRCTRL 0x811F #define CBC10DIRECTCONF2 0x810E @@ -24,6 +32,8 @@ #define CBCREGRDLSB 0x811A #define CBCREGRDMSB 0x811B #define CBCREGRDWRSEL 0x811C +#define EXT_COARSE_TUNE_RATEA 0x814D +#define EXT_COARSE_TUNE_RATEB 0x814E =20 #define CBREFREFCLK_GATE_OVR_EN BIT(7) =20 @@ -32,12 +42,15 @@ #define MRX_FSM_STATE 0xC1 =20 /* M-PHY registers */ +#define MPLL_SKIPCAL_COARSE_TUNE 0x28 #define RX_OVRD_IN_1(n) (0x3006 + ((n) * 0x100)) #define RX_PCS_OUT(n) (0x300F + ((n) * 0x100)) #define FAST_FLAGS(n) (0x401C + ((n) * 0x100)) +#define RX_ADAPT_DFE(n) (0x401E + ((n) * 0x100)) #define RX_AFE_ATT_IDAC(n) (0x4000 + ((n) * 0x100)) #define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100)) #define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100)) +#define RAWAONLANEN_DIG_MPLLA_COARSE_TUNE 0x7014 =20 /* Tx/Rx FSM state */ enum rx_fsm_state { @@ -64,6 +77,11 @@ struct ufshcd_dme_attr_val { u8 peer; }; =20 +struct ufs_dwc_phy_pair_data { + u32 addr; + u32 value; +}; + int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status status); int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, --=20 2.17.1