From nobody Fri Sep 25 13:56:18 2026 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CE5A47ACF6; Fri, 11 Sep 2026 15:38:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789141104; cv=none; b=KegJGIka0pWEuDDl5Yg/XMMqRiom6KrfuW1WGuXp8A/EXx8yEIUPoL6hXbzt7V6q04ZPnZMuE2Euc1z80tBuGaypktbrUJ+kJmLupg+BeCKSZllJ8hPia4VKh1ahHYDpxkiT09ow2UyqkMDte17CHXNfKQe0oMXMvYc54YRxpw4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789141104; c=relaxed/simple; bh=QzcExhrYuXnEZ7sW1ceH2vX8BTjdwMxPasQkVjImVic=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JSISz53zmPWDetSGCTFKEbcB+0QWsJem93KHEv91Y3U+DZISs6xiFkCbm8IWOukwU0KibImn1xAR8BILwE1HsQrT+Er7Qojm8EeyDM/5ptuqoV77e3sLgfYeksiTQoPTXh/XuXyAy7269JGyfN290omw//JTo+oVod3IocSakdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=WQwPS5Su; dkim=permerror (0-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=0EaU7Wc/; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="WQwPS5Su"; dkim=permerror (0-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="0EaU7Wc/" DKIM-Signature: v=1; a=rsa-sha256; s=202507r; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1789141091; bh=3yqcx7zDAq4gYSOjr2GBmU7 MbuQrcW/L7w2LoJLYyA4=; b=WQwPS5Su81bR4eDLmuWJUWEeyV56TJyXYzOUiolQB1oWJp3s6W +ldiDSsxl7OQe8B/mRmY+lJDmDCbDod3D2306bJz/sM33kM1seJysEM1ts3OEWVvP5E81YiA20c oAbHDHiraIYn2XBVCSe6g+sYqj4TPNnMZzE0vOC7Aa/OJTz7DUeicDniEW9NBv4P5xf04+rM+s7 w2iYt81b5bPr68hwxzJ6quzDklCXaYiTKJvv1wpd2SPIfCsAyX3weUJhnCo5jVgq/YEc0Eym8p3 IEXb0Ix9zCodbWxhbIxZnC0rF9y24hhkGdRKt4ZckBVyIxw5Vk6yInwGIJRhuM6wqaw==; DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1789141091; bh=3yqcx7zDAq4gYSOjr2GBmU7 MbuQrcW/L7w2LoJLYyA4=; b=0EaU7Wc/KrBSD1ffzJekICsFP+upo6NjdlMuWgk+XQ0LRCxbUM mU5H2BTmR2LhfUoY11m8qYt6Dev7x1vPRXCA==; From: Nickolay Goppen Date: Fri, 11 Sep 2026 18:38:00 +0300 Subject: [PATCH v2 1/3] dt-bindings: display: panel: Add bindings for Novatek NT51021 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260911-qcom-novatek-nt51021-panels-v2-1-135e3190a7fb@mainlining.org> References: <20260911-qcom-novatek-nt51021-panels-v2-0-135e3190a7fb@mainlining.org> In-Reply-To: <20260911-qcom-novatek-nt51021-panels-v2-0-135e3190a7fb@mainlining.org> To: Neil Armstrong , Jessica Zhang , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Nickolay Goppen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ryanbrue.dev@gmail.com X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789141089; l=3292; i=setotau@mainlining.org; s=20250815; h=from:subject:message-id; bh=QzcExhrYuXnEZ7sW1ceH2vX8BTjdwMxPasQkVjImVic=; b=d2ZUoDWzDjfOQc4toMdnOzHuZRDS8bnr6gPtJOMRubdrRgJ04P2ikOYPgY8vx/YD3awKl2EyY DLjCCO6AHaoBU6JVMONLztfqRXAG5EaAnNNrC7ouu6PSzdcssBnDMcS X-Developer-Key: i=setotau@mainlining.org; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= Novatek NT51021 is a display driver IC that can drive DSI panel. It is also present in the BOE TV101WUM-NX0 video mode panel, which is a WUXGA panel with a resolution of 1200x1920 and 10.1 inches size. It is found in Xiaomi Mi Pad 4 Plus. Also it's present in the BOE-TV080WUM-NX2 video mode panel, which also has a resolution of 1200x1920, but 8 inches size. It is found in Xiaomi Mi Pad 4. This patch adds the bindings for display driver for the IC, with support added for this BOE TV101WUM-NX0 and TV080WUM-NX2 WUXGA video mode panels. Signed-off-by: Nickolay Goppen --- .../bindings/display/panel/novatek,nt51021.yaml | 89 ++++++++++++++++++= ++++ 1 file changed, 89 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt5102= 1.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt51021.ya= ml new file mode 100644 index 000000000000..550aefaead46 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt51021.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt51021.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT51021 based DSI display Panels + +maintainers: + - Nickolay Goppen + +description: | + The NT51021 IC from Novatek is a generic DSI Panel IC used to drive dsi + panels. + Right now, support is added only for a BOE WUXGA LCD display panels with= a + resolution of 1200x1920. They are video mode DSI panels. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - boe,tv101wum-nx0 + - boe,tv080wum-nx2 + - const: novatek,nt51021 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + description: phandle of gpio for reset line - This should be 8mA, gpio + can be configured using mux, pinctrl, pinctrl-names (active low) + + vdd-supply: + description: phandle of the regulator that provides the supply voltage + for digital circuits + + avdd-supply: + description: phandle of the regulator that provides the supply voltage + for analog circuits + + havdd-supply: + description: phandle of the regulator that provides the supply voltage + for analog circuits + + port: true + backlight: true + +required: + - compatible + - reg + - vdd-supply + - avdd-supply + - havdd-supply + - reset-gpios + - port + +unevaluatedProperties: false + +examples: + - |+ + #include + + dsi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + panel@0 { + compatible =3D "boe,tv101wum-nx0", "novatek,nt51021"; + reg =3D <0>; + vdd-supply =3D <&lcd_pwr>; + avdd-supply =3D <&lcd_pwr>; + havdd-supply =3D <&lcd_pwr>; + + backlight =3D <&i2c_backlight>; + reset-gpios =3D <&tlmm 62 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + }; + +... --=20 2.55.0 From nobody Fri Sep 25 13:56:18 2026 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B390439F63; Fri, 11 Sep 2026 15:38:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789141129; cv=none; b=W6Vc1VkPpz+CLtC5PiYVxVYCEt7w7c7KxHUjqVjRW79PkMmy2W4gwYorSc6Z3Abi4WNsdU8JmnxOHp9d3dU7ReE8hSgL8iFR2L7AVjZQgSGx1OurV1JtIMclZvLjh4NmZ4WGtZeWJjbgvkn/+VoelUu4xFEb+p2T1mAoaHkyNQs= ARC-Message-Signature: i=1; a=rsa-sha256; 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From: Nickolay Goppen Date: Fri, 11 Sep 2026 18:38:01 +0300 Subject: [PATCH v2 2/3] drivers: gpu: drm: panel: Add BOE NT51021 driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260911-qcom-novatek-nt51021-panels-v2-2-135e3190a7fb@mainlining.org> References: <20260911-qcom-novatek-nt51021-panels-v2-0-135e3190a7fb@mainlining.org> In-Reply-To: <20260911-qcom-novatek-nt51021-panels-v2-0-135e3190a7fb@mainlining.org> To: Neil Armstrong , Jessica Zhang , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Nickolay Goppen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ryanbrue.dev@gmail.com, Alexey Minnekhanov X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789141089; l=41094; i=setotau@mainlining.org; s=20250815; h=from:subject:message-id; bh=uhcwLE+XC8Qm/BUUK2a1bxZsizXwU4aFFlSESX+bGIA=; b=aYYB29VjAD0LdEdJr6FoPgGLU6moSBUeb+DLihqIszssgVLPNQyTMSKwK6h+/sUolglAbA4le 2nszRz9oi/fAdRIfDc6ESMqovtxMILCcs42WFLTLjKE+pPwEKN7K2Vo X-Developer-Key: i=setotau@mainlining.org; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= Add driver for BOE NT51021-based 8-inch and 10-inch DSI video mode panels used in Xiaomi Mi Pad 4 and Mi Pad 4 Plus (xiaomi-clover) tablets. NT51021-based panels also support content-adaptive brightness control by generating a PWM signal for backlight driver IC. Content adaptation means that content grey level scale can be increased while simultaneously decreasing brightness of the backlight to achieve same perceived brightness. This makes the power consumption of backlight be reduced with keeping acceptable display quality. Both panels are very similar, differences are only in init sequence and resolution. Co-developed-by: Alexey Minnekhanov Signed-off-by: Alexey Minnekhanov Signed-off-by: Nickolay Goppen --- drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-novatek-nt51021.c | 791 ++++++++++++++++++++++= ++++ 3 files changed, 801 insertions(+) diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index cbdf7b8f7f7a..b7c11990b46f 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -727,6 +727,15 @@ config DRM_PANEL_NOVATEK_NT39016 Say Y here if you want to enable support for the panels built around the Novatek NT39016 display controller. =20 +config DRM_PANEL_NOVATEK_NT51021 + tristate "Novatek NT51021 DSI panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for the panels built + around the Novatek NT51021 Display controller. + config DRM_PANEL_OLIMEX_LCD_OLINUXINO tristate "Olimex LCD-OLinuXino panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 3b523cf37833..3fe7c2e579d3 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36672E) +=3D panel-novat= ek-nt36672e.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT37700F) +=3D panel-novatek-nt37700f.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT37801) +=3D panel-novatek-nt37801.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT39016) +=3D panel-novatek-nt39016.o +obj-$(CONFIG_DRM_PANEL_NOVATEK_NT51021) +=3D panel-novatek-nt51021.o obj-$(CONFIG_DRM_PANEL_MANTIX_MLAF057WE51) +=3D panel-mantix-mlaf057we51.o obj-$(CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO) +=3D panel-olimex-lcd-olinuxi= no.o obj-$(CONFIG_DRM_PANEL_ORISETECH_OTA5601A) +=3D panel-orisetech-ota5601a.o diff --git a/drivers/gpu/drm/panel/panel-novatek-nt51021.c b/drivers/gpu/dr= m/panel/panel-novatek-nt51021.c new file mode 100644 index 000000000000..61dd283769a7 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-novatek-nt51021.c @@ -0,0 +1,791 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2025, Nickolay Goppen +// Copyright (c) 2024, Alexey Minnekhanov + +/* + * This panel IC doesn't use the set_display_on command although + * it uses set_display_off command. This is not an error. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct novatek_nt51021_desc; + +struct novatek_nt51021_variant { + int (*init)(struct novatek_nt51021_desc *ctx); + + const struct drm_display_mode *display_mode; +}; + +struct novatek_nt51021_desc { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct regulator_bulk_data *supplies; + struct gpio_desc *reset_gpio; + + const struct novatek_nt51021_variant *variant; +}; + +static const struct regulator_bulk_data nt51021_novatek_supplies[] =3D { + { .supply =3D "vdd" }, + { .supply =3D "avdd" }, + { .supply =3D "havdd" }, +}; + +static inline struct novatek_nt51021_desc *to_novatek_panel(struct drm_pan= el *panel) +{ + return container_of_const(panel, struct novatek_nt51021_desc, panel); +} + +static void nt51021_novatek_reset(struct novatek_nt51021_desc *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + msleep(20); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(10000, 11000); +} + +static void nt51021_cabc_on(struct mipi_dsi_multi_context *dsi_ctx) +{ + if (dsi_ctx->accum_err) + return; + + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x8f, 0x00); + mipi_dsi_usleep_range(dsi_ctx, 1000, 2000); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x8f, 0xa5); + mipi_dsi_usleep_range(dsi_ctx, 1000, 2000); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x83, 0xbb); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x84, 0x22); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x90, 0x40); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x8f, 0x00); + mipi_dsi_usleep_range(dsi_ctx, 1000, 2000); +} + +static void nt51021_cabc_off(struct mipi_dsi_multi_context *dsi_ctx) +{ + if (dsi_ctx->accum_err) + return; + + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x8f, 0xa5); + mipi_dsi_usleep_range(dsi_ctx, 1000, 2000); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x83, 0xbb); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x84, 0x22); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x90, 0xc0); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x8f, 0x00); + mipi_dsi_usleep_range(dsi_ctx, 1000, 2000); +} + +static int boe_tv080wum_nx2_init(struct novatek_nt51021_desc *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi }; + + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0xa5); + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x01, 0x00); + mipi_dsi_msleep(&dsi_ctx, 20); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0xa5); + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8c, 0x8e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x6c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x8b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0xf0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8b, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0x20); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x97, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0x15); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfd, 0x1b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0xaa); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0x4b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x85, 0x04); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x86, 0x08); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x98, 0xc1); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0xaa); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x05); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x0c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0x22); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x34); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x44); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x5d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x66); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x70); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x3b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x53); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x69); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x6a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x6c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x6b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x75); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x83); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x99); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x9a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0xd0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0xdb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0xe1); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0xe7); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xda, 0xed); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdb, 0xf4); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdc, 0xfb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xde, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdf, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe0, 0x15); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe1, 0x1c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe2, 0x32); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe3, 0x44); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe4, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x60); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0x6b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x74); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0x7e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0x14); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0x25); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xeb, 0x4d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, 0x63); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x71); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0x6a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xef, 0x6c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x6b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf1, 0x75); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf2, 0x83); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf3, 0x99); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf4, 0x9a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf5, 0xd0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf6, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0xdb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf8, 0xe1); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf9, 0xe7); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0xed); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0xf4); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfc, 0xfb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfe, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0xbb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x22); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa1, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa2, 0xfe); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa3, 0xfa); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa4, 0xf7); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa5, 0xf3); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa6, 0xf1); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa7, 0xed); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa8, 0xeb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0xe9); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaa, 0xe6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaf, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x35); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x89); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x99); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x99); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x0d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x1a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0x16); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9a, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9b, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x96, 0xe6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x99, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x05); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x0c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0x22); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x34); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x44); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x5d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x66); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x70); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x3b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x53); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x69); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x6a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x6c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x6b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x75); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x83); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x99); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x9a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0xd0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0xdb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0xe1); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0xe7); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xda, 0xed); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdb, 0xf4); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdc, 0xfb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xde, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdf, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe0, 0x15); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe1, 0x1c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe2, 0x32); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe3, 0x44); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe4, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x60); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0x6b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x74); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0x7e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0x14); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0x25); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xeb, 0x4d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, 0x63); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x71); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0x6a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xef, 0x6c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x6b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf1, 0x75); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf2, 0x83); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf3, 0x99); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf4, 0x9a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf5, 0xd0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf6, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0xdb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf8, 0xe1); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf9, 0xe7); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0xed); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0xf4); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfc, 0xfb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfe, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0xcc); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x33); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x05); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x0c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0x22); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x34); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x44); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x5d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x66); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x70); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x3b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x53); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x69); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x6a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x6c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x6b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x75); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x83); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x99); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x9a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0xd0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0xdb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0xe1); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0xe7); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xda, 0xed); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdb, 0xf4); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdc, 0xfb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xde, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdf, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe0, 0x15); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe1, 0x1c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe2, 0x32); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe3, 0x44); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe4, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x60); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0x6b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x74); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0x7e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0x14); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0x25); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xeb, 0x4d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, 0x63); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x71); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0x6a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xef, 0x6c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x6b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf1, 0x75); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf2, 0x83); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf3, 0x99); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf4, 0x9a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf5, 0xd0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf6, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0xdb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf8, 0xe1); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf9, 0xe7); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0xed); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0xf4); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfc, 0xfb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfe, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9f, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0xbb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x22); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x94, 0xba); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 5000, 6000); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0x00); + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); + + nt51021_cabc_on(&dsi_ctx); + + return dsi_ctx.accum_err; +} + +static int boe_tv101wum_nx0_init(struct novatek_nt51021_desc *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi }; + + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0xa5); + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x01, 0x00); + mipi_dsi_msleep(&dsi_ctx, 20); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0xa5); + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8c, 0x8e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0x12); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfd, 0x1b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x6c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0xfc); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x97, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8b, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0x20); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0xaa); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0x4b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x85, 0x04); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x86, 0x08); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x98, 0xc1); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9c, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0xaa); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x0e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0x1f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x30); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x3f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x4b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x55); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x5d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x68); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0xe3); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0xea); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x07); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x08); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x09); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x1d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x5b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0xb6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0xbd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0xc5); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0xcd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xda, 0xe0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdb, 0xeb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdc, 0xf8); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xde, 0xfc); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdf, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe0, 0x0e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe1, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe2, 0x1f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe3, 0x30); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe4, 0x3f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x4b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0x55); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x5d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0x68); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0xe3); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0xea); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xeb, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0x07); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xef, 0x08); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x09); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf1, 0x1d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf2, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf3, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf4, 0x5b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf5, 0xb6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf6, 0xbd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0xc5); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf8, 0xcd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf9, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0xe0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0xeb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfc, 0xf8); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfe, 0xfc); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0xbb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x22); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa1, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa2, 0xfe); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa3, 0xfa); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa4, 0xf7); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa5, 0xf3); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa6, 0xf1); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa7, 0xed); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa8, 0xeb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0xe9); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaa, 0xe6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaf, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x12); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x23); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x34); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x77); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x0d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x1a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0x16); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9a, 0x10); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9b, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x96, 0xe6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x99, 0x06); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x0e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0x1f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x30); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x3f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x4b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x55); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x5d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x68); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0xe3); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0xea); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x07); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x08); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x09); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x1d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x5b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0xb6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0xbd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0xc5); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0xcd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xda, 0xe0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdb, 0xeb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdc, 0xf8); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xde, 0xfc); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdf, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe0, 0x0e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe1, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe2, 0x1f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe3, 0x30); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe4, 0x3f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x4b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0x55); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x5d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0x68); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0xe3); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0xea); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xeb, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0x07); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xef, 0x08); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x09); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf1, 0x1d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf2, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf3, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf4, 0x5b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf5, 0xb6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf6, 0xbd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0xc5); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf8, 0xcd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf9, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0xe0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0xeb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfc, 0xf8); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfe, 0xfc); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0xcc); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x33); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x0e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0x1f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x30); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x3f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x4b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x55); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x5d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x68); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0xe3); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0xea); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x07); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x08); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x09); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x1d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x5b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0xb6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0xbd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0xc5); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0xcd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xda, 0xe0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdb, 0xeb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdc, 0xf8); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xde, 0xfc); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdf, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe0, 0x0e); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe1, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe2, 0x1f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe3, 0x30); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe4, 0x3f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x4b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0x55); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x5d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0x68); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0xe3); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0xea); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xeb, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x0a); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0x07); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xef, 0x08); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x09); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf1, 0x1d); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf2, 0x31); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf3, 0x52); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf4, 0x5b); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf5, 0xb6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf6, 0xbd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0xc5); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf8, 0xcd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf9, 0xd6); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0xe0); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0xeb); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfc, 0xf8); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfd, 0xff); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfe, 0xfc); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x0f); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9f, 0xff); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 5000, 6000); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0x00); + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); + + nt51021_cabc_on(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); + + return dsi_ctx.accum_err; +} + +static int nt51021_novatek_off(struct novatek_nt51021_desc *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi }; + + nt51021_cabc_off(&dsi_ctx); + + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0xa5); + mipi_dsi_msleep(&dsi_ctx, 20); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 130); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 70); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0x00); + mipi_dsi_usleep_range(&dsi_ctx, 4000, 5000); + + return dsi_ctx.accum_err; +} + +static int nt51021_novatek_prepare(struct drm_panel *panel) +{ + struct novatek_nt51021_desc *ctx =3D to_novatek_panel(panel); + struct device *dev =3D &ctx->dsi->dev; + int ret; + + ret =3D regulator_bulk_enable(ARRAY_SIZE(nt51021_novatek_supplies), ctx->= supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators: %d\n", ret); + return ret; + } + nt51021_novatek_reset(ctx); + + ret =3D ctx->variant->init(ctx); + if (ret < 0) { + dev_err(dev, "Failed to initialize panel: %d\n", ret); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(nt51021_novatek_supplies), ctx->suppli= es); + return ret; + } + + return 0; +} + +static int nt51021_novatek_unprepare(struct drm_panel *panel) +{ + struct novatek_nt51021_desc *ctx =3D to_novatek_panel(panel); + struct device *dev =3D &ctx->dsi->dev; + int ret; + + ret =3D nt51021_novatek_off(ctx); + if (ret < 0) + dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(nt51021_novatek_supplies), ctx->supplie= s); + + return 0; +} + +static int nt51021_novatek_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct novatek_nt51021_desc *ctx =3D to_novatek_panel(panel); + + return drm_connector_helper_get_modes_fixed(connector, + ctx->variant->display_mode); +} + +static const struct drm_panel_funcs nt51021_novatek_panel_funcs =3D { + .prepare =3D nt51021_novatek_prepare, + .unprepare =3D nt51021_novatek_unprepare, + .get_modes =3D nt51021_novatek_get_modes, +}; + +static int nt51021_novatek_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev =3D &dsi->dev; + struct novatek_nt51021_desc *ctx; + int ret; + + ctx =3D devm_drm_panel_alloc(dev, struct novatek_nt51021_desc, panel, + &nt51021_novatek_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + if (IS_ERR(ctx)) + return PTR_ERR(ctx); + + ctx->variant =3D of_device_get_match_data(dev); + if (!ctx->variant) + return dev_err_probe(dev, -ENODEV, "No match data\n"); + + ret =3D devm_regulator_bulk_get_const(dev, + ARRAY_SIZE(nt51021_novatek_supplies), + nt51021_novatek_supplies, + &ctx->supplies); + if (ret < 0) + return ret; + + ctx->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); + + ctx->dsi =3D dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes =3D 4; + dsi->format =3D MIPI_DSI_FMT_RGB888; + dsi->mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_LPM; + + ctx->panel.prepare_prev_first =3D true; + + ret =3D drm_panel_of_backlight(&ctx->panel); + if (ret) + return dev_err_probe(dev, ret, "Failed to get backlight\n"); + + devm_drm_panel_add(dev, &ctx->panel); + + ret =3D devm_mipi_dsi_attach(dev, dsi); + + return 0; +} + +static const struct drm_display_mode boe_tv080wum_nx2_mode =3D { + .clock =3D (1200 + 84 + 4 + 60) * (1920 + 36 + 1 + 25) * 60 / 1000, + .hdisplay =3D 1200, + .hsync_start =3D 1200 + 84, + .hsync_end =3D 1200 + 84 + 4, + .htotal =3D 1200 + 84 + 4 + 60, + .vdisplay =3D 1920, + .vsync_start =3D 1920 + 36, + .vsync_end =3D 1920 + 36 + 1, + .vtotal =3D 1920 + 36 + 1 + 25, + .width_mm =3D 107, + .height_mm =3D 172, + .type =3D DRM_MODE_TYPE_DRIVER, +}; + +static const struct drm_display_mode boe_tv101wum_nx0_mode =3D { + .clock =3D (1200 + 172 + 4 + 32) * (1920 + 25 + 1 + 14) * 60 / 1000, + .hdisplay =3D 1200, + .hsync_start =3D 1200 + 172, + .hsync_end =3D 1200 + 172 + 4, + .htotal =3D 1200 + 172 + 4 + 32, + .vdisplay =3D 1920, + .vsync_start =3D 1920 + 25, + .vsync_end =3D 1920 + 25 + 1, + .vtotal =3D 1920 + 25 + 1 + 14, + .width_mm =3D 135, + .height_mm =3D 216, + .type =3D DRM_MODE_TYPE_DRIVER, +}; + +static const struct novatek_nt51021_variant boe_tv080wum_nx2_data =3D { + .init =3D boe_tv080wum_nx2_init, + .display_mode =3D &boe_tv080wum_nx2_mode, +}; + +static const struct novatek_nt51021_variant boe_tv101wum_nx0_data =3D { + .init =3D boe_tv101wum_nx0_init, + .display_mode =3D &boe_tv101wum_nx0_mode, +}; + +static const struct of_device_id nt51021_novatek_of_match[] =3D { + { .compatible =3D "boe,tv080wum-nx2", .data =3D &boe_tv080wum_nx2_data }, + { .compatible =3D "boe,tv101wum-nx0", .data =3D &boe_tv101wum_nx0_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, nt51021_novatek_of_match); + +static struct mipi_dsi_driver nt51021_boe_driver =3D { + .probe =3D nt51021_novatek_probe, + .driver =3D { + .name =3D "panel-novatek-nt51021", + .of_match_table =3D nt51021_novatek_of_match, + }, +}; +module_mipi_dsi_driver(nt51021_boe_driver); + +MODULE_AUTHOR("Nickolay Goppen "); +MODULE_AUTHOR("Alexey Minnekhanov "); +MODULE_DESCRIPTION("DRM driver for Novatek NT51021-based DSI panels"); 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DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1789141092; bh=OATDRvWIhuV2v8n55fSDver iCL2HGH/4EkvtPirdd0Y=; b=li5Mh+gdWMlKtzKoU5EGysAl02u1UFlyw/0WzDUk2584Tl2Krc ZValRyQbOejivMmuZfq+VY4VkV/GWDVG+yBw==; From: Nickolay Goppen Date: Fri, 11 Sep 2026 18:38:02 +0300 Subject: [PATCH v2 3/3] MAINTAINERS: Add myself as a maintainer of NT51021 panel driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260911-qcom-novatek-nt51021-panels-v2-3-135e3190a7fb@mainlining.org> References: <20260911-qcom-novatek-nt51021-panels-v2-0-135e3190a7fb@mainlining.org> In-Reply-To: <20260911-qcom-novatek-nt51021-panels-v2-0-135e3190a7fb@mainlining.org> To: Neil Armstrong , Jessica Zhang , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Nickolay Goppen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ryanbrue.dev@gmail.com X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789141089; l=772; i=setotau@mainlining.org; s=20250815; h=from:subject:message-id; bh=zD9oZKRsCcU0BIHbOPpViTHvx1OPAy7to3vbd/4GBpA=; b=8gI9KLvHBhtUk5K3U2ubweplEguh9EA5WUqcstLUkTLId5aiDDPOMMWY9cjsgOp9BMHhWrEWI S0kIq39cIJkAGhw+sVowTm4MbYnBX4qbceiI8IQuMgZN4CjnfuZaK8y X-Developer-Key: i=setotau@mainlining.org; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= Signed-off-by: Nickolay Goppen --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7291238bc09f..3e2e6b94e6ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8354,6 +8354,12 @@ S: Maintained F: Documentation/devicetree/bindings/display/panel/novatek,nt37801.yaml F: drivers/gpu/drm/panel/panel-novatek-nt37801.c =20 +DRM DRIVER FOR NOVATEK NT51021 PANELS +M: Nickolay Goppen +S: Maintained +F: Documentation/devicetree/bindings/display/panel/novatek,nt51021.yaml +F: drivers/gpu/drm/panel/panel-novatek-nt51021.c + DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS M: Lyude Paul M: Danilo Krummrich --=20 2.55.0