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charset="utf-8" From: Daniel Wagner The calculation of the upper limit for queues does not depend solely on the number of online CPUs; for example, the isolcpus kernel command-line option must also be considered. To account for this, the block layer provides a helper function to retrieve the maximum number of queues. Use it to set an appropriate upper queue number limit. This patch brings aacraid in line with the API migration initiated for other SCSI drivers in commit 94970cfb5f10 ("scsi: use block layer helpers to calculate num of queues"). Signed-off-by: Daniel Wagner Reviewed-by: Martin K. Petersen Reviewed-by: Hannes Reinecke Signed-off-by: Aaron Tomlin Tested-by: Ionut Nechita --- drivers/scsi/aacraid/comminit.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/scsi/aacraid/comminit.c b/drivers/scsi/aacraid/commini= t.c index 9bd3f5b868bc..ec165b57182d 100644 --- a/drivers/scsi/aacraid/comminit.c +++ b/drivers/scsi/aacraid/comminit.c @@ -469,8 +469,7 @@ void aac_define_int_mode(struct aac_dev *dev) } =20 /* Don't bother allocating more MSI-X vectors than cpus */ - msi_count =3D min(dev->max_msix, - (unsigned int)num_online_cpus()); + msi_count =3D blk_mq_num_online_queues(dev->max_msix); =20 dev->max_msix =3D msi_count; =20 --=20 2.55.0 From nobody Fri Sep 25 16:01:40 2026 Received: from LO3P265CU004.outbound.protection.outlook.com (mail-uksouthazon11020093.outbound.protection.outlook.com [52.101.196.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECF214E56F9; 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charset="utf-8" From: Daniel Wagner The core scheduler recently transitioned to compiling SMP data structures unconditionally to reduce code complexity - see commit cac5cefbade9 ("sched/smp: Make SMP unconditional"). In alignment with this philosophy of reducing dual-path maintenance, this patch removes the #ifdef CONFIG_SMP guards and the dedicated !SMP fallback logic here. While the !SMP path provided a slightly simpler execution flow for uniprocessor kernels (avoiding SMP-specific overhead), maintaining these separate code paths adds unnecessary complexity and testing burden. Removing these guards simplifies the codebase by standardizing entirely on the SMP logic, which safely resolves to single-CPU operations on UP configurations. Signed-off-by: Daniel Wagner Reviewed-by: Martin K. Petersen Reviewed-by: Hannes Reinecke Signed-off-by: Aaron Tomlin Tested-by: Ionut Nechita --- lib/group_cpus.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/lib/group_cpus.c b/lib/group_cpus.c index e6e18d7a49bb..b8d54398f88a 100644 --- a/lib/group_cpus.c +++ b/lib/group_cpus.c @@ -9,8 +9,6 @@ #include #include =20 -#ifdef CONFIG_SMP - static void grp_spread_init_one(struct cpumask *irqmsk, struct cpumask *nm= sk, unsigned int cpus_per_grp) { @@ -564,22 +562,4 @@ struct cpumask *group_cpus_evenly(unsigned int numgrps= , unsigned int *nummasks) *nummasks =3D min(nr_present + nr_others, numgrps); return masks; } -#else /* CONFIG_SMP */ -struct cpumask *group_cpus_evenly(unsigned int numgrps, unsigned int *numm= asks) -{ - struct cpumask *masks; - - if (numgrps =3D=3D 0) - return NULL; - - masks =3D kzalloc_objs(*masks, numgrps); - if (!masks) - return NULL; - - /* assign all CPUs(cpu 0) to the 1st group only */ - cpumask_copy(&masks[0], cpu_possible_mask); - *nummasks =3D 1; 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Thu, 10 Sep 2026 16:43:00 +0000 Received: from CWLP123MB6607.GBRP123.PROD.OUTLOOK.COM ([fe80::cec4:77ab:262e:d230]) by CWLP123MB6607.GBRP123.PROD.OUTLOOK.COM ([fe80::cec4:77ab:262e:d230%4]) with mapi id 15.21.0406.007; Thu, 10 Sep 2026 16:43:00 +0000 From: Aaron Tomlin To: axboe@kernel.dk, tglx@kernel.org, aacraid@microsemi.com, James.Bottomley@HansenPartnership.com, mkp@kernel.org, frederic@kernel.org, bigeasy@linutronix.de Cc: atomlin@atomlin.com, ionut.nechita@windriver.com, corbet@lwn.net, vincent.guittot@linaro.org, mingo@redhat.com, peterz@infradead.org, radu@rendec.net, akpm@linux-foundation.org, steve@abita.co, sean@ashe.io, chjohnst@gmail.com, neelx@suse.com, mproche@gmail.com, nick.lange@gmail.com, marco.crivellari@suse.com, rishil1999@outlook.com, linux-doc@vger.kernel.org, linux-block@vger.kernel.org, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v16 3/9] lib/group_cpus: Add group_mask_cpus_evenly() Date: Thu, 10 Sep 2026 12:42:31 -0400 Message-ID: <20260910164237.500196-4-atomlin@atomlin.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910164237.500196-1-atomlin@atomlin.com> References: <20260910164237.500196-1-atomlin@atomlin.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: DS7PR05CA0006.namprd05.prod.outlook.com (2603:10b6:5:3b9::11) To CWLP123MB6607.GBRP123.PROD.OUTLOOK.COM (2603:10a6:400:183::5) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CWLP123MB6607:EE_|CW1P123MB096022:EE_ X-MS-Office365-Filtering-Correlation-Id: 4cb095c5-58f1-4c65-41dc-08df0f5a9311 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|366016|376014|7416014|6133799003|18002099003|22082099003|56012099006|10067099003; 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charset="utf-8" From: Daniel Wagner This commit introduces group_mask_cpus_evenly(), which allows callers to distribute a specific CPU mask evenly across groups. It serves as a bounded version of group_cpus_evenly(). While group_cpus_evenly() operates on the global cpu_possible_mask, group_mask_cpus_evenly() confines the distribution strictly within the boundaries of the caller-provided mask. It preserves the kernel's native two-stage spreading logic-first prioritising CPUs that are physically present (cpu_present_mask) to prevent I/O starvation, and then distributing any remaining vectors to non-present CPUs to maintain hotplug safety. Signed-off-by: Daniel Wagner Reviewed-by: Hannes Reinecke Co-developed-by: Aaron Tomlin Signed-off-by: Aaron Tomlin Tested-by: Ionut Nechita --- include/linux/group_cpus.h | 3 + lib/group_cpus.c | 110 +++++++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/include/linux/group_cpus.h b/include/linux/group_cpus.h index 9d4e5ab6c314..defab4123a82 100644 --- a/include/linux/group_cpus.h +++ b/include/linux/group_cpus.h @@ -10,5 +10,8 @@ #include =20 struct cpumask *group_cpus_evenly(unsigned int numgrps, unsigned int *numm= asks); +struct cpumask *group_mask_cpus_evenly(unsigned int numgrps, + const struct cpumask *mask, + unsigned int *nummasks); =20 #endif diff --git a/lib/group_cpus.c b/lib/group_cpus.c index b8d54398f88a..75bd082e00bf 100644 --- a/lib/group_cpus.c +++ b/lib/group_cpus.c @@ -563,3 +563,113 @@ struct cpumask *group_cpus_evenly(unsigned int numgrp= s, unsigned int *nummasks) return masks; } EXPORT_SYMBOL_GPL(group_cpus_evenly); + +/** + * group_mask_cpus_evenly - Group all CPUs evenly per NUMA/CPU locality + * @numgrps: number of cpumasks to create + * @mask: CPUs to consider for the grouping + * @nummasks: number of initialized cpumasks + * + * Return: cpumask array if successful, NULL otherwise. Only the CPUs + * marked in the mask will be considered for the grouping. And each + * element includes CPUs assigned to this group. nummasks contains the + * number of initialized masks which can be less than numgrps. + * + * Try to put close CPUs from viewpoint of CPU and NUMA locality into + * the same group. + * + * We guarantee in the resulting grouping that all CPUs specified in the + * provided mask are covered, and no same CPU is assigned to multiple + * groups. + */ +struct cpumask *group_mask_cpus_evenly(unsigned int numgrps, + const struct cpumask *mask, + unsigned int *nummasks) +{ + unsigned int curgrp =3D 0, nr_present =3D 0, nr_others =3D 0; + cpumask_var_t *node_to_cpumask; + cpumask_var_t nmsk, local_mask, npresmsk; + int ret =3D -ENOMEM; + struct cpumask *masks =3D NULL; + + if (numgrps =3D=3D 0) + return NULL; + + if (!zalloc_cpumask_var(&nmsk, GFP_KERNEL)) + return NULL; + + if (!zalloc_cpumask_var(&local_mask, GFP_KERNEL)) + goto fail_nmsk; + + if (!zalloc_cpumask_var(&npresmsk, GFP_KERNEL)) + goto fail_local_mask; + + node_to_cpumask =3D alloc_node_to_cpumask(); + if (!node_to_cpumask) + goto fail_npresmsk; + + masks =3D kzalloc_objs(*masks, numgrps); + if (!masks) + goto fail_node_to_cpumask; + + build_node_to_cpumask(node_to_cpumask); + + /* + * Create a stable snapshot of the mask. The grouping algorithm + * requires the CPU count to remain constant across its multiple + * passes. This prevents allocation failures if the caller passes a + * dynamic mask (e.g., cpu_online_mask) that changes concurrently. + */ + cpumask_copy(local_mask, mask); + + /* + * Grouping present CPUs first. We intersect the provided mask with + * cpu_present_mask to ensure that we prioritise physically + * available CPUs for the initial distribution. + */ + cpumask_and(npresmsk, local_mask, cpu_present_mask); + ret =3D __group_cpus_evenly(curgrp, numgrps, node_to_cpumask, + npresmsk, nmsk, masks); + if (ret < 0) + goto fail_node_to_cpumask; + nr_present =3D ret; + + /* + * Allocate non-present CPUs starting from the next group to be + * handled. If the grouping of present CPUs already exhausted the + * group space, assign the non-present CPUs to the already + * allocated out groups. + */ + if (nr_present >=3D numgrps) + curgrp =3D 0; + else + curgrp =3D nr_present; + cpumask_andnot(npresmsk, local_mask, npresmsk); + ret =3D __group_cpus_evenly(curgrp, numgrps, node_to_cpumask, + npresmsk, nmsk, masks); + if (ret >=3D 0) + nr_others =3D ret; + +fail_node_to_cpumask: + free_node_to_cpumask(node_to_cpumask); + +fail_npresmsk: + free_cpumask_var(npresmsk); + +fail_local_mask: + free_cpumask_var(local_mask); + +fail_nmsk: + free_cpumask_var(nmsk); + if (ret < 0) { + kfree(masks); + return NULL; + } + *nummasks =3D min(nr_present + nr_others, numgrps); + if (*nummasks =3D=3D 0) { + kfree(masks); + return NULL; + } + return masks; +} +EXPORT_SYMBOL_GPL(group_mask_cpus_evenly); --=20 2.55.0 From nobody Fri Sep 25 16:01:40 2026 Received: from LO2P265CU024.outbound.protection.outlook.com (mail-uksouthazon11021137.outbound.protection.outlook.com [52.101.95.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27A2C4BE45B; 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charset="utf-8" The "isolcpus=3D" boot parameter parser in housekeeping_isolcpus_setup() contains an out-of-bounds memory read bug when handling unterminated flags. When parsing the boot parameter string, the logic expects flags to be comma-separated. If a user passes an unrecognised or legitimate flag at the very end of the string without a trailing comma (e.g., "isolcpus=3Dunknown"), the strict strncmp() checks will fail. The execution then falls through to a fallback for loop designed to skip the unknown sub-parameter. This inner loop consumes characters until it encounters either a comma or the NULL terminator ('\0'). When the loop terminates due to hitting the end of the string, the str pointer rests exactly on the NULL terminator. However, immediately following this inner loop, the code unconditionally executes str++. This advances the pointer past the end of the string and into uninitialised memory. The outer while (isalpha(*str)) loop subsequently evaluates this out-of-bounds memory. If the adjacent byte happens to be alphabetical, the parser will continue reading garbage data, potentially leading to undefined behavior or boot anomalies. Fix this by adding a bounds check immediately before the pointer increment. This ensures the parsing loop cleanly terminates when reaching the end of the boot parameter string. Reported-by: sashiko-bot@kernel.org Fixes: 3662daf023500 ("sched/isolation: Allow "isolcpus=3D" to skip unknown= sub-parameters") Cc: stable@vger.kernel.org Reviewed-by: Valentin Schneider Signed-off-by: Aaron Tomlin Tested-by: Ionut Nechita --- kernel/sched/isolation.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/sched/isolation.c b/kernel/sched/isolation.c index 156025ef81b7..9f02e9264a3f 100644 --- a/kernel/sched/isolation.c +++ b/kernel/sched/isolation.c @@ -369,6 +369,8 @@ static int __init housekeeping_isolcpus_setup(char *str) } =20 pr_info("isolcpus: Skipped unknown flag %.*s\n", len, par); + if (!*str) + break; str++; } =20 --=20 2.55.0 From nobody Fri Sep 25 16:01:40 2026 Received: from LO2P265CU024.outbound.protection.outlook.com (mail-uksouthazon11021137.outbound.protection.outlook.com [52.101.95.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53646526A9E; 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charset="utf-8" From: Daniel Wagner Multiqueue drivers spread I/O queues and managed interrupts across all CPUs for optimal performance. However, these drivers are not aware of CPU isolation requirements and will distribute queues and interrupt vectors without considering the isolcpus configuration. The existing isolcpus=3Dmanaged_irq parameter attempts post-allocation affinity steering, but this is best-effort and fails on modern multiqueue storage where the number of queues meets or exceeds the CPU count. Introduce a new isolcpus flag, "managed_irq_strict", that allows users to strictly define which CPUs should have multiqueue hardware queues and managed interrupts assigned. This enforces pre-allocation queue bounding and mask exclusion, preventing managed hardware interrupts from ever targeting isolated cores. Because managed_irq_strict is a strict superset of managed_irq, specifying managed_irq_strict automatically enables HK_FLAG_MANAGED_IRQ as well. This ensures subsystems that rely on managed interrupt isolation (e.g. Hyper-V VMBus channel distribution) continue to function seamlessly. Signed-off-by: Daniel Wagner Reviewed-by: Martin K. Petersen Reviewed-by: Hannes Reinecke Signed-off-by: Aaron Tomlin Tested-by: Ionut Nechita --- include/linux/sched/isolation.h | 1 + kernel/sched/isolation.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/include/linux/sched/isolation.h b/include/linux/sched/isolatio= n.h index cf0fd03dd7a2..bda3003ce86f 100644 --- a/include/linux/sched/isolation.h +++ b/include/linux/sched/isolation.h @@ -18,6 +18,7 @@ enum hk_type { HK_TYPE_MANAGED_IRQ, /* Inverse of boot-time nohz_full=3D or isolcpus=3Dnohz arguments */ HK_TYPE_KERNEL_NOISE, + HK_TYPE_MANAGED_IRQ_STRICT, HK_TYPE_MAX, =20 /* diff --git a/kernel/sched/isolation.c b/kernel/sched/isolation.c index 9f02e9264a3f..7e9e78a18fb9 100644 --- a/kernel/sched/isolation.c +++ b/kernel/sched/isolation.c @@ -17,6 +17,7 @@ enum hk_flags { HK_FLAG_DOMAIN =3D BIT(HK_TYPE_DOMAIN), HK_FLAG_MANAGED_IRQ =3D BIT(HK_TYPE_MANAGED_IRQ), HK_FLAG_KERNEL_NOISE =3D BIT(HK_TYPE_KERNEL_NOISE), + HK_FLAG_MANAGED_IRQ_STRICT =3D BIT(HK_TYPE_MANAGED_IRQ_STRICT), }; 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charset="utf-8" From: Daniel Wagner Extend the capabilities of the generic CPU to hardware queue (hctx) mapping code, so it maps housekeeping CPUs and isolated CPUs to the hardware queues evenly. Example mapping result: 16 online CPUs isolcpus=3Dmanaged_irq_strict,2-3,6-7,12-13 Queue mapping: hctx0: default 0 2 hctx1: default 1 3 hctx2: default 4 6 hctx3: default 5 7 hctx4: default 8 12 hctx5: default 9 13 hctx6: default 10 hctx7: default 11 hctx8: default 14 hctx9: default 15 IRQ mapping: irq 42 affinity 0 effective 0 nvme0q0 irq 43 affinity 0 effective 0 nvme0q1 irq 44 affinity 1 effective 1 nvme0q2 irq 45 affinity 4 effective 4 nvme0q3 irq 46 affinity 5 effective 5 nvme0q4 irq 47 affinity 8 effective 8 nvme0q5 irq 48 affinity 9 effective 9 nvme0q6 irq 49 affinity 10 effective 10 nvme0q7 irq 50 affinity 11 effective 11 nvme0q8 irq 51 affinity 14 effective 14 nvme0q9 irq 52 affinity 15 effective 15 nvme0q10 In this scenario, the system has 16 online CPUs with 6 isolated cores (2, 3, 6, 7, 12, and 13) and 10 housekeeping cores (0, 1, 4, 5, 8, 9, 10, 11, 14, and 15): 1. Queue allocation and ownership Rather than allocating 16 hardware queues, the block layer allocates only 10 hardware contexts (hctx0 to hctx9), corresponding strictly to the 10 housekeeping CPUs. The 6 isolated CPUs do not own dedicated hardware queues; instead, they are mapped across the existing active housekeeping queues (e.g. isolated CPU 2 shares hctx0 with CPU 0). This ensures tasks running on isolated CPUs can still issue I/O without restriction. 2. Interrupt routing All device interrupts, including the NVMe admin queue (irq 42) and the 10 I/O completion queues (irq 43 to 52), target housekeeping CPUs exclusively. When a task on isolated CPU 2 issues I/O via hctx0, the resulting completion interrupt (irq 43) fires on housekeeping CPU 0. Consequently, isolated CPUs are never interrupted by device hardware, guaranteeing zero latency disturbance for isolated workloads. A corner case is when the number of online CPUs and present CPUs differ and the driver asks for less queues than online CPUs, e.g. 8 online CPUs, 16 possible CPUs isolcpus=3Dmanaged_irq_strict,2-3,6-7,12-13 virtio_blk.num_request_queues=3D2 Queue mapping: hctx0: default 0 1 2 3 4 5 6 7 8 12 13 hctx1: default 9 10 11 14 15 IRQ mapping irq 27 affinity 0 effective 0 virtio0-config irq 28 affinity 0-1,4-5,8 effective 5 virtio0-req.0 irq 29 affinity 9-11,14-15 effective 0 virtio0-req.1 This corner case demonstrates behaviour when hardware queue counts are constrained (only 2 request queues) on a system with CPU hotplug (8 CPUs online out of 16 possible): 1. Coarse queue grouping Because the driver requests only 2 queues, the 10 possible housekeeping CPUs are partitioned into two groups: hctx0 receives CPUs 0-1, 4-5, and 8, while hctx1 receives CPUs 9-11 and 14-15. All isolated CPUs (both online cores 2-3, 6-7 and offline cores 12-13) are mapped to hctx0 to share submission capacity without allocating excess queues. 2. Isolation and hotplug protection in interrupt affinity Although hctx0 serves both housekeeping and isolated CPUs, the resulting interrupt affinity mask for irq 28 (affinity 0-1,4-5,8) strictly includes only the housekeeping cores, completely excluding isolated cores 2-3, 6-7, and 12-13. Furthermore, for hctx1 (irq 29), whose assigned housekeeping CPUs (9-11, 14-15) are currently offline, the kernel routes the effective interrupt to an available online housekeeping core (CPU 0), guaranteeing that interrupts never spill onto isolated cores under any hotplug state. Noteworthy is that for the normal/default configuration (without isolcpus=3D) the mapping will change for systems which have non hyperthreading CPUs. The main assignment loop will completely rely that group_mask_cpus_evenly to do the right thing. The old code would distribute the CPUs linearly over the hardware context: queue mapping for /dev/nvme0n1 hctx0: default 0 8 hctx1: default 1 9 hctx2: default 2 10 hctx3: default 3 11 hctx4: default 4 12 hctx5: default 5 13 hctx6: default 6 14 hctx7: default 7 15 The assign each hardware context the map generated by the group_mask_cpus_evenly function: queue mapping for /dev/nvme0n1 hctx0: default 0 1 hctx1: default 2 3 hctx2: default 4 5 hctx3: default 6 7 hctx4: default 8 9 hctx5: default 10 11 hctx6: default 12 13 hctx7: default 14 15 In case of hyperthreading CPUs, the resulting map stays the same. Signed-off-by: Daniel Wagner Co-developed-by: Aaron Tomlin Signed-off-by: Aaron Tomlin Tested-by: Ionut Nechita --- block/blk-mq-cpumap.c | 163 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 145 insertions(+), 18 deletions(-) diff --git a/block/blk-mq-cpumap.c b/block/blk-mq-cpumap.c index 705da074ad6c..cec5b26bd57c 100644 --- a/block/blk-mq-cpumap.c +++ b/block/blk-mq-cpumap.c @@ -22,8 +22,15 @@ static unsigned int blk_mq_num_queues(const struct cpuma= sk *mask, { unsigned int num; =20 - num =3D cpumask_weight(mask); - return min_not_zero(num, max_queues); + if (housekeeping_enabled(HK_TYPE_MANAGED_IRQ_STRICT)) + num =3D cpumask_weight_and(mask, housekeeping_cpumask(HK_TYPE_MANAGED_IR= Q_STRICT)); + else + num =3D cpumask_weight(mask); + /* + * Ensure that a count of zero does not inadvertently result in + * allocating the maximum number of queues. + */ + return min_not_zero(num ?: 1U, max_queues); } =20 /** @@ -33,7 +40,8 @@ static unsigned int blk_mq_num_queues(const struct cpumas= k *mask, * ignored. * * Calculates the number of queues to be used for a multiqueue - * device based on the number of possible CPUs. + * device based on the number of possible CPUs. This helper + * takes isolcpus settings into account. */ unsigned int blk_mq_num_possible_queues(unsigned int max_queues) { @@ -48,7 +56,8 @@ EXPORT_SYMBOL_GPL(blk_mq_num_possible_queues); * ignored. * * Calculates the number of queues to be used for a multiqueue - * device based on the number of online CPUs. + * device based on the number of online CPUs. This helper + * takes isolcpus settings into account. */ unsigned int blk_mq_num_online_queues(unsigned int max_queues) { @@ -56,23 +65,81 @@ unsigned int blk_mq_num_online_queues(unsigned int max_= queues) } EXPORT_SYMBOL_GPL(blk_mq_num_online_queues); =20 +static void blk_mq_map_fallback(struct blk_mq_queue_map *qmap) +{ + unsigned int cpu; + + /* + * Map all CPUs to the first hctx of this specific map, respecting + * the map's boundaries so secondary maps do not route into the default m= ap. + */ + for_each_possible_cpu(cpu) + qmap->mq_map[cpu] =3D qmap->queue_offset; +} + void blk_mq_map_queues(struct blk_mq_queue_map *qmap) { - const struct cpumask *masks; + struct cpumask *masks; + const struct cpumask *constraint; unsigned int queue, cpu, nr_masks; + unsigned long *active_hctx; =20 - masks =3D group_cpus_evenly(qmap->nr_queues, &nr_masks); - if (!masks) { - for_each_possible_cpu(cpu) - qmap->mq_map[cpu] =3D qmap->queue_offset; - return; - } + active_hctx =3D bitmap_zalloc(qmap->nr_queues, GFP_KERNEL); + if (!active_hctx) + goto fallback; =20 - for (queue =3D 0; queue < qmap->nr_queues; queue++) { - for_each_cpu(cpu, &masks[queue % nr_masks]) + if (housekeeping_enabled(HK_TYPE_MANAGED_IRQ_STRICT)) + constraint =3D housekeeping_cpumask(HK_TYPE_MANAGED_IRQ_STRICT); + else + constraint =3D cpu_possible_mask; + + /* Map CPUs to the hardware contexts (hctx) */ + masks =3D group_mask_cpus_evenly(qmap->nr_queues, constraint, &nr_masks); + if (!masks) + goto free_fallback_hctx; + + /* + * Iterate directly over the generated CPU masks. + * Calculate the final, highest hardware queue index that maps to this + * mask. This skips all intermediate overwrites and safely evaluates + * active_hctx only for queues that survive the mapping. + */ + for (unsigned int idx =3D 0; idx < nr_masks; idx++) { + queue =3D qmap->nr_queues - 1 - + ((qmap->nr_queues - 1 - idx) % nr_masks); + + for_each_cpu(cpu, &masks[idx]) qmap->mq_map[cpu] =3D qmap->queue_offset + queue; + + __set_bit(queue, active_hctx); + } + + /* + * If the active_hctx bitmap is empty, attempting to route unassigned + * CPUs will map them out-of-bounds. Fall back instead. + */ + if (bitmap_empty(active_hctx, qmap->nr_queues)) + goto free_fallback; + + /* Map any unassigned CPU evenly to the hardware contexts (hctx) */ + queue =3D find_first_bit(active_hctx, qmap->nr_queues); + for_each_cpu_andnot(cpu, cpu_possible_mask, constraint) { + qmap->mq_map[cpu] =3D qmap->queue_offset + queue; + queue =3D find_next_bit_wrap(active_hctx, qmap->nr_queues, queue + 1); } + + kfree(masks); + bitmap_free(active_hctx); + + return; + +free_fallback: kfree(masks); +free_fallback_hctx: + bitmap_free(active_hctx); + +fallback: + blk_mq_map_fallback(qmap); } EXPORT_SYMBOL_GPL(blk_mq_map_queues); =20 @@ -109,24 +176,84 @@ void blk_mq_map_hw_queues(struct blk_mq_queue_map *qm= ap, struct device *dev, unsigned int offset) =20 { - const struct cpumask *mask; + cpumask_var_t mask; + const struct cpumask *constraint; + unsigned long *active_hctx; unsigned int queue, cpu; =20 if (!dev->bus->irq_get_affinity) + goto map_software; + + active_hctx =3D bitmap_zalloc(qmap->nr_queues, GFP_KERNEL); + if (!active_hctx) goto fallback; =20 + if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { + bitmap_free(active_hctx); + goto fallback; + } + + if (housekeeping_enabled(HK_TYPE_MANAGED_IRQ_STRICT)) + constraint =3D housekeeping_cpumask(HK_TYPE_MANAGED_IRQ_STRICT); + else + constraint =3D cpu_possible_mask; + + /* Map CPUs to the hardware contexts (hctx) */ for (queue =3D 0; queue < qmap->nr_queues; queue++) { - mask =3D dev->bus->irq_get_affinity(dev, queue + offset); - if (!mask) - goto fallback; + const struct cpumask *affinity_mask; + + affinity_mask =3D dev->bus->irq_get_affinity(dev, offset + queue); + if (!affinity_mask) + goto free_map_software; =20 - for_each_cpu(cpu, mask) + for_each_cpu(cpu, affinity_mask) { qmap->mq_map[cpu] =3D qmap->queue_offset + queue; + cpumask_set_cpu(cpu, mask); + } } =20 + /* + * Evaluate active_hctx after mapping to handle overlapping masks. + * This ensures queues that were overwritten do not falsely pass validati= on. + */ + for_each_cpu(cpu, mask) { + if (cpumask_test_cpu(cpu, constraint)) { + queue =3D qmap->mq_map[cpu] - qmap->queue_offset; + __set_bit(queue, active_hctx); + } + } + + /* + * If no assigned CPU matches the constraint, the active_hctx + * bitmap will be empty. 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charset="utf-8" From: Daniel Wagner When isolcpus=3Dmanaged_irq_strict is enabled and the last housekeeping CPU for a given hctx goes offline, no CPU would be left to handle I/O. To prevent I/O stalls, disallow offlining housekeeping CPUs that are still serving isolated CPUs. Signed-off-by: Daniel Wagner Reviewed-by: Hannes Reinecke Co-developed-by: Aaron Tomlin Signed-off-by: Aaron Tomlin Tested-by: Ionut Nechita --- block/blk-mq.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/block/blk-mq.c b/block/blk-mq.c index a26a11c73ee3..6e903e1310e9 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -3690,6 +3690,64 @@ static bool blk_mq_hctx_has_requests(struct blk_mq_h= w_ctx *hctx) return data.has_rq; } =20 +static bool blk_mq_hctx_can_offline_hk_cpu(struct blk_mq_hw_ctx *hctx, + unsigned int this_cpu) +{ + const struct cpumask *hk_mask =3D housekeeping_cpumask(HK_TYPE_MANAGED_IR= Q_STRICT); + int cpu, fallback_isolated_cpu =3D -1; + + /* + * During system suspend or hibernation, tasks are frozen and all + * CPUs are being taken offline. Allow offlining to proceed so + * suspend is not aborted. + */ + if (cpuhp_tasks_frozen) + return true; + + /* + * If the CPU being offlined is not a housekeeping CPU, + * offlining it will not strand isolated CPUs. Allow it. + */ + if (!cpumask_test_cpu(this_cpu, hk_mask)) + return true; + /* + * If this CPU is not mapped to this specific hardware context, + * offlining it will not affect the context's I/O routing. Allow it. + */ + if (blk_mq_map_queue_type(hctx->queue, hctx->type, this_cpu) !=3D hctx) + return true; + /* + * Iterate over all online CPUs and manually check their mapping. + * We cannot use hctx->cpumask here because blk_mq_map_swqueue() + * intentionally strips isolated CPUs from it to prevent kworker + * routing. + */ + for_each_online_cpu(cpu) { + struct blk_mq_hw_ctx *h; + + if (cpu =3D=3D this_cpu) + continue; + + h =3D blk_mq_map_queue_type(hctx->queue, hctx->type, cpu); + if (h !=3D hctx) + continue; + + if (cpumask_test_cpu(cpu, hk_mask)) + return true; + + if (fallback_isolated_cpu =3D=3D -1) + fallback_isolated_cpu =3D cpu; + } + + if (fallback_isolated_cpu !=3D -1) { + pr_warn("blk-mq: cannot offline CPU %u: online isolated CPU %d is still = mapped to hctx%u\n", + this_cpu, fallback_isolated_cpu, hctx->queue_num); + return false; + } + + return true; +} + static bool blk_mq_hctx_has_online_cpu(struct blk_mq_hw_ctx *hctx, unsigned int this_cpu) { @@ -3722,6 +3780,11 @@ static int blk_mq_hctx_notify_offline(unsigned int c= pu, struct hlist_node *node) struct blk_mq_hw_ctx, cpuhp_online); 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Thu, 10 Sep 2026 16:43:20 +0000 Received: from CWLP123MB6607.GBRP123.PROD.OUTLOOK.COM ([fe80::cec4:77ab:262e:d230]) by CWLP123MB6607.GBRP123.PROD.OUTLOOK.COM ([fe80::cec4:77ab:262e:d230%4]) with mapi id 15.21.0406.007; Thu, 10 Sep 2026 16:43:19 +0000 From: Aaron Tomlin To: axboe@kernel.dk, tglx@kernel.org, aacraid@microsemi.com, James.Bottomley@HansenPartnership.com, mkp@kernel.org, frederic@kernel.org, bigeasy@linutronix.de Cc: atomlin@atomlin.com, ionut.nechita@windriver.com, corbet@lwn.net, vincent.guittot@linaro.org, mingo@redhat.com, peterz@infradead.org, radu@rendec.net, akpm@linux-foundation.org, steve@abita.co, sean@ashe.io, chjohnst@gmail.com, neelx@suse.com, mproche@gmail.com, nick.lange@gmail.com, marco.crivellari@suse.com, rishil1999@outlook.com, linux-doc@vger.kernel.org, linux-block@vger.kernel.org, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v16 8/9] genirq/affinity: Restrict managed IRQ affinity to housekeeping CPUs Date: Thu, 10 Sep 2026 12:42:36 -0400 Message-ID: <20260910164237.500196-9-atomlin@atomlin.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910164237.500196-1-atomlin@atomlin.com> References: <20260910164237.500196-1-atomlin@atomlin.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BN9PR03CA0746.namprd03.prod.outlook.com (2603:10b6:408:110::31) To CWLP123MB6607.GBRP123.PROD.OUTLOOK.COM (2603:10a6:400:183::5) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CWLP123MB6607:EE_|CWLP123MB4179:EE_ X-MS-Office365-Filtering-Correlation-Id: 03d92886-fc9d-4831-bc7a-08df0f5a9ecb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|23010399003|366016|10067099003|56012099006|6133799003|3023799007|18002099003|22082099003; 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charset="utf-8" At present, the managed interrupt spreading algorithm distributes vectors across all available CPUs within a given node or system. On systems employing CPU isolation (e.g. "isolcpus=3Dmanaged_irq_strict"), this behaviour defeats the primary purpose of isolation by routing hardware interrupts (such as NVMe completion queues) directly to isolated cores. Update irq_create_affinity_masks() to respect the housekeeping CPU mask. By passing the HK_TYPE_MANAGED_IRQ_STRICT mask directly to the topological distribution function (group_mask_cpus_evenly()), we ensure that managed interrupts are kept strictly off isolated CPUs. This patch additionally addresses the architectural constraints of restricted vector distribution: 1. Vector limits and multi-set scaling Updated irq_calc_affinity_vectors() to bound the maximum number of allocated vectors to the weight of the housekeeping mask for single-set drivers. For drivers providing a calc_sets() callback, vector calculations continue to scale with the driver's requested set sizes (maxvec - resv), preventing unnecessary queue contention across distinct functional sets while irq_create_affinity_masks() guarantees that all allocated vectors remain strictly restricted to housekeeping CPUs. 2. Multi-set alignment and leak prevention When isolation constraints result in fewer available masks than requested vectors for a given set, the remaining vector slots are padded with the housekeeping mask. This replaces the historical irq_default_affinity padding, ensuring excess managed queues do not leak interrupts onto isolated CPUs. 3. Minimum vector safety net To prevent fatal -ENOSPC device probe aborts on heavily isolated systems (where the housekeeping CPU count might be lower than a device's structural minimum), the final vector calculation is safeguarded to never drop below minvec. Queues will safely share the available housekeeping CPUs instead of failing the probe. 4. Zero overhead The housekeeping mask is conditionally assigned via a direct pointer, completely avoiding temporary mask allocations (e.g. alloc_cpumask_var) and bitwise operations when CPU isolation is disabled. This guarantees zero performance or memory overhead for standard configurations. Signed-off-by: Aaron Tomlin Tested-by: Ionut Nechita --- kernel/irq/affinity.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/kernel/irq/affinity.c b/kernel/irq/affinity.c index 78f2418a8925..7796882a567a 100644 --- a/kernel/irq/affinity.c +++ b/kernel/irq/affinity.c @@ -8,6 +8,7 @@ #include #include #include +#include =20 static void default_calc_sets(struct irq_affinity *affd, unsigned int affv= ecs) { @@ -25,8 +26,10 @@ static void default_calc_sets(struct irq_affinity *affd,= unsigned int affvecs) struct irq_affinity_desc * irq_create_affinity_masks(unsigned int nvecs, struct irq_affinity *affd) { - unsigned int affvecs, curvec, usedvecs, i; + unsigned int affvecs, curvec, usedvecs, i, j; struct irq_affinity_desc *masks =3D NULL; + const struct cpumask *hk_mask =3D housekeeping_cpumask(HK_TYPE_MANAGED_IR= Q_STRICT); + bool hk_enabled =3D housekeeping_enabled(HK_TYPE_MANAGED_IRQ_STRICT); =20 /* * Determine the number of vectors which need interrupt affinities @@ -70,19 +73,29 @@ irq_create_affinity_masks(unsigned int nvecs, struct ir= q_affinity *affd) */ for (i =3D 0, usedvecs =3D 0; i < affd->nr_sets; i++) { unsigned int nr_masks, this_vecs =3D affd->set_size[i]; - struct cpumask *result =3D group_cpus_evenly(this_vecs, &nr_masks); + struct cpumask *result; + const struct cpumask *mask; =20 + if (hk_enabled) + mask =3D hk_mask; + else + mask =3D cpu_possible_mask; + + result =3D group_mask_cpus_evenly(this_vecs, mask, + &nr_masks); if (!result) { kfree(masks); return NULL; } - - for (int j =3D 0; j < nr_masks; j++) + for (j =3D 0; j < nr_masks; j++) cpumask_copy(&masks[curvec + j].mask, &result[j]); + for (j =3D nr_masks; j < this_vecs; j++) + cpumask_copy(&masks[curvec + j].mask, mask); + kfree(result); =20 - curvec +=3D nr_masks; - usedvecs +=3D nr_masks; + curvec +=3D this_vecs; + usedvecs +=3D this_vecs; } =20 /* Fill out vectors at the end that don't need affinity */ @@ -117,8 +130,10 @@ unsigned int irq_calc_affinity_vectors(unsigned int mi= nvec, unsigned int maxvec, =20 if (affd->calc_sets) set_vecs =3D maxvec - resv; + else if (housekeeping_enabled(HK_TYPE_MANAGED_IRQ_STRICT)) + set_vecs =3D cpumask_weight(housekeeping_cpumask(HK_TYPE_MANAGED_IRQ_STR= ICT)); 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charset="utf-8" From: Daniel Wagner The managed_irq_strict flag informs multiqueue device drivers where to place hardware queues and managed interrupt vectors. Document this new flag in the isolcpus command-line argument description, describe its relationship and precedence with respect to the legacy managed_irq flag, and document HK_TYPE_MANAGED_IRQ_STRICT in the core housekeeping guide. Signed-off-by: Daniel Wagner Reviewed-by: Hannes Reinecke Co-developed-by: Aaron Tomlin Signed-off-by: Aaron Tomlin Tested-by: Ionut Nechita --- .../admin-guide/kernel-parameters.txt | 37 ++++++++++++++++++- Documentation/core-api/housekeeping.rst | 6 ++- 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 68647ff4bdd2..eb608e5139a6 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2822,7 +2822,6 @@ Kernel parameters "number of CPUs in system - 1". =20 managed_irq - Isolate from being targeted by managed interrupts which have an interrupt mask containing isolated CPUs. The affinity of managed interrupts is @@ -2845,6 +2844,42 @@ Kernel parameters housekeeping CPUs has no influence on those queues. =20 + managed_irq_strict + Strictly restrict multiqueue hardware queue + allocation and managed interrupt affinity to + housekeeping CPUs. Unlike the best-effort + managed_irq flag, this option guarantees that + managed interrupts and multiqueue block device + queues are never created for or mapped to isolated + CPUs. + + In the block layer (blk-mq), device queue allocation + and CPU-to-queue mappings are restricted to + housekeeping CPUs. For devices using managed + interrupts, hardware completion interrupts are routed + exclusively to housekeeping cores, shielding isolated + CPUs from I/O interruptions even if they initiated the + request. + + If both managed_irq and managed_irq_strict are + specified, managed_irq_strict takes precedence. + + Note: Using managed_irq_strict restricts the number + of allocated hardware queues to match the number of + housekeeping CPUs for single-set drivers. This + prevents MSI-X vector exhaustion and forces isolated + CPUs to share submission queues. + + Note: Offlining housekeeping CPUs which serve + isolated CPUs will fail. The isolated CPUs must + be offlined before offlining the housekeeping + CPUs. + + Note: When I/O is submitted by an application on + an isolated CPU, the hardware completion + interrupt is handled entirely by a housekeeping + CPU. + The format of is described above. =20 iucv=3D [HW,NET] diff --git a/Documentation/core-api/housekeeping.rst b/Documentation/core-a= pi/housekeeping.rst index ccb0a88b9cb3..6d08c71e6c0e 100644 --- a/Documentation/core-api/housekeeping.rst +++ b/Documentation/core-api/housekeeping.rst @@ -23,7 +23,7 @@ CPU. It is simply a CPU that can execute housekeeping wor= k. There must always be at least one online housekeeping CPU at any time. The CPUs that are not isolated are automatically assigned as housekeeping. =20 -Housekeeping is currently divided in four features described +Housekeeping is currently divided in five features described by the ``enum hk_type type``: =20 1. HK_TYPE_DOMAIN matches the work moved away by scheduler domain @@ -44,6 +44,10 @@ by the ``enum hk_type type``: to HK_TYPE_DOMAIN except it ignores the isolation performed by cpusets. =20 +5. HK_TYPE_MANAGED_IRQ_STRICT matches the multiqueue block devices and + managed IRQs strictly restricted to housekeeping CPUs through + ``isolcpus=3Dmanaged_irq_strict``. + =20 Housekeeping cpumasks =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.55.0