From nobody Fri Sep 25 16:02:15 2026 Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ABA049DBBD for ; Thu, 10 Sep 2026 14:27:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789050424; cv=none; b=dmpUHv9iGyWTwegd1N1spzy01O+ewRiaGuvQCHYnidEjliHHAx81gfw4eIJ6yudyQtKL6yYgc/OBA308qJ7I3O176dBa2vA4NP0cZesEU7EKL7lrCZGG0SxNIkrhZCEBHqL2G4b3/BPuhIHO9QTGhhHNH4yOhOIBG4969N1rRXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789050424; c=relaxed/simple; bh=Uf1Mg8lC343lrJXvoIgHa/B0FLZkPDMfcU2FIL1W/tU=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=tYOswQ/gNkP36OMx1A9+bWcPoLxWBb1TdbtvvSdJ7WsyEG+rh2ubd9O2l/fuNpeLX1kajbrbilIzDjke+6T8CYRi8rZehC/Cl8TmAgZQnhjRopj/FxHC7D199nAsUh3MV75OeQTARTBrI57rYl4yVHAVKnHqkmmonBTvpojXE4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--praan.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=eSTWOUE9; arc=none smtp.client-ip=209.85.214.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--praan.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="eSTWOUE9" Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2db8c152622so26485545ad.2 for ; Thu, 10 Sep 2026 07:27:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1789050420; x=1789655220; darn=vger.kernel.org; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:from:to:cc:subject:date:message-id:reply-to :content-type; bh=VsODB2LlW2OUQJwkogRDDD6IthNc90JrH7J5IUx28AQ=; b=eSTWOUE9FGatUskMo+/4U9RiWsprBbNBPyEZsI9iygxHZixe5LncK/zPgclCeJYBhD YlZBeJ2NVmv9jgqz8fmle2gvUjMjehUCSjwTEz+F+UX980Dnbayn5ztqhJSc0bcXJaNP HEBbahlGTySFinFWe8zlzQ6wDf/OrkrzVy6zv1xTYn/WKj6+ln7qq0IG1JDwLzi4Ze3W iiJRxLPIf0IqTmHtRAjZdRNv8kvi2I36V0GlmMXQohNvfeAh40O+S2HlSDVpmS0UDiwV 1M/DPbuVmmPCrPa4OR79oitRlvaUR19LleRzSiMmnrrQ5Rt23jDq5SLl3Agr3TtRHlu2 HVQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1789050420; x=1789655220; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=VsODB2LlW2OUQJwkogRDDD6IthNc90JrH7J5IUx28AQ=; b=JAoZePjH/pNDVGmnmK3rD6AvmWihbliz+TySYLEYWGIXZroSAnS3yQe4etyss2nOA5 j1zPI+WIC4vO1xy6LOXIDOCY0dVLe4vCFRtOCBayLJlclUkPQVl2zucx9Woeez+MjvOI xUr2Q8HJnQddNCoHKNciUUwyc8XsAE1gtslVJa11SBQUFdq7XYyYDm3CMlerOy8j19b8 Woh4FTvErq3dqBDvgISUJ9RTkRaEZp5p6iMxyZ6cM1eQzrS/bUPLOb+PVHuTS571BSTX J3Jhli2Imy5tS+cka9SgpREFMiMe1XJsQADDIOTz2yrWC44yU8UR/1xa/+xaIf9SIMZy 183w== X-Forwarded-Encrypted: i=1; AKwUvBzCdfLdhfNIY2BnV7S416mzdw5ZQGfzPJXsFPZ9ReT+OiQlBWGsRS9MG3RFls67xKX6g/VXnfSmvNfCehA=@vger.kernel.org X-Gm-Message-State: AFuF++lThWuwvFF4rpjKZUZo7CbuiKAxi4Ih9lzbkPyEreEAO8Yb5Jnq /2YisJI/gdfoHgKzdXnVhY5qNU2R9l3Q+VqRvPr44psKiW5aWqqZ+X7fHcYSRtMrX/EpuWiptaG dlQ== X-Received: from pgbd26-n2.prod.google.com ([2002:a05:6a02:64da:20b0:cbe:efab:fa5a]) (user=praan job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:4310:b0:3d3:adbf:777c with SMTP id adf61e73a8af0-3da3a0b7121mr62384226637.24.1789050420087; Thu, 10 Sep 2026 07:27:00 -0700 (PDT) Date: Thu, 10 Sep 2026 14:26:52 +0000 In-Reply-To: <20260910142655.3281464-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260910142655.3281464-1-praan@google.com> X-Mailer: git-send-email 2.55.0.1003.g10538fe699-goog Message-ID: <20260910142655.3281464-2-praan@google.com> Subject: [PATCH v4 1/4] iommu/amd: Refactor device probe and capability initialization From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Suravee Suthikulpanit , Vasant Hegde , Ankit Soni , Jason Gunthorpe , Bjorn Helgaas , Samiullah Khawaja , Pranjal Shrivastava Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Restructure the device probe path to improve readability and prepare for cleaner error handling. Refactor check_device() into lookup_device to explicitly validate and return the amd_iommu ptr & devid. Refactor iommu_init_device() to return the allocated dev_data. Consolidate all PCI cap inits (MSI domains, PASID, ATS) into a new helper: iommu_init_device_caps(). Suggested-by: Vasant Hegde Reviewed-by: Jason Gunthorpe Reviewed-by: Vasant Hegde Signed-off-by: Pranjal Shrivastava --- drivers/iommu/amd/iommu.c | 117 +++++++++++++++++++------------------- 1 file changed, 59 insertions(+), 58 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4dc306a4b5c6..5e144a60c397 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -675,7 +675,8 @@ static void pdev_disable_caps(struct pci_dev *pdev) * This function checks if the driver got a valid device from the caller to * avoid dereferencing invalid pointers. */ -static bool check_device(struct device *dev) +static bool lookup_device(struct device *dev, + struct amd_iommu **iommu_out, u16 *devid_out) { struct amd_iommu_pci_seg *pci_seg; struct amd_iommu *iommu; @@ -690,7 +691,7 @@ static bool check_device(struct device *dev) devid =3D PCI_SBDF_TO_DEVID(sbdf); =20 iommu =3D rlookup_amd_iommu(dev); - if (!iommu) + if (!iommu || !iommu->iommu.ops) return false; =20 /* Out of our scope? */ @@ -698,47 +699,33 @@ static bool check_device(struct device *dev) if (devid > pci_seg->last_bdf) return false; =20 + *iommu_out =3D iommu; + *devid_out =3D devid; return true; } =20 -static int iommu_init_device(struct amd_iommu *iommu, struct device *dev) +static struct iommu_dev_data *iommu_init_device(struct amd_iommu *iommu, + struct device *dev, u16 devid) { struct iommu_dev_data *dev_data; - int devid, sbdf; - - if (dev_iommu_priv_get(dev)) - return 0; =20 - sbdf =3D get_device_sbdf_id(dev); - if (sbdf < 0) - return sbdf; - - devid =3D PCI_SBDF_TO_DEVID(sbdf); dev_data =3D find_dev_data(iommu, devid); if (!dev_data) - return -ENOMEM; + return ERR_PTR(-ENOMEM); =20 dev_data->dev =3D dev; =20 /* - * The dev_iommu_priv_set() needes to be called before setup_aliases. + * The dev_iommu_priv_set() needs to be called before setup_aliases. * Otherwise, subsequent call to dev_iommu_priv_get() will fail. */ dev_iommu_priv_set(dev, dev_data); setup_aliases(iommu, dev); =20 - /* - * By default we use passthrough mode for IOMMUv2 capable device. - * But if amd_iommu=3Dforce_isolation is set (e.g. to debug DMA to - * invalid address), we ignore the capability for the device so - * it'll be forced to go into translation mode. - */ - if ((iommu_default_passthrough() || !amd_iommu_force_isolation) && - dev_is_pci(dev) && amd_iommu_gt_ppr_supported()) { - dev_data->flags =3D pdev_get_caps(to_pci_dev(dev)); - } + /* Wait for DTE updates to go through */ + iommu_completion_wait(iommu); =20 - return 0; + return dev_data; } =20 static void iommu_ignore_device(struct amd_iommu *iommu, struct device *de= v) @@ -2487,49 +2474,73 @@ static void detach_device(struct device *dev) mutex_unlock(&dev_data->mutex); } =20 +static void iommu_init_device_caps(struct iommu_dev_data *dev_data, + struct device *dev, + struct amd_iommu *iommu) +{ + if (FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2)) + dev_data->max_irqs =3D MAX_IRQS_PER_TABLE_2K; + else + dev_data->max_irqs =3D MAX_IRQS_PER_TABLE_512; + + amd_iommu_set_pci_msi_domain(dev, iommu); + + if (!dev_is_pci(dev)) + return; + + /* + * By default we use passthrough mode for IOMMUv2 capable device. + * But if amd_iommu=3Dforce_isolation is set (e.g. to debug DMA to + * invalid address), we ignore the capability for the device so + * it'll be forced to go into translation mode. + */ + if ((iommu_default_passthrough() || !amd_iommu_force_isolation) && + amd_iommu_gt_ppr_supported()) { + dev_data->flags =3D pdev_get_caps(to_pci_dev(dev)); + } + + /* + * If IOMMU and device supports PASID then it will contain max + * supported PASIDs, else it will be zero. + */ + if (amd_iommu_pasid_supported() && + pdev_pasid_supported(dev_data)) { + dev_data->max_pasids =3D min_t(u32, iommu->iommu.max_pasids, + pci_max_pasids(to_pci_dev(dev))); + } + + pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT); +} + static struct iommu_device *amd_iommu_probe_device(struct device *dev) { struct iommu_device *iommu_dev; struct amd_iommu *iommu; struct iommu_dev_data *dev_data; - int ret; - - if (!check_device(dev)) - return ERR_PTR(-ENODEV); - - iommu =3D rlookup_amd_iommu(dev); - if (!iommu) - return ERR_PTR(-ENODEV); + u16 devid; =20 - /* Not registered yet? */ - if (!iommu->iommu.ops) + if (!lookup_device(dev, &iommu, &devid)) return ERR_PTR(-ENODEV); =20 if (dev_iommu_priv_get(dev)) return &iommu->iommu; =20 - ret =3D iommu_init_device(iommu, dev); - if (ret) { + dev_data =3D iommu_init_device(iommu, dev, devid); + if (IS_ERR(dev_data)) { dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); - iommu_dev =3D ERR_PTR(ret); + iommu_dev =3D ERR_CAST(dev_data); iommu_ignore_device(iommu, dev); goto out_err; } =20 - amd_iommu_set_pci_msi_domain(dev, iommu); + iommu_init_device_caps(dev_data, dev, iommu); iommu_dev =3D &iommu->iommu; =20 /* - * If IOMMU and device supports PASID then it will contain max - * supported PASIDs, else it will be zero. + * When DMA translation is unavailable return error so the iommu core + * won't attempt domain attach for this device, while preserving its + * rlookup entry for interrupt remapping. */ - dev_data =3D dev_iommu_priv_get(dev); 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Thu, 10 Sep 2026 07:27:05 -0700 (PDT) Date: Thu, 10 Sep 2026 14:26:53 +0000 In-Reply-To: <20260910142655.3281464-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260910142655.3281464-1-praan@google.com> X-Mailer: git-send-email 2.55.0.1003.g10538fe699-goog Message-ID: <20260910142655.3281464-3-praan@google.com> Subject: [PATCH v4 2/4] iommu/amd: Remove iommu_ignore_device() From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Suravee Suthikulpanit , Vasant Hegde , Ankit Soni , Jason Gunthorpe , Bjorn Helgaas , Samiullah Khawaja , Pranjal Shrivastava , sashiko-bot@kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The iommu_ignore_device() helper was historically called on device initialization failure to clear the primary Device Table Entry (DTE) via memset() and nullify the rlookup_table entry. However, clearing the DTE on probe failure is problematic: 1. During normal boot, DTEs start out unconfigured (blocking DMA), making clearing redundant. 2. During kdump boot, pre-existing translations should be kept running until deferred attach rather than abruptly clearing them, which risks breaking in-flight transfers. 3. Writing to the DTE table via memset without flushing the hardware DTE cache risks aliasing & torn writes. 4. Clearing the rlookup_table entry breaks interrupt remapping for devices that fail probe or operate in translation-less modes. Remove iommu_ignore_device() entirely and simplify the error return paths in amd_iommu_probe_device(). Suggested-by: Jason Gunthorpe Suggested-by: Vasant Hegde Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/all/20260529153216.2AD1E1F00899@smtp.kernel= .org/ Signed-off-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe Reviewed-by: Vasant Hegde --- drivers/iommu/amd/iommu.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 5e144a60c397..7f8b51c28a7e 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -728,22 +728,6 @@ static struct iommu_dev_data *iommu_init_device(struct= amd_iommu *iommu, return dev_data; } =20 -static void iommu_ignore_device(struct amd_iommu *iommu, struct device *de= v) -{ - struct amd_iommu_pci_seg *pci_seg =3D iommu->pci_seg; - struct dev_table_entry *dev_table =3D get_dev_table(iommu); - int devid, sbdf; - - sbdf =3D get_device_sbdf_id(dev); - if (sbdf < 0) - return; - - devid =3D PCI_SBDF_TO_DEVID(sbdf); - pci_seg->rlookup_table[devid] =3D NULL; - memset(&dev_table[devid], 0, sizeof(struct dev_table_entry)); - - setup_aliases(iommu, dev); -} =20 =20 /*************************************************************************= *** @@ -2528,9 +2512,7 @@ static struct iommu_device *amd_iommu_probe_device(st= ruct device *dev) dev_data =3D iommu_init_device(iommu, dev, devid); if (IS_ERR(dev_data)) { dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); - iommu_dev =3D ERR_CAST(dev_data); - iommu_ignore_device(iommu, dev); - goto out_err; + return ERR_CAST(dev_data); } =20 iommu_init_device_caps(dev_data, dev, iommu); @@ -2544,11 +2526,9 @@ static struct iommu_device *amd_iommu_probe_device(s= truct device *dev) if (amd_iommu_pgtable =3D=3D PD_MODE_NONE) { pr_warn_once("%s: DMA translation not supported by iommu.\n", __func__); - iommu_dev =3D ERR_PTR(-ENODEV); - goto out_err; + return ERR_PTR(-ENODEV); } =20 -out_err: return iommu_dev; } =20 --=20 2.55.0.1003.g10538fe699-goog From nobody Fri Sep 25 16:02:15 2026 Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7C944A1DE0 for ; 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Thu, 10 Sep 2026 07:27:07 -0700 (PDT) Date: Thu, 10 Sep 2026 14:26:54 +0000 In-Reply-To: <20260910142655.3281464-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260910142655.3281464-1-praan@google.com> X-Mailer: git-send-email 2.55.0.1003.g10538fe699-goog Message-ID: <20260910142655.3281464-4-praan@google.com> Subject: [PATCH v4 3/4] iommu/amd: Fail probe on ATS configuration failure From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Suravee Suthikulpanit , Vasant Hegde , Ankit Soni , Jason Gunthorpe , Bjorn Helgaas , Samiullah Khawaja , Pranjal Shrivastava Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the driver to call pci_prepare_ats() after checking if pci_ats_supported() and fail the probe_device if pci_prepare_ats() returns an error. Additionally, update pdev_enable_cap_ats() to WARN_ON() a failure in pci_enable_ats(). Reviewed-by: Vasant Hegde Reviewed-by: Jason Gunthorpe Reviewed-by: Samiullah Khawaja Signed-off-by: Pranjal Shrivastava --- drivers/iommu/amd/iommu.c | 39 +++++++++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 7f8b51c28a7e..195097365413 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -573,10 +573,17 @@ static inline int pdev_enable_cap_ats(struct pci_dev = *pdev) if (amd_iommu_iotlb_sup && (dev_data->flags & AMD_IOMMU_DEVICE_FLAG_ATS_SUP)) { ret =3D pci_enable_ats(pdev, PAGE_SHIFT); - if (!ret) { - dev_data->ats_enabled =3D 1; - dev_data->ats_qdep =3D pci_ats_queue_depth(pdev); - } + + /* + * pci_enable_ats() should not fail here because earlier + * checks have already verified support & config. + */ + if (WARN_ON(ret)) + return ret; + + dev_data->ats_enabled =3D 1; + dev_data->ats_qdep =3D pci_ats_queue_depth(pdev); + ret =3D 0; } =20 return ret; @@ -2458,10 +2465,12 @@ static void detach_device(struct device *dev) mutex_unlock(&dev_data->mutex); } =20 -static void iommu_init_device_caps(struct iommu_dev_data *dev_data, - struct device *dev, - struct amd_iommu *iommu) +static int iommu_init_device_caps(struct iommu_dev_data *dev_data, + struct device *dev, + struct amd_iommu *iommu) { + int ret; + if (FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2)) dev_data->max_irqs =3D MAX_IRQS_PER_TABLE_2K; else @@ -2470,7 +2479,7 @@ static void iommu_init_device_caps(struct iommu_dev_d= ata *dev_data, amd_iommu_set_pci_msi_domain(dev, iommu); =20 if (!dev_is_pci(dev)) - return; + return 0; =20 /* * By default we use passthrough mode for IOMMUv2 capable device. @@ -2493,7 +2502,13 @@ static void iommu_init_device_caps(struct iommu_dev_= data *dev_data, pci_max_pasids(to_pci_dev(dev))); } =20 - pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT); + if (pci_ats_supported(to_pci_dev(dev))) { + ret =3D pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT); + if (ret) + return ret; + } + + return 0; } =20 static struct iommu_device *amd_iommu_probe_device(struct device *dev) @@ -2502,6 +2517,7 @@ static struct iommu_device *amd_iommu_probe_device(st= ruct device *dev) struct amd_iommu *iommu; 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charset="utf-8" Currently, pci_prepare_ats() internally calls pci_ats_supported() and returns -EINVAL if the device does not support ATS. While this provides a silent safety check, it conflates support detection with configuration. Update pci_prepare_ats() to wrap the internal pci_ats_supported check in a WARN_ON(). This mandates all callers to call pci_prepare_ats() only if the function supports ATS. Update the function documentation to mention that callers must verify ATS support (via pci_ats_supported()) before calling pci_prepare_ats(). Reviewed-by: Vasant Hegde Suggested-by: Baolu Lu Reviewed-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Signed-off-by: Pranjal Shrivastava --- drivers/pci/ats.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 9cb23780093d..f1434f86ac40 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -56,7 +56,9 @@ EXPORT_SYMBOL_GPL(pci_ats_supported); * @ps: the IOMMU page shift * * This must be done by the IOMMU driver on the PF before any VFs are crea= ted to - * ensure that the VF can have ATS enabled. + * ensure that the VF can have ATS enabled. Callers must verify that ATS is + * supported by the device (e.g. via pci_ats_supported()) before calling t= his + * function. * * Returns 0 on success, or negative on failure. */ @@ -64,7 +66,7 @@ int pci_prepare_ats(struct pci_dev *dev, int ps) { u16 ctrl; =20 - if (!pci_ats_supported(dev)) + if (WARN_ON(!pci_ats_supported(dev))) return -EINVAL; =20 if (WARN_ON(dev->ats_enabled)) --=20 2.55.0.1003.g10538fe699-goog