From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 504823D9665; Thu, 10 Sep 2026 09:20:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032048; cv=none; b=F6QUIv5eiRlbHKSOCC90iiH/zsDrCVgfYY5Xhai2lIHYqXVqxZBelC6tB2OpxHDgZnm3aeHtYUHNm+KB78sDMhHFGReZV2yaskY0DqMZmlSeqX2QSRdmDYulUkvTpS0vXR/M4n06NZVRPvBsTZMbOO1tg6lxV+K9S28wEnh4pxI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032048; c=relaxed/simple; bh=3T1bI55DxPKUxrkKbaXUdzwvIf7IgcntNDx2QtDpXe8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qk/WIB2ow/lEgbU6Z35nWtzj1yHXdNi1nK/aBdV9UsGPDVjUY8VcwdBSpQUlbosCsVxll60CmNjqnoxbQIQnCn7fvahK8FXLCHacBfCb8ZvHSwt6Wcoww2dEsOtAyUtAltiRHYrWiTebRA0vRFvxtwGhtbNqTRSu7xqzf1gCBYk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=C4oj1QqG; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="C4oj1QqG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789032043; bh=3T1bI55DxPKUxrkKbaXUdzwvIf7IgcntNDx2QtDpXe8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C4oj1QqGfpW70EK+8nkaMyUbjYlaYjaM0XyaSUVOc51wD+Y8B0dhQDfJpqNbL65n4 L0+tXVYa8lB9ZSm5YslAhr3INTzLcruGD7eo/e+WKd5t1VTwjLgDFRa1zZuATN84qb 75WwwwzRXGBD1pXhlVj6uYfvv+Qg7O2q9QfTw3WtWyF1ZQGsqsGJU5Hk55mgP/oANH ojXC/dxgTy7ohJsR+x+DmLwZbwHguNY7+3YvENzE+gZK00Cr5PqicbPTk90xyleZGC 3JsQ+JTdop5tliS3lNmdyvtEvI+XnoTIiO8lVYVWqTeoI1BIpyRPgHaLXUmpK+7Qxe UIgMa7LSUZ/GA== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id A523117E0945; Thu, 10 Sep 2026 11:20:42 +0200 (CEST) From: AngeloGioacchino Del Regno To: mani@kernel.org Cc: chunfeng.yun@mediatek.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, justin.yeh@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com, Krzysztof Kozlowski , Manivannan Sadhasivam Subject: [PATCH v4 01/12] dt-bindings: phy: Document MT8195 and MT8196 DisplayPort PHYs Date: Thu, 10 Sep 2026 11:20:27 +0200 Message-ID: <20260910092038.48291-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> References: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds bindings for the DisplayPort and Embedded DisplayPort PHYs found in the MediaTek MT8195 SoC (and variants of) and for the Embedded DisplayPort found in the MT8196 SoC (and variants). This PHY supports varying impedance calibrations for the various signals to reach an optimal EYE signal pattern for any specific board(s), especially useful for very high bitrates such as HBR3 and higher, depending on board design. Reviewed-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/phy/mediatek,mt8195-dp-phy.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt8195-d= p-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt8195-dp-phy.y= aml b/Documentation/devicetree/bindings/phy/mediatek,mt8195-dp-phy.yaml new file mode 100644 index 000000000000..1c2dc4f03cd6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,mt8195-dp-phy.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,mt8195-dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC DisplayPort Transmitter PHY + +maintainers: + - AngeloGioacchino Del Regno + +properties: + compatible: + enum: + - mediatek,mt8195-dp-phy + - mediatek,mt8196-edp-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + nvmem-cells: + description: PHY calibrations from eFuse for optimal EYE signal pattern + items: + - description: PHY-Global Reference Bias trim + - description: PHY-Global AUX Transmitter clock impedance adjustment + - description: Lane 0 Transmitter impedance selection (P-MOSFET) + - description: Lane 0 Transmitter impedance selection (N-MOSFET) + - description: Lane 1 Transmitter impedance selection (P-MOSFET) + - description: Lane 1 Transmitter impedance selection (N-MOSFET) + - description: Lane 2 Transmitter impedance selection (P-MOSFET) + - description: Lane 2 Transmitter impedance selection (N-MOSFET) + - description: Lane 3 Transmitter impedance selection (P-MOSFET) + - description: Lane 3 Transmitter impedance selection (N-MOSFET) + + nvmem-cell-names: + items: + - const: rbias-trim + - const: impedance-txclk + - const: impedance-lane0p + - const: impedance-lane0n + - const: impedance-lane1p + - const: impedance-lane1n + - const: impedance-lane2p + - const: impedance-lane2n + - const: impedance-lane3p + - const: impedance-lane3n + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@1c500000 { + compatible =3D "mediatek,mt8195-dp-phy"; + reg =3D <0x1c500000 0x2000>; + #phy-cells =3D <0>; + nvmem-cells =3D <&edp_glb_bias_trim>, <&edp_clktx_impsel>, + <&edp_imp_ln0_pmos>, <&edp_imp_ln0_nmos>, + <&edp_imp_ln1_pmos>, <&edp_imp_ln1_nmos>, + <&edp_imp_ln2_pmos>, <&edp_imp_ln2_nmos>, + <&edp_imp_ln3_pmos>, <&edp_imp_ln3_nmos>; + nvmem-cell-names =3D "rbias-trim", "impedance-txclk", + "impedance-lane0p", "impedance-lane0n", + "impedance-lane1p", "impedance-lane1n", + "impedance-lane2p", "impedance-lane2n", + "impedance-lane3p", "impedance-lane3n"; + }; --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 335DF3DCDB1; Thu, 10 Sep 2026 09:20:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 10 Sep 2026 11:20:43 +0200 (CEST) From: AngeloGioacchino Del Regno To: mani@kernel.org Cc: chunfeng.yun@mediatek.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, justin.yeh@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com, Manivannan Sadhasivam Subject: [PATCH v4 02/12] phy: phy-mtk-dp: Rename regs to regmap in struct mtk_dp_phy Date: Thu, 10 Sep 2026 11:20:28 +0200 Message-ID: <20260910092038.48291-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> References: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation to perform further cleanups and to extend the driver to support more SoCs, rename the `regs` member to `regmap` to improve readability, as this is a common name across many kernel drivers for a struct regmap. Reviewed-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-dp.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index d7024a144335..bf7b3a95e72d 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -79,7 +79,7 @@ XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) =20 struct mtk_dp_phy { - struct regmap *regs; + struct regmap *regmap; }; =20 static int mtk_dp_phy_init(struct phy *phy) @@ -94,13 +94,13 @@ static int mtk_dp_phy_init(struct phy *phy) DRIVING_PARAM_8_DEFAULT }; =20 - regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, + regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE0_DRIVING_PARAM_3, driving_params, ARRAY_SIZE(driving_params)); - regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, + regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE1_DRIVING_PARAM_3, driving_params, ARRAY_SIZE(driving_params)); - regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, + regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE2_DRIVING_PARAM_3, driving_params, ARRAY_SIZE(driving_params)); - regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, + regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE3_DRIVING_PARAM_3, driving_params, ARRAY_SIZE(driving_params)); =20 return 0; @@ -131,10 +131,10 @@ static int mtk_dp_phy_configure(struct phy *phy, unio= n phy_configure_opts *opts) val =3D BIT_RATE_HBR3; break; } - regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); + regmap_write(dp_phy->regmap, MTK_DP_PHY_DIG_BIT_RATE, val); } =20 - regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1, + regmap_update_bits(dp_phy->regmap, MTK_DP_PHY_DIG_PLL_CTL_1, TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); =20 return 0; @@ -144,10 +144,10 @@ static int mtk_dp_phy_reset(struct phy *phy) { struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); =20 - regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, + regmap_update_bits(dp_phy->regmap, MTK_DP_PHY_DIG_SW_RST, DP_GLB_SW_RST_PHYD, 0); usleep_range(50, 200); - regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, + regmap_update_bits(dp_phy->regmap, MTK_DP_PHY_DIG_SW_RST, DP_GLB_SW_RST_PHYD, 1); =20 return 0; @@ -176,7 +176,7 @@ static int mtk_dp_phy_probe(struct platform_device *pde= v) if (!dp_phy) return -ENOMEM; =20 - dp_phy->regs =3D regs; + dp_phy->regmap =3D regs; phy =3D devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops); if (IS_ERR(phy)) return dev_err_probe(dev, PTR_ERR(phy), --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69FE33DDAFA; Thu, 10 Sep 2026 09:20:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032049; cv=none; b=u01qTrHLJHNAM6ZE19p2syIFGaeVpF7kyYl37BybmvY67JP+wi/66vtcLKH4kgwmLZ4i8nrFt0o/UH3KDHD2XsbifndcMBa0tRTBY66V1AHxhF5nVgDTwo1LrAyXLMgtgdQnTfzMRojm1IZ40K+OO93ij026dLapPvGX1XnF6wE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032049; c=relaxed/simple; bh=HAFCIlvbN2dc3YOTNS3f1xU94js5Nu7PxNVA7m6vO/4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CjT0bbJP2qjGYVcZAbFhWQnsT3WfYYHw6KVts2uWlnEFyPLLqJUSlQd8uQ8Gyd3mfpY611c5SlbPGtXyRJXXscZJZgwcuVyWi1xBdJYyv0r25HEVWq088u4s4/bpXCPub3DleMCRei/tuTwbPkTBHeYBR40meAJzcrNZeEPGfC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=EhwJKaD3; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="EhwJKaD3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789032045; bh=HAFCIlvbN2dc3YOTNS3f1xU94js5Nu7PxNVA7m6vO/4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EhwJKaD3Rg79euKBLroowzkjFZJzVpn+qftHHTJX4VDRc87gY6vZnGmqLEO9LPkN6 /NrEYTGL/9TI3YfrZCgJzPkWP1j8fpkuSej9QcmMUrRLurwlELYj2XobEa3YKTUTC2 TvK+F0yanH2bcD6n56zfhjFFbtCT8u9DrReuWcMRpoUEm6gQdRbQQ/jpxDVMIXB/FQ wbrvcK4DKwXc7kIsH9IMiLFZ6fGzrOiZBuZwnzOfF07WJtdS09CYACsXuH0XOzpMgI 7ak6EWpegTnxWscT9Dx38a7cmYe/UcqNiTfkPnt9NSqFY0bqK8lwKPmf/r9Erud/k0 cqH2EiJpyCzdA== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7F6F817E0D7F; Thu, 10 Sep 2026 11:20:44 +0200 (CEST) From: AngeloGioacchino Del Regno To: mani@kernel.org Cc: chunfeng.yun@mediatek.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, justin.yeh@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com, Manivannan Sadhasivam Subject: [PATCH v4 03/12] phy: phy-mtk-dp: Allow probing with devicetree match Date: Thu, 10 Sep 2026 11:20:29 +0200 Message-ID: <20260910092038.48291-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> References: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make it possible to decouple the registration of the DisplayPort PHY driver from the DisplayPort IP driver by adding a devicetree match to probe the PHY, registering an OF PHY provider and this device's own MMIO regmap - if, and only if, this PHY driver was registered with an OF match. In order to retain compatibility with older devicetrees that are not declaring the DisplayPort PHY as a separate node, the legacy code was moved in a `mtk_dp_phy_legacy_probe()` function, which gets called if the driver was registered by the DisplayPort one. Reviewed-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-dp.c | 88 +++++++++++++++++++++++++++---- 1 file changed, 78 insertions(+), 10 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index bf7b3a95e72d..d241004e2828 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -12,6 +12,7 @@ #include #include #include +#include #include =20 #define PHY_OFFSET 0x1000 @@ -79,6 +80,7 @@ XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) =20 struct mtk_dp_phy { + struct device *dev; struct regmap *regmap; }; =20 @@ -160,43 +162,109 @@ static const struct phy_ops mtk_dp_phy_dev_ops =3D { .owner =3D THIS_MODULE, }; =20 +static void mtk_dp_phy_legacy_remove_lookup(void *data) +{ + struct phy *phy =3D data; + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + + phy_remove_lookup(phy, "dp", dev_name(dp_phy->dev)); +} + +static int mtk_dp_phy_legacy_probe(struct platform_device *pdev, struct mt= k_dp_phy *dp_phy) +{ + struct device *dev =3D &pdev->dev; + struct phy *phy; + int ret; + + dp_phy->regmap =3D *(struct regmap **)dev->platform_data; + if (!dp_phy->regmap) + return dev_err_probe(dev, -EINVAL, "No platform data available\n"); + + phy =3D devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "Failed to create DP PHY\n"); + + phy_set_drvdata(phy, dp_phy); + ret =3D phy_create_lookup(phy, "dp", dev_name(dev)); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, mtk_dp_phy_legacy_remove_lookup, ph= y); + if (ret) + return ret; + + return 0; +} + +static const struct regmap_config mtk_dp_phy_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .disable_locking =3D true, +}; + static int mtk_dp_phy_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; + struct phy_provider *provider; struct mtk_dp_phy *dp_phy; + void __iomem *base; struct phy *phy; - struct regmap *regs; - - regs =3D *(struct regmap **)dev->platform_data; - if (!regs) - return dev_err_probe(dev, -EINVAL, - "No data passed, requires struct regmap**\n"); + int ret; =20 dp_phy =3D devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL); if (!dp_phy) return -ENOMEM; =20 - dp_phy->regmap =3D regs; + dp_phy->dev =3D dev; + + /* If there's no devicetree, go for legacy pdev probe */ + if (!dev->of_node) + return mtk_dp_phy_legacy_probe(pdev, dp_phy); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + dp_phy->regmap =3D devm_regmap_init_mmio(dev, base, &mtk_dp_phy_regmap_cf= g); + if (IS_ERR(dp_phy->regmap)) + return PTR_ERR(dp_phy->regmap); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + phy =3D devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops); if (IS_ERR(phy)) return dev_err_probe(dev, PTR_ERR(phy), "Failed to create DP PHY\n"); =20 phy_set_drvdata(phy, dp_phy); - if (!dev->of_node) - phy_create_lookup(phy, "dp", dev_name(dev)); + + provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(provider)) + return PTR_ERR(provider); =20 return 0; } =20 +static const struct of_device_id mtk_dp_phy_of_match[] =3D { + { .compatible =3D "mediatek,mt8195-dp-phy" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_dp_phy_of_match); + static struct platform_driver mtk_dp_phy_driver =3D { .probe =3D mtk_dp_phy_probe, .driver =3D { .name =3D "mediatek-dp-phy", + .of_match_table =3D mtk_dp_phy_of_match, }, }; module_platform_driver(mtk_dp_phy_driver); =20 +MODULE_AUTHOR("AngeloGioacchino Del Regno "); MODULE_AUTHOR("Markus Schneider-Pargmann "); -MODULE_DESCRIPTION("MediaTek DP PHY Driver"); +MODULE_DESCRIPTION("MediaTek DisplayPort PHY Driver"); MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50C9B3DDB0D; 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Thu, 10 Sep 2026 11:20:45 +0200 (CEST) From: AngeloGioacchino Del Regno To: mani@kernel.org Cc: chunfeng.yun@mediatek.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, justin.yeh@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com, Manivannan Sadhasivam Subject: [PATCH v4 04/12] phy: phy-mtk-dp: Migrate register offsets to SoC specific pdata Date: Thu, 10 Sep 2026 11:20:30 +0200 Message-ID: <20260910092038.48291-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> References: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for newer SoCs and for adding more capabilities to this driver in an efficient manner, migrate all of the hardcoded register offsets to SoC specific pdata and assign that for both DT and platform probing. While at it also cleanup writing the driving parameters to the PHY by iterating through all lanes with a loop instead: note that for that to happen the default 0/1/2 driving parameters were added, those are really just zero. Reviewed-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-dp.c | 145 ++++++++++++++++++++++++------ 1 file changed, 116 insertions(+), 29 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index d241004e2828..20974650d940 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -4,6 +4,10 @@ * * Copyright (c) 2022, BayLibre Inc. * Copyright (c) 2022, MediaTek Inc. + * + * Major refactoring + * Copyright (c) 2026, Collabora Ltd. + * AngeloGioacchino Del Regno */ =20 #include @@ -15,24 +19,29 @@ #include #include =20 -#define PHY_OFFSET 0x1000 +#define MTK_DP_PHY_MAX_LANES 4 =20 -#define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x14) +/* DP_PHYD_PLL_CTL_1 */ #define TPLL_SSC_EN BIT(3) =20 -#define MTK_DP_PHY_DIG_BIT_RATE (PHY_OFFSET + 0x3C) -#define BIT_RATE_RBR 0 -#define BIT_RATE_HBR 1 -#define BIT_RATE_HBR2 2 -#define BIT_RATE_HBR3 3 +/* DP_PHYD_BIT_RATE */ +#define PHYD_DIG_RG_BIT_RATE GENMASK(1, 0) +# define BIT_RATE_RBR 0 +# define BIT_RATE_HBR 1 +# define BIT_RATE_HBR2 2 +# define BIT_RATE_HBR3 3 + +/* DP_PHYD_SW_RST */ +#define PHYD_DIG_GLB_SW_RST_B GENMASK(7, 0) +# define DP_GLB_SW_RST_PHYD BIT(0) +# define DP_GLB_SW_RST_TFIFO_ANA BIT(1) +# define DP_GLB_SW_RST_XTAL_CLK BIT(2) +# define DP_GLB_SW_RST_MAIN_LINK BIT(3) =20 -#define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38) -#define DP_GLB_SW_RST_PHYD BIT(0) +#define DRIVING_PARAM_0_DEFAULT 0x0 +#define DRIVING_PARAM_1_DEFAULT 0x0 +#define DRIVING_PARAM_2_DEFAULT 0x0 =20 -#define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138) -#define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238) -#define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338) -#define MTK_DP_LANE3_DRIVING_PARAM_3 (PHY_OFFSET + 0x438) #define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4) #define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12)) #define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19) @@ -79,15 +88,62 @@ #define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \ XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) =20 +enum mtk_dp_phyd_dig_lane_regidx { + DP_PHYD_LAN_DRIVING_PARAM_0, + DP_PHYD_LAN_MAX +}; + +enum mtk_dp_phyd_dig_glb_regidx { + DP_PHYD_PLL_CTL_0, + DP_PHYD_PLL_CTL_1, + DP_PHYD_SW_RST, + DP_PHYD_BIT_RATE, + DP_PHYD_GLOBAL_MAX +}; + +static const u8 mt8195_phy_dig_lane_regs[DP_PHYD_LAN_MAX] =3D { + [DP_PHYD_LAN_DRIVING_PARAM_0] =3D 0x2c, +}; + +static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL_MAX] =3D { + [DP_PHYD_PLL_CTL_0] =3D 0x10, + [DP_PHYD_PLL_CTL_1] =3D 0x14, + [DP_PHYD_SW_RST] =3D 0x38, + [DP_PHYD_BIT_RATE] =3D 0x3c, +}; + +/** + * struct mtk_dp_phy_pdata - Platform data and defaults for MediaTek DP/eD= P PHY + * @off_dig_glb: Base offset for dptx_phyd_sifslv_dig_glb + * @off_dig_lane: Base offsets for dptx_phyd_sifslv_dig_lan (for each la= ne) + * @regs_dig_glb: Register (layout) offsets for dig_glb + * @regs_dig_lane: Register (layout) offsets for dig_lan + */ +struct mtk_dp_phy_pdata { + /* Register offsets */ + u16 off_dig_glb; + u16 off_dig_lane[MTK_DP_PHY_MAX_LANES]; + + /* Register maps */ + const u8 *regs_dig_glb; + const u8 *regs_dig_lane; +}; + struct mtk_dp_phy { struct device *dev; struct regmap *regmap; + const struct mtk_dp_phy_pdata *pdata; }; =20 static int mtk_dp_phy_init(struct phy *phy) { struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; + const u32 reg =3D pdata->regs_dig_lane[DP_PHYD_LAN_DRIVING_PARAM_0]; static const u32 driving_params[] =3D { + DRIVING_PARAM_0_DEFAULT, + DRIVING_PARAM_1_DEFAULT, + DRIVING_PARAM_2_DEFAULT, DRIVING_PARAM_3_DEFAULT, DRIVING_PARAM_4_DEFAULT, DRIVING_PARAM_5_DEFAULT, @@ -95,15 +151,21 @@ static int mtk_dp_phy_init(struct phy *phy) DRIVING_PARAM_7_DEFAULT, DRIVING_PARAM_8_DEFAULT }; - - regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE0_DRIVING_PARAM_3, - driving_params, ARRAY_SIZE(driving_params)); - regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE1_DRIVING_PARAM_3, - driving_params, ARRAY_SIZE(driving_params)); - regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE2_DRIVING_PARAM_3, - driving_params, ARRAY_SIZE(driving_params)); - regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE3_DRIVING_PARAM_3, - driving_params, ARRAY_SIZE(driving_params)); + int i, ret; + + /* + * Assume that all lanes need the same driving parameters: this + * will bulk write from DRIVING_PARAM_0 to DRIVING_PARAM_8 on + * all lanes (a grand total of [9 * num_lanes] 32-bit writes) + */ + for (i =3D 0; i < MTK_DP_PHY_MAX_LANES; i++) { + ret =3D regmap_bulk_write(dp_phy->regmap, + pdata->off_dig_lane[i] + reg, + driving_params, + ARRAY_SIZE(driving_params)); + if (ret) + return ret; + }; =20 return 0; } @@ -111,9 +173,12 @@ static int mtk_dp_phy_init(struct phy *phy) static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts = *opts) { struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; u32 val; =20 if (opts->dp.set_rate) { + const u32 reg_bit_rate =3D pdata->regs_dig_glb[DP_PHYD_BIT_RATE]; + switch (opts->dp.link_rate) { default: dev_err(&phy->dev, @@ -133,10 +198,11 @@ static int mtk_dp_phy_configure(struct phy *phy, unio= n phy_configure_opts *opts) val =3D BIT_RATE_HBR3; break; } - regmap_write(dp_phy->regmap, MTK_DP_PHY_DIG_BIT_RATE, val); + regmap_write(dp_phy->regmap, pdata->off_dig_glb + reg_bit_rate, val); } =20 - regmap_update_bits(dp_phy->regmap, MTK_DP_PHY_DIG_PLL_CTL_1, + regmap_update_bits(dp_phy->regmap, + pdata->off_dig_glb + pdata->regs_dig_glb[DP_PHYD_PLL_CTL_1], TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); =20 return 0; @@ -145,12 +211,17 @@ static int mtk_dp_phy_configure(struct phy *phy, unio= n phy_configure_opts *opts) static int mtk_dp_phy_reset(struct phy *phy) { struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; + const u32 reg_rst =3D pdata->regs_dig_glb[DP_PHYD_SW_RST]; + + /* Clearing bits sets reset state */ + regmap_clear_bits(dp_phy->regmap, pdata->off_dig_glb + reg_rst, DP_GLB_SW= _RST_PHYD); =20 - regmap_update_bits(dp_phy->regmap, MTK_DP_PHY_DIG_SW_RST, - DP_GLB_SW_RST_PHYD, 0); + /* PHYD needs 50uS to guarantee reset done */ usleep_range(50, 200); - regmap_update_bits(dp_phy->regmap, MTK_DP_PHY_DIG_SW_RST, - DP_GLB_SW_RST_PHYD, 1); + + /* Setting bits means go out of reset */ + regmap_set_bits(dp_phy->regmap, pdata->off_dig_glb + reg_rst, DP_GLB_SW_R= ST_PHYD); =20 return 0; } @@ -170,12 +241,19 @@ static void mtk_dp_phy_legacy_remove_lookup(void *dat= a) phy_remove_lookup(phy, "dp", dev_name(dp_phy->dev)); } =20 +static const struct mtk_dp_phy_pdata mt8195_dp_phy_data; + static int mtk_dp_phy_legacy_probe(struct platform_device *pdev, struct mt= k_dp_phy *dp_phy) { struct device *dev =3D &pdev->dev; struct phy *phy; int ret; =20 + /* + * If legacy platform driver probe, assume this is MT8195 or compatible + * with a devicetree that was not migrated to the new, proper bindings. + */ + dp_phy->pdata =3D &mt8195_dp_phy_data; dp_phy->regmap =3D *(struct regmap **)dev->platform_data; if (!dp_phy->regmap) return dev_err_probe(dev, -EINVAL, "No platform data available\n"); @@ -235,6 +313,8 @@ static int mtk_dp_phy_probe(struct platform_device *pde= v) if (ret) return ret; =20 + dp_phy->pdata =3D device_get_match_data(dev); + phy =3D devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops); if (IS_ERR(phy)) return dev_err_probe(dev, PTR_ERR(phy), @@ -249,8 +329,15 @@ static int mtk_dp_phy_probe(struct platform_device *pd= ev) return 0; } =20 +static const struct mtk_dp_phy_pdata mt8195_dp_phy_data =3D { + .off_dig_glb =3D 0x1000, + .off_dig_lane =3D (const u16[]) { 0x1100, 0x1200, 0x1300, 0x1400 }, + .regs_dig_glb =3D mt8195_phy_dig_glb_regs, + .regs_dig_lane =3D mt8195_phy_dig_lane_regs, +}; + static const struct of_device_id mtk_dp_phy_of_match[] =3D { - { .compatible =3D "mediatek,mt8195-dp-phy" }, + { .compatible =3D "mediatek,mt8195-dp-phy", .data =3D &mt8195_dp_phy_data= }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_dp_phy_of_match); --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0348E3C062C; Thu, 10 Sep 2026 09:20:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032051; cv=none; b=JzGYgJy8q7TN9eyiQOA/+O5WRLzZdzLiLlPEoVpQJJ99RKO4j9RMPthHhlA/f3qvAu56HpMMuRrUcVZN/QEZyBefLR8PsYJ/Ktbbu6BOGjki0srAEHMCynqn8gM+b4pRwMBGy3j48Qx+Z2l21q0cg54shF1tS/364HRx9nAFSbs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Add .power_on() and .power_off() callbacks to mtk_dp_phy_dev_ops to be able to call those with phy_power_on() and phy_power_off() API in the DisplayPort driver to be able to stop using all of those hardcoded register writes in that external driver. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam --- drivers/phy/mediatek/phy-mtk-dp.c | 68 +++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index 20974650d940..4247506ceb99 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -21,6 +21,9 @@ =20 #define MTK_DP_PHY_MAX_LANES 4 =20 +/* DP_PHYA_GLB_FORCE_CTRL_1 */ +#define CKM_CKTX0_EN_FORCE_MODE BIT(10) + /* DP_PHYD_PLL_CTL_1 */ #define TPLL_SSC_EN BIT(3) =20 @@ -38,6 +41,11 @@ # define DP_GLB_SW_RST_XTAL_CLK BIT(2) # define DP_GLB_SW_RST_MAIN_LINK BIT(3) =20 +/* DP_PHYD_AUX_RX_CTL */ +#define PHYD_DIG_DPAUX_RX_EN BIT(0) +#define PHYD_DIG_XTP_GLB_CKDET_EN BIT(1) +#define PHYD_DIG_DPAUX_RX_DEGLITCH_EN BIT(2) + #define DRIVING_PARAM_0_DEFAULT 0x0 #define DRIVING_PARAM_1_DEFAULT 0x0 #define DRIVING_PARAM_2_DEFAULT 0x0 @@ -88,6 +96,12 @@ #define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \ XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) =20 +enum mtk_dp_phya_ana_glb_regidx { + DP_PHYA_GLB_FORCE_CTRL_0, + DP_PHYA_GLB_FORCE_CTRL_1, + DP_PHYA_GLOBAL_MAX +}; + enum mtk_dp_phyd_dig_lane_regidx { DP_PHYD_LAN_DRIVING_PARAM_0, DP_PHYD_LAN_MAX @@ -98,9 +112,15 @@ enum mtk_dp_phyd_dig_glb_regidx { DP_PHYD_PLL_CTL_1, DP_PHYD_SW_RST, DP_PHYD_BIT_RATE, + DP_PHYD_AUX_RX_CTL, DP_PHYD_GLOBAL_MAX }; =20 +static const u8 mt8195_phy_ana_glb_regs[DP_PHYA_GLOBAL_MAX] =3D { + [DP_PHYA_GLB_FORCE_CTRL_0] =3D 0x30, + [DP_PHYA_GLB_FORCE_CTRL_1] =3D 0x34, +}; + static const u8 mt8195_phy_dig_lane_regs[DP_PHYD_LAN_MAX] =3D { [DP_PHYD_LAN_DRIVING_PARAM_0] =3D 0x2c, }; @@ -110,21 +130,26 @@ static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBA= L_MAX] =3D { [DP_PHYD_PLL_CTL_1] =3D 0x14, [DP_PHYD_SW_RST] =3D 0x38, [DP_PHYD_BIT_RATE] =3D 0x3c, + [DP_PHYD_AUX_RX_CTL] =3D 0x40, }; =20 /** * struct mtk_dp_phy_pdata - Platform data and defaults for MediaTek DP/eD= P PHY + * @off_ana_glb: Base offset for dptx_phyd_sifslv_ana_glb * @off_dig_glb: Base offset for dptx_phyd_sifslv_dig_glb * @off_dig_lane: Base offsets for dptx_phyd_sifslv_dig_lan (for each la= ne) + * @regs_ana_glb: Register (layout) offsets for ana_glb * @regs_dig_glb: Register (layout) offsets for dig_glb * @regs_dig_lane: Register (layout) offsets for dig_lan */ struct mtk_dp_phy_pdata { /* Register offsets */ + u16 off_ana_glb; u16 off_dig_glb; u16 off_dig_lane[MTK_DP_PHY_MAX_LANES]; =20 /* Register maps */ + const u8 *regs_ana_glb; const u8 *regs_dig_glb; const u8 *regs_dig_lane; }; @@ -208,6 +233,45 @@ static int mtk_dp_phy_configure(struct phy *phy, union= phy_configure_opts *opts) return 0; } =20 +static int mtk_dp_phy_power_on(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; + const u8 *regs_dig =3D pdata->regs_dig_glb; + const u8 *regs_ana =3D pdata->regs_ana_glb; + + /* Enable AUX Channel with RX De-Glitch and input clock detection */ + regmap_write(dp_phy->regmap, + pdata->off_dig_glb + regs_dig[DP_PHYD_AUX_RX_CTL], + PHYD_DIG_DPAUX_RX_EN | + PHYD_DIG_XTP_GLB_CKDET_EN | + PHYD_DIG_DPAUX_RX_DEGLITCH_EN); + + regmap_clear_bits(dp_phy->regmap, + pdata->off_ana_glb + regs_ana[DP_PHYA_GLB_FORCE_CTRL_1], + CKM_CKTX0_EN_FORCE_MODE); + + return 0; +} + +static int mtk_dp_phy_power_off(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; + const u8 *regs_dig =3D pdata->regs_dig_glb; + const u8 *regs_ana =3D pdata->regs_ana_glb; + + regmap_set_bits(dp_phy->regmap, + pdata->off_ana_glb + regs_ana[DP_PHYA_GLB_FORCE_CTRL_1], + CKM_CKTX0_EN_FORCE_MODE); + + /* Disable RX unconditionally */ + regmap_write(dp_phy->regmap, + pdata->off_dig_glb + regs_dig[DP_PHYD_AUX_RX_CTL], 0); + + return 0; +} + static int mtk_dp_phy_reset(struct phy *phy) { struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); @@ -228,6 +292,8 @@ static int mtk_dp_phy_reset(struct phy *phy) =20 static const struct phy_ops mtk_dp_phy_dev_ops =3D { .init =3D mtk_dp_phy_init, + .power_on =3D mtk_dp_phy_power_on, + .power_off =3D mtk_dp_phy_power_off, .configure =3D mtk_dp_phy_configure, .reset =3D mtk_dp_phy_reset, .owner =3D THIS_MODULE, @@ -330,8 +396,10 @@ static int mtk_dp_phy_probe(struct platform_device *pd= ev) } =20 static const struct mtk_dp_phy_pdata mt8195_dp_phy_data =3D { + .off_ana_glb =3D 0x0, .off_dig_glb =3D 0x1000, .off_dig_lane =3D (const u16[]) { 0x1100, 0x1200, 0x1300, 0x1400 }, + .regs_ana_glb =3D mt8195_phy_ana_glb_regs, .regs_dig_glb =3D mt8195_phy_dig_glb_regs, .regs_dig_lane =3D mt8195_phy_dig_lane_regs, }; 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Thu, 10 Sep 2026 11:20:47 +0200 (CEST) From: AngeloGioacchino Del Regno To: mani@kernel.org Cc: chunfeng.yun@mediatek.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, justin.yeh@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com Subject: [PATCH v4 06/12] phy: phy-mtk-dp: Support set_lanes in configure and properly cleanup Date: Thu, 10 Sep 2026 11:20:32 +0200 Message-ID: <20260910092038.48291-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> References: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for enabling a specifically requested number of lanes in the .configure() callback and disable all lanes in power off and reset callbacks for proper hardware cleanup. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam --- drivers/phy/mediatek/phy-mtk-dp.c | 57 +++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index 4247506ceb99..276391d991aa 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -10,6 +10,7 @@ * AngeloGioacchino Del Regno */ =20 +#include #include #include #include @@ -50,6 +51,9 @@ #define DRIVING_PARAM_1_DEFAULT 0x0 #define DRIVING_PARAM_2_DEFAULT 0x0 =20 +/* DP_PHYD_TX_CTL_0 */ +#define PHYD_TX_LN_EN GENMASK(7, 4) + #define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4) #define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12)) #define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19) @@ -113,6 +117,7 @@ enum mtk_dp_phyd_dig_glb_regidx { DP_PHYD_SW_RST, DP_PHYD_BIT_RATE, DP_PHYD_AUX_RX_CTL, + DP_PHYD_TX_CTL_0, DP_PHYD_GLOBAL_MAX }; =20 @@ -131,6 +136,7 @@ static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL_= MAX] =3D { [DP_PHYD_SW_RST] =3D 0x38, [DP_PHYD_BIT_RATE] =3D 0x3c, [DP_PHYD_AUX_RX_CTL] =3D 0x40, + [DP_PHYD_TX_CTL_0] =3D 0x44, }; =20 /** @@ -200,6 +206,7 @@ static int mtk_dp_phy_configure(struct phy *phy, union = phy_configure_opts *opts) struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; u32 val; + int i; =20 if (opts->dp.set_rate) { const u32 reg_bit_rate =3D pdata->regs_dig_glb[DP_PHYD_BIT_RATE]; @@ -226,6 +233,17 @@ static int mtk_dp_phy_configure(struct phy *phy, union= phy_configure_opts *opts) regmap_write(dp_phy->regmap, pdata->off_dig_glb + reg_bit_rate, val); } =20 + if (opts->dp.set_lanes) { + const u32 reg_dig_tx_ctl =3D pdata->regs_dig_glb[DP_PHYD_TX_CTL_0]; + + val =3D 0; + for (i =3D 0; i < opts->dp.lanes; i++) + val |=3D FIELD_PREP(PHYD_TX_LN_EN, BIT(i)); + + regmap_update_bits(dp_phy->regmap, pdata->off_dig_glb + reg_dig_tx_ctl, + PHYD_TX_LN_EN, val); + } + regmap_update_bits(dp_phy->regmap, pdata->off_dig_glb + pdata->regs_dig_glb[DP_PHYD_PLL_CTL_1], TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); @@ -254,12 +272,39 @@ static int mtk_dp_phy_power_on(struct phy *phy) return 0; } =20 +static int mtk_dp_phy_disable_all_lanes(struct mtk_dp_phy *dp_phy) +{ + const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; + const u8 *regs =3D pdata->regs_dig_glb; + int ret; + u32 val; + + /* Get mask of currently enabled lane */ + regmap_read(dp_phy->regmap, pdata->off_dig_glb + regs[DP_PHYD_TX_CTL_0], = &val); + val =3D FIELD_GET(PHYD_TX_LN_EN, val); + if (val =3D=3D 0) + return 0; + + /* Disable all lanes (needs to be done one by one, from last to first) */ + do { + u32 lane_num =3D fls(val) - 1; + val &=3D ~BIT(lane_num); + + regmap_clear_bits(dp_phy->regmap, + pdata->off_dig_glb + regs[DP_PHYD_TX_CTL_0], + FIELD_PREP(PHYD_TX_LN_EN, BIT(lane_num))); + } while (val); + + return 0; +} + static int mtk_dp_phy_power_off(struct phy *phy) { struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; const u8 *regs_dig =3D pdata->regs_dig_glb; const u8 *regs_ana =3D pdata->regs_ana_glb; + int ret; =20 regmap_set_bits(dp_phy->regmap, pdata->off_ana_glb + regs_ana[DP_PHYA_GLB_FORCE_CTRL_1], @@ -269,6 +314,12 @@ static int mtk_dp_phy_power_off(struct phy *phy) regmap_write(dp_phy->regmap, pdata->off_dig_glb + regs_dig[DP_PHYD_AUX_RX_CTL], 0); =20 + ret =3D mtk_dp_phy_disable_all_lanes(dp_phy); + if (ret) { + dev_err(dp_phy->dev, "Could not disable lanes for poweroff!\n"); + return ret; + } + return 0; } =20 @@ -277,6 +328,7 @@ static int mtk_dp_phy_reset(struct phy *phy) struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; const u32 reg_rst =3D pdata->regs_dig_glb[DP_PHYD_SW_RST]; + int ret; =20 /* Clearing bits sets reset state */ regmap_clear_bits(dp_phy->regmap, pdata->off_dig_glb + reg_rst, DP_GLB_SW= _RST_PHYD); @@ -287,6 +339,11 @@ static int mtk_dp_phy_reset(struct phy *phy) /* Setting bits means go out of reset */ regmap_set_bits(dp_phy->regmap, pdata->off_dig_glb + reg_rst, DP_GLB_SW_R= ST_PHYD); =20 + /* Disable all lanes and continue reset even if this fails, but notify */ + ret =3D mtk_dp_phy_disable_all_lanes(dp_phy); + if (ret) + dev_err(dp_phy->dev, "Could not disable lanes during reset!\n"); + return 0; } =20 --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 968963DCDA4; Thu, 10 Sep 2026 09:20:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032052; cv=none; b=KAwt9DYv0cTvL90z/wxIQ2ZqpyF5Y/YP6NTIKRk7hG3Nh8ATzl5aF5AkhnWFlGMQnQ8sP0Uqg3igMnbfkwnXedKFCsgu3L97E781J8l6FfiMphWPUHDRIJmPgDNrE6byDDO4O8EyFzEPwHxQLLpSuUuoZsQKQdePsyhLqyKN3jc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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d=collabora.com; s=mail; t=1789032048; bh=WTVMQxnGADESJuhn7zz/Hiaj/YXUMi4pSU91iU+djqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ca8DBvRtV5wXcgzxRYPqpbUIYFRrzQyL9gkw+mu+feBFiW+VwC6OzzykVpUxiJVmU 0MTHmH6sohdxtH6C1J+QPl9v56kCMQgfki4MDJBFxCy04ByCxOfTLPACtouet0QXm8 vxUQkjWpei+nt8cR+Xa4POxfAmmNVZL4XuLR7bdRmD6I83V8LZ44w3hwS/AepKLQkY /R411VgA3vO0VG+b4WVRbf3aRBBK5Zrmn8mViVTwhujZsIsAzV2ch4d6EGphVYjgjK jmkFmRcjRzxoKHolBe46AHfMSJpE3qfHokSXdaAhaFomzvISKOn5SeCe8GSh67stGx nK+33VNovo+/g== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 0F55617E124A; Thu, 10 Sep 2026 11:20:48 +0200 (CEST) From: AngeloGioacchino Del Regno To: mani@kernel.org Cc: chunfeng.yun@mediatek.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, justin.yeh@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com, Manivannan Sadhasivam Subject: [PATCH v4 07/12] phy: phy-mtk-dp: Support setting volt swing and preemphasis values Date: Thu, 10 Sep 2026 11:20:33 +0200 Message-ID: <20260910092038.48291-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> References: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for honoring the set_voltages request to set the voltage swing and preemphasis values in the .configure() callback. For proper hardware cleanup, reset both in the .reset() callback. Reviewed-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-dp.c | 44 ++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index 276391d991aa..692049f78833 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -54,6 +54,11 @@ /* DP_PHYD_TX_CTL_0 */ #define PHYD_TX_LN_EN GENMASK(7, 4) =20 +/* DP_PHYD_DRIVING_FORCE */ +#define PHYD_DP_TX_FORCE_VOLT_SWING_EN BIT(0) +#define PHYD_DP_TX_FORCE_VOLT_SWING_VAL GENMASK(2, 1) +#define PHYD_DP_TX_FORCE_PRE_EMPH_VAL GENMASK(4, 3) + #define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4) #define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12)) #define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19) @@ -107,6 +112,7 @@ enum mtk_dp_phya_ana_glb_regidx { }; =20 enum mtk_dp_phyd_dig_lane_regidx { + DP_PHYD_LAN_DRIVING_FORCE, DP_PHYD_LAN_DRIVING_PARAM_0, DP_PHYD_LAN_MAX }; @@ -127,6 +133,7 @@ static const u8 mt8195_phy_ana_glb_regs[DP_PHYA_GLOBAL_= MAX] =3D { }; =20 static const u8 mt8195_phy_dig_lane_regs[DP_PHYD_LAN_MAX] =3D { + [DP_PHYD_LAN_DRIVING_FORCE] =3D 0x18, [DP_PHYD_LAN_DRIVING_PARAM_0] =3D 0x2c, }; =20 @@ -244,6 +251,30 @@ static int mtk_dp_phy_configure(struct phy *phy, union= phy_configure_opts *opts) PHYD_TX_LN_EN, val); } =20 + if (opts->dp.set_voltages) { + const u32 reg_drv_force =3D pdata->regs_dig_lane[DP_PHYD_LAN_DRIVING_FOR= CE]; + + if (opts->dp.lanes > 4) { + dev_err(&phy->dev, "Wrong lanes config %u\n", opts->dp.lanes); + return -EINVAL; + } + + for (i =3D 0; i < opts->dp.lanes; i++) { + const u32 off_dig_lane =3D pdata->off_dig_lane[i]; + u32 val; + + val =3D FIELD_PREP(PHYD_DP_TX_FORCE_VOLT_SWING_VAL, opts->dp.voltage[i]= ); + val |=3D FIELD_PREP(PHYD_DP_TX_FORCE_PRE_EMPH_VAL, opts->dp.pre[i]); + val |=3D PHYD_DP_TX_FORCE_VOLT_SWING_EN; + + regmap_update_bits(dp_phy->regmap, off_dig_lane + reg_drv_force, + PHYD_DP_TX_FORCE_VOLT_SWING_EN | + PHYD_DP_TX_FORCE_VOLT_SWING_VAL | + PHYD_DP_TX_FORCE_PRE_EMPH_VAL, + val); + } + } + regmap_update_bits(dp_phy->regmap, pdata->off_dig_glb + pdata->regs_dig_glb[DP_PHYD_PLL_CTL_1], TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); @@ -328,7 +359,8 @@ static int mtk_dp_phy_reset(struct phy *phy) struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; const u32 reg_rst =3D pdata->regs_dig_glb[DP_PHYD_SW_RST]; - int ret; + const u32 reg_drv_force =3D pdata->regs_dig_lane[DP_PHYD_LAN_DRIVING_FORC= E]; + int i, ret; =20 /* Clearing bits sets reset state */ regmap_clear_bits(dp_phy->regmap, pdata->off_dig_glb + reg_rst, DP_GLB_SW= _RST_PHYD); @@ -344,6 +376,16 @@ static int mtk_dp_phy_reset(struct phy *phy) if (ret) dev_err(dp_phy->dev, "Could not disable lanes during reset!\n"); =20 + /* Reset Voltage Swing and Preemphasis values */ + for (i =3D 0; i < MTK_DP_PHY_MAX_LANES; i++) { + const u32 off_dig_lane =3D pdata->off_dig_lane[i]; + + regmap_clear_bits(dp_phy->regmap, off_dig_lane + reg_drv_force, + PHYD_DP_TX_FORCE_VOLT_SWING_EN | + PHYD_DP_TX_FORCE_VOLT_SWING_VAL | + PHYD_DP_TX_FORCE_PRE_EMPH_VAL); + } + return 0; } =20 --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A82EA3E1701; Thu, 10 Sep 2026 09:20:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032054; cv=none; b=c9Tme7nzh4aC5wCMBoV2++TmueIexjzoVK8XEpz2VquMbgSsJoVfghLO6fJhYNQcxIVZ0SxY9Tr4UZZDVbBDROwpmryJ2FZrzet/VoLqCwqrME3tKDdKNf3lAI0K2vYOPGN0FTVtL6U1FhhuGSIHrJooeXu7nJBZeNOcSiweoPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032054; c=relaxed/simple; bh=BnCi7Acd5BflxpbDWeVMB8fqCiQSyP34XJyY0PjhG98=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=L14FExY6QW8Se5dszoQ8JAqbQKHGd94iFzM8WuOaNkUQqX9y8OuzerQAAemzWhT6+IYq9CKHUk6OAEDCY15pLGdHKNOt0rzlEX6howIul4+TOapJEItAxKIRNLfsiHRdDzeSIxglKkd6th+nhb0UA8EcghvzS7XPwaZONqpe8Bc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=mW45gh4g; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="mW45gh4g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789032049; bh=BnCi7Acd5BflxpbDWeVMB8fqCiQSyP34XJyY0PjhG98=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mW45gh4giXXOs93JWvaUhw6kACIdzznN+MZu/ZnthlUjv2QuMD382aFi4r1hHE6xI +gFd7+VbTPOzHpJ0K5DUhe9YHtaJL9p9duaODSHLFVYSboNFZvkzVhKc2QfI/NZ6yt CHeeveD0W6+7IzPIR635lbVM55hI85JW4gD7QJqkP0wg/igpUnchO6b7CVfuRYLVxR w2NinbNDpSYZhZciQQ6c9bsHbZZbj1vYTMTeKLL6JVAb06Jvd8fXFv31qmyI+FaVQ3 n5D/SmArVOgxDv6DscM5M5RCnxSGP/Ba8VPZvmhNBineuI2NVwDcSWcTdLrRvZZ+Cy UOyOSbGhR0T2Q== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id EB0D217E0917; Thu, 10 Sep 2026 11:20:48 +0200 (CEST) From: AngeloGioacchino Del Regno To: mani@kernel.org Cc: chunfeng.yun@mediatek.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, justin.yeh@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com Subject: [PATCH v4 08/12] phy: phy-mtk-dp: Add support for digital and analog calibration Date: Thu, 10 Sep 2026 11:20:34 +0200 Message-ID: <20260910092038.48291-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> References: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for reading the calibration values from eFuse: if present, write those - otherwise, rely on the defaults from SoC-specific data. This also adds support for writing the calibration values for the analog part of the PHY. Note that before this change, only default hardcoded calibration values were supported for the digital driving parameters. Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-dp.c | 289 +++++++++++++++++++++++++++--- 1 file changed, 261 insertions(+), 28 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index 692049f78833..2f4cf52d922c 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,19 @@ =20 #define MTK_DP_PHY_MAX_LANES 4 =20 +/* DP_PHYA_GLB_BIAS_GEN_0 (PHYA - Analog) */ +#define XTP_GLB_BIAS_INT_R_CTRL GENMASK(20, 16) + +/* DP_PHYA_GLB_FORCE_CTRL_1 */ +#define CKM_CKTX0_EN_FORCE_MODE BIT(10) + +/* DP_PHYA_GLB_DPAUX_TX */ +#define CKM_PT0_CKTX_IMPSEL GENMASK(23, 20) + +/* DP_PHYA_LAN_LANE_TX_0 */ +#define XTP_LN_TX_IMPSEL_PMOS GENMASK(15, 12) +#define XTP_LN_TX_IMPSEL_NMOS GENMASK(19, 16) + /* DP_PHYA_GLB_FORCE_CTRL_1 */ #define CKM_CKTX0_EN_FORCE_MODE BIT(10) =20 @@ -59,11 +73,29 @@ #define PHYD_DP_TX_FORCE_VOLT_SWING_VAL GENMASK(2, 1) #define PHYD_DP_TX_FORCE_PRE_EMPH_VAL GENMASK(4, 3) =20 +/* + * DRIVING_PARAM_X (PHYD - Digital) + * + * Driving param registers are split in three sets, all containing settings + * for Voltage Swing and Pre-Emphasis for each lane's differential pair. + * + * All three sets share the same layout, but for different physical signal= s; + * In particular: + * [0-2]: LC TX CM (Minus / Negative Edge) + * [3-5]: LC TX C (Logic State Change Point) + * [6-8]: LC TX CP (Plus / Positive Edge) + * + * And they contain values for: + * [0,3,6]: Swing 0 Pre[0-3] + * [1,4,7]: Swing 1 Pre[0-2] and Swing 2 Pre0 + * [2,5,8]: Swing 2 Pre1 and Swing 3 Pre0 + */ +#define PHYD_DIG_NUM_DRV_PARA_REGS 9 #define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4) #define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12)) #define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19) #define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29) -#define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \ +#define MT8195_DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT = | \ XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \ XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \ XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT) @@ -72,21 +104,21 @@ #define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT GENMASK(12, 9) #define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (BIT(18) | BIT(21)) #define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29) -#define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \ +#define MT8195_DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT = | \ XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \ XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \ XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT) =20 #define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT (BIT(3) | BIT(5)) #define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT GENMASK(13, 12) -#define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \ +#define MT8195_DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT = | \ XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT) =20 #define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0 #define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT GENMASK(10, 10) #define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT GENMASK(19, 19) #define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT GENMASK(28, 28) -#define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \ +#define MT8195_DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT= | \ XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \ XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \ XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT) @@ -95,22 +127,30 @@ #define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT GENMASK(10, 9) #define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT GENMASK(19, 18) #define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT 0 -#define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \ +#define MT8195_DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT= | \ XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \ XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \ XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT) =20 #define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT GENMASK(3, 3) #define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT 0 -#define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \ +#define MT8195_DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT= | \ XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) =20 enum mtk_dp_phya_ana_glb_regidx { + DP_PHYA_GLB_BIAS_GEN_0, + DP_PHYA_GLB_BIAS_GEN_1, + DP_PHYA_GLB_DPAUX_TX, DP_PHYA_GLB_FORCE_CTRL_0, DP_PHYA_GLB_FORCE_CTRL_1, DP_PHYA_GLOBAL_MAX }; =20 +enum mtk_dp_phya_ana_lane_regidx { + DP_PHYA_LAN_LANE_TX_0, + DP_PHYA_LAN_MAX +}; + enum mtk_dp_phyd_dig_lane_regidx { DP_PHYD_LAN_DRIVING_FORCE, DP_PHYD_LAN_DRIVING_PARAM_0, @@ -128,10 +168,17 @@ enum mtk_dp_phyd_dig_glb_regidx { }; =20 static const u8 mt8195_phy_ana_glb_regs[DP_PHYA_GLOBAL_MAX] =3D { + [DP_PHYA_GLB_BIAS_GEN_0] =3D 0x0, + [DP_PHYA_GLB_BIAS_GEN_1] =3D 0x4, + [DP_PHYA_GLB_DPAUX_TX] =3D 0x8, [DP_PHYA_GLB_FORCE_CTRL_0] =3D 0x30, [DP_PHYA_GLB_FORCE_CTRL_1] =3D 0x34, }; =20 +static const u8 mt8195_phy_ana_lane_regs[DP_PHYA_LAN_MAX] =3D { + [DP_PHYA_LAN_LANE_TX_0] =3D 0x4, +}; + static const u8 mt8195_phy_dig_lane_regs[DP_PHYD_LAN_MAX] =3D { [DP_PHYD_LAN_DRIVING_FORCE] =3D 0x18, [DP_PHYD_LAN_DRIVING_PARAM_0] =3D 0x2c, @@ -146,49 +193,94 @@ static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBA= L_MAX] =3D { [DP_PHYD_TX_CTL_0] =3D 0x44, }; =20 +/** + * struct mtk_dp_phya_imp_sel - Per-Lane Impedance Selection + * @pmos: Impedance selection for P-Channel MOSFET + * @nmos: Impedance selection for N-Channel MOSFET + */ +struct mtk_dp_phya_imp_sel { + u8 pmos : 4; + u8 nmos : 4; +}; + /** * struct mtk_dp_phy_pdata - Platform data and defaults for MediaTek DP/eD= P PHY * @off_ana_glb: Base offset for dptx_phyd_sifslv_ana_glb + * @off_ana_lane: Base offsets for dptx_phyd_sifslv_ana_lan (for each la= ne) * @off_dig_glb: Base offset for dptx_phyd_sifslv_dig_glb * @off_dig_lane: Base offsets for dptx_phyd_sifslv_dig_lan (for each la= ne) * @regs_ana_glb: Register (layout) offsets for ana_glb + * @regs_ana_lane: Register (layout) offsets for ana_lan * @regs_dig_glb: Register (layout) offsets for dig_glb * @regs_dig_lane: Register (layout) offsets for dig_lan + * @ana_bias_r: Internal resistance "R" Selection Settings (global) + * @ana_cktx_imp: TX Clock Impedance Selection Settings (global) + * @ana_lanes_imp: TX Impedance Selection Settings (for all lanes) + * @driving_params: Voltage Swing and Pre-Emphasis settings (for all lanes) */ struct mtk_dp_phy_pdata { /* Register offsets */ u16 off_ana_glb; + u16 off_ana_lane[MTK_DP_PHY_MAX_LANES]; u16 off_dig_glb; u16 off_dig_lane[MTK_DP_PHY_MAX_LANES]; =20 /* Register maps */ const u8 *regs_ana_glb; + const u8 *regs_ana_lane; const u8 *regs_dig_glb; const u8 *regs_dig_lane; + + /* Calibration defaults */ + u8 ana_bias_r; + u8 ana_cktx_imp; + struct mtk_dp_phya_imp_sel ana_lanes_imp; + u32 driving_params[PHYD_DIG_NUM_DRV_PARA_REGS]; }; =20 struct mtk_dp_phy { struct device *dev; struct regmap *regmap; const struct mtk_dp_phy_pdata *pdata; + + u8 ana_bias_r; + u8 ana_cktx_imp; + struct mtk_dp_phya_imp_sel ana_impsel[MTK_DP_PHY_MAX_LANES]; }; =20 -static int mtk_dp_phy_init(struct phy *phy) +static void mtk_dp_phy_set_analog_calibration_params(struct mtk_dp_phy *dp= _phy) +{ + const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; + const u8 *regs_ana_glb =3D pdata->regs_ana_glb; + const u8 *regs_ana_lane =3D pdata->regs_ana_lane; + int i; + + regmap_update_bits(dp_phy->regmap, + pdata->off_ana_glb + regs_ana_glb[DP_PHYA_GLB_BIAS_GEN_0], + XTP_GLB_BIAS_INT_R_CTRL, + FIELD_PREP(XTP_GLB_BIAS_INT_R_CTRL, dp_phy->ana_bias_r)); + + regmap_update_bits(dp_phy->regmap, + pdata->off_ana_glb + regs_ana_glb[DP_PHYA_GLB_DPAUX_TX], + CKM_PT0_CKTX_IMPSEL, + FIELD_PREP(CKM_PT0_CKTX_IMPSEL, dp_phy->ana_cktx_imp)); + + for (i =3D 0; i < MTK_DP_PHY_MAX_LANES; i++) { + struct mtk_dp_phya_imp_sel *ana_imp =3D &dp_phy->ana_impsel[i]; + u32 val =3D FIELD_PREP(XTP_LN_TX_IMPSEL_PMOS, ana_imp->pmos) | + FIELD_PREP(XTP_LN_TX_IMPSEL_NMOS, ana_imp->nmos); + u32 off_ana_lane =3D pdata->off_ana_lane[i]; + + regmap_update_bits(dp_phy->regmap, + off_ana_lane + regs_ana_lane[DP_PHYA_LAN_LANE_TX_0], + XTP_LN_TX_IMPSEL_PMOS | XTP_LN_TX_IMPSEL_NMOS, val); + } +} + +static void mtk_dp_phy_set_digital_drv_params(struct mtk_dp_phy *dp_phy) { - struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; const u32 reg =3D pdata->regs_dig_lane[DP_PHYD_LAN_DRIVING_PARAM_0]; - static const u32 driving_params[] =3D { - DRIVING_PARAM_0_DEFAULT, - DRIVING_PARAM_1_DEFAULT, - DRIVING_PARAM_2_DEFAULT, - DRIVING_PARAM_3_DEFAULT, - DRIVING_PARAM_4_DEFAULT, - DRIVING_PARAM_5_DEFAULT, - DRIVING_PARAM_6_DEFAULT, - DRIVING_PARAM_7_DEFAULT, - DRIVING_PARAM_8_DEFAULT - }; int i, ret; =20 /* @@ -196,14 +288,19 @@ static int mtk_dp_phy_init(struct phy *phy) * will bulk write from DRIVING_PARAM_0 to DRIVING_PARAM_8 on * all lanes (a grand total of [9 * num_lanes] 32-bit writes) */ - for (i =3D 0; i < MTK_DP_PHY_MAX_LANES; i++) { - ret =3D regmap_bulk_write(dp_phy->regmap, - pdata->off_dig_lane[i] + reg, - driving_params, - ARRAY_SIZE(driving_params)); - if (ret) - return ret; - }; + for (i =3D 0; i < MTK_DP_PHY_MAX_LANES; i++) + regmap_bulk_write(dp_phy->regmap, pdata->off_dig_lane[i] + reg, + pdata->driving_params, + ARRAY_SIZE(pdata->driving_params)); +} + +static int mtk_dp_phy_init(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + struct device *dev =3D &phy->dev; + + mtk_dp_phy_set_digital_drv_params(dp_phy); + mtk_dp_phy_set_analog_calibration_params(dp_phy); =20 return 0; } @@ -398,6 +495,107 @@ static const struct phy_ops mtk_dp_phy_dev_ops =3D { .owner =3D THIS_MODULE, }; =20 +static void mtk_dp_phy_get_default_cal_data(struct mtk_dp_phy *dp_phy) +{ + const struct mtk_dp_phy_pdata *pdata =3D dp_phy->pdata; + int i; + + dp_phy->ana_bias_r =3D pdata->ana_bias_r; + dp_phy->ana_cktx_imp =3D pdata->ana_cktx_imp; + + /* Copy the default lane impedance settings to all lanes */ + for (i =3D 0; i < MTK_DP_PHY_MAX_LANES; i++) + memcpy(&dp_phy->ana_impsel[i], &pdata->ana_lanes_imp, + sizeof(dp_phy->ana_impsel[0])); + + return; +} + +static int mtk_dp_phy_get_one_cal_para(struct device *dev, const char *nam= e, u8 max_val) +{ + u8 buf_byte; + u16 buf; + int ret; + + /* + * All of the calibrations are always max 8 bits long, but some may + * be split between two different 8-bits cells: handle this corner + * case by retrying reading as u16. + */ + ret =3D nvmem_cell_read_u8(dev, name, &buf_byte); + if (ret) + ret =3D nvmem_cell_read_u16(dev, name, &buf); + else + buf =3D buf_byte; + + if (ret) + return dev_err_probe(dev, ret, "Cannot get calibration data for %s\n", n= ame); + + if (buf =3D=3D 0) { + dev_warn(dev, "No calibration for %s. Using defaults\n", name); + return -ENOENT; + } + + if (buf > max_val) + return dev_err_probe(dev, -ERANGE, "Bad value %u retrieved for %s\n", bu= f, name); + + return buf; +} + +static int mtk_dp_phy_get_calibration_data(struct mtk_dp_phy *dp_phy) +{ + char mtk_dp_cal_lane_imp_name[] =3D "impedance-laneXM"; + struct device *dev =3D dp_phy->dev; + int i, ret; + + ret =3D mtk_dp_phy_get_one_cal_para(dev, "rbias-trim", FIELD_MAX(XTP_GLB_= BIAS_INT_R_CTRL)); + if (ret < 0) + goto end; + dp_phy->ana_bias_r =3D ret; + + ret =3D mtk_dp_phy_get_one_cal_para(dev, "impedance-txclk", FIELD_MAX(CKM= _PT0_CKTX_IMPSEL)); + if (ret < 0) + goto end; + dp_phy->ana_cktx_imp =3D ret; + + /* Get impedance params for each lane */ + for (i =3D 0; i < MTK_DP_PHY_MAX_LANES; i++) { + /* P-MOSFET first */ + snprintf(mtk_dp_cal_lane_imp_name, ARRAY_SIZE(mtk_dp_cal_lane_imp_name), + "impedance-lane%dp", i); + ret =3D mtk_dp_phy_get_one_cal_para(dev, mtk_dp_cal_lane_imp_name, + FIELD_MAX(XTP_LN_TX_IMPSEL_PMOS)); + if (ret < 0) + goto end; + dp_phy->ana_impsel[i].pmos =3D ret; + + /* ...and then N-MOSFET too */ + snprintf(mtk_dp_cal_lane_imp_name, ARRAY_SIZE(mtk_dp_cal_lane_imp_name), + "impedance-lane%dn", i); + ret =3D mtk_dp_phy_get_one_cal_para(dev, mtk_dp_cal_lane_imp_name, + FIELD_MAX(XTP_LN_TX_IMPSEL_NMOS)); + if (ret < 0) + goto end; + dp_phy->ana_impsel[i].nmos =3D ret; + } +end: + if (ret < 0) { + /* + * If any of the calibration values is missing, or if there + * is no calibration at all in the eFuses, copy the default + * one entirely (as partial values shall not be mixed!) + */ + if (ret =3D=3D -ENOENT) { + dev_info(dev, "Using calibration default values\n"); + mtk_dp_phy_get_default_cal_data(dp_phy); + return 0; + } + return ret; + }; + + return 0; +} + static void mtk_dp_phy_legacy_remove_lookup(void *data) { struct phy *phy =3D data; @@ -429,6 +627,13 @@ static int mtk_dp_phy_legacy_probe(struct platform_dev= ice *pdev, struct mtk_dp_p "Failed to create DP PHY\n"); =20 phy_set_drvdata(phy, dp_phy); + + /* + * Set default calibration data before exposing the PHY. + * For legacy probe, mtk_dp will set calibrations from eFuse, if found. + */ + mtk_dp_phy_get_default_cal_data(dp_phy); + ret =3D phy_create_lookup(phy, "dp", dev_name(dev)); if (ret) return ret; @@ -480,6 +685,15 @@ static int mtk_dp_phy_probe(struct platform_device *pd= ev) =20 dp_phy->pdata =3D device_get_match_data(dev); =20 + if (IS_REACHABLE(CONFIG_NVMEM)) { + ret =3D mtk_dp_phy_get_calibration_data(dp_phy); + if (ret) + return ret; + } else { + /* Use default calibration data */ + mtk_dp_phy_get_default_cal_data(dp_phy); + } + phy =3D devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops); if (IS_ERR(phy)) return dev_err_probe(dev, PTR_ERR(phy), @@ -495,12 +709,31 @@ static int mtk_dp_phy_probe(struct platform_device *p= dev) } =20 static const struct mtk_dp_phy_pdata mt8195_dp_phy_data =3D { - .off_ana_glb =3D 0x0, + .off_ana_glb =3D 0, + .off_ana_lane =3D (const u16[]) { 0x100, 0x200, 0x300, 0x400 }, .off_dig_glb =3D 0x1000, .off_dig_lane =3D (const u16[]) { 0x1100, 0x1200, 0x1300, 0x1400 }, .regs_ana_glb =3D mt8195_phy_ana_glb_regs, + .regs_ana_lane =3D mt8195_phy_ana_lane_regs, .regs_dig_glb =3D mt8195_phy_dig_glb_regs, .regs_dig_lane =3D mt8195_phy_dig_lane_regs, + .ana_bias_r =3D 15, + .ana_cktx_imp =3D 8, + .ana_lanes_imp =3D { + .pmos =3D 8, + .nmos =3D 8, + }, + .driving_params =3D (const u32[]) { + [0] =3D 0, + [1] =3D 0, + [2] =3D 0, + [3] =3D MT8195_DRIVING_PARAM_3_DEFAULT, + [4] =3D MT8195_DRIVING_PARAM_4_DEFAULT, + [5] =3D MT8195_DRIVING_PARAM_5_DEFAULT, + [6] =3D MT8195_DRIVING_PARAM_6_DEFAULT, + [7] =3D MT8195_DRIVING_PARAM_7_DEFAULT, + [8] =3D MT8195_DRIVING_PARAM_8_DEFAULT + }, }; =20 static const struct of_device_id mtk_dp_phy_of_match[] =3D { --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A09953DCD83; Thu, 10 Sep 2026 09:20:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032055; cv=none; b=gfJdK6P9KWzzNwfMdGIkpYuU4ebtcGPVDoN0gn1e5eemfcD/o60ncBhWpfjL6nVcEAQ0ML/73GMAJgzxuzOX4Nwh37pttSv9dYhRNnlONwvKjCexuHmdGMB/CwOqPFwVZ1vJuk5hC+dG5vUPhZmM1iWliwST2aUcG0cBGAvq1Co= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032055; c=relaxed/simple; bh=wCt+fRXRNJGhOrrdM1gKT+BP+rAjTu+ESd2chmIHmIo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Thu, 10 Sep 2026 11:20:49 +0200 (CEST) From: AngeloGioacchino Del Regno To: mani@kernel.org Cc: chunfeng.yun@mediatek.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, justin.yeh@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com, Manivannan Sadhasivam Subject: [PATCH v4 09/12] phy: phy-mtk-dp: Rewrite and document default driving param macros Date: Thu, 10 Sep 2026 11:20:35 +0200 Message-ID: <20260910092038.48291-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> References: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use FIELD_PREP_CONST and add nicer definitions/macros to build the default driving parameters for the PHY and, while at it, also add comments explaining what they are supposed to set in the PHY. Reviewed-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-dp.c | 86 +++++++++++++++---------------- 1 file changed, 41 insertions(+), 45 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index 2f4cf52d922c..8e1fc4e16ba6 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -91,51 +91,47 @@ * [2,5,8]: Swing 2 Pre1 and Swing 3 Pre0 */ #define PHYD_DIG_NUM_DRV_PARA_REGS 9 -#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4) -#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12)) -#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19) -#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29) -#define MT8195_DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT = | \ - XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT) - -#define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT GENMASK(4, 3) -#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT GENMASK(12, 9) -#define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (BIT(18) | BIT(21)) -#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29) -#define MT8195_DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT = | \ - XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT) - -#define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT (BIT(3) | BIT(5)) -#define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT GENMASK(13, 12) -#define MT8195_DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT = | \ - XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT) - -#define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0 -#define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT GENMASK(10, 10) -#define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT GENMASK(19, 19) -#define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT GENMASK(28, 28) -#define MT8195_DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT= | \ - XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT) - -#define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0 -#define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT GENMASK(10, 9) -#define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT GENMASK(19, 18) -#define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT 0 -#define MT8195_DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT= | \ - XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT) - -#define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT GENMASK(3, 3) -#define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT 0 -#define MT8195_DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT= | \ - XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) +#define XTP_LN_TX_LCTXC_SW0_PRE0 GENMASK(5, 0) +#define XTP_LN_TX_LCTXC_SW0_PRE1 GENMASK(13, 8) +#define XTP_LN_TX_LCTXC_SW0_PRE2 GENMASK(21, 16) +#define XTP_LN_TX_LCTXC_SW0_PRE3 GENMASK(29, 24) + +#define XTP_LN_TX_LCTXC_SW1_PRE0 GENMASK(5, 0) +#define XTP_LN_TX_LCTXC_SW1_PRE1 GENMASK(13, 8) +#define XTP_LN_TX_LCTXC_SW1_PRE2 GENMASK(21, 16) +#define XTP_LN_TX_LCTXC_SW2_PRE0 GENMASK(29, 24) + +#define XTP_LN_TX_LCTXC_SW2_PRE1 GENMASK(5, 0) +#define XTP_LN_TX_LCTXC_SW3_PRE0 GENMASK(13, 8) + +#define BUILD_DRIVING_PARAM_0(sw0_pre0, sw0_pre1, sw0_pre2, sw0_pre3) ( \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE0, sw0_pre0) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE1, sw0_pre1) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE2, sw0_pre2) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE3, sw0_pre3) \ +) + +#define BUILD_DRIVING_PARAM_12(sw1_pre0, sw1_pre1, sw1_pre2, sw2_pre0) (\ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW1_PRE0, sw1_pre0) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW1_PRE1, sw1_pre1) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW1_PRE2, sw1_pre2) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW2_PRE0, sw2_pre0) \ +) + +#define BUILD_DRIVING_PARAM_23(sw2_pre1, sw3_pre0) ( \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW2_PRE1, sw2_pre1) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW3_PRE0, sw3_pre0) \ +) + +/* MT8195: Logic State Change Point (LC TX C) */ +#define MT8195_DRIVING_PARAM_3_DEFAULT BUILD_DRIVING_PARAM_0( 16, 20, 24, = 32) +#define MT8195_DRIVING_PARAM_4_DEFAULT BUILD_DRIVING_PARAM_12(24, 30, 36, = 32) +#define MT8195_DRIVING_PARAM_5_DEFAULT BUILD_DRIVING_PARAM_23(40, 48) + +/* MT8195: Positive Edge (LC TX CP) */ +#define MT8195_DRIVING_PARAM_6_DEFAULT BUILD_DRIVING_PARAM_0( 0, 4, 8, 16) +#define MT8195_DRIVING_PARAM_7_DEFAULT BUILD_DRIVING_PARAM_12(0, 6, 12, 0) +#define MT8195_DRIVING_PARAM_8_DEFAULT BUILD_DRIVING_PARAM_23(8, 0) =20 enum mtk_dp_phya_ana_glb_regidx { DP_PHYA_GLB_BIAS_GEN_0, --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7B4A3E44EE; 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Thu, 10 Sep 2026 11:20:50 +0200 (CEST) From: AngeloGioacchino Del Regno To: mani@kernel.org Cc: chunfeng.yun@mediatek.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, justin.yeh@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com, Manivannan Sadhasivam Subject: [PATCH v4 10/12] phy: phy-mtk-dp: Add bitrate register val definitions to SoC data Date: Thu, 10 Sep 2026 11:20:36 +0200 Message-ID: <20260910092038.48291-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> References: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for the eDP PHY found in newer SoCs, transfer the bitrate register value definitions to SoC specific data. Reviewed-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-dp.c | 36 +++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index 8e1fc4e16ba6..643666c454f4 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -44,10 +44,6 @@ =20 /* DP_PHYD_BIT_RATE */ #define PHYD_DIG_RG_BIT_RATE GENMASK(1, 0) -# define BIT_RATE_RBR 0 -# define BIT_RATE_HBR 1 -# define BIT_RATE_HBR2 2 -# define BIT_RATE_HBR3 3 =20 /* DP_PHYD_SW_RST */ #define PHYD_DIG_GLB_SW_RST_B GENMASK(7, 0) @@ -163,6 +159,14 @@ enum mtk_dp_phyd_dig_glb_regidx { DP_PHYD_GLOBAL_MAX }; =20 +enum mtk_dp_phyd_bit_rate_regval { + DP_PHYD_BIT_RATE_RBR, + DP_PHYD_BIT_RATE_HBR, + DP_PHYD_BIT_RATE_HBR2, + DP_PHYD_BIT_RATE_HBR3, + DP_PHYD_BIT_RATE_MAX, +}; + static const u8 mt8195_phy_ana_glb_regs[DP_PHYA_GLOBAL_MAX] =3D { [DP_PHYA_GLB_BIAS_GEN_0] =3D 0x0, [DP_PHYA_GLB_BIAS_GEN_1] =3D 0x4, @@ -189,6 +193,13 @@ static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL= _MAX] =3D { [DP_PHYD_TX_CTL_0] =3D 0x44, }; =20 +static const u8 mt8195_phy_dig_bitrate_val[DP_PHYD_BIT_RATE_MAX] =3D { + [DP_PHYD_BIT_RATE_RBR] =3D 0, + [DP_PHYD_BIT_RATE_HBR] =3D 1, + [DP_PHYD_BIT_RATE_HBR2] =3D 2, + [DP_PHYD_BIT_RATE_HBR3] =3D 3 +}; + /** * struct mtk_dp_phya_imp_sel - Per-Lane Impedance Selection * @pmos: Impedance selection for P-Channel MOSFET @@ -209,6 +220,7 @@ struct mtk_dp_phya_imp_sel { * @regs_ana_lane: Register (layout) offsets for ana_lan * @regs_dig_glb: Register (layout) offsets for dig_glb * @regs_dig_lane: Register (layout) offsets for dig_lan + * @val_dig_bitrate:IP Version specific register values for Bit Rate setti= ng * @ana_bias_r: Internal resistance "R" Selection Settings (global) * @ana_cktx_imp: TX Clock Impedance Selection Settings (global) * @ana_lanes_imp: TX Impedance Selection Settings (for all lanes) @@ -227,6 +239,9 @@ struct mtk_dp_phy_pdata { const u8 *regs_dig_glb; const u8 *regs_dig_lane; =20 + /* IP-Version specific register value arrays */ + const u8 *val_dig_bitrate; + /* Calibration defaults */ u8 ana_bias_r; u8 ana_cktx_imp; @@ -310,6 +325,7 @@ static int mtk_dp_phy_configure(struct phy *phy, union = phy_configure_opts *opts) =20 if (opts->dp.set_rate) { const u32 reg_bit_rate =3D pdata->regs_dig_glb[DP_PHYD_BIT_RATE]; + enum mtk_dp_phyd_bit_rate_regval regval_idx; =20 switch (opts->dp.link_rate) { default: @@ -318,19 +334,20 @@ static int mtk_dp_phy_configure(struct phy *phy, unio= n phy_configure_opts *opts) opts->dp.link_rate); return -EINVAL; case 1620: - val =3D BIT_RATE_RBR; + regval_idx =3D DP_PHYD_BIT_RATE_RBR; break; case 2700: - val =3D BIT_RATE_HBR; + regval_idx =3D DP_PHYD_BIT_RATE_HBR; break; case 5400: - val =3D BIT_RATE_HBR2; + regval_idx =3D DP_PHYD_BIT_RATE_HBR2; break; case 8100: - val =3D BIT_RATE_HBR3; + regval_idx =3D DP_PHYD_BIT_RATE_HBR3; break; } - regmap_write(dp_phy->regmap, pdata->off_dig_glb + reg_bit_rate, val); + regmap_write(dp_phy->regmap, pdata->off_dig_glb + reg_bit_rate, + pdata->val_dig_bitrate[regval_idx]); } =20 if (opts->dp.set_lanes) { @@ -713,6 +730,7 @@ static const struct mtk_dp_phy_pdata mt8195_dp_phy_data= =3D { .regs_ana_lane =3D mt8195_phy_ana_lane_regs, .regs_dig_glb =3D mt8195_phy_dig_glb_regs, .regs_dig_lane =3D mt8195_phy_dig_lane_regs, + .val_dig_bitrate =3D mt8195_phy_dig_bitrate_val, .ana_bias_r =3D 15, .ana_cktx_imp =3D 8, .ana_lanes_imp =3D { --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93F373E5EEB; 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Thu, 10 Sep 2026 11:20:51 +0200 (CEST) From: AngeloGioacchino Del Regno To: mani@kernel.org Cc: chunfeng.yun@mediatek.com, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, justin.yeh@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com Subject: [PATCH v4 11/12] phy: phy-mtk-dp: Add PHYD Lane EN register mask to SoC data Date: Thu, 10 Sep 2026 11:20:37 +0200 Message-ID: <20260910092038.48291-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> References: <20260910092038.48291-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for the eDP PHY found in newer SoCs, transfer the register mask for PHYD_TX_LN_EN to SoC specific data. Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-dp.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index 643666c454f4..30f9fa6e6b9b 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -220,6 +220,7 @@ struct mtk_dp_phya_imp_sel { * @regs_ana_lane: Register (layout) offsets for ana_lan * @regs_dig_glb: Register (layout) offsets for dig_glb * @regs_dig_lane: Register (layout) offsets for dig_lan + * @mask_dig_tx_ln: Register mask for PHYD_TX_LN_EN field * @val_dig_bitrate:IP Version specific register values for Bit Rate setti= ng * @ana_bias_r: Internal resistance "R" Selection Settings (global) * @ana_cktx_imp: TX Clock Impedance Selection Settings (global) @@ -239,6 +240,9 @@ struct mtk_dp_phy_pdata { const u8 *regs_dig_glb; const u8 *regs_dig_lane; =20 + /* Register masks */ + u32 mask_dig_tx_ln; + /* IP-Version specific register value arrays */ const u8 *val_dig_bitrate; =20 @@ -355,10 +359,10 @@ static int mtk_dp_phy_configure(struct phy *phy, unio= n phy_configure_opts *opts) =20 val =3D 0; for (i =3D 0; i < opts->dp.lanes; i++) - val |=3D FIELD_PREP(PHYD_TX_LN_EN, BIT(i)); + val |=3D field_prep(pdata->mask_dig_tx_ln, BIT(i)); =20 regmap_update_bits(dp_phy->regmap, pdata->off_dig_glb + reg_dig_tx_ctl, - PHYD_TX_LN_EN, val); + pdata->mask_dig_tx_ln, val); } =20 if (opts->dp.set_voltages) { @@ -422,7 +426,7 @@ static int mtk_dp_phy_disable_all_lanes(struct mtk_dp_p= hy *dp_phy) =20 /* Get mask of currently enabled lane */ regmap_read(dp_phy->regmap, pdata->off_dig_glb + regs[DP_PHYD_TX_CTL_0], = &val); - val =3D FIELD_GET(PHYD_TX_LN_EN, val); + val =3D field_get(pdata->mask_dig_tx_ln, val); if (val =3D=3D 0) return 0; =20 @@ -433,7 +437,7 @@ static int mtk_dp_phy_disable_all_lanes(struct mtk_dp_p= hy *dp_phy) =20 regmap_clear_bits(dp_phy->regmap, pdata->off_dig_glb + regs[DP_PHYD_TX_CTL_0], - FIELD_PREP(PHYD_TX_LN_EN, BIT(lane_num))); + field_prep(pdata->mask_dig_tx_ln, BIT(lane_num))); } while (val); =20 return 0; @@ -730,6 +734,7 @@ static const struct mtk_dp_phy_pdata mt8195_dp_phy_data= =3D { .regs_ana_lane =3D mt8195_phy_ana_lane_regs, .regs_dig_glb =3D mt8195_phy_dig_glb_regs, .regs_dig_lane =3D mt8195_phy_dig_lane_regs, + .mask_dig_tx_ln =3D PHYD_TX_LN_EN, .val_dig_bitrate =3D mt8195_phy_dig_bitrate_val, .ana_bias_r =3D 15, .ana_cktx_imp =3D 8, --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E3B33ED3B4; Thu, 10 Sep 2026 09:20:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789032058; cv=none; b=agU3Uk7K4onFcgVuJ6iMtIi5krACSsxZKdNkExlBoLl2fNFjDK7D1+BLRp2r6vcbyZYR2TSraNHRVGKg+wUSZ2D8KaoO+4jSsKg1gyb7jh9CZ0st6JPlpyAQ7gF6CwQXNDOjBwll7lb9+xEbQ7J43p2FaqYLt65sk8ZUIkiBVZw= ARC-Message-Signature: i=1; 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charset="utf-8" The MT8196 SoC features an updated PHY IP compared to the older ones, and there is one that is specific to Embedded DisplayPort. Add support for the eDP PHY found in the MediaTek MT8196 SoC and all of its variants. Reviewed-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-dp.c | 66 ++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c index 30f9fa6e6b9b..6d06e1c39e3b 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -5,7 +5,7 @@ * Copyright (c) 2022, BayLibre Inc. * Copyright (c) 2022, MediaTek Inc. * - * Major refactoring + * Major refactoring and new SoCs support * Copyright (c) 2026, Collabora Ltd. * AngeloGioacchino Del Regno */ @@ -43,6 +43,7 @@ #define TPLL_SSC_EN BIT(3) =20 /* DP_PHYD_BIT_RATE */ +#define PHYD_DIG_RG_BIT_RATE_V2 GENMASK(3, 0) #define PHYD_DIG_RG_BIT_RATE GENMASK(1, 0) =20 /* DP_PHYD_SW_RST */ @@ -63,6 +64,7 @@ =20 /* DP_PHYD_TX_CTL_0 */ #define PHYD_TX_LN_EN GENMASK(7, 4) +#define PHYD_TX_LN_EN_V2 GENMASK(3, 0) =20 /* DP_PHYD_DRIVING_FORCE */ #define PHYD_DP_TX_FORCE_VOLT_SWING_EN BIT(0) @@ -129,6 +131,16 @@ #define MT8195_DRIVING_PARAM_7_DEFAULT BUILD_DRIVING_PARAM_12(0, 6, 12, 0) #define MT8195_DRIVING_PARAM_8_DEFAULT BUILD_DRIVING_PARAM_23(8, 0) =20 +/* MT8196/MT6991: Logic State Change Point (LC TX C) */ +#define MT8196_DRIVING_PARAM_3_DEFAULT BUILD_DRIVING_PARAM_0( 10, 12, 14, = 17) +#define MT8196_DRIVING_PARAM_4_DEFAULT BUILD_DRIVING_PARAM_12(14, 17, 18, = 18) +#define MT8196_DRIVING_PARAM_5_DEFAULT BUILD_DRIVING_PARAM_23(21, 24) + +/* MT8196/MT6991: Positive Edge (LC TX CP) */ +#define MT8196_DRIVING_PARAM_6_DEFAULT BUILD_DRIVING_PARAM_0( 0, 2, 4, 7) +#define MT8196_DRIVING_PARAM_7_DEFAULT BUILD_DRIVING_PARAM_12(0, 3, 6, 0) +#define MT8196_DRIVING_PARAM_8_DEFAULT BUILD_DRIVING_PARAM_23(3, 0) + enum mtk_dp_phya_ana_glb_regidx { DP_PHYA_GLB_BIAS_GEN_0, DP_PHYA_GLB_BIAS_GEN_1, @@ -184,6 +196,11 @@ static const u8 mt8195_phy_dig_lane_regs[DP_PHYD_LAN_M= AX] =3D { [DP_PHYD_LAN_DRIVING_PARAM_0] =3D 0x2c, }; =20 +static const u8 mt8196_phy_dig_lane_regs[DP_PHYD_LAN_MAX] =3D { + [DP_PHYD_LAN_DRIVING_FORCE] =3D 0x30, + [DP_PHYD_LAN_DRIVING_PARAM_0] =3D 0x34, +}; + static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL_MAX] =3D { [DP_PHYD_PLL_CTL_0] =3D 0x10, [DP_PHYD_PLL_CTL_1] =3D 0x14, @@ -193,6 +210,15 @@ static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL= _MAX] =3D { [DP_PHYD_TX_CTL_0] =3D 0x44, }; =20 +static const u8 mt8196_phy_dig_glb_regs[DP_PHYD_GLOBAL_MAX] =3D { + [DP_PHYD_PLL_CTL_0] =3D 0x10, + [DP_PHYD_PLL_CTL_1] =3D 0x14, + [DP_PHYD_SW_RST] =3D 0x38, + [DP_PHYD_BIT_RATE] =3D 0x3c, + [DP_PHYD_AUX_RX_CTL] =3D 0x40, + [DP_PHYD_TX_CTL_0] =3D 0x74, +}; + static const u8 mt8195_phy_dig_bitrate_val[DP_PHYD_BIT_RATE_MAX] =3D { [DP_PHYD_BIT_RATE_RBR] =3D 0, [DP_PHYD_BIT_RATE_HBR] =3D 1, @@ -200,6 +226,13 @@ static const u8 mt8195_phy_dig_bitrate_val[DP_PHYD_BIT= _RATE_MAX] =3D { [DP_PHYD_BIT_RATE_HBR3] =3D 3 }; =20 +static const u8 mt8196_edp_phy_dig_bitrate_val[DP_PHYD_BIT_RATE_MAX] =3D { + [DP_PHYD_BIT_RATE_RBR] =3D 1, + [DP_PHYD_BIT_RATE_HBR] =3D 4, + [DP_PHYD_BIT_RATE_HBR2] =3D 7, + [DP_PHYD_BIT_RATE_HBR3] =3D 9 +}; + /** * struct mtk_dp_phya_imp_sel - Per-Lane Impedance Selection * @pmos: Impedance selection for P-Channel MOSFET @@ -755,8 +788,39 @@ static const struct mtk_dp_phy_pdata mt8195_dp_phy_dat= a =3D { }, }; =20 +static const struct mtk_dp_phy_pdata mt8196_edp_phy_data =3D { + .off_ana_glb =3D 0x400, + .off_ana_lane =3D (const u16[]) { 0x0, 0x100, 0x200, 0x300 }, + .off_dig_glb =3D 0x1400, + .off_dig_lane =3D (const u16[]) { 0x1000, 0x1100, 0x1200, 0x1300 }, + .regs_ana_glb =3D mt8195_phy_ana_glb_regs, + .regs_ana_lane =3D mt8195_phy_ana_lane_regs, + .regs_dig_glb =3D mt8196_phy_dig_glb_regs, + .regs_dig_lane =3D mt8196_phy_dig_lane_regs, + .mask_dig_tx_ln =3D PHYD_TX_LN_EN_V2, + .val_dig_bitrate =3D mt8196_edp_phy_dig_bitrate_val, + .ana_bias_r =3D 15, + .ana_cktx_imp =3D 8, + .ana_lanes_imp =3D { + .pmos =3D 8, + .nmos =3D 8, + }, + .driving_params =3D (const u32[]) { + [0] =3D 0, + [1] =3D 0, + [2] =3D 0, + [3] =3D MT8196_DRIVING_PARAM_3_DEFAULT, + [4] =3D MT8196_DRIVING_PARAM_4_DEFAULT, + [5] =3D MT8196_DRIVING_PARAM_5_DEFAULT, + [6] =3D MT8196_DRIVING_PARAM_6_DEFAULT, + [7] =3D MT8196_DRIVING_PARAM_7_DEFAULT, + [8] =3D MT8196_DRIVING_PARAM_8_DEFAULT + }, +}; + static const struct of_device_id mtk_dp_phy_of_match[] =3D { { .compatible =3D "mediatek,mt8195-dp-phy", .data =3D &mt8195_dp_phy_data= }, + { .compatible =3D "mediatek,mt8196-edp-phy", .data =3D &mt8196_edp_phy_da= ta }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_dp_phy_of_match); --=20 2.55.0