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charset="utf-8" Define SMCCC Arch function IDs for CLEAN_INV_MEMREGION and its ATTRIBUTES call, and add RATE_LIMITED/BUSY return codes from DEN0028 for callers that need transient error handling. Signed-off-by: Srirangan Madhavan Reviewed-by: Jonathan Cameron Reviewed-by: Bence Cs=C3=B3k=C3=A1s --- include/linux/arm-smccc.h | 21 +++++++++++++++++++-- tools/include/linux/arm-smccc.h | 21 +++++++++++++++++++-- 2 files changed, 38 insertions(+), 4 deletions(-) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 4de81848fe2e..2e205320d88a 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -116,6 +116,22 @@ ARM_SMCCC_SMC_32, \ ARM_SMCCC_OWNER_CPU, 0x10) =20 +/* + * DEN0028 v1.7 defines these cache maintenance functions as SMC64 + * because they carry 64-bit memory range arguments. + */ +#define ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x5) + +#define ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION_ATTRIBUTES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x6) + #define ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID \ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ARM_SMCCC_SMC_32, \ @@ -305,13 +321,14 @@ 0x53) =20 /* - * Return codes defined in ARM DEN 0070A - * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C + * Return codes defined by Arm SMCCC (DEN0028 v1.7). */ #define SMCCC_RET_SUCCESS 0 #define SMCCC_RET_NOT_SUPPORTED -1 #define SMCCC_RET_NOT_REQUIRED -2 #define SMCCC_RET_INVALID_PARAMETER -3 +#define SMCCC_RET_RATE_LIMITED -4 +#define SMCCC_RET_BUSY -5 =20 #ifndef __ASSEMBLY__ =20 diff --git a/tools/include/linux/arm-smccc.h b/tools/include/linux/arm-smcc= c.h index 63ce9bebccd3..ae5637b3240f 100644 --- a/tools/include/linux/arm-smccc.h +++ b/tools/include/linux/arm-smccc.h @@ -96,6 +96,22 @@ ARM_SMCCC_SMC_32, \ 0, 0x3fff) =20 +/* + * DEN0028 v1.7 defines these cache maintenance functions as SMC64 + * because they carry 64-bit memory range arguments. + */ +#define ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x5) + +#define ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION_ATTRIBUTES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x6) + #define ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID \ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ARM_SMCCC_SMC_32, \ @@ -182,12 +198,13 @@ 0x53) =20 /* - * Return codes defined in ARM DEN 0070A - * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C + * Return codes defined by Arm SMCCC (DEN0028 v1.7). */ #define SMCCC_RET_SUCCESS 0 #define SMCCC_RET_NOT_SUPPORTED -1 #define SMCCC_RET_NOT_REQUIRED -2 #define SMCCC_RET_INVALID_PARAMETER -3 +#define SMCCC_RET_RATE_LIMITED -4 +#define SMCCC_RET_BUSY -5 =20 #endif /*__LINUX_ARM_SMCCC_H*/ --=20 2.43.0 From nobody Fri Sep 25 16:50:58 2026 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012001.outbound.protection.outlook.com [40.107.209.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11EE43F0A81; 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charset="utf-8" Add a cache maintenance provider for the Arm SMCCC cache clean+invalidate interface. The provider discovers SMCCC support and attributes at init time, serializes firmware calls, handles transient BUSY and RATE_LIMITED responses with bounded retries, and registers with the generic cache coherency framework used by memregion callers. Signed-off-by: Srirangan Madhavan Reviewed-by: Jonathan Cameron Acked-by: Conor Dooley Reviewed-by: Bence Cs=C3=B3k=C3=A1s --- drivers/cache/Kconfig | 11 +++ drivers/cache/Makefile | 2 + drivers/cache/arm_smccc_cache.c | 149 ++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 drivers/cache/arm_smccc_cache.c diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 1518449d47b5..57fd1823dec5 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -42,6 +42,17 @@ menuconfig CACHEMAINT_FOR_HOTPLUG =20 if CACHEMAINT_FOR_HOTPLUG =20 +config ARM_SMCCC_CACHE + bool "Arm SMCCC cache maintenance provider" + depends on ARM64 && HAVE_ARM_SMCCC_DISCOVERY + help + Enable support for the Arm SMCCC cache clean+invalidate + interface as a provider for memory hotplug-like cache + maintenance operations. + The provider registers only when firmware advertises the + SMCCC calls and attributes, so systems without firmware support + continue without this registered provider. + config HISI_SOC_HHA tristate "HiSilicon Hydra Home Agent (HHA) device driver" depends on (ARM64 && ACPI) || COMPILE_TEST diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index b3362b15d6c1..55736a032d6f 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -4,4 +4,6 @@ obj-$(CONFIG_AX45MP_L2_CACHE) +=3D ax45mp_cache.o obj-$(CONFIG_SIFIVE_CCACHE) +=3D sifive_ccache.o obj-$(CONFIG_STARFIVE_STARLINK_CACHE) +=3D starfive_starlink_cache.o =20 +# Providers below depend on CACHEMAINT_FOR_HOTPLUG. +obj-$(CONFIG_ARM_SMCCC_CACHE) +=3D arm_smccc_cache.o obj-$(CONFIG_HISI_SOC_HHA) +=3D hisi_soc_hha.o diff --git a/drivers/cache/arm_smccc_cache.c b/drivers/cache/arm_smccc_cach= e.c new file mode 100644 index 000000000000..1cfa8f8809d0 --- /dev/null +++ b/drivers/cache/arm_smccc_cache.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 NVIDIA Corporation + * + * Arm SMCCC cache maintenance provider using cache clean+invalidate calls. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMCCC_CACHE_MAX_RETRIES 5 +#define SMCCC_CACHE_DEFAULT_DELAY_US 1000UL +#define SMCCC_CACHE_MAX_DELAY_US 20000UL + +struct smccc_cache { + /* Must be first member */ + struct cache_coherency_ops_inst cci; + struct mutex lock; /* Serializes SMCCC cache maintenance calls. */ + u64 rate_limit; + u32 latency_us; +}; + +static int smccc_cache_status_to_errno(s32 status) +{ + switch (status) { + case SMCCC_RET_SUCCESS: + return 0; + case SMCCC_RET_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SMCCC_RET_INVALID_PARAMETER: + return -EINVAL; + case SMCCC_RET_RATE_LIMITED: + return -EAGAIN; + case SMCCC_RET_BUSY: + return -EBUSY; + default: + return -EIO; + } +} + +static unsigned long smccc_cache_delay_us(const struct smccc_cache *cache) +{ + unsigned long delay_us =3D 0; + + if (cache->rate_limit) + delay_us =3D DIV_ROUND_UP_ULL(USEC_PER_SEC, cache->rate_limit); + + if (cache->latency_us) + delay_us =3D max(delay_us, (unsigned long)cache->latency_us); + + /* + * Firmware may advertise neither a rate limit nor a latency hint; use + * a small bounded backoff instead of retrying in a tight loop. + */ + if (!delay_us) + delay_us =3D SMCCC_CACHE_DEFAULT_DELAY_US; + + return min(delay_us, SMCCC_CACHE_MAX_DELAY_US); +} + +static int smccc_cache_wbinv(struct cache_coherency_ops_inst *cci, + struct cc_inval_params *invp) +{ + struct smccc_cache *cache =3D container_of(cci, struct smccc_cache, cci); + unsigned long delay_us =3D smccc_cache_delay_us(cache); + struct arm_smccc_res res =3D {}; + int ret; + + if (!invp->size) + return -EINVAL; + + /* + * Serialize the full retry sequence. With the default bounds, a caller + * may hold the mutex across up to five 20ms backoff sleeps. + */ + guard(mutex)(&cache->lock); + + for (unsigned int i =3D 0; i < SMCCC_CACHE_MAX_RETRIES; i++) { + /* Long firmware operations can trigger watchdog checks. */ + touch_nmi_watchdog(); + + arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION, + invp->addr, invp->size, 0UL, &res); + + ret =3D smccc_cache_status_to_errno((s32)res.a0); + if (!ret) + return 0; + + if (ret !=3D -EBUSY && ret !=3D -EAGAIN) + return ret; + + fsleep(delay_us); + } + + return ret; +} + +static const struct cache_coherency_ops smccc_cache_ops =3D { + .wbinv =3D smccc_cache_wbinv, +}; + +static int __init smccc_cache_init(void) +{ + struct arm_smccc_res res =3D {}; + struct smccc_cache *cache; + int ret; + + if (arm_smccc_get_version() < ARM_SMCCC_VERSION_1_1) + return -ENODEV; + + if (arm_smccc_1_1_get_conduit() =3D=3D SMCCC_CONDUIT_NONE) + return -ENODEV; + + arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION, &res); + if ((s32)res.a0 < 0) + return -ENODEV; + + arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION_ATTRIBUTES, + &res); + if ((s32)res.a0) + return -ENODEV; + + cache =3D cache_coherency_ops_instance_alloc(&smccc_cache_ops, + struct smccc_cache, cci); + if (!cache) + return -ENOMEM; + + mutex_init(&cache->lock); + cache->latency_us =3D lower_32_bits(res.a2); + cache->rate_limit =3D res.a3; + + ret =3D cache_coherency_ops_instance_register(&cache->cci); + if (ret) { + mutex_destroy(&cache->lock); + cache_coherency_ops_instance_put(&cache->cci); + return ret; + } + + return 0; +} +arch_initcall(smccc_cache_init); --=20 2.43.0