From nobody Fri Sep 25 17:46:10 2026 Received: from ms2.novatek.com.tw (ms2.novatek.com.tw [210.202.87.108]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D18C336EDA; Thu, 10 Sep 2026 03:01:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.202.87.108 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789009296; cv=none; b=KTV1KpfjiNFNV0xp3pYDWzewTFnBkNExqLK7oD3RiX5Q9wykFhnI4Y1sXZ361ATSBNi/ORHpqvyGjb6ukb9ZGhV6GjQ9QN/o8/kZZmb93buP66y9A1BDodSTFYXhWv++WMg1+3HDP4bxcnouIeWzJiFDK+UWiF9jN+MVKL4vv+c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789009296; c=relaxed/simple; bh=EEqiWU7cZvXAzZ9csQjQnedtLTAVMQ0aBVt+/XCpE6A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=f3e7F1FM327E8QVYZN7Xm8PBQwaO0OQ7quYrwki9STga+1jaVEtj54w3X+JWATNKhF/MgCVZc3V9DRliLsD6Ax5/c+OkIUc8sg8LkvR6flSwR/1QL+OrY3YPbDSB0GusRb87uY1gtSverND3kVsh5sWiYppj9sbGCbi+kSbFOno= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=novatek.com.tw; spf=pass smtp.mailfrom=novatek.com.tw; dkim=pass (1024-bit key) header.d=novatek.com.tw header.i=@novatek.com.tw header.b=A5k4To6p; arc=none smtp.client-ip=210.202.87.108 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=novatek.com.tw Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=novatek.com.tw Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=novatek.com.tw header.i=@novatek.com.tw header.b="A5k4To6p" X-UUID: e87934ceacc311f191248d90cf864ef8-20260910 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=novatek.com.tw; s=dk; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=ohXBQ9cjjLeOILIUCU8A0Er0GcQi4hKc916yvsLLEuk=; b=A5k4To6pWe/QkfNlvb911bZEM/4VVBtLZSWMdpSDjMkpIp7h2WMJXLqdo23/69OTtBIQaCoiPcwG3grnubIvSto7Me0qynQbIvxyNtej+tNqZc0d5KgtS6r/7j0pEelsQuDciyqO5oAHo0L6KGn5pDIEMQxHkW21xN/uJ4cXuH8=; X-UUID: e87934ceacc311f191248d90cf864ef8-20260910 Received: from spmgt1 [(172.20.13.10)] by ms2.novatek.com.tw (envelope-from ) (Generic MTA) with ESMTP id 132575931; Thu, 10 Sep 2026 11:01:24 +0800 Received: from oabuild50.novatek.com.tw (oabuild50.novatek.com.tw [172.20.20.160]) by spmgt1 (Postfix) with ESMTP id 6B9EE1A22CB; Thu, 10 Sep 2026 11:01:24 +0800 (CST) Received: by oabuild50.novatek.com.tw (Postfix, from userid 1005) id 0E7EAC600DC; Thu, 10 Sep 2026 11:01:23 +0800 (CST) From: nina_kuo@novatek.com.tw To: andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ben_huang@novatek.com.tw, toby_chui@novatek.com.tw, shihpei_hsu@novatek.com.tw Subject: [PATCH v9 1/3] dt-bindings: i2c: Add Novatek NT72676 I2C controller Date: Thu, 10 Sep 2026 11:01:20 +0800 Message-Id: <20260910030123.215609-2-nina_kuo@novatek.com.tw> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20260910030123.215609-1-nina_kuo@novatek.com.tw> References: <20260910030123.215609-1-nina_kuo@novatek.com.tw> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ben Huang Add Devicetree binding documentation for Novatek NT72676 I2C controller. Signed-off-by: Ben Huang Signed-off-by: Nina Kuo Reviewed-by: Rob Herring (Arm) --- .../bindings/i2c/novatek,nt72676-i2c.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/novatek,nt72676-i= 2c.yaml diff --git a/Documentation/devicetree/bindings/i2c/novatek,nt72676-i2c.yaml= b/Documentation/devicetree/bindings/i2c/novatek,nt72676-i2c.yaml new file mode 100644 index 000000000000..7d9275b1039c --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/novatek,nt72676-i2c.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/novatek,nt72676-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT72676 I2C Controller + +maintainers: + - Ben Huang + - Jason JJ Wu + +description: > + Novatek NT72676 SoC provides multiple I2C controller instances that share + the same register layout and transfer programming model. + + Generic I2C controllers are directly accessible by the host CPU and driv= en + by a 96 MHz AHB clock. + + STBC I2C controllers are driven by a 12 MHz clock from the STBC (Standby + Controller, an 8051-based microcontroller). Before accessing an STBC I2C + controller, the host CPU must authenticate with the STBC and switch + ownership of the controller to the host CPU. The presence of the + novatek,stbc-syscon property identifies an STBC I2C controller requiring + this initialization sequence. + +properties: + compatible: + const: novatek,nt72676-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + default: 100000 + enum: [ 100000, 400000 ] + + novatek,stbc-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: > + Phandle to the STBC system controller used to authenticate host + access and switch ownership of the STBC I2C controller to the host + CPU during initialization. + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c@fc040a00 { + compatible =3D "novatek,nt72676-i2c"; + reg =3D <0xfc040a00 0x40>; + interrupts =3D ; + clocks =3D <&stbc_i2c_clock>; + clock-frequency =3D <400000>; + novatek,stbc-syscon =3D <&stbc>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; --=20 2.40.1 From nobody Fri Sep 25 17:46:10 2026 Received: from ms2.novatek.com.tw (ms2.novatek.com.tw [210.202.87.108]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 433D4386455; Thu, 10 Sep 2026 03:01:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.202.87.108 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789009300; cv=none; b=RgvwlmccOyzJOTyuoV5gLq02A33VmpJN4gPt3jKosQvQgViJGEppo7WFU8p10xZQzs+1UFsAMrJO5AGNNveyUNLHvdZ4NMUF+wt3dloou/DcBR5ZjKYTWWaAJIS6qXK2GSE2MuOeijW7sTAmX44bSgNmMxxFwJnzVzJ6zWMobuU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789009300; c=relaxed/simple; bh=MzxKCpFZXCeneHPDxZ9pMv3Ln78urQNuCjNT4TVUbJM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=l51dRgdRsifRc5aJs5QP+iHaQiSZicvAFdGeVWcDrfN3RGDQdeLsOpEIxf0fwdd7g1oXwxXq9mA7S7erAcJohGOO1SXkjiY/E/ibhWlVDbPVjQ29BBmS8wrGbYErJBSlKp2ohK+IGKWiXU0c4UUMJTMKfptYtdK1DOnIG7mNN8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=novatek.com.tw; spf=pass smtp.mailfrom=novatek.com.tw; dkim=pass (1024-bit key) header.d=novatek.com.tw header.i=@novatek.com.tw header.b=gkg2islp; arc=none smtp.client-ip=210.202.87.108 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=novatek.com.tw Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=novatek.com.tw Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=novatek.com.tw header.i=@novatek.com.tw header.b="gkg2islp" X-UUID: e87a9404acc311f191248d90cf864ef8-20260910 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=novatek.com.tw; s=dk; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=9QGtG+EvhWZchLH6qo6LuCxWM6Wb03f1PdeD7i8VNLg=; b=gkg2islppklugWBZUztohAXWiGOxsqlD7hB8YFqk9Oy5OurfYE1Ex0xYdfOgDu2lbpRuwfHmVfJVigqb91phagRBKSuj4RQ1E1RSiAd4zcEY3Owc1ivTyDLDF9k4RvP9Ul71K7XtH7SEzxBGo/o7tkUcIThP0b4IwC6j0j2kBbQ=; X-UUID: e87a9404acc311f191248d90cf864ef8-20260910 Received: from spmgt1 [(172.20.13.10)] by ms2.novatek.com.tw (envelope-from ) (Generic MTA) with ESMTP id 587303770; Thu, 10 Sep 2026 11:01:24 +0800 Received: from oabuild50.novatek.com.tw (oabuild50.novatek.com.tw [172.20.20.160]) by spmgt1 (Postfix) with ESMTP id 6DC571A22CC; Thu, 10 Sep 2026 11:01:24 +0800 (CST) Received: by oabuild50.novatek.com.tw (Postfix, from userid 1005) id 130F8C600DD; Thu, 10 Sep 2026 11:01:23 +0800 (CST) From: nina_kuo@novatek.com.tw To: andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ben_huang@novatek.com.tw, toby_chui@novatek.com.tw, shihpei_hsu@novatek.com.tw Subject: [PATCH v9 2/3] i2c: nt72676: Add Novatek NT72676 I2C controller driver Date: Thu, 10 Sep 2026 11:01:21 +0800 Message-Id: <20260910030123.215609-3-nina_kuo@novatek.com.tw> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20260910030123.215609-1-nina_kuo@novatek.com.tw> References: <20260910030123.215609-1-nina_kuo@novatek.com.tw> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ben Huang This driver performs the fundamental read/write functions as an I2C controller and supports Standard-mode and Fast-mode. Default operation is Standard-mode. Signed-off-by: Ben Huang Signed-off-by: Nina Kuo --- drivers/i2c/busses/Kconfig | 11 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-nt72676.c | 725 +++++++++++++++++++++++++++++++ 3 files changed, 737 insertions(+) create mode 100644 drivers/i2c/busses/i2c-nt72676.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index d7b89508311f..07ec6046fa51 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -962,6 +962,17 @@ config I2C_NPCM controllers. Driver can also support slave mode (select I2C_SLAVE). =20 +config I2C_NT72676 + tristate "Novatek NT72676 I2C controller" + depends on OF + depends on COMMON_CLK || COMPILE_TEST + help + Say Y here if you want to enable I2C bus controller on + Novatek NT72676 SoC. + This driver performs fundamental read/write functions + as an I2C bus controller and supports Standard-mode and + Fast-mode. Default operation is Standard-mode. + config I2C_OCORES tristate "OpenCores I2C Controller" help diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 3755c54b3d82..e5440de0fe14 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -90,6 +90,7 @@ obj-$(CONFIG_I2C_MV64XXX) +=3D i2c-mv64xxx.o obj-$(CONFIG_I2C_MXS) +=3D i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) +=3D i2c-nomadik.o obj-$(CONFIG_I2C_NPCM) +=3D i2c-npcm7xx.o +obj-$(CONFIG_I2C_NT72676) +=3D i2c-nt72676.o obj-$(CONFIG_I2C_OCORES) +=3D i2c-ocores.o obj-$(CONFIG_I2C_OMAP) +=3D i2c-omap.o obj-$(CONFIG_I2C_OWL) +=3D i2c-owl.o diff --git a/drivers/i2c/busses/i2c-nt72676.c b/drivers/i2c/busses/i2c-nt72= 676.c new file mode 100644 index 000000000000..1308d692fc40 --- /dev/null +++ b/drivers/i2c/busses/i2c-nt72676.c @@ -0,0 +1,725 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026 Novatek Microelectronics Corp. + * Author: Ben Huang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define I2C_REG_CTRL 0x00 +#define I2C_REG_CLK 0x04 +#define I2C_REG_ACK 0x08 +#define I2C_REG_SIZE 0x0C +#define I2C_REG_FIFO1 0x10 +#define I2C_REG_SUBADDR 0x20 +#define I2C_REG_PINGPONG 0x24 +#define I2C_REG_INTR 0x28 +#define I2C_REG_FIFO2 0x2C +#define I2C_REG_DUTY 0x3C +#define I2C_CLR_FIFO1 BIT(7) +#define I2C_CLR_FIFO2 BIT(23) +#define I2C_BUF_LITTLE_ENDIAN BIT(13) +#define I2C_BUSY BIT(1) +#define I2C_ENABLE BIT(2) +#define I2C_REPEAT_ENABLE BIT(7) +#define I2C_READ_OPERATION BIT(8) +#define I2C_NACK BIT(24) +#define I2C_CLOCK_DUTY_ENABLE BIT(21) +#define I2C_CLOCK_STRETCH_ENABLE BIT(27) +#define I2C_MASTER_CLK_STRETCH_ENABLE BIT(28) +#define I2C_TRIGGER BIT(0) +#define I2C_IRQ_CLK_STR_TIMEOUT BIT(12) +#define I2C_IRQ_NACK BIT(11) +#define I2C_IRQ_RX_FULL BIT(10) +#define I2C_IRQ_TX_EMPTY BIT(9) +#define I2C_IRQ_FINISH BIT(8) +#define I2C_IRQ_FLAG (I2C_IRQ_CLK_STR_TIMEOUT |\ + I2C_IRQ_NACK | \ + I2C_IRQ_RX_FULL | \ + I2C_IRQ_TX_EMPTY | \ + I2C_IRQ_FINISH) +#define I2C_IRQ_CLEAR_ALL GENMASK(20, 16) +#define I2C_IRQ_ENABLE_SETTING GENMASK(4, 0) +#define I2C_SUBADDR_ENABLE BIT(6) +#define I2C_16BITSUBADDR_ENABLE BIT(16) +#define I2C_24BITSUBADDR_ENABLE BIT(17) +#define I2C_32BITSUBADDR_ENABLE BIT(18) +#define I2C_ACK_CTRL_COUNTER 0x000001E0 +#define I2C_TX_EMPTY_FIFO1 BIT(6) +#define I2C_TX_EMPTY_FIFO2 BIT(22) +#define I2C_RX_FULL_FIFO1 BIT(5) +#define I2C_RX_FULL_FIFO2 BIT(21) + +#define STBC_REG_PSWD 0x0204 +#define STBC_REG_KEYPASS 0x0208 +#define STBC_REG_I2C_SWITCH 0x0220 +#define STBC_PSWD_DATA1 0x72682 +#define STBC_PSWD_DATA2 0x28627 +#define STBC_KEYPASS_ENABLE BIT(0) +#define STBC_AGPIO_SWITCH_TO_CPU BIT(14) + +#define FIFO_CHUNK_SIZE 16 +#define FIFO_WORD_BYTES 4 + +enum { + SUBADDR_DISABLE =3D 0, + SUBADDR_8BITS, + SUBADDR_16BITS, + SUBADDR_24BITS, + SUBADDR_32BITS, +}; + +#define SUBADDR_MAX_LEN SUBADDR_32BITS + +enum { + FIFO_1 =3D 0, + FIFO_2, + FIFO_ALL +}; + +struct nvt_i2c_bus { + void __iomem *base; + struct i2c_adapter adapter; + struct device *dev; + struct completion msg_complete; + struct clk *clk; + unsigned long input_clk_rate; + unsigned int bus_clk_rate; + bool stbc_i2c; + struct regmap *stbc_regmap; + int irq; + /* lock for msg and reg protection */ + spinlock_t lock; + /* used for xfer, protected by lock */ + struct i2c_msg *current_msg; + int subaddr_mode; + int remaining; + int write_ptr; + int read_ptr; + int fifo_idx; + int error_code; +}; + +static void nt72676_i2c_writel(u32 val, struct nvt_i2c_bus *i2c, unsigned = int reg) +{ + writel(val, i2c->base + reg); +} + +static u32 nt72676_i2c_readl(struct nvt_i2c_bus *i2c, unsigned int reg) +{ + return readl(i2c->base + reg); +} + +static int nvt_i2c_stbc_auth(struct nvt_i2c_bus *i2c) +{ + int ret; + + if (!i2c->stbc_i2c) + return 0; + + ret =3D regmap_write(i2c->stbc_regmap, STBC_REG_PSWD, STBC_PSWD_DATA1); + if (ret) + return ret; + + ret =3D regmap_write(i2c->stbc_regmap, STBC_REG_PSWD, STBC_PSWD_DATA2); + if (ret) + return ret; + + ret =3D regmap_write(i2c->stbc_regmap, STBC_REG_KEYPASS, STBC_KEYPASS_ENA= BLE); + if (ret) + return ret; + + return regmap_update_bits(i2c->stbc_regmap, STBC_REG_I2C_SWITCH, + STBC_AGPIO_SWITCH_TO_CPU, STBC_AGPIO_SWITCH_TO_CPU); +} + +static void nvt_i2c_set_clk(struct nvt_i2c_bus *i2c) +{ + unsigned int clk_div =3D 0; + unsigned int duty =3D 0; + + clk_div =3D i2c->input_clk_rate / i2c->bus_clk_rate; + nt72676_i2c_writel(clk_div << 1, i2c, I2C_REG_CLK); + + duty =3D (clk_div * 9 + 10) / 20; + nt72676_i2c_writel(duty << 16, i2c, I2C_REG_DUTY); + + nt72676_i2c_writel(I2C_ACK_CTRL_COUNTER, i2c, I2C_REG_ACK); +} + +static int nvt_i2c_set_subaddr(struct nvt_i2c_bus *i2c, + const struct i2c_msg *msgs, + int num) +{ + unsigned int i, subaddr =3D 0; + + /* Sub-address can only be a write with maximum size of 4 bytes. */ + if (WARN_ON(num !=3D 2)) + return -EINVAL; + if (!msgs || !msgs[0].buf || + msgs[0].len > i2c->adapter.quirks->max_comb_1st_msg_len || + (msgs[0].flags & I2C_M_RD) || !(msgs[1].flags & I2C_M_RD) || + msgs[0].addr !=3D msgs[1].addr) { + dev_dbg(i2c->dev, "Invalid sub-address format\n"); + return -EOPNOTSUPP; + } + + i2c->subaddr_mode =3D msgs[0].len; + for (i =3D 0; i < msgs[0].len; i++) + subaddr |=3D (unsigned int)msgs[0].buf[i] << (8 * (msgs[0].len - 1 - i)); + nt72676_i2c_writel(subaddr, i2c, I2C_REG_SUBADDR); + + return 0; +} + +static int nvt_i2c_init(struct nvt_i2c_bus *i2c) +{ + if (i2c->stbc_i2c) { + int ret =3D nvt_i2c_stbc_auth(i2c); + + if (ret) + return ret; + } + nt72676_i2c_writel(I2C_IRQ_CLEAR_ALL, i2c, I2C_REG_INTR); + nvt_i2c_set_clk(i2c); + nt72676_i2c_writel(I2C_BUF_LITTLE_ENDIAN, i2c, I2C_REG_PINGPONG); + + return 0; +} + +static void nvt_i2c_reset(struct nvt_i2c_bus *i2c) +{ + nt72676_i2c_writel(I2C_IRQ_CLEAR_ALL, i2c, I2C_REG_INTR); + if (i2c->error_code) { + nt72676_i2c_writel(nt72676_i2c_readl(i2c, I2C_REG_CTRL) & ~I2C_ENABLE, + i2c, I2C_REG_CTRL); + nt72676_i2c_writel(nt72676_i2c_readl(i2c, I2C_REG_CTRL) | I2C_ENABLE, + i2c, I2C_REG_CTRL); + } +} + +static void nvt_i2c_release(struct nvt_i2c_bus *i2c) +{ + nt72676_i2c_writel(nt72676_i2c_readl(i2c, I2C_REG_CTRL) & ~I2C_ENABLE, + i2c, I2C_REG_CTRL); + nt72676_i2c_writel(I2C_IRQ_CLEAR_ALL, i2c, I2C_REG_INTR); +} + +static int nvt_i2c_suspend(struct device *dev) +{ + struct nvt_i2c_bus *i2c =3D dev_get_drvdata(dev); + unsigned long flags; + + i2c_mark_adapter_suspended(&i2c->adapter); + + spin_lock_irqsave(&i2c->lock, flags); + i2c->current_msg =3D NULL; + nvt_i2c_release(i2c); + spin_unlock_irqrestore(&i2c->lock, flags); + + return 0; +} + +static int nvt_i2c_resume(struct device *dev) +{ + struct nvt_i2c_bus *i2c =3D dev_get_drvdata(dev); + int ret =3D nvt_i2c_init(i2c); + + if (ret) { + dev_err(i2c->dev, "Failed to resume\n"); + return ret; + } + + i2c_mark_adapter_resumed(&i2c->adapter); + + return 0; +} + +static void nvt_i2c_clear_fifo(struct nvt_i2c_bus *i2c, unsigned int which) +{ + unsigned int regval =3D nt72676_i2c_readl(i2c, I2C_REG_PINGPONG); + + switch (which) { + case FIFO_1: + regval |=3D I2C_CLR_FIFO1; + break; + case FIFO_2: + regval |=3D I2C_CLR_FIFO2; + break; + case FIFO_ALL: + regval |=3D I2C_CLR_FIFO1 | I2C_CLR_FIFO2; + break; + default: + break; + } + nt72676_i2c_writel(regval, i2c, I2C_REG_PINGPONG); +} + +static void nvt_i2c_write_fifo(struct nvt_i2c_bus *i2c, + unsigned int fifo_reg, + const unsigned char *buf, + unsigned int buf_offset, + unsigned int length) +{ + unsigned int reg_idx =3D 0, copy_bytes =3D 0, j =3D 0, value =3D 0; + + while (length > 0) { + value =3D 0; + copy_bytes =3D min(FIFO_WORD_BYTES, length); + for (j =3D 0; j < copy_bytes; j++) + value |=3D ((unsigned int)buf[buf_offset + j]) << (j * 8); + + nt72676_i2c_writel(value, i2c, fifo_reg + reg_idx * 4); + buf_offset +=3D copy_bytes; + length -=3D copy_bytes; + reg_idx++; + } +} + +static void nvt_i2c_read_fifo(struct nvt_i2c_bus *i2c, + unsigned int fifo_reg, + unsigned char *buf, + unsigned int buf_offset, + unsigned int length) +{ + unsigned int reg_idx =3D 0, copy_bytes =3D 0, j =3D 0, value =3D 0; + + while (length > 0) { + value =3D nt72676_i2c_readl(i2c, fifo_reg + reg_idx * 4); + copy_bytes =3D min(FIFO_WORD_BYTES, length); + for (j =3D 0; j < copy_bytes; j++) + buf[buf_offset + j] =3D (unsigned char)(value >> (j * 8)); + + buf_offset +=3D copy_bytes; + length -=3D copy_bytes; + reg_idx++; + } +} + +static void nvt_i2c_handle(struct nvt_i2c_bus *i2c, struct i2c_msg *msg, b= ool is_read) +{ + unsigned int bytes, fiforeg; + + if (WARN_ON(!msg->buf)) + return; + + bytes =3D min(FIFO_CHUNK_SIZE, i2c->remaining); + fiforeg =3D i2c->fifo_idx =3D=3D FIFO_1 ? I2C_REG_FIFO1 : I2C_REG_FIFO2; + + if (is_read) { + nvt_i2c_read_fifo(i2c, fiforeg, msg->buf, i2c->read_ptr, bytes); + i2c->read_ptr +=3D bytes; + } else { + nvt_i2c_write_fifo(i2c, fiforeg, msg->buf, i2c->write_ptr, bytes); + i2c->write_ptr +=3D bytes; + } + nvt_i2c_clear_fifo(i2c, i2c->fifo_idx); + i2c->remaining -=3D bytes; + i2c->fifo_idx ^=3D 1; +} + +static irqreturn_t nvt_i2c_isr(int irq, void *dev_id) +{ + struct nvt_i2c_bus *i2c =3D dev_id; + unsigned int status, clr =3D 0; + struct i2c_msg *msg; + int do_complete =3D 0; + + spin_lock(&i2c->lock); + status =3D nt72676_i2c_readl(i2c, I2C_REG_INTR); + /* IRQ from other I2C, ignored */ + if (!(status & I2C_IRQ_FLAG)) { + spin_unlock(&i2c->lock); + return IRQ_NONE; + } + + msg =3D i2c->current_msg; + if (!msg) { + nt72676_i2c_writel(I2C_IRQ_CLEAR_ALL, i2c, I2C_REG_INTR); + spin_unlock(&i2c->lock); + return IRQ_HANDLED; + } + + if (status & I2C_IRQ_CLK_STR_TIMEOUT) { + i2c->error_code =3D -ETIMEDOUT; + clr |=3D I2C_IRQ_CLK_STR_TIMEOUT << 8; + } else if (status & I2C_IRQ_NACK) { + i2c->error_code =3D -ENXIO; + clr |=3D I2C_IRQ_NACK << 8; + } else if (status & I2C_IRQ_RX_FULL) { + if (i2c->remaining > 0) + nvt_i2c_handle(i2c, msg, true); + clr |=3D I2C_IRQ_RX_FULL << 8; + } else if (status & I2C_IRQ_TX_EMPTY) { + if (i2c->remaining > 0) + nvt_i2c_handle(i2c, msg, false); + clr |=3D I2C_IRQ_TX_EMPTY << 8; + } else if (status & I2C_IRQ_FINISH) { + if (i2c->remaining > 0 && (msg->flags & I2C_M_RD)) + nvt_i2c_handle(i2c, msg, true); + clr |=3D I2C_IRQ_FINISH << 8; + do_complete =3D 1; + } + if (i2c->error_code) + do_complete =3D 1; + + nt72676_i2c_writel(status | clr, i2c, I2C_REG_INTR); + if (do_complete) + complete(&i2c->msg_complete); + spin_unlock(&i2c->lock); + + return IRQ_HANDLED; +} + +static void nvt_i2c_ctrl_init(struct nvt_i2c_bus *i2c) +{ + int i =3D 0; + + nt72676_i2c_writel(0, i2c, I2C_REG_CTRL); + for (i =3D 0; i < 4; i++) { + nt72676_i2c_writel(0, i2c, I2C_REG_FIFO1 + i * 4); + nt72676_i2c_writel(0, i2c, I2C_REG_FIFO2 + i * 4); + } + nvt_i2c_clear_fifo(i2c, FIFO_ALL); + nt72676_i2c_writel(0, i2c, I2C_REG_SUBADDR); + i2c->subaddr_mode =3D SUBADDR_DISABLE; +} + +static int nvt_i2c_check_msg(const struct i2c_msg *msg) +{ + if (!msg || !msg->buf || !msg->len) + return -EINVAL; + + return 0; +} + +static void nvt_i2c_prepare_xfer(struct nvt_i2c_bus *i2c, struct i2c_msg *= msg) +{ + reinit_completion(&i2c->msg_complete); + i2c->remaining =3D msg->len; + i2c->current_msg =3D msg; + i2c->write_ptr =3D 0; + i2c->read_ptr =3D 0; + i2c->error_code =3D 0; + i2c->fifo_idx =3D FIFO_1; +} + +static int nvt_i2c_write(struct nvt_i2c_bus *i2c, struct i2c_msg *msg) +{ + int ret, offset =3D 0, write_bytes, fifo_num; + unsigned int ctrl_mask =3D 0; + unsigned long flags; + + ret =3D nvt_i2c_check_msg(msg); + if (ret) + return ret; + + spin_lock_irqsave(&i2c->lock, flags); + nvt_i2c_prepare_xfer(i2c, msg); + + nt72676_i2c_writel((msg->len * 8) << 8, i2c, I2C_REG_SIZE); + + /* Write FIFO data first */ + for (fifo_num =3D FIFO_1; fifo_num < FIFO_ALL && offset < msg->len; fifo_= num++) { + write_bytes =3D min(FIFO_CHUNK_SIZE, msg->len - offset); + nvt_i2c_write_fifo(i2c, fifo_num =3D=3D FIFO_1 ? I2C_REG_FIFO1 : I2C_REG= _FIFO2, + msg->buf, offset, write_bytes); + offset +=3D write_bytes; + } + i2c->write_ptr =3D offset; + i2c->remaining =3D msg->len - offset; + i2c->fifo_idx =3D FIFO_1; + + /* Enable interrupt */ + nt72676_i2c_writel(I2C_IRQ_ENABLE_SETTING | I2C_IRQ_CLEAR_ALL, + i2c, I2C_REG_INTR); + + /* Trigger */ + switch (i2c->subaddr_mode) { + case SUBADDR_8BITS: + ctrl_mask |=3D I2C_SUBADDR_ENABLE; + break; + case SUBADDR_16BITS: + ctrl_mask |=3D I2C_SUBADDR_ENABLE | I2C_16BITSUBADDR_ENABLE; + break; + case SUBADDR_24BITS: + ctrl_mask |=3D I2C_SUBADDR_ENABLE | I2C_24BITSUBADDR_ENABLE; + break; + case SUBADDR_32BITS: + ctrl_mask |=3D I2C_SUBADDR_ENABLE | I2C_32BITSUBADDR_ENABLE; + break; + default: + break; + } + ctrl_mask |=3D (((msg->addr << 1) << 8) | I2C_ENABLE | + I2C_CLOCK_DUTY_ENABLE | I2C_CLOCK_STRETCH_ENABLE | + I2C_MASTER_CLK_STRETCH_ENABLE | I2C_TRIGGER); + nt72676_i2c_writel(ctrl_mask, i2c, I2C_REG_CTRL); + spin_unlock_irqrestore(&i2c->lock, flags); + + ret =3D wait_for_completion_timeout(&i2c->msg_complete, i2c->adapter.time= out); + + spin_lock_irqsave(&i2c->lock, flags); + if (!ret) + i2c->error_code =3D -ETIMEDOUT; + nvt_i2c_reset(i2c); + ret =3D i2c->error_code; + i2c->current_msg =3D NULL; + spin_unlock_irqrestore(&i2c->lock, flags); + + if (ret) + dev_dbg(i2c->dev, "Write failed (err:%d); SA[0x%X]\n", + i2c->error_code, msg->addr); + + return ret; +} + +static int nvt_i2c_read(struct nvt_i2c_bus *i2c, struct i2c_msg *msg) +{ + unsigned int ctrl_mask =3D 0; + unsigned long flags; + int ret; + + ret =3D nvt_i2c_check_msg(msg); + if (ret) + return ret; + + spin_lock_irqsave(&i2c->lock, flags); + nvt_i2c_prepare_xfer(i2c, msg); + + nt72676_i2c_writel((msg->len * 8) << 8, i2c, I2C_REG_SIZE); + + /* Enable interrupt */ + nt72676_i2c_writel(I2C_IRQ_ENABLE_SETTING | I2C_IRQ_CLEAR_ALL, + i2c, I2C_REG_INTR); + + /* Trigger */ + switch (i2c->subaddr_mode) { + case SUBADDR_8BITS: + ctrl_mask |=3D I2C_SUBADDR_ENABLE; + break; + case SUBADDR_16BITS: + ctrl_mask |=3D I2C_SUBADDR_ENABLE | I2C_16BITSUBADDR_ENABLE; + break; + case SUBADDR_24BITS: + ctrl_mask |=3D I2C_SUBADDR_ENABLE | I2C_24BITSUBADDR_ENABLE; + break; + case SUBADDR_32BITS: + ctrl_mask |=3D I2C_SUBADDR_ENABLE | I2C_32BITSUBADDR_ENABLE; + break; + default: + break; + } + ctrl_mask |=3D (((msg->addr << 1) << 8) | I2C_ENABLE | + I2C_REPEAT_ENABLE | I2C_READ_OPERATION | + I2C_CLOCK_DUTY_ENABLE | I2C_CLOCK_STRETCH_ENABLE | + I2C_MASTER_CLK_STRETCH_ENABLE | I2C_TRIGGER); + nt72676_i2c_writel(ctrl_mask, i2c, I2C_REG_CTRL); + spin_unlock_irqrestore(&i2c->lock, flags); + + ret =3D wait_for_completion_timeout(&i2c->msg_complete, i2c->adapter.time= out); + + spin_lock_irqsave(&i2c->lock, flags); + if (!ret) + i2c->error_code =3D -ETIMEDOUT; + nvt_i2c_reset(i2c); + ret =3D i2c->error_code; + i2c->current_msg =3D NULL; + spin_unlock_irqrestore(&i2c->lock, flags); + + if (ret) + dev_dbg(i2c->dev, "Read failed (err:%d); SA[0x%X]\n", + i2c->error_code, msg->addr); + + return ret; +} + +static int nvt_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg msgs[], + int num) +{ + struct nvt_i2c_bus *i2c =3D i2c_get_adapdata(adap); + struct i2c_msg *msg =3D &msgs[0]; + int ret =3D 0; + + nvt_i2c_ctrl_init(i2c); + + if (num =3D=3D 2) { + ret =3D nvt_i2c_set_subaddr(i2c, msgs, num); + if (ret) + return ret; + msg =3D &msgs[1]; + } + + if (msg->flags & I2C_M_RD) + ret =3D nvt_i2c_read(i2c, msg); + else + ret =3D nvt_i2c_write(i2c, msg); + + if (ret < 0) + return ret; + return num; +} + +static u32 nvt_i2c_func(struct i2c_adapter *adap) +{ + return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL) & ~I2C_FUNC_SMBUS_QUICK; +} + +static const struct i2c_algorithm nvt_i2c_algo =3D { + .master_xfer =3D nvt_i2c_xfer, + .functionality =3D nvt_i2c_func, +}; + +static int nvt_i2c_parse_dts(struct nvt_i2c_bus *i2c) +{ + struct device *dev =3D i2c->dev; + struct device_node *np =3D dev->of_node; + int ret; + + /* read DTS(novatek,stbc-syscon) for STBC I2C */ + i2c->stbc_i2c =3D of_property_present(dev->of_node, "novatek,stbc-syscon"= ); + if (i2c->stbc_i2c) { + i2c->stbc_regmap =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "novatek,stbc-syscon"); + if (IS_ERR(i2c->stbc_regmap)) + return dev_err_probe(dev, PTR_ERR(i2c->stbc_regmap), + "Failed to get STBC syscon\n"); + } + + /* read DTS(clock-frequency) */ + ret =3D of_property_read_u32(np, "clock-frequency", &i2c->bus_clk_rate); + if (ret || !i2c->bus_clk_rate) { + dev_info(dev, "Not set dtb clock-frequency, set default 100kHz\n"); + i2c->bus_clk_rate =3D I2C_MAX_STANDARD_MODE_FREQ; + } + + return 0; +} + +static const struct of_device_id nvt_i2c_of_match[] =3D { + { .compatible =3D "novatek,nt72676-i2c" }, + { } +}; +MODULE_DEVICE_TABLE(of, nvt_i2c_of_match); + +static const struct i2c_adapter_quirks nvt_i2c_quirks =3D { + .flags =3D I2C_AQ_COMB_WRITE_THEN_READ | I2C_AQ_NO_ZERO_LEN, + .max_num_msgs =3D 2, + .max_write_len =3D 4096, + .max_read_len =3D 4096, + .max_comb_1st_msg_len =3D SUBADDR_MAX_LEN, + .max_comb_2nd_msg_len =3D 4096, +}; + +static int nvt_i2c_probe(struct platform_device *pdev) +{ + struct nvt_i2c_bus *i2c; + int ret; + + i2c =3D devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + + i2c->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(i2c->base)) + return PTR_ERR(i2c->base); + + spin_lock_init(&i2c->lock); + init_completion(&i2c->msg_complete); + i2c->dev =3D &pdev->dev; + + ret =3D nvt_i2c_parse_dts(i2c); + if (ret) + return ret; + + i2c->clk =3D devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(i2c->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), + "devm_clk_get_enabled fail\n"); + + i2c->input_clk_rate =3D clk_get_rate(i2c->clk); + if (!i2c->input_clk_rate) + return dev_err_probe(&pdev->dev, -EINVAL, "Invalid input clock rate\n"); + + if (i2c->input_clk_rate < i2c->bus_clk_rate) + return dev_err_probe(&pdev->dev, -EINVAL, + "Input clock rate %lu is lower than bus frequency %u\n", + i2c->input_clk_rate, i2c->bus_clk_rate); + + i2c->irq =3D platform_get_irq(pdev, 0); + if (i2c->irq < 0) + return i2c->irq; + + ret =3D nvt_i2c_init(i2c); + if (ret) + return dev_err_probe(&pdev->dev, ret, "nvt_i2c_init fail\n"); + + ret =3D devm_request_irq(&pdev->dev, i2c->irq, nvt_i2c_isr, + IRQF_SHARED, dev_name(&pdev->dev), i2c); + if (ret) { + nvt_i2c_release(i2c); + return dev_err_probe(&pdev->dev, ret, "devm_request_irq fail\n"); + } + + /* Setup I2C adapter */ + i2c->adapter.owner =3D THIS_MODULE; + i2c->adapter.algo =3D &nvt_i2c_algo; + i2c->adapter.dev.of_node =3D pdev->dev.of_node; + i2c->adapter.dev.parent =3D &pdev->dev; + i2c->adapter.quirks =3D &nvt_i2c_quirks; + i2c->adapter.timeout =3D 3 * HZ; + strscpy(i2c->adapter.name, dev_name(&pdev->dev), sizeof(i2c->adapter.name= )); + i2c_set_adapdata(&i2c->adapter, i2c); + + ret =3D i2c_add_adapter(&i2c->adapter); + if (ret) { + nvt_i2c_release(i2c); + return dev_err_probe(&pdev->dev, ret, "Failed to add adapter\n"); + } + + platform_set_drvdata(pdev, i2c); + + return 0; +} + +static void nvt_i2c_remove(struct platform_device *pdev) +{ + struct nvt_i2c_bus *i2c =3D platform_get_drvdata(pdev); + unsigned long flags; + + i2c_del_adapter(&i2c->adapter); + spin_lock_irqsave(&i2c->lock, flags); + nvt_i2c_release(i2c); + spin_unlock_irqrestore(&i2c->lock, flags); +} + +static const struct dev_pm_ops nvt_i2c_pm_ops =3D { + .resume_early =3D nvt_i2c_resume, + .suspend_late =3D nvt_i2c_suspend, +}; + +static struct platform_driver nvt_i2c_driver =3D { + .probe =3D nvt_i2c_probe, + .remove =3D nvt_i2c_remove, + .driver =3D { + .name =3D "nt72676_i2c", + .pm =3D &nvt_i2c_pm_ops, + .of_match_table =3D of_match_ptr(nvt_i2c_of_match), + }, +}; +module_platform_driver(nvt_i2c_driver); + +MODULE_DESCRIPTION("Novatek NT72676 SoC I2C Bus Driver"); +MODULE_AUTHOR("Ben Huang "); +MODULE_LICENSE("GPL"); --=20 2.40.1 From nobody Fri Sep 25 17:46:10 2026 Received: from ms2.novatek.com.tw (ms2.novatek.com.tw [210.202.87.108]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A435359A89; Thu, 10 Sep 2026 03:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.202.87.108 ARC-Seal: i=1; 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Thu, 10 Sep 2026 11:01:24 +0800 (CST) Received: by oabuild50.novatek.com.tw (Postfix, from userid 1005) id 16431C600DD; Thu, 10 Sep 2026 11:01:23 +0800 (CST) From: nina_kuo@novatek.com.tw To: andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ben_huang@novatek.com.tw, toby_chui@novatek.com.tw, shihpei_hsu@novatek.com.tw Subject: [PATCH v9 3/3] MAINTAINERS: Add entry for Novatek NT72676 I2C controller driver Date: Thu, 10 Sep 2026 11:01:22 +0800 Message-Id: <20260910030123.215609-4-nina_kuo@novatek.com.tw> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20260910030123.215609-1-nina_kuo@novatek.com.tw> References: <20260910030123.215609-1-nina_kuo@novatek.com.tw> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ben Huang Add a maintainer entry for Novatek NT72676 I2C controller driver. Signed-off-by: Ben Huang Signed-off-by: Nina Kuo --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c392ded5322a..40a22cfa206a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19437,6 +19437,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/g= it/nolibc/linux-nolibc.git F: tools/include/nolibc/ F: tools/testing/selftests/nolibc/ =20 +NOVATEK NT72676 I2C CONTROLLER DRIVER +M: Ben Huang +L: linux-i2c@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/i2c/novatek,nt72676-i2c.yaml +F: drivers/i2c/busses/i2c-nt72676.c + NOVATEK NVT-TS I2C TOUCHSCREEN DRIVER M: Hans de Goede L: linux-input@vger.kernel.org --=20 2.40.1