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Thu, 10 Sep 2026 16:11:36 +0200 From: Patrice Chotard Date: Thu, 10 Sep 2026 16:11:22 +0200 Subject: [PATCH 1/3] dt-bindings: nvmem: add binding for STM32MPX TAMP backup registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260910-upstream_nvram_reworked-v1-1-521c16175cef@foss.st.com> References: <20260910-upstream_nvram_reworked-v1-0-521c16175cef@foss.st.com> In-Reply-To: <20260910-upstream_nvram_reworked-v1-0-521c16175cef@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Christophe Roullier , Srinivas Kandagatla CC: Simeon Marijon , , , , , Patrice Chotard X-Mailer: b4 0.16.0 X-ClientProxiedBy: STKCAS1NODE1.st.com (10.75.128.134) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MI3PEPF00008481:EE_|AS4PR10MB5647:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fceb9c1-4ede-43cd-f707-08df0f456dbf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|23010399003|18002099003|22082099003|56012099006|3023799007|10067099003|11063799006; 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The backup registers is a part of the TAMP device of STM32 MPU. Signed-off-by: Simeon Marijon Signed-off-by: Patrice Chotard Reviewed-by: Rob Herring (Arm) --- .../bindings/nvmem/st,stm32-tamp-nvram.yaml | 57 ++++++++++++++++++= ++++ MAINTAINERS | 7 +++ 2 files changed, 64 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/st,stm32-tamp-nvram.ya= ml b/Documentation/devicetree/bindings/nvmem/st,stm32-tamp-nvram.yaml new file mode 100644 index 000000000000..4af3b88db566 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/st,stm32-tamp-nvram.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/st,stm32-tamp-nvram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 backup registers as NVMEM + +description: | + This represents STM32 backup registers area presented as nvmem cells. + This contains various information (e.g. boot mode passed to bootloaders). + +maintainers: + - Simeon Marijon + - Patrice Chotard + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + enum: + - st,stm32mp15-tamp-nvram + - st,stm32mp25-tamp-nvram + + reg: + description: + TAMP Registers bank location and size. + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + nvram: nvram@5c00a100 { + reg =3D <0x5c00a100 0x80>; + compatible =3D "st,stm32mp15-tamp-nvram"; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + /* Data cells */ + wakeup_sec: tamp-bkp@0 { + reg =3D <0x0 0x4>; + }; + boot_mode: tamp-bkp@50 { + /*see boot mode selection feature*/ + reg =3D <0x50 0x4>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 3a19da74d00c..b634c037c229 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26261,6 +26261,13 @@ F: Documentation/arch/arm/stm32/stm32-dma-mdma-cha= ining.rst F: Documentation/devicetree/bindings/dma/stm32/ F: drivers/dma/stm32/ =20 +STM32 TAMP DRIVERS +M: Simeon Marijon +M: Patrice Chotard +L: linux-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/nvmem/st,stm32-tamp-nvram.yaml + STM32 TIMER/LPTIMER DRIVERS M: Fabrice Gasnier S: Maintained --=20 2.43.0 From nobody Fri Sep 25 16:04:38 2026 Received: from OSPPR02CU001.outbound.protection.outlook.com (mail-norwayeastazon11013069.outbound.protection.outlook.com [40.107.159.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C052A33B97D; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XNY4kiQZp/HNRS0IgvGpU4WC3oEhPLqzC4MrYqg0mNf0OF+a4aqn8WsRJ3z2YTZYyiPeBly/4QgUNfDlq4tz2KAbWKRF20MajJ+JM0cC7C6KL5z9TjISEqEH20dnSgnb5zuiYv6isPXUXi70/wEn5BDIuPATxX+ewMuWVV6ybXOs316Q4TkJcggRS7MosH23OtDLLC8d/eTQTDPYm3d5krsyQxeS/hNKClDMfZ5QdS8Bt42cdPbe+sJpk1pk46WiETflWMmO368UvHIhBpbEnNaemBW3RgZ6ne6Cyrydo0PtS4ksfJ8zULfTHIGocl3IkSGlKabQOxLAJ+X9a+DgDEy5OFWFkZmxU3HzubQgvBcZ5thEy0tkYAEBebk9XwaM3Wr1hTLO5ho0qCjDdAxolbmSrR4SrsWhgOEw+Wz0ii6gv3QtCVInEwdkHuuPkKFd X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 14:11:38.6920 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f576c7d-f4d7-4ac7-0728-08df0f456e4f X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: MI3PEPF00008481.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MI3PR10MB9922 The STM32 TAMP node (compatible "st,stm32-tamp", "syscon", "simple-mfd") exposes its backup registers through an nvram child node described by nvmem/st,stm32-tamp-nvram.yaml. That requires the TAMP node to carry "#address-cells", "#size-cells", "ranges" and an "nvram@..." child. st,stm32-syscon.yaml uses "additionalProperties: false" and only allowed reg/clocks/#clock-cells, so wiring the nvram provider into the DTSI made "make dtbs_check" fail on every STM32MP TAMP node: tamp@5c00a000 (st,stm32-tamp): '#address-cells', '#size-cells', 'nvram@5c00a100', 'ranges' do not match any of the regexes: '^pinctrl-[0-9]+$' Allow the addressing properties and the nvram child, gated on the st,stm32-tamp compatible so the other syscon variants stay strict. "#size-cells" may be 1 or 2: the STM32MP21 soc bus uses two size cells (an empty "ranges" requires the node to match its parent) while the other STM32MP SoCs use one. Signed-off-by: Patrice Chotard --- .../bindings/arm/stm32/st,stm32-syscon.yaml | 28 ++++++++++++++++++= ++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.ya= ml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 95d2319afe23..8a0e751591f6 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -39,6 +39,21 @@ properties: "#clock-cells": const: 0 =20 + "#address-cells": + const: 1 + + "#size-cells": + enum: [1, 2] + + ranges: true + +patternProperties: + "^nvram@[0-9a-f]+$": + type: object + description: + TAMP backup registers exposed as an NVMEM provider. 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Each registers ([0..127] for STM32MP2, [0..31] for STM32MP1) could be exposed as nvmem cells under the nvram node in device tree. Signed-off-by: Simeon Marijon Signed-off-by: Gatien Chevallier Signed-off-by: Patrice Chotard --- MAINTAINERS | 1 + drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/stm32-tamp-nvram.c | 729 +++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 742 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b634c037c229..63c69f8a93f0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26267,6 +26267,7 @@ M: Patrice Chotard L: linux-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/nvmem/st,stm32-tamp-nvram.yaml +F: drivers/nvmem/stm32-tamp-nvram.c =20 STM32 TIMER/LPTIMER DRIVERS M: Fabrice Gasnier diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index c36c2a4c2a0b..1d71d0097bc2 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -504,6 +504,16 @@ config NVMEM_STM32_ROMEM This driver can also be built as a module. If so, the module will be called nvmem-stm32-romem. =20 +config NVMEM_STM32_TAMP + tristate "STMicroelectronics STM32 TAMP backup registers support" + depends on ARCH_STM32 || COMPILE_TEST + help + Say y here to enable access for STMicroelectronics STM32 + TAMP backup registers. + + This driver can also be built as a module. If so, the module + will be called nvmem_stm32_tamp_nvram + config NVMEM_SUNPLUS_OCOTP tristate "Sunplus SoC OTP support" depends on SOC_SP7021 || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 2bbfb9ff1885..2e9c55d1855a 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -86,6 +86,8 @@ nvmem_sprd_efuse-y :=3D sprd-efuse.o obj-$(CONFIG_NVMEM_STM32_ROMEM) +=3D nvmem_stm32_romem.o nvmem_stm32_romem-y :=3D stm32-romem.o nvmem_stm32_romem-$(CONFIG_NVMEM_STM32_BSEC_OPTEE_TA) +=3D stm32-bsec-opte= e-ta.o +obj-$(CONFIG_NVMEM_STM32_TAMP) +=3D nvmem_stm32_tamp_nvram.o +nvmem_stm32_tamp_nvram-y :=3D stm32-tamp-nvram.o obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) +=3D nvmem_sunplus_ocotp.o nvmem_sunplus_ocotp-y :=3D sunplus-ocotp.o obj-$(CONFIG_NVMEM_SUNXI_SID) +=3D nvmem_sunxi_sid.o diff --git a/drivers/nvmem/stm32-tamp-nvram.c b/drivers/nvmem/stm32-tamp-nv= ram.c new file mode 100644 index 000000000000..4cb305429fa4 --- /dev/null +++ b/drivers/nvmem/stm32-tamp-nvram.c @@ -0,0 +1,729 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STM32 Tamp backup registers access driver + * + * Copyright (C) 2026, STMicroelectronics - All Rights Reserved + * Author: Simeon Marijon for STMicroelectron= ics. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RIF_CID1 0x1 +#define CURRENT_CID RIF_CID1 +#define NB_ZONES_STM32MP1 3 +#define NB_ZONES_STM32MP2 7 +#define NB_REGS_STM32MP1 32 +#define NB_REGS_STM32MP2 128 + +#define _TAMP_SECCFGR 0x20U +#define _TAMP_BKPRIFR(x) (0x70U + 0x4U * ((x) - 1)) +#define _TAMP_RXCIDCFGR(x) (0x80U + 0x4U * ((x))) + +#define BKPREG_PROTECTION_ZONE_1 0 +#define BKPREG_PROTECTION_ZONE_2 1 +#define BKPREG_PROTECTION_ZONE_3 2 + +#define BKPREG_PROTECTION_ZONE_1_RIF1 0 +#define BKPREG_PROTECTION_ZONE_1_RIF2 1 +#define BKPREG_PROTECTION_ZONE_2_RIF1 2 +#define BKPREG_PROTECTION_ZONE_2_RIF2 3 +#define BKPREG_PROTECTION_ZONE_3_RIF1 4 +#define BKPREG_PROTECTION_ZONE_3_RIF0 5 +#define BKPREG_PROTECTION_ZONE_3_RIF2 6 +#define NB_COMPARTMENT_STM32MP2 3 + +enum stm32_tamp_bkpreg_access { + BKP_READ_WRITE, + BKP_READ, + BKP_NO +}; + +struct stm32_tamp_nvram_priv { + struct nvmem_config cfg; + const struct stm32_tamp_nvram_plat *data; + int *idx_bkpreg_zones_end; + struct device *dev; + struct regmap *config_regmap; + struct regmap *bkpregs_regmap; + enum stm32_tamp_bkpreg_access *bkpreg_access; +}; + +struct stm32_tamp_nvram_plat { + const unsigned int nb_zones; + const unsigned int nb_regs; + const struct regmap_config *bkpregs_regmap_cfg; + const struct reg_field *config_reg_fields; +}; + +static const struct reg_field stm32mp1_tamp_nvram_zone_cfg_fields[NB_ZONES= _STM32MP1 - 1] =3D { + [BKPREG_PROTECTION_ZONE_1] =3D REG_FIELD(_TAMP_SECCFGR, 0, 7), + [BKPREG_PROTECTION_ZONE_2] =3D REG_FIELD(_TAMP_SECCFGR, 16, 23), +}; + +static const struct reg_field stm32mp25_tamp_nvram_zone_cfg_fields[NB_ZONE= S_STM32MP2 - 1] =3D { + [BKPREG_PROTECTION_ZONE_1_RIF1] =3D REG_FIELD(_TAMP_BKPRIFR(1), 0, 7), + [BKPREG_PROTECTION_ZONE_1_RIF2] =3D REG_FIELD(_TAMP_SECCFGR, 0, 7), + [BKPREG_PROTECTION_ZONE_2_RIF1] =3D REG_FIELD(_TAMP_BKPRIFR(2), 0, 7), + [BKPREG_PROTECTION_ZONE_2_RIF2] =3D REG_FIELD(_TAMP_SECCFGR, 16, 23), + [BKPREG_PROTECTION_ZONE_3_RIF1] =3D REG_FIELD(_TAMP_BKPRIFR(3), 0, 7), + [BKPREG_PROTECTION_ZONE_3_RIF0] =3D REG_FIELD(_TAMP_BKPRIFR(3), 16, 23), +}; + +static const struct reg_field stm32mp25_tamp_nvram_rxcidcfg_cfen_fields[NB= _COMPARTMENT_STM32MP2] =3D { + REG_FIELD(_TAMP_RXCIDCFGR(0), 0, 0), + REG_FIELD(_TAMP_RXCIDCFGR(1), 0, 0), + REG_FIELD(_TAMP_RXCIDCFGR(2), 0, 0), +}; + +static const struct reg_field stm32mp25_tamp_nvram_rxcidcfg_fields[NB_COMP= ARTMENT_STM32MP2] =3D { + REG_FIELD(_TAMP_RXCIDCFGR(0), 4, 6), + REG_FIELD(_TAMP_RXCIDCFGR(1), 4, 6), + REG_FIELD(_TAMP_RXCIDCFGR(2), 4, 6), +}; + +static enum stm32_tamp_bkpreg_access stm32mp1_tamp_bkpreg_access[NB_ZONES_= STM32MP1] =3D { + [BKPREG_PROTECTION_ZONE_1] =3D BKP_NO, + [BKPREG_PROTECTION_ZONE_2] =3D BKP_READ, + [BKPREG_PROTECTION_ZONE_3] =3D BKP_READ_WRITE, +}; + +static int stm32_tamp_is_compartment_isolation_enabled_mp2x(struct stm32_t= amp_nvram_priv *priv) +{ + int nb_compartment_enabled =3D 0; + struct device *dev =3D priv->dev; + u32 cfen; + struct regmap_field *cfen_field; + + for (int i =3D 0; i < NB_COMPARTMENT_STM32MP2; i++) { + cfen_field =3D devm_regmap_field_alloc(dev, + priv->config_regmap, + stm32mp25_tamp_nvram_rxcidcfg_cfen_fields[i]); + if (IS_ERR(cfen_field)) { + dev_err(dev, "Can't allocate field for reading configuration\n"); + return -ENOMEM; + } + + if (regmap_field_read(cfen_field, &cfen)) { + dev_err(dev, "Can't read field for registers zones\n"); + devm_regmap_field_free(dev, cfen_field); + return -EINVAL; + } + + nb_compartment_enabled +=3D cfen; + devm_regmap_field_free(dev, cfen_field); + } + + if (!nb_compartment_enabled) + return 0; + else if (nb_compartment_enabled =3D=3D NB_COMPARTMENT_STM32MP2) + return 1; + else + return -EINVAL; +} + +static bool *stm32_tamp_get_compartment_owner_mp2x(struct stm32_tamp_nvram= _priv *priv) +{ + struct device *dev =3D priv->dev; + struct regmap_field *cid_field; + u32 cid_per_zone; + int isolation_enabled; + bool *compartment_owner; + + isolation_enabled =3D stm32_tamp_is_compartment_isolation_enabled_mp2x(pr= iv); + if (isolation_enabled < 0) + return ERR_PTR(-EINVAL); + + compartment_owner =3D devm_kcalloc(dev, + NB_COMPARTMENT_STM32MP2, + sizeof(*compartment_owner), + GFP_KERNEL); + + if (!compartment_owner) + return ERR_PTR(-ENOMEM); + + for (int i =3D 0; i < NB_COMPARTMENT_STM32MP2; i++) { + if (isolation_enabled) { + cid_field =3D devm_regmap_field_alloc(dev, + priv->config_regmap, + stm32mp25_tamp_nvram_rxcidcfg_fields[i] + ); + if (IS_ERR(cid_field)) + return ERR_PTR(-ENOMEM); + + if (regmap_field_read(cid_field, &cid_per_zone)) { + dev_err(dev, "Can't read field for registers zones\n"); + devm_regmap_field_free(dev, cid_field); + devm_kfree(dev, compartment_owner); + return ERR_PTR(-EINVAL); + } + + if (cid_per_zone =3D=3D CURRENT_CID) + compartment_owner[i] =3D true; + else + compartment_owner[i] =3D false; + + devm_regmap_field_free(dev, cid_field); + } else { + compartment_owner[i] =3D true; + } + } + + return compartment_owner; +} + +static enum stm32_tamp_bkpreg_access *stm32_tamp_get_access_rights_mp2x(st= ruct stm32_tamp_nvram_priv + *priv) +{ + struct device *dev =3D priv->dev; + unsigned int nb_zones =3D priv->data->nb_zones; + bool *compartment_owner; + enum stm32_tamp_bkpreg_access *bkpreg_access; + + compartment_owner =3D stm32_tamp_get_compartment_owner_mp2x(priv); + if (IS_ERR(compartment_owner)) + return ERR_PTR(-ENODEV); + + bkpreg_access =3D devm_kcalloc(dev, + NB_ZONES_STM32MP2, + sizeof(*bkpreg_access), + GFP_KERNEL); + + if (!bkpreg_access) + return ERR_PTR(-ENOMEM); + + for (int protection_zone_idx =3D 0; protection_zone_idx < nb_zones; + protection_zone_idx++) { + switch (protection_zone_idx) { + case BKPREG_PROTECTION_ZONE_1_RIF1: + bkpreg_access[protection_zone_idx] =3D BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_1_RIF2: + bkpreg_access[protection_zone_idx] =3D BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_2_RIF1: + if (compartment_owner[1] || compartment_owner[2]) + bkpreg_access[protection_zone_idx] =3D BKP_READ; + else + bkpreg_access[protection_zone_idx] =3D BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_2_RIF2: + if (compartment_owner[1] || compartment_owner[2]) + bkpreg_access[protection_zone_idx] =3D BKP_READ; + else + bkpreg_access[protection_zone_idx] =3D BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_3_RIF1: + if (compartment_owner[1]) + bkpreg_access[protection_zone_idx] =3D BKP_READ_WRITE; + else if (compartment_owner[0] || compartment_owner[2]) + bkpreg_access[protection_zone_idx] =3D BKP_READ; + else + bkpreg_access[protection_zone_idx] =3D BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_3_RIF0: + if (compartment_owner[0]) + bkpreg_access[protection_zone_idx] =3D BKP_READ_WRITE; + else if (compartment_owner[1] || compartment_owner[2]) + bkpreg_access[protection_zone_idx] =3D BKP_READ; + else + bkpreg_access[protection_zone_idx] =3D BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_3_RIF2: + if (compartment_owner[2]) + bkpreg_access[protection_zone_idx] =3D BKP_READ_WRITE; + else if (compartment_owner[0] || compartment_owner[1]) + bkpreg_access[protection_zone_idx] =3D BKP_READ; + else + bkpreg_access[protection_zone_idx] =3D BKP_NO; + break; + default: + devm_kfree(dev, bkpreg_access); + return ERR_PTR(-ENODEV); + } + } + + return bkpreg_access; +} + +static int stm32_tamp_nvram_bkpreg_get_zone(struct stm32_tamp_nvram_priv *= priv, int reg) +{ + int *idx_bkpreg_zones_end =3D priv->idx_bkpreg_zones_end; + int nb_zones =3D priv->data->nb_zones; + int protection_zone_idx; + + if (reg < 0) + return -1; /* negative reg is the boundary of an empty zone */ + + for (protection_zone_idx =3D 0; protection_zone_idx < nb_zones; protectio= n_zone_idx++) { + if (reg <=3D idx_bkpreg_zones_end[protection_zone_idx]) + break; + } + + if (protection_zone_idx >=3D nb_zones) + return -1; /* the reg is not a part of any zone */ + + return protection_zone_idx; +} + +static bool stm32_tamp_nvram_rights(struct stm32_tamp_nvram_priv *priv, in= t reg, bool read_only) +{ + struct device *dev =3D priv->dev; + int protection_zone_idx =3D stm32_tamp_nvram_bkpreg_get_zone(priv, reg); + + if (protection_zone_idx < 0) + return false; + + switch (priv->bkpreg_access[protection_zone_idx]) { + case BKP_READ_WRITE: + return true; + case BKP_READ: + return read_only; + case BKP_NO: + return false; + default: + dev_err(dev, "Can't get access rights for the zone\n"); + return false; + } + + return false; +} + +static bool stm32_tamp_nvram_readable_bkpreg(struct device *dev, unsigned = int reg) +{ + struct stm32_tamp_nvram_priv *priv =3D dev_get_drvdata(dev); + + if (!priv) + return false; + + if (!stm32_tamp_nvram_rights(priv, ALIGN_DOWN(reg, sizeof(u32)) / sizeof(= u32), true)) + return false; + + return true; +} + +static bool stm32_tamp_nvram_writeable_bkpreg(struct device *dev, unsigned= int reg) +{ + struct stm32_tamp_nvram_priv *priv =3D dev_get_drvdata(dev); + + if (!priv) + return false; + + if (!stm32_tamp_nvram_rights(priv, ALIGN_DOWN(reg, sizeof(u32)) / sizeof(= u32), false)) + return false; + + return true; +} + +static const struct regmap_config stm32mp1_tamp_nvram_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .readable_reg =3D stm32_tamp_nvram_readable_bkpreg, + .writeable_reg =3D stm32_tamp_nvram_writeable_bkpreg, + .max_register =3D 0x80, +}; + +static const struct regmap_config stm32mp2_tamp_nvram_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .readable_reg =3D stm32_tamp_nvram_readable_bkpreg, + .writeable_reg =3D stm32_tamp_nvram_writeable_bkpreg, + .max_register =3D 0x200, +}; + +static const struct stm32_tamp_nvram_plat stm32mp1_tamp_nvram =3D { + .nb_zones =3D NB_ZONES_STM32MP1, + .nb_regs =3D NB_REGS_STM32MP1, + .bkpregs_regmap_cfg =3D &stm32mp1_tamp_nvram_regmap_cfg, + .config_reg_fields =3D stm32mp1_tamp_nvram_zone_cfg_fields, +}; + +static const struct stm32_tamp_nvram_plat stm32mp25_tamp_nvram =3D { + .nb_zones =3D NB_ZONES_STM32MP2, + .nb_regs =3D NB_REGS_STM32MP2, + .bkpregs_regmap_cfg =3D &stm32mp2_tamp_nvram_regmap_cfg, + .config_reg_fields =3D stm32mp25_tamp_nvram_zone_cfg_fields, +}; + +static int stm32_tamp_nvram_write_byte(struct stm32_tamp_nvram_priv *priv,= u32 offset, u8 byte) +{ + int offset_aligned =3D ALIGN_DOWN(offset, sizeof(u32)); + int byte_in_word =3D offset - offset_aligned; + u32 read_value, to_be_writen_value; + u32 reg_idx =3D offset_aligned / sizeof(u32); + + if (!stm32_tamp_nvram_rights(priv, reg_idx, false)) + return -EIO; + + if (regmap_read(priv->bkpregs_regmap, offset_aligned, &read_value)) + return -EIO; + + to_be_writen_value =3D read_value & ~(0xFFUL << byte_in_word * 8); + to_be_writen_value |=3D (u32)byte << (byte_in_word * 8); + + return regmap_write(priv->bkpregs_regmap, offset_aligned, to_be_writen_va= lue); +} + +static int stm32_tamp_nvram_read_byte(struct stm32_tamp_nvram_priv *priv, = u32 offset, u8 *byte) +{ + int offset_aligned =3D ALIGN_DOWN(offset, sizeof(u32)); + int byte_in_word =3D offset - offset_aligned; + u32 read_value; + u32 reg_idx =3D offset_aligned / sizeof(u32); + + if (!stm32_tamp_nvram_rights(priv, reg_idx, true)) + return -EIO; + + if (regmap_read(priv->bkpregs_regmap, offset_aligned, &read_value)) + return -EIO; + + *byte =3D (read_value >> (byte_in_word * 8)) & 0xFF; + + return 0; +} + +static int stm32_tamp_nvram_read(void *context, unsigned int offset, void = *buf, size_t bytes) +{ + struct stm32_tamp_nvram_priv *priv =3D context; + struct device *dev =3D priv->dev; + u8 byte; + u8 *buf_u8 =3D buf; + u32 temp_u32; + int i, ret; + size_t total =3D offset + bytes; + u32 reg_idx; + + i =3D offset; + while (i < total) { + reg_idx =3D i / sizeof(u32); + if (i + sizeof(u32) <=3D total && IS_ALIGNED(i, sizeof(u32))) { + if (!stm32_tamp_nvram_rights(priv, reg_idx, true)) { + dev_dbg(dev, "Backup register %u is not allowed to be read\n", + reg_idx); + temp_u32 =3D 0; + } else if (regmap_read(priv->bkpregs_regmap, i, &temp_u32)) { + return -EIO; + } + memcpy(buf_u8, &temp_u32, sizeof(u32)); + buf_u8 +=3D sizeof(u32); + i +=3D sizeof(u32); + } else { + ret =3D stm32_tamp_nvram_read_byte(priv, i, &byte); + if (ret) { + dev_dbg(dev, "Backup register %u is not allowed to be read\n", + reg_idx); + byte =3D 0; + } + *buf_u8 =3D byte; + i++; + buf_u8++; + } + } + + return 0; +} + +static int stm32_tamp_nvram_write(void *context, unsigned int offset, void= *buf, size_t bytes) +{ + struct stm32_tamp_nvram_priv *priv =3D context; + struct device *dev =3D priv->dev; + u8 *buf_u8 =3D (u8 *)buf; + u32 temp_u32; + size_t total =3D offset + bytes; + int i, ret; + u32 reg_idx; + + i =3D offset; + while (i < total) { + reg_idx =3D i / sizeof(u32); + if (i + sizeof(u32) <=3D total && IS_ALIGNED(i, sizeof(u32))) { + if (stm32_tamp_nvram_rights(priv, reg_idx, false)) { + memcpy(&temp_u32, buf_u8, sizeof(u32)); + if (regmap_write(priv->bkpregs_regmap, i, temp_u32)) + return -EIO; + } else { + dev_dbg(dev, "Backup register %u is not allowed to be written", + reg_idx); + } + buf_u8 +=3D sizeof(u32); + i +=3D sizeof(u32); + } else { + ret =3D stm32_tamp_nvram_write_byte(priv, i, *buf_u8); + if (ret) + dev_dbg(dev, "Backup register %u is not allowed to be written", + reg_idx); + i++; + buf_u8++; + } + } + + return 0; +} + +static int *stm32_tamp_nvram_get_backup_zones(struct stm32_tamp_nvram_priv= *priv) +{ + struct device *dev =3D priv->dev; + int nb_zones =3D priv->data->nb_zones; + int zone_idx; + int *idx_bkpreg_zones_end; + struct regmap *tamp_regmap =3D priv->config_regmap; + u32 offset_field; + + idx_bkpreg_zones_end =3D devm_kcalloc(dev, + nb_zones, + sizeof(*idx_bkpreg_zones_end), + GFP_KERNEL); + if (!idx_bkpreg_zones_end) { + dev_err(dev, "Can't allocate registers zones\n"); + return ERR_PTR(-ENOMEM); + } + + /* Get the n-1 frontiers of zone within the tamp configuration registers = */ + for (zone_idx =3D 0; zone_idx < nb_zones - 1; zone_idx++) { + const struct reg_field reg_field =3D priv->data->config_reg_fields[zone_= idx]; + struct regmap_field *field =3D devm_regmap_field_alloc(dev, + tamp_regmap, + reg_field); + + if (IS_ERR(field)) { + dev_err(dev, "Can't allocate registers zones\n"); + devm_kfree(dev, idx_bkpreg_zones_end); + return ERR_PTR(-ENOMEM); + } + + if (regmap_field_read(field, &offset_field)) { + dev_err(dev, "Can't read field for registers zones\n"); + devm_kfree(dev, idx_bkpreg_zones_end); + return ERR_PTR(-EIO); + } + + idx_bkpreg_zones_end[zone_idx] =3D offset_field - 1; + } + + /* The last zone end is defined by the number of registers in TAMP */ + idx_bkpreg_zones_end[zone_idx] =3D priv->data->nb_regs - 1; + + return idx_bkpreg_zones_end; +} + +static const struct of_device_id stm32_tamp_nvram_of_match[] =3D { + { .compatible =3D "st,stm32mp15-tamp-nvram", + .data =3D &stm32mp1_tamp_nvram }, + { .compatible =3D "st,stm32mp25-tamp-nvram", + .data =3D &stm32mp25_tamp_nvram }, + {}, +}; + +static int stm32_tamp_nvram_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct stm32_tamp_nvram_priv *priv; + struct resource *res; + struct device_node *of_node; + const struct of_device_id *of_id; + void __iomem *base_addr; + unsigned int *zones_end; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D &pdev->dev; + + of_node =3D dev_of_node(dev); + if (!of_node) { + dev_err(dev, "Can't get of node of the device\n"); + return -ENODEV; + } + + of_id =3D of_match_node(stm32_tamp_nvram_of_match, of_node); + if (!of_id) { + dev_err(dev, "Can't get of_id of the device\n"); + return -ENODEV; + } + + priv->data =3D (struct stm32_tamp_nvram_plat *)of_id->data; + if (!priv->data) { + dev_err(dev, "Can't get platform data of the node\n"); + return -ENODEV; + } + + priv->config_regmap =3D syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(priv->config_regmap)) { + dev_dbg(dev, "Deferring till parent probed\n"); + return -EPROBE_DEFER; + } + + priv->idx_bkpreg_zones_end =3D stm32_tamp_nvram_get_backup_zones(priv); + if (IS_ERR(priv->idx_bkpreg_zones_end)) { + dev_dbg(dev, "Can't determine protection zone\n"); + return -ENODEV; + } + + zones_end =3D priv->idx_bkpreg_zones_end; + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res) { + dev_err(dev, "Can't get resource\n"); + return -ENODEV; + } + + base_addr =3D devm_ioremap_resource(dev, res); + if (IS_ERR(base_addr)) { + dev_err(dev, "Can't remap resource\n"); + return PTR_ERR(base_addr); + } + + priv->cfg.name =3D "stm32-tamp-nvram"; + priv->cfg.word_size =3D 1; + priv->cfg.stride =3D 1; + priv->cfg.dev =3D dev; + priv->cfg.priv =3D priv; + priv->cfg.owner =3D THIS_MODULE; + priv->cfg.type =3D NVMEM_TYPE_BATTERY_BACKED; + priv->cfg.size =3D resource_size(res); + priv->cfg.reg_read =3D stm32_tamp_nvram_read; + priv->cfg.reg_write =3D stm32_tamp_nvram_write; + + if (of_device_is_compatible(pdev->dev.of_node, + "st,stm32mp25-tamp-nvram")) { + priv->bkpreg_access =3D stm32_tamp_get_access_rights_mp2x(priv); + + if (IS_ERR(priv->bkpreg_access)) + return -ENODEV; + + dev_dbg(dev, "\n" + "Zone 1-RIF1 %3d - %3d %c%c\n" + "Zone 1-RIF2 %3d - %3d %c%c\n" + "Zone 2-RIF1 %3d - %3d %c%c\n" + "Zone 2-RIF2 %3d - %3d %c%c\n" + "Zone 3-RIF1 %3d - %3d %c%c\n" + "Zone 3-RIF0 %3d - %3d %c%c\n" + "Zone 3-RIF2 %3d - %3d %c%c\n", + 0, + zones_end[BKPREG_PROTECTION_ZONE_1_RIF1], + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_1_RIF1], + true) ? 'R' : '-', + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_1_RIF1], + false) ? 'W' : '-', + zones_end[BKPREG_PROTECTION_ZONE_1_RIF1] + 1, + zones_end[BKPREG_PROTECTION_ZONE_1_RIF2], + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_1_RIF2], + true) ? 'R' : '-', + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_1_RIF2], + false) ? 'W' : '-', + zones_end[BKPREG_PROTECTION_ZONE_1_RIF2] + 1, + zones_end[BKPREG_PROTECTION_ZONE_2_RIF1], + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_2_RIF1], + true) ? 'R' : '-', + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_2_RIF1], + false) ? 'W' : '-', + zones_end[BKPREG_PROTECTION_ZONE_2_RIF1] + 1, + zones_end[BKPREG_PROTECTION_ZONE_2_RIF2], + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_2_RIF2], + true) ? 'R' : '-', + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_2_RIF2], + false) ? 'W' : '-', + zones_end[BKPREG_PROTECTION_ZONE_2_RIF2] + 1, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF1], + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF1], + true) ? 'R' : '-', + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF1], + false) ? 'W' : '-', + zones_end[BKPREG_PROTECTION_ZONE_3_RIF1] + 1, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF0], + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF0], + true) ? 'R' : '-', + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF0], + false) ? 'W' : '-', + zones_end[BKPREG_PROTECTION_ZONE_3_RIF0] + 1, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF2], + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF2], + true) ? 'R' : '-', + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF2], + false) ? 'W' : '-' + ); + } else if (of_device_is_compatible(pdev->dev.of_node, "st,stm32mp15-tamp-= nvram")) { + priv->bkpreg_access =3D stm32mp1_tamp_bkpreg_access; + + dev_dbg(dev, "\n" + "Zone 1 %3d - %3d %c%c\n" + "Zone 2 %3d - %3d %c%c\n" + "Zone 3 %3d - %3d %c%c\n", + 0, + zones_end[BKPREG_PROTECTION_ZONE_1], + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_1], + true) ? 'R' : '-', + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_1], + false) ? 'W' : '-', + zones_end[BKPREG_PROTECTION_ZONE_1] + 1, + zones_end[BKPREG_PROTECTION_ZONE_2], + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_2], + true) ? 'R' : '-', + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_2], + false) ? 'W' : '-', + zones_end[BKPREG_PROTECTION_ZONE_2] + 1, + zones_end[BKPREG_PROTECTION_ZONE_3], + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_3], + true) ? 'R' : '-', + stm32_tamp_nvram_rights(priv, + zones_end[BKPREG_PROTECTION_ZONE_3], + false) ? 'W' : '-'); + } + + platform_set_drvdata(pdev, priv); + priv->bkpregs_regmap =3D devm_regmap_init_mmio(dev, base_addr, + priv->data->bkpregs_regmap_cfg); + if (IS_ERR(priv->bkpregs_regmap)) { + dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(priv->bkpregs_regma= p)); + return PTR_ERR(priv->bkpregs_regmap); + } + + return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg)); +} + +MODULE_DEVICE_TABLE(of, stm32_tamp_nvram_of_match); + +static struct platform_driver stm32_tamp_nvram_driver =3D { + .probe =3D stm32_tamp_nvram_probe, + .driver =3D { + .name =3D "stm32-tamp-nvram", + .of_match_table =3D stm32_tamp_nvram_of_match, + }, +}; + +module_platform_driver(stm32_tamp_nvram_driver) +MODULE_AUTHOR("Simeon Marijon "); +MODULE_DESCRIPTION("STMicroelectronics STM32 NVMEM TAMP Backup registers"); +MODULE_LICENSE("GPL"); --=20 2.43.0