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On Shikra SoC, the SoundWire controller is assigned to an Execution Environment (EE), which determines which banked register window must be used for interrupt, FIFO, and status register access on SoundWire v2.0 and later hardware. Add a dedicated qcom,shikra-soundwire compatible so the driver can select the correct register layout for Shikra at probe time. Signed-off-by: Mohammad Rafi Shaik Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yam= l b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index 8e6973fa2..81532cf69 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,shikra-soundwire - qcom,soundwire-v1.3.0 - qcom,soundwire-v1.5.0 - qcom,soundwire-v1.5.1 --=20 2.34.1 From nobody Fri Sep 25 17:49:32 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F234F3C1F5B for ; Thu, 10 Sep 2026 06:21:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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The existing driver assumes the SoundWire controller is assigned to EE1, which is true for all currently supported Qualcomm SoCs. Shikra is an exception and assigns the controller to EE0. As a result, the relevant register windows are located at different offsets and cannot be accessed using the default EE1 register layout. Add an ee field to the SoC match data and introduce a dedicated qcom,shikra-soundwire compatible with ee =3D 0. The driver uses this information at probe time to select the correct register layout, while all existing platforms continue to use the default EE1 configuration. Signed-off-by: Mohammad Rafi Shaik --- drivers/soundwire/qcom.c | 85 ++++++++++++++++++++++++++++++++++++++++----= ---- 1 file changed, 71 insertions(+), 14 deletions(-) diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 35ffffd54..6e0c5fb10 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -25,7 +25,9 @@ #define SWRM_COMP_SW_RESET 0x008 #define SWRM_COMP_STATUS 0x014 #define SWRM_LINK_MANAGER_EE 0x018 -#define SWRM_EE_CPU 1 +#define SWRM_EE_CPU0 0 +#define SWRM_EE_CPU1 1 +#define SWRM_EE_CPU SWRM_EE_CPU1 #define SWRM_FRM_GEN_ENABLED BIT(0) #define SWRM_VERSION_1_3_0 0x01030000 #define SWRM_VERSION_1_5_1 0x01050001 @@ -118,6 +120,7 @@ #define SWRM_V2_0_CLK_CTRL 0x5060 #define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0) #define SWRM_V2_0_LINK_STATUS 0x5064 +#define SWRM_V2_REG_EE_STRIDE 0x1000 =20 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 @@ -201,6 +204,7 @@ struct qcom_swrm_ctrl { struct mutex port_lock; struct clk *hclk; int irq; + u32 ee; unsigned int version; int wake_irq; int num_din_ports; @@ -224,6 +228,7 @@ struct qcom_swrm_ctrl { /* Per-Slave SCP_ADDRPAGE1/2 shadow; -1 =3D unknown. */ s16 page1_cache[SDW_MAX_DEVICES + 1]; s16 page2_cache[SDW_MAX_DEVICES + 1]; + unsigned int reg_layout_local[SWRM_OFFSET_DP_SAMPLECTRL2_BANK + 1]; }; =20 struct qcom_swrm_data { @@ -232,6 +237,7 @@ struct qcom_swrm_data { bool sw_clk_gate_required; u32 max_reg; const unsigned int *reg_layout; + u32 ee; }; =20 static const unsigned int swrm_v1_3_reg_layout[] =3D { @@ -258,6 +264,7 @@ static const struct qcom_swrm_data swrm_v1_3_data =3D { .default_cols =3D 16, .max_reg =3D SWR_V1_3_MSTR_MAX_REG_ADDR, .reg_layout =3D swrm_v1_3_reg_layout, + .ee =3D SWRM_EE_CPU, }; =20 static const struct qcom_swrm_data swrm_v1_5_data =3D { @@ -265,6 +272,7 @@ static const struct qcom_swrm_data swrm_v1_5_data =3D { .default_cols =3D 16, .max_reg =3D SWR_V1_3_MSTR_MAX_REG_ADDR, .reg_layout =3D swrm_v1_3_reg_layout, + .ee =3D SWRM_EE_CPU, }; =20 static const struct qcom_swrm_data swrm_v1_6_data =3D { @@ -273,6 +281,7 @@ static const struct qcom_swrm_data swrm_v1_6_data =3D { .sw_clk_gate_required =3D true, .max_reg =3D SWR_V1_3_MSTR_MAX_REG_ADDR, .reg_layout =3D swrm_v1_3_reg_layout, + .ee =3D SWRM_EE_CPU, }; =20 static const unsigned int swrm_v2_0_reg_layout[] =3D { @@ -300,6 +309,7 @@ static const struct qcom_swrm_data swrm_v2_0_data =3D { .sw_clk_gate_required =3D true, .max_reg =3D SWR_V2_0_MSTR_MAX_REG_ADDR, .reg_layout =3D swrm_v2_0_reg_layout, + .ee =3D SWRM_EE_CPU, }; =20 static const unsigned int swrm_v3_0_reg_layout[] =3D { @@ -327,9 +337,51 @@ static const struct qcom_swrm_data swrm_v3_0_data =3D { .sw_clk_gate_required =3D true, .max_reg =3D SWR_V2_0_MSTR_MAX_REG_ADDR, .reg_layout =3D swrm_v3_0_reg_layout, + .ee =3D SWRM_EE_CPU, +}; + +static const struct qcom_swrm_data swrm_shikra_data =3D { + .default_rows =3D 50, + .default_cols =3D 16, + .sw_clk_gate_required =3D true, + .max_reg =3D SWR_V2_0_MSTR_MAX_REG_ADDR, + .reg_layout =3D swrm_v3_0_reg_layout, + .ee =3D SWRM_EE_CPU0, }; #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) =20 +static void qcom_swrm_set_ee_register_layout(struct qcom_swrm_ctrl *ctrl, + const struct qcom_swrm_data *data) +{ + int ee_offset; + + memcpy(ctrl->reg_layout_local, data->reg_layout, + sizeof(ctrl->reg_layout_local)); + ctrl->reg_layout =3D ctrl->reg_layout_local; + + if (ctrl->version < SWRM_VERSION_2_0_0) + return; + + /* + * The register layout constants are defined for EE1 (the default for + * most Qualcomm SoCs). For SoCs where the SoundWire master is assigned + * to EE0, the interrupt, FIFO and status register windows are shifted + * by one EE stride (0x1000) relative to the EE1 base addresses. + */ + ee_offset =3D ((int)ctrl->ee - SWRM_EE_CPU) * SWRM_V2_REG_EE_STRIDE; + if (!ee_offset) + return; + + ctrl->reg_layout_local[SWRM_REG_FRAME_GEN_ENABLED] +=3D ee_offset; + ctrl->reg_layout_local[SWRM_REG_INTERRUPT_STATUS] +=3D ee_offset; + ctrl->reg_layout_local[SWRM_REG_INTERRUPT_CLEAR] +=3D ee_offset; + ctrl->reg_layout_local[SWRM_REG_INTERRUPT_CPU_EN] +=3D ee_offset; + ctrl->reg_layout_local[SWRM_REG_CMD_FIFO_WR_CMD] +=3D ee_offset; + ctrl->reg_layout_local[SWRM_REG_CMD_FIFO_RD_CMD] +=3D ee_offset; + ctrl->reg_layout_local[SWRM_REG_CMD_FIFO_STATUS] +=3D ee_offset; + ctrl->reg_layout_local[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] +=3D ee_offset; +} + static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val) { @@ -910,12 +962,13 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); =20 if (ctrl->version =3D=3D SWRM_VERSION_1_7_0) { - ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); + ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, ctrl->ee); ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, - SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); + SWRM_MCP_BUS_CLK_START << ctrl->ee); } else if (ctrl->version >=3D SWRM_VERSION_2_0_0) { - ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); - ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, + ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, ctrl->ee); + ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL + + ((int)ctrl->ee - SWRM_EE_CPU) * SWRM_V2_REG_EE_STRIDE, SWRM_V2_0_CLK_CTRL_CLK_START); } else { ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); @@ -941,11 +994,9 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], 0xFFFFFFFF); =20 - /* enable CPU IRQs */ - if (ctrl->mmio) { - ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], - SWRM_INTERRUPT_STATUS_RMSK); - } + /* enable CPU IRQs for the selected EE window */ + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], + SWRM_INTERRUPT_STATUS_RMSK); =20 /* Set IRQ to PULSE */ ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, @@ -1580,6 +1631,7 @@ static int qcom_swrm_probe(struct platform_device *pd= ev) memset(ctrl->page2_cache, 0xff, sizeof(ctrl->page2_cache)); =20 data =3D of_device_get_match_data(dev); + ctrl->ee =3D data->ee; ctrl->max_reg =3D data->max_reg; ctrl->reg_layout =3D data->reg_layout; ctrl->rows_index =3D sdw_find_row_index(data->default_rows); @@ -1659,6 +1711,7 @@ static int qcom_swrm_probe(struct platform_device *pd= ev) prop->default_row =3D data->default_rows; =20 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version); + qcom_swrm_set_ee_register_layout(ctrl, data); =20 ret =3D devm_request_threaded_irq(dev, ctrl->irq, NULL, qcom_swrm_irq_handler, @@ -1769,16 +1822,19 @@ static int __maybe_unused swrm_runtime_resume(struc= t device *dev) reset_control_reset(ctrl->audio_cgcr); =20 if (ctrl->version =3D=3D SWRM_VERSION_1_7_0) { - ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); + ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, ctrl->ee); ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, - SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); + SWRM_MCP_BUS_CLK_START << ctrl->ee); } else if (ctrl->version >=3D SWRM_VERSION_2_0_0) { - ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); - ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, + ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, ctrl->ee); + ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL + + ((int)ctrl->ee - SWRM_EE_CPU) * + SWRM_V2_REG_EE_STRIDE, SWRM_V2_0_CLK_CTRL_CLK_START); } else { ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); } + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); =20 @@ -1854,6 +1910,7 @@ static const struct of_device_id qcom_swrm_of_match[]= =3D { { .compatible =3D "qcom,soundwire-v1.7.0", .data =3D &swrm_v1_5_data }, { .compatible =3D "qcom,soundwire-v2.0.0", .data =3D &swrm_v2_0_data }, { .compatible =3D "qcom,soundwire-v3.1.0", .data =3D &swrm_v3_0_data }, + { .compatible =3D "qcom,shikra-soundwire", .data =3D &swrm_shikra_data }, {/* sentinel */}, }; =20 --=20 2.34.1