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Wed, 09 Sep 2026 12:37:26 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 1/3] soc: renesas: rz-sysc: Configure AOF registers from dma-ranges Date: Wed, 9 Sep 2026 20:36:37 +0100 Message-ID: <20260909193640.8069-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260909193640.8069-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260909193640.8069-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Some RZ SoCs contain bus masters that can only generate 32-bit addresses but need to access memory located above the 4 GiB boundary. The System Controller (SYSC) provides Address Offset Function (AOF) registers that translate the upper address bits on a per-master basis to extend the accessible physical address range. Each such master only ever places bits [29:0] of its own address directly onto the interconnect. Bits [31:30] of that same 32-bit address are not used as address bits at all -- instead they select one of four 6-bit fields (Reg0-Reg3) in the master's SYS_AOFn register. The selected field supplies the corresponding bits [34:30] or [35:30] of the actual bus transaction, effectively splitting the master's native 4 GiB address space into four independently relocatable 1 GiB windows and letting each be redirected anywhere in a 35-bit (masters limited to DDR0/DDR1 access) or 36-bit (masters that can also reach PCIe0/PCIe1) physical address space. Add generic infrastructure to configure the AOF registers from the firmware-provided dma-ranges property instead of relying on hardcoded register programming. Each supported bus master is described by its MMIO base address, corresponding SYS_AOF register index, and address width. At probe time, the driver matches the bus master against this description -- via the addressable child node of a devicetree "simple-bus" wrapper carrying dma-ranges -- and programs the appropriate AOF register by decomposing each dma-ranges entry into the 1 GiB-aligned segments it maps to, translating the child (device-side) address into the field it selects and the parent (physical) address into the value written to that field. Validate the dma-ranges entries before programming the hardware by checking 1 GiB alignment on both the child and parent addresses, ensuring the described child range does not exceed the master's own 4 GiB address space (i.e. does not require more than the four available 1 GiB translation windows), and verifying that the requested physical target is representable within the bus master's address width. Populate the AOF description table for the RZ/V2H SDHI controllers, which use SYS_AOF16-18. Signed-off-by: Lad Prabhakar --- drivers/soc/renesas/r9a09g057-sys.c | 9 +++ drivers/soc/renesas/rz-sysc.c | 118 ++++++++++++++++++++++++++++ drivers/soc/renesas/rz-sysc.h | 22 ++++++ 3 files changed, 149 insertions(+) diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a0= 9g057-sys.c index 308492c31acb..960fcba668b3 100644 --- a/drivers/soc/renesas/r9a09g057-sys.c +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -82,6 +82,12 @@ static void rzv2h_sys_print_id(struct device *dev, dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); } =20 +static const struct rz_aof_unit rzv2h_aof_units[] =3D { + { .base =3D 0x15c00000, .index =3D 16, .addr_bits =3D 35 }, /* SDHI0 -> S= YS_AOF16 */ + { .base =3D 0x15c10000, .index =3D 17, .addr_bits =3D 35 }, /* SDHI1 -> S= YS_AOF17 */ + { .base =3D 0x15c20000, .index =3D 18, .addr_bits =3D 35 }, /* SDHI2 -> S= YS_AOF18 */ +}; + static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __= initconst =3D { .family =3D "RZ/V2H", .id =3D 0x847a447, @@ -89,6 +95,9 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_so= c_id_init_data __initco .revision_mask =3D GENMASK(31, 28), .specific_id_mask =3D GENMASK(27, 0), .print_id =3D rzv2h_sys_print_id, + .aof_units =3D rzv2h_aof_units, + .num_aof_units =3D ARRAY_SIZE(rzv2h_aof_units), + .aof_base =3D 0x0500, }; =20 static bool rzv2h_regmap_readable_writeable_reg(unsigned int reg) diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index 0e92c415d4be..2dae4a0de99b 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,121 @@ struct rz_sysc { struct device *dev; }; =20 +static const struct rz_aof_unit * +rz_aof_lookup(const struct rz_sysc_soc_id_init_data *soc_data, u32 base) +{ + unsigned int i; + + for (i =3D 0; i < soc_data->num_aof_units; i++) + if (soc_data->aof_units[i].base =3D=3D base) + return &soc_data->aof_units[i]; + + return NULL; +} + +static int rz_aof_parse_bus(struct rz_sysc *sysc, + const struct rz_sysc_soc_id_init_data *soc_data, + struct device_node *bus_np) +{ + const struct rz_aof_unit *unit; + struct device_node *child; + struct resource res; + const __be32 *ranges; + int naddr, nsize, cell_sz, len, nentries, i; + u32 reg_val =3D 0; + + child =3D NULL; + for_each_child_of_node(bus_np, child) { + if (of_address_to_resource(child, 0, &res) =3D=3D 0) + break; + } + if (!child) { + dev_warn(sysc->dev, "%pOF: no addressable child found\n", bus_np); + return -EINVAL; + } + + if (!of_device_is_available(child)) { + dev_dbg(sysc->dev, "%pOF: %pOF is disabled, skipping AOF setup\n", + bus_np, child); + of_node_put(child); + return 0; + } + + unit =3D rz_aof_lookup(soc_data, (u32)res.start); + of_node_put(child); + if (!unit) { + dev_warn(sysc->dev, "%pOF: no AOF unit for base %pa\n", bus_np, &res.sta= rt); + return -ENODEV; + } + + naddr =3D of_n_addr_cells(bus_np); + nsize =3D of_n_size_cells(bus_np); + cell_sz =3D (naddr * 2 + nsize) * sizeof(u32); + + ranges =3D of_get_property(bus_np, "dma-ranges", &len); + if (!ranges || !cell_sz || len % cell_sz) { + dev_err(sysc->dev, "%pOF: malformed dma-ranges\n", bus_np); + return -EINVAL; + } + nentries =3D len / cell_sz; + + for (i =3D 0; i < nentries; i++) { + const __be32 *p =3D ranges + i * (naddr * 2 + nsize); + u64 child_addr =3D of_read_number(p, naddr); + u64 parent_addr =3D of_read_number(p + naddr, naddr); + u64 size =3D of_read_number(p + 2 * naddr, nsize); + unsigned int nseg =3D DIV_ROUND_UP_ULL(size, SZ_1G); + unsigned int sel0 =3D (child_addr >> 30) & 0x3; + u64 tgt0 =3D parent_addr >> 30; + unsigned int s; + + if (child_addr & (SZ_1G - 1) || parent_addr & (SZ_1G - 1)) { + dev_err(sysc->dev, "%pOF: entry %d not 1GiB aligned\n", bus_np, i); + return -EINVAL; + } + + for (s =3D 0; s < nseg; s++) { + unsigned int sel =3D sel0 + s; + u64 tgt =3D tgt0 + s; + + if (sel > 3) { + dev_err(sysc->dev, "%pOF: entry %d overflows the 4 fields\n", + bus_np, i); + return -EINVAL; + } + if (unit->addr_bits =3D=3D 35 && (tgt & BIT(5))) { + dev_err(sysc->dev, + "%pOF: target 0x%llx needs bit[5], unit is 35-bit only\n", + bus_np, tgt << 30); + return -EINVAL; + } + reg_val &=3D ~(0x3fu << (sel * 8)); + reg_val |=3D (tgt & 0x3f) << (sel * 8); + } + } + + writel(reg_val, sysc->base + SYS_AOF_OFFSET(soc_data->aof_base, unit->ind= ex)); + + return 0; +} + +static void rz_sysc_setup_aof(struct rz_sysc *sysc, + const struct rz_sysc_soc_id_init_data *soc_data) +{ + struct device_node *np; + + if (!soc_data->aof_units || !soc_data->num_aof_units) + return; + + for_each_node_with_property(np, "dma-ranges") { + if (!of_device_is_compatible(np, "simple-bus")) + continue; + + if (rz_aof_parse_bus(sysc, soc_data, np)) + dev_warn(sysc->dev, "AOF setup failed for %pOF\n", np); + } +} + static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_i= d *match) { const struct rz_sysc_init_data *sysc_data =3D match->data; @@ -137,6 +253,8 @@ static int rz_sysc_probe(struct platform_device *pdev) if (ret) return ret; =20 + rz_sysc_setup_aof(sysc, data->soc_id_init_data); + regmap_cfg->name =3D "rz_sysc_regs"; regmap_cfg->reg_bits =3D 32; regmap_cfg->reg_stride =3D 4; diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index e55f3258d703..481d5d5a0577 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -12,6 +12,18 @@ #include #include =20 +/** + * struct rz_aof_unit - RZ AOF unit description + * @base: MMIO base of the master IP (low 32 bits; all < 4G) + * @index: index of SYS_AOFn (0-based) + * @addr_bits: address width of the master IP (35 or 36 bits) + */ +struct rz_aof_unit { + u32 base; + u8 index; + u8 addr_bits; +}; + /** * struct rz_syc_soc_id_init_data - RZ SYSC SoC identification initializat= ion data * @family: RZ SoC family @@ -21,6 +33,10 @@ * @specific_id_mask: SYSC SoC ID specific ID mask * @print_id: print SoC-specific extended device identification * @pwrrdy_pwrseq: has pwrrdy register controlled through power sequencer + * @aof_units: array of AOF units for this SoC, or NULL if it has none + * @num_aof_units: number of entries in @aof_units + * @aof_base: offset of SYS_AOF0 from the SYSC base; ignored if @aof_units= is NULL + * (this offset is SoC-specific, unlike the fixed inter-registe= r stride) */ struct rz_sysc_soc_id_init_data { const char * const family; @@ -31,8 +47,14 @@ struct rz_sysc_soc_id_init_data { void (*print_id)(struct device *dev, void __iomem *sysc_base, struct soc_device_attribute *soc_dev_attr); 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Wed, 09 Sep 2026 12:37:27 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:d357:e592:d56c:d3b5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49d26be64a5sm13123995e9.6.2026.09.09.12.37.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 12:37:26 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 2/3] arm64: dts: renesas: r9a09g057: Move SDHI nodes into bus nodes Date: Wed, 9 Sep 2026 20:36:38 +0100 Message-ID: <20260909193640.8069-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260909193640.8069-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260909193640.8069-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Wrap sdhi0, sdhi1, and sdhi2 in dedicated "simple-bus" wrapper nodes (aof_sdhi0_bus, aof_sdhi1_bus, aof_sdhi2_bus), each carrying a dma-ranges property. Add dma-ranges to the enclosing bus node instead of the SDHI node itself, since of_dma_configure() applies a dma-ranges property found on a device's parent bus node, not one placed directly on the device. Wrapping each SDHI instance in its own simple-bus node lets each one carry an independent dma-ranges without affecting its siblings. The same dma-ranges also let the rz-sysc driver derive the SYS_AOFn address extension register programming for each SDHI instance, identified by its MMIO base, per the SoC's address space extension mechanism. Set each wrapper's dma-ranges to: dma-ranges =3D <0x0 0x40000000 0x0 0x40000000 0x0 0xc0000000>; Leave the corresponding SDHI's low 1 GiB device-side segment (0x0 - 0x3fffffff, SRAM/peripheral/xSPI/PCIe space) at its identity-mapped reset default, and remap its remaining 3 GiB device-side space (0x40000000-0xffffffff) 1:1 onto the same physical range. DDR on this SoC spans up to 16 GiB starting at 0x40000000 (DDR0 and DDR1 combined), so this 3 GiB range stays entirely within DDR0's native base and changes nothing for any of the three SDHI instances. Allow boards that need a different target window (e.g. DDR1, or a dedicated reserved-memory pool) to override dma-ranges per instance, as done for SDHI1 on the RZ/V2H EVK in a subsequent commit. Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 123 +++++++++++++-------- 1 file changed, 75 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index bbaab75681c2..34639106d2cc 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1577,63 +1577,90 @@ usb3_phy1: usb-phy@15880000 { status =3D "disabled"; }; =20 - sdhi0: mmc@15c00000 { - compatible =3D "renesas,sdhi-r9a09g057"; - reg =3D <0x0 0x15c00000 0 0x10000>; - interrupts =3D , - ; - clocks =3D <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, - <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; - clock-names =3D "core", "clkh", "cd", "aclk"; - resets =3D <&cpg 0xa7>; - power-domains =3D <&cpg>; - status =3D "disabled"; - - sdhi0_vqmmc: vqmmc-regulator { - regulator-name =3D "SDHI0-VQMMC"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <3300000>; + aof_sdhi0_bus: sdhi0-bus { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + dma-ranges =3D <0x0 0x40000000 0x0 0x40000000 0x0 0xc0000000>; + + sdhi0: mmc@15c00000 { + compatible =3D "renesas,sdhi-r9a09g057"; + reg =3D <0x0 0x15c00000 0 0x10000>; + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, + <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; + clock-names =3D "core", "clkh", "cd", "aclk"; + resets =3D <&cpg 0xa7>; + power-domains =3D <&cpg>; status =3D "disabled"; + + sdhi0_vqmmc: vqmmc-regulator { + regulator-name =3D "SDHI0-VQMMC"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + status =3D "disabled"; + }; }; }; =20 - sdhi1: mmc@15c10000 { - compatible =3D "renesas,sdhi-r9a09g057"; - reg =3D <0x0 0x15c10000 0 0x10000>; - interrupts =3D , - ; - clocks =3D <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, - <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; - clock-names =3D "core", "clkh", "cd", "aclk"; - resets =3D <&cpg 0xa8>; - power-domains =3D <&cpg>; - status =3D "disabled"; - - sdhi1_vqmmc: vqmmc-regulator { - regulator-name =3D "SDHI1-VQMMC"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <3300000>; + aof_sdhi1_bus: sdhi1-bus { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + dma-ranges =3D <0x0 0x40000000 0x0 0x40000000 0x0 0xc0000000>; + + sdhi1: mmc@15c10000 { + compatible =3D "renesas,sdhi-r9a09g057"; + reg =3D <0x0 0x15c10000 0 0x10000>; + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, + <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; + clock-names =3D "core", "clkh", "cd", "aclk"; + resets =3D <&cpg 0xa8>; + power-domains =3D <&cpg>; status =3D "disabled"; + + sdhi1_vqmmc: vqmmc-regulator { + regulator-name =3D "SDHI1-VQMMC"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + status =3D "disabled"; + }; }; }; =20 - sdhi2: mmc@15c20000 { - compatible =3D "renesas,sdhi-r9a09g057"; - reg =3D <0x0 0x15c20000 0 0x10000>; - interrupts =3D , - ; - clocks =3D <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, - <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; - clock-names =3D "core", "clkh", "cd", "aclk"; - resets =3D <&cpg 0xa9>; - power-domains =3D <&cpg>; - status =3D "disabled"; - - sdhi2_vqmmc: vqmmc-regulator { - regulator-name =3D "SDHI2-VQMMC"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <3300000>; + aof_sdhi2_bus: sdhi2-bus { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + dma-ranges =3D <0x0 0x40000000 0x0 0x40000000 0x0 0xc0000000>; + + sdhi2: mmc@15c20000 { + compatible =3D "renesas,sdhi-r9a09g057"; + reg =3D <0x0 0x15c20000 0 0x10000>; + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, + <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; + clock-names =3D "core", "clkh", "cd", "aclk"; + resets =3D <&cpg 0xa9>; + power-domains =3D <&cpg>; status =3D "disabled"; + + sdhi2_vqmmc: vqmmc-regulator { + regulator-name =3D "SDHI2-VQMMC"; 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Wed, 09 Sep 2026 12:37:27 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 3/3] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Move SDHI1 dma range from 8-12 GiB Date: Wed, 9 Sep 2026 20:36:39 +0100 Message-ID: <20260909193640.8069-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260909193640.8069-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260909193640.8069-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Relocate SDHI1's AOF-remapped DMA window to physical 8-12 GiB (0x2_0000_0000-0x2_ffff_ffff), by updating the dma-ranges entry on aof_sdhi1_bus so that SDHI1's full 4 GiB device-side address space (child base 0x0, size 4 GiB) is linearly remapped starting at parent base 0x2_0000_0000. Since SDHI1's DMA-visible addresses no longer correspond 1:1 to ordinary system RAM, buffers handed to it must be guaranteed to physically reside within this window. Add a restricted-dma-pool reserved-memory region covering the same 8-12 GiB range and attach it to sdhi1 via memory-region, so the kernel bounces SDHI1's DMA buffers through this pool instead of allowing dma_alloc_coherent()/ dma_map_sg() to hand back arbitrary physical pages outside the range the programmed SYS_AOF17 fields can actually reach. Signed-off-by: Lad Prabhakar --- .../boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 0926ab891fa5..6845d576af42 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -99,6 +99,17 @@ reg_3p3v: regulator-3p3v { regulator-always-on; }; =20 + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + sdhi1_aof_pool: sdhi1-aof-pool@200000000 { + compatible =3D "restricted-dma-pool"; + reg =3D <0x2 0x00000000 0x0 0x08000000>; + }; + }; + vqmmc_sdhi1: regulator-vccq-sdhi1 { compatible =3D "regulator-gpio"; regulator-name =3D "SDHI1 VccQ"; @@ -130,6 +141,10 @@ y1: y1-clock { }; }; =20 +&aof_sdhi1_bus { + dma-ranges =3D <0x0 0x00000000 0x2 0x00000000 0x1 0x00000000>; +}; + &audio_extal_clk { clock-frequency =3D <22579200>; }; @@ -542,6 +557,7 @@ &scif { }; =20 &sdhi1 { + memory-region =3D <&sdhi1_aof_pool>; pinctrl-0 =3D <&sdhi1_pins>; pinctrl-1 =3D <&sdhi1_pins>; pinctrl-names =3D "default", "state_uhs"; --=20 2.55.0