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Wed, 9 Sep 2026 03:41:47 -0700 From: Kartik Rajput Date: Wed, 9 Sep 2026 16:11:19 +0530 Subject: [PATCH 1/4] dt-bindings: ufs: Add nvidia,tegra264-ufs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-tegra264-ufs-v1-1-e4a9831702a0@nvidia.com> References: <20260909-tegra264-ufs-v1-0-e4a9831702a0@nvidia.com> In-Reply-To: <20260909-tegra264-ufs-v1-0-e4a9831702a0@nvidia.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , "Jonathan Hunter" , "James E.J. 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The controller supports UFS 3.1 up to HS-G4B on two data lanes. Signed-off-by: Kartik Rajput --- .../bindings/ufs/nvidia,tegra264-ufs.yaml | 124 +++++++++++++++++= ++++ 1 file changed, 124 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/nvidia,tegra264-ufs.yaml= b/Documentation/devicetree/bindings/ufs/nvidia,tegra264-ufs.yaml new file mode 100644 index 000000000000..5a9837cb43dd --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/nvidia,tegra264-ufs.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/nvidia,tegra264-ufs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 UFS Host Controller + +maintainers: + - Kartik Rajput + - Thierry Reding + +properties: + compatible: + const: nvidia,tegra264-ufs + + reg: + items: + - description: UFS Host Controller registers + - description: UFS auxiliary registers + + reg-names: + items: + - const: ufs + - const: aux + + clocks: + items: + - description: UFS host controller functional clock + - description: UFS host controller divider clock + - description: UFS reference clock (PLLREFUFS output) + - description: UFS device-side reference clock + - description: M-PHY reference clock (UPHY0 PLL4 digital output) + + clock-names: + items: + - const: ufs + - const: div + - const: ref + - const: ref-dev + - const: phy + + resets: + items: + - description: UFS host controller reset + - description: UFS host controller AXI-master reset + - description: UFS host controller low-power sequencer reset + + reset-names: + items: + - const: ufs + - const: axi + - const: lp + + phys: + items: + - description: M-PHY lane 0 transmit + - description: M-PHY lane 0 receive + - description: M-PHY lane 1 transmit + - description: M-PHY lane 1 receive + + phy-names: + items: + - const: mphy-l0-tx + - const: mphy-l0-rx + - const: mphy-l1-tx + - const: mphy-l1-rx + + iommus: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - iommus + - dma-coherent + +allOf: + - $ref: ufs-common.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + ufs@b8d0000 { + compatible =3D "nvidia,tegra264-ufs"; + reg =3D <0xb8d0000 0x10000>, + <0xb8e0000 0x8000>; + reg-names =3D "ufs", "aux"; + interrupts =3D ; + clocks =3D <&bpmp TEGRA264_CLK_UFSHC_CG_SYS>, + <&bpmp TEGRA264_CLK_UFSHC_CG_SYS_DIV>, + <&bpmp TEGRA264_CLK_PLLREFUFS_CLKOUT624>, + <&bpmp TEGRA264_CLK_PLLREFUFS_UFSDEV_REFCLKOUT>, + <&bpmp TEGRA264_CLK_UPHY0_PLL4_XDIG>; + clock-names =3D "ufs", "div", "ref", "ref-dev", "phy"; + resets =3D <&bpmp TEGRA264_RESET_UFSHC>, + <&bpmp TEGRA264_RESET_UFSHC_AXI_M>, + <&bpmp TEGRA264_RESET_UFSHC_LP_SEQ>; + reset-names =3D "ufs", "axi", "lp"; + phys =3D <&mphy TEGRA_MPHY_L0_TX>, + <&mphy TEGRA_MPHY_L0_RX>, + <&mphy TEGRA_MPHY_L1_TX>, + <&mphy TEGRA_MPHY_L1_RX>; + phy-names =3D "mphy-l0-tx", "mphy-l0-rx", + "mphy-l1-tx", "mphy-l1-rx"; + iommus =3D <&smmu 0x20>; + dma-coherent; + }; +... --=20 2.43.0 From nobody Fri Sep 25 19:15:45 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012008.outbound.protection.outlook.com [52.101.43.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B9EF52BE2E; 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Add it here in preparation for the Tegra264 UFS host controller driver, which also programs the two fields. Signed-off-by: Kartik Rajput --- include/ufs/unipro.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h index 9c168703b104..f6d83878f2a6 100644 --- a/include/ufs/unipro.h +++ b/include/ufs/unipro.h @@ -6,6 +6,8 @@ #ifndef _UNIPRO_H_ #define _UNIPRO_H_ =20 +#include + /* * M-TX Configuration Attributes */ @@ -232,8 +234,12 @@ #define VS_POWERSTATE 0xD083 #define VS_MPHYCFGUPDT 0xD085 #define VS_DEBUGOMC 0xD09E +#define VS_DEBUGSAVECONFIGTIME 0xD0A0 #define VS_MPHYDISABLE 0xD0C1 =20 +#define VS_DEBUGSAVECONFIGTIME_TREF GENMASK(4, 2) +#define VS_DEBUGSAVECONFIGTIME_SCT GENMASK(1, 0) + #define PA_GRANULARITY_MIN_VAL 1 #define PA_GRANULARITY_MAX_VAL 6 =20 --=20 2.43.0 From nobody Fri Sep 25 19:15:45 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012025.outbound.protection.outlook.com [52.101.43.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C246524B07; 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The attribute now has a name in the shared UniPro header, so use it and drop the comments and the redundant (u32) cast. No functional change. Signed-off-by: Kartik Rajput --- drivers/ufs/host/ufs-hisi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c index 993e20ac211d..79417c16c627 100644 --- a/drivers/ufs/host/ufs-hisi.c +++ b/drivers/ufs/host/ufs-hisi.c @@ -318,8 +318,7 @@ static void ufs_hisi_pwr_change_pre_change(struct ufs_h= ba *hba) * Boston platform need to set SaveConfigTime to 0x13, * and change sync length to maximum value */ - /* VS_DebugSaveConfigTime */ - ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13); + ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGSAVECONFIGTIME), 0x13); /* g1 sync length */ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f); /* g2 sync length */ @@ -335,8 +334,7 @@ static void ufs_hisi_pwr_change_pre_change(struct ufs_h= ba *hba) =20 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) { pr_info("ufs flash device must set VS_DebugSaveConfigTime 0x10\n"); - /* VS_DebugSaveConfigTime */ - ufshcd_dme_set(hba, UIC_ARG_MIB(0xD0A0), 0x10); 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Wed, 9 Sep 2026 03:42:04 -0700 From: Kartik Rajput Date: Wed, 9 Sep 2026 16:11:22 +0530 Subject: [PATCH 4/4] scsi: ufs: tegra: Add Tegra264 UFS host controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-tegra264-ufs-v1-4-e4a9831702a0@nvidia.com> References: <20260909-tegra264-ufs-v1-0-e4a9831702a0@nvidia.com> In-Reply-To: <20260909-tegra264-ufs-v1-0-e4a9831702a0@nvidia.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , "Jonathan Hunter" , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel CC: Thierry Reding , , , , , Kartik Rajput X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788950501; l=19800; i=kkartik@nvidia.com; s=20260909; h=from:subject:message-id; bh=6pXddh1gf2VZ/Qgwi25kI9xoIc9q4i4lNz3wR056/FM=; b=IdQG+v/X7seHDAuVwRMXQt+Adea/5aYuDduts4ur9CGsblzGWtRCVEzPidWNcRxogfu9TFiWP +1KZdk5m+8NB0FulxYjYeAgd8qqXVPNEq8mhN//IqD36LK8XMaF6DAJ X-Developer-Key: i=kkartik@nvidia.com; a=ed25519; pk=V+1YkJqxCruxUVxLXtAG3f5k8O5skT0X4/QIB75KZ64= X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A894:EE_|DS0PR12MB9324:EE_ X-MS-Office365-Filtering-Correlation-Id: bcf861ac-53c4-45ce-4496-08df0e5f0a54 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|23010399003|7416014|6133799003|22082099003|18002099003|56012099006|10067099003|921020|11063799006; X-Microsoft-Antispam-Message-Info: vOqGxMyPfkesGbcfnXB0Gneouy10ytgCxTTZ5mZXgCXs5E0OB6KhFN1hc642fVmkj5RO9lzEcdU0Es+R/mNixPVBKYfq3An2v+R12N5mdS8BPcE8Fp1o6A6Q5s96t4p4qlyf/eNRLaTctzrWYpU7KTdVHEM2OC/PUNB4z0KuSKPzWk38jJy2pTN4qisR2+HadFgHl8gVDNwRSZE91xuopa/RdS1KqXRUoR0Q9Bpr+MjILSNojg/0IsJ+VjSLO5I5Mw6pAspDK7qwUgFxovU0Fb/2+qOGiK65qbgzSXgQBmP8IHmQNaBAmYhIrNJxE/K3tEP5HwxVUH44pxII63HWSFc7mVsxxbgrmt+ODw99FFSvrKmEFMpJ4nGme+xv5qFzg+/1By9HDqGc9sDLK8BQpLDn/3h3L7k/Zcm/FarW4C1SQaTWGaEs3h3m8oX4KBk4L6fdCJSXgHA0GxNeBupbYfJuDM3+hCA9vg6nZP6ByMsKAFa24+6NnQYnHR9pUvt/WWcxz2Md4MEPDw4Pp374fu1VmhJUeL7Cv6OUFGsMHCSPl/t/9ANca4/qU0+iotmQXHBuUhVJfjW7SzYHfnUmGLaUE69yaj/Tv2/Wd7wmYOYCof3MPO3yJbKWFxomMAiSgTsJXJp/1MpAYcylr1jQ+ZL1r4Bpf9afQ/EXoY06SqAobeyb3Y0vWVQ7H2V3HL5ZP0WDu6lTI+3+6ohxyLKji86B2Ik1iYNsCogFRTEsafoZiXtTFMo8wAkj0u6SSOD/ X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(23010399003)(7416014)(6133799003)(22082099003)(18002099003)(56012099006)(10067099003)(921020)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sFjDU+FZUtQlko87mKYZATqIR0WEinRuhCoXCvvm87Er3ISNMSOmrDp246wkLs6E9rY+UUzuhuqCtJMUcSbf7y1HCI4UrQvA0AbHsu63Rg+aws7gLx5xCx0Nx7PwQIpHt2aFocKRYjLT/w4ERy9wymrdzLVMZ8kKHFXzAJx7A2FnXYVg9y05q40mhbksKBXFOo2xS8QIjNjl9GaHF+FTwxaU4Bk92MrIFmFtoaCXrA2gJrZjCUieQglmmWWvIDicmcFcuAnVUryZVQtrwPUSAnFmw1fBWamCjDVZkE/7Qac3CD61Oa9eRmOk0MiUx8jGjxRMMU3xG80T2HXTPCcsuLwod3lXxLIG5XWt5I2pDhRPTV4MLvQjtfCw0BlcaZfqFRrpMYDgSU/bj9wSqsFZ60+gPZPfaRasrvsvIvMnck0tUyhDOyyIQRKaZrct6r1J X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2026 10:42:26.6091 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bcf861ac-53c4-45ce-4496-08df0e5f0a54 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A894.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9324 Add a driver for the UFS host controller found on NVIDIA Tegra264 SoCs. The controller has Tegra-specific auxiliary registers, clocks and resets, and it drives the four M-PHY lane directions exposed by the Tegra264 M-PHY driver. Co-developed-by: Thierry Reding Signed-off-by: Thierry Reding Signed-off-by: Kartik Rajput --- drivers/ufs/host/Kconfig | 13 + drivers/ufs/host/Makefile | 1 + drivers/ufs/host/ufs-tegra.c | 687 +++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 701 insertions(+) diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig index ff170c0b6da0..e4c565fce53c 100644 --- a/drivers/ufs/host/Kconfig +++ b/drivers/ufs/host/Kconfig @@ -168,3 +168,16 @@ config SCSI_UFS_AMD_VERSAL2 =20 Select this if you have UFS controller on AMD Versal Gen 2 SoC. If unsure, say N. + +config SCSI_UFS_TEGRA + tristate "NVIDIA Tegra264 UFS controller platform driver" + depends on SCSI_UFSHCD_PLATFORM && (ARCH_TEGRA_264_SOC || COMPILE_TEST) + select PHY_TEGRA_MPHY + help + Enable support for the UFS host controller on NVIDIA Tegra264 + SoCs. The driver relies on the Tegra264 M-PHY driver + (PHY_TEGRA_MPHY) for the two data lanes and implements the + vendor register programming required for HS-mode transitions + and system suspend/resume. + + If unsure, say N. diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile index 7d8db67eb23c..1459a081cc9d 100644 --- a/drivers/ufs/host/Makefile +++ b/drivers/ufs/host/Makefile @@ -14,5 +14,6 @@ obj-$(CONFIG_SCSI_UFS_MEDIATEK) +=3D ufs-mediatek.o obj-$(CONFIG_SCSI_UFS_RENESAS) +=3D ufs-renesas.o obj-$(CONFIG_SCSI_UFS_ROCKCHIP) +=3D ufs-rockchip.o obj-$(CONFIG_SCSI_UFS_SPRD) +=3D ufs-sprd.o +obj-$(CONFIG_SCSI_UFS_TEGRA) +=3D ufs-tegra.o ufshcd-dwc.o obj-$(CONFIG_SCSI_UFS_TI_J721E) +=3D ti-j721e-ufs.o obj-$(CONFIG_SCSI_UFS_AMD_VERSAL2) +=3D ufs-amd-versal2.o ufshcd-dwc.o diff --git a/drivers/ufs/host/ufs-tegra.c b/drivers/ufs/host/ufs-tegra.c new file mode 100644 index 000000000000..859fe0af66e5 --- /dev/null +++ b/drivers/ufs/host/ufs-tegra.c @@ -0,0 +1,687 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// NVIDIA Tegra264 UFS host controller driver. + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "ufshcd-dwc.h" +#include "ufshcd-pltfrm.h" +#include "ufshci-dwc.h" + +#define UFSHC_DWC_BLOCK_BUSTHRTL 0xc0 +#define MBL(x) (((x) & 0x7) << 13) +#define MBL_MASK (0x7 << 13) + +#define HCLKDIV(x) ((x) & 0xff) + +#define UFSHC_AUX_SW_EN_CLK_SLCG 0x08 +#define CLK_OVR_ON BIT(0) + +#define UFSHC_AUX_DEV_CTRL 0x14 +#define DEV_CTRL_CLK_EN BIT(0) +#define DEV_CTRL_RESET BIT(1) + +#define UFS_TEGRA_PHY_CLK_HS_RATE_HZ 5840000000UL + +/* DWC UFSHC BUSTHRTL max AXI burst length. */ +#define UFS_TEGRA_MBL_MAX 0x5 + +/* DWC UniPro save-config-time reference and value fields. */ +#define UFS_TEGRA_SAVECONFIGTIME_TREF 0x6 +#define UFS_TEGRA_SAVECONFIGTIME_SCT 0x3 + +/* HS G1..G4 sync burst length advertised to the peer. */ +#define UFS_TEGRA_HSG_SYNC_LEN 0x4f + +/* Local UniPro DME timeout values sent to the peer via PA_PWRMODEUSERDATA= . */ +#define UFS_TEGRA_FC0_TIMEOUT 0x1fff +#define UFS_TEGRA_TC0_TIMEOUT 0xffff +#define UFS_TEGRA_AFC0_TIMEOUT 0x7fff + +struct ufs_tegra { + void __iomem *aux; + + struct reset_control_bulk_data *resets; + unsigned int num_resets; + + struct clk *ufs_clk; + struct clk *phy_clk; + + struct phy *mphy_l0_rx; + struct phy *mphy_l0_tx; + struct phy *mphy_l1_rx; + struct phy *mphy_l1_tx; + + bool mphy_on; + + struct ufs_host_params host_params; +}; + +static int ufs_tegra_init_resources(struct ufs_hba *hba) +{ + struct platform_device *pdev =3D to_platform_device(hba->dev); + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + + ufs->aux =3D devm_platform_ioremap_resource_byname(pdev, "aux"); + if (IS_ERR(ufs->aux)) + return PTR_ERR(ufs->aux); + + return 0; +} + +static const struct reset_control_bulk_data ufs_tegra_resets[] =3D { + { .id =3D "ufs" }, + { .id =3D "axi" }, + { .id =3D "lp" }, +}; + +static int ufs_tegra_parse_reset_info(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + struct device *dev =3D hba->dev; + + ufs->num_resets =3D ARRAY_SIZE(ufs_tegra_resets); + + ufs->resets =3D devm_kmemdup(dev, ufs_tegra_resets, sizeof(ufs_tegra_rese= ts), GFP_KERNEL); + if (!ufs->resets) + return -ENOMEM; + + return devm_reset_control_bulk_get_exclusive(dev, ufs->num_resets, ufs->r= esets); +} + +static int ufs_tegra_parse_clock_info(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + struct ufs_clk_info *clki; + + list_for_each_entry(clki, &hba->clk_list_head, list) { + if (!strcmp(clki->name, "ufs")) + ufs->ufs_clk =3D clki->clk; + + if (!strcmp(clki->name, "phy")) + ufs->phy_clk =3D clki->clk; + } + + if (!ufs->ufs_clk || !ufs->phy_clk) + return -ENODEV; + + return 0; +} + +static int ufs_tegra_parse_phy_info(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + struct device *dev =3D hba->dev; + + ufs->mphy_l0_rx =3D devm_phy_get(dev, "mphy-l0-rx"); + if (IS_ERR(ufs->mphy_l0_rx)) + return PTR_ERR(ufs->mphy_l0_rx); + + ufs->mphy_l0_tx =3D devm_phy_get(dev, "mphy-l0-tx"); + if (IS_ERR(ufs->mphy_l0_tx)) + return PTR_ERR(ufs->mphy_l0_tx); + + ufs->mphy_l1_rx =3D devm_phy_get(dev, "mphy-l1-rx"); + if (IS_ERR(ufs->mphy_l1_rx)) + return PTR_ERR(ufs->mphy_l1_rx); + + ufs->mphy_l1_tx =3D devm_phy_get(dev, "mphy-l1-tx"); + if (IS_ERR(ufs->mphy_l1_tx)) + return PTR_ERR(ufs->mphy_l1_tx); + + return 0; +} + +static void ufs_tegra_set_caps(struct ufs_hba *hba) +{ + hba->caps |=3D UFSHCD_CAP_INTR_AGGR; + hba->caps |=3D UFSHCD_CAP_WB_EN; + + hba->spm_lvl =3D UFS_PM_LVL_5; +} + +static void ufs_tegra_configure_aux(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + u32 value; + + value =3D readl(ufs->aux + UFSHC_AUX_DEV_CTRL); + value |=3D DEV_CTRL_CLK_EN; + writel(value, ufs->aux + UFSHC_AUX_DEV_CTRL); + + /* Let the reference clock stabilise before deasserting device reset. */ + usleep_range(1000, 2000); + + value |=3D DEV_CTRL_RESET; + writel(value, ufs->aux + UFSHC_AUX_DEV_CTRL); +} + +static void ufs_tegra_aux_init(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + u32 value; + + value =3D readl(ufs->aux + UFSHC_AUX_DEV_CTRL); + value &=3D ~(DEV_CTRL_CLK_EN | DEV_CTRL_RESET); + writel(value, ufs->aux + UFSHC_AUX_DEV_CTRL); + + /* Ensure the clear is observed before we re-enable. */ + usleep_range(100, 200); + + ufs_tegra_configure_aux(hba); +} + +static void ufs_tegra_update_hclk_div(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + u32 ufs_clk_mhz; + + ufs_clk_mhz =3D clk_get_rate(ufs->ufs_clk) / USEC_PER_SEC; + ufshcd_writel(hba, HCLKDIV(ufs_clk_mhz), DWC_UFS_REG_HCLKDIV); +} + +static int ufs_tegra_init(struct ufs_hba *hba) +{ + struct platform_device *pdev =3D to_platform_device(hba->dev); + struct device *dev =3D &pdev->dev; + struct ufs_tegra *ufs; + int err; + + ufs =3D devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); + if (!ufs) + return -ENOMEM; + + ufshcd_set_variant(hba, ufs); + + err =3D ufs_tegra_init_resources(hba); + if (err) + return err; + + err =3D ufs_tegra_parse_clock_info(hba); + if (err) + return err; + + err =3D ufs_tegra_parse_reset_info(hba); + if (err) + return err; + + err =3D ufs_tegra_parse_phy_info(hba); + if (err) + return err; + + ufs_tegra_set_caps(hba); + + ufshcd_init_host_params(&ufs->host_params); + ufs->host_params.hs_rx_gear =3D UFS_HS_G4; + ufs->host_params.hs_tx_gear =3D UFS_HS_G4; + + err =3D reset_control_bulk_deassert(ufs->num_resets, ufs->resets); + if (err) + return err; + + ufs_tegra_aux_init(hba); + ufs_tegra_update_hclk_div(hba); + + return 0; +} + +static int ufs_tegra_mphy_init(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + int err; + + err =3D phy_init(ufs->mphy_l0_rx); + if (err) { + dev_err(hba->dev, "failed to initialize mphy-l0-rx\n"); + return err; + } + + err =3D phy_init(ufs->mphy_l0_tx); + if (err) { + dev_err(hba->dev, "failed to initialize mphy-l0-tx\n"); + goto out_exit_l0_rx; + } + + err =3D phy_init(ufs->mphy_l1_rx); + if (err) { + dev_err(hba->dev, "failed to initialize mphy-l1-rx\n"); + goto out_exit_l0_tx; + } + + err =3D phy_init(ufs->mphy_l1_tx); + if (err) { + dev_err(hba->dev, "failed to initialize mphy-l1-tx\n"); + goto out_exit_l1_rx; + } + + return 0; + +out_exit_l1_rx: + phy_exit(ufs->mphy_l1_rx); +out_exit_l0_tx: + phy_exit(ufs->mphy_l0_tx); +out_exit_l0_rx: + phy_exit(ufs->mphy_l0_rx); + + return err; +} + +static void ufs_tegra_mphy_exit(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + + phy_exit(ufs->mphy_l0_rx); + phy_exit(ufs->mphy_l0_tx); + phy_exit(ufs->mphy_l1_rx); + phy_exit(ufs->mphy_l1_tx); +} + +static int ufs_tegra_mphy_power_on(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + int err; + + err =3D phy_power_on(ufs->mphy_l0_rx); + if (err) { + dev_err(hba->dev, "failed to power on mphy-l0-rx\n"); + return err; + } + + err =3D phy_power_on(ufs->mphy_l0_tx); + if (err) { + dev_err(hba->dev, "failed to power on mphy-l0-tx\n"); + goto out_power_off_l0_rx; + } + + err =3D phy_power_on(ufs->mphy_l1_rx); + if (err) { + dev_err(hba->dev, "failed to power on mphy-l1-rx\n"); + goto out_power_off_l0_tx; + } + + err =3D phy_power_on(ufs->mphy_l1_tx); + if (err) { + dev_err(hba->dev, "failed to power on mphy-l1-tx\n"); + goto out_power_off_l1_rx; + } + + return 0; + +out_power_off_l1_rx: + phy_power_off(ufs->mphy_l1_rx); +out_power_off_l0_tx: + phy_power_off(ufs->mphy_l0_tx); +out_power_off_l0_rx: + phy_power_off(ufs->mphy_l0_rx); + + return err; +} + +static void ufs_tegra_mphy_power_off(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + + phy_power_off(ufs->mphy_l0_rx); + phy_power_off(ufs->mphy_l0_tx); + phy_power_off(ufs->mphy_l1_rx); + phy_power_off(ufs->mphy_l1_tx); +} + +static int ufs_tegra_mphy_enable(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + int err; + + if (ufs->mphy_on) + return 0; + + err =3D ufs_tegra_mphy_init(hba); + if (err) + return err; + + err =3D ufs_tegra_mphy_power_on(hba); + if (err) { + ufs_tegra_mphy_exit(hba); + return err; + } + + ufs->mphy_on =3D true; + + /* Allow M-PHY to settle after power-on. */ + usleep_range(500, 600); + + return 0; +} + +static void ufs_tegra_mphy_disable(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + + if (!ufs->mphy_on) + return; + + ufs_tegra_mphy_power_off(hba); + ufs_tegra_mphy_exit(hba); + + ufs->mphy_on =3D false; +} + +static int ufs_tegra_mphy_configure_tx(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + int err; + + err =3D phy_configure(ufs->mphy_l0_tx, NULL); + if (err) + return err; + + return phy_configure(ufs->mphy_l1_tx, NULL); +} + +static int ufs_tegra_mphy_calibrate_tx(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + int err; + + err =3D phy_calibrate(ufs->mphy_l0_tx); + if (err) + return err; + + return phy_calibrate(ufs->mphy_l1_tx); +} + +static int ufs_tegra_mphy_calibrate_rx(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + int err; + + err =3D phy_configure(ufs->mphy_l1_rx, NULL); + if (err) + return err; + + err =3D phy_configure(ufs->mphy_l0_rx, NULL); + if (err) + return err; + + err =3D phy_calibrate(ufs->mphy_l1_rx); + if (err) + return err; + + return phy_calibrate(ufs->mphy_l0_rx); +} + +static void ufs_tegra_exit(struct ufs_hba *hba) +{ + ufs_tegra_mphy_disable(hba); +} + +static int ufs_tegra_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, + enum ufs_notify_change_status status) +{ + if (status =3D=3D PRE_CHANGE) + return 0; + + /* Runtime H8 park keeps the M-PHY powered; only tear it down + * on the full-teardown paths (system suspend, shutdown, or + * runtime PM with LINK_OFF). + */ + if (pm_op =3D=3D UFS_RUNTIME_PM && !ufshcd_is_link_off(hba)) + return 0; + + ufs_tegra_mphy_disable(hba); + + if (pm_op !=3D UFS_RUNTIME_PM) + ufshcd_set_link_off(hba); + + return 0; +} + +static int ufs_tegra_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) +{ + /* Skip when the M-PHY was left powered by the suspend path. */ + if (ufshcd_is_link_active(hba) || ufshcd_is_link_hibern8(hba)) + return 0; + + return ufs_tegra_mphy_enable(hba); +} + +static int ufs_tegra_reset(struct ufs_tegra *ufs) +{ + int err; + + err =3D reset_control_bulk_assert(ufs->num_resets, ufs->resets); + if (err) + return err; + + usleep_range(100, 200); + + err =3D reset_control_bulk_deassert(ufs->num_resets, ufs->resets); + if (err) + return err; + + usleep_range(500, 600); + + return 0; +} + +static int ufs_tegra_power_up_sequence(struct ufs_hba *hba) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + int err; + + err =3D ufs_tegra_reset(ufs); + if (err) + return err; + + return ufs_tegra_mphy_enable(hba); +} + +static void ufs_tegra_setup(struct ufs_hba *hba) +{ + ufs_tegra_configure_aux(hba); + ufs_tegra_update_hclk_div(hba); + ufshcd_rmwl(hba, MBL_MASK, MBL(UFS_TEGRA_MBL_MAX), UFSHC_DWC_BLOCK_BUSTHR= TL); +} + +static int ufs_tegra_hce_enable_notify(struct ufs_hba *hba, enum ufs_notif= y_change_status status) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + u32 value; + int err; + + switch (status) { + case PRE_CHANGE: + err =3D ufs_tegra_power_up_sequence(hba); + if (err) + return err; + + /* Assert device reset; POST_CHANGE releases it via + * ufs_tegra_configure_aux() so the HCE toggle pulses it. + */ + value =3D readl(ufs->aux + UFSHC_AUX_DEV_CTRL); + value &=3D ~DEV_CTRL_RESET; + writel(value, ufs->aux + UFSHC_AUX_DEV_CTRL); + break; + case POST_CHANGE: + value =3D readl(ufs->aux + UFSHC_AUX_SW_EN_CLK_SLCG); + value &=3D ~CLK_OVR_ON; + writel(value, ufs->aux + UFSHC_AUX_SW_EN_CLK_SLCG); + + ufs_tegra_setup(hba); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ufs_tegra_link_startup_notify(struct ufs_hba *hba, enum ufs_not= ify_change_status status) +{ + static const struct ufshcd_dme_attr_val post_change_attrs[] =3D { + { UIC_ARG_MIB(T_CONNECTIONSTATE), 0x1, DME_LOCAL }, + { UIC_ARG_MIB(PA_TXHSG1SYNCLENGTH), UFS_TEGRA_HSG_SYNC_LEN, DME_LOCAL }, + { UIC_ARG_MIB(PA_TXHSG2SYNCLENGTH), UFS_TEGRA_HSG_SYNC_LEN, DME_LOCAL }, + { UIC_ARG_MIB(PA_TXHSG3SYNCLENGTH), UFS_TEGRA_HSG_SYNC_LEN, DME_LOCAL }, + { UIC_ARG_MIB(PA_TXHSG4SYNCLENGTH), UFS_TEGRA_HSG_SYNC_LEN, DME_LOCAL }, + { UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), UFS_TEGRA_FC0_TIMEOUT, = DME_LOCAL }, + { UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), UFS_TEGRA_TC0_TIMEOUT, DME_= LOCAL }, + { UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), UFS_TEGRA_AFC0_TIMEOUT, DME_L= OCAL }, + { UIC_ARG_MIB(PA_PWRMODEUSERDATA0), UFS_TEGRA_FC0_TIMEOUT, DME_LOCAL }, + { UIC_ARG_MIB(PA_PWRMODEUSERDATA1), UFS_TEGRA_TC0_TIMEOUT, DME_LOCAL }, + { UIC_ARG_MIB(PA_PWRMODEUSERDATA2), UFS_TEGRA_AFC0_TIMEOUT, DME_LOCAL }, + }; + int err; + + switch (status) { + case PRE_CHANGE: + /* Arm TX calibration; RX capabilities are advertised in + * tegra_mphy_rx_power_on(). + */ + err =3D ufs_tegra_mphy_configure_tx(hba); + if (err) + return err; + break; + + case POST_CHANGE: + err =3D ufs_tegra_mphy_calibrate_tx(hba); + if (err) + return err; + + err =3D ufshcd_dwc_dme_set_attrs(hba, post_change_attrs, + ARRAY_SIZE(post_change_attrs)); + if (err) + return err; + + err =3D ufs_tegra_mphy_calibrate_rx(hba); + if (err) + return err; + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int ufs_tegra_negotiate_pwr_mode(struct ufs_hba *hba, + const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + + return ufshcd_negotiate_pwr_params(&ufs->host_params, dev_max_params, dev= _req_params); +} + +static int ufs_tegra_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, + struct ufs_pa_layer_attr *dev_req_params) +{ + struct ufs_tegra *ufs =3D ufshcd_get_variant(hba); + u32 value; + int err; + + if (status !=3D PRE_CHANGE) + return 0; + + err =3D ufshcd_dme_get(hba, UIC_ARG_MIB(VS_DEBUGSAVECONFIGTIME), &value); + if (err) + return err; + + value &=3D ~VS_DEBUGSAVECONFIGTIME_TREF; + value |=3D FIELD_PREP(VS_DEBUGSAVECONFIGTIME_TREF, UFS_TEGRA_SAVECONFIGTI= ME_TREF); + value &=3D ~VS_DEBUGSAVECONFIGTIME_SCT; + value |=3D FIELD_PREP(VS_DEBUGSAVECONFIGTIME_SCT, UFS_TEGRA_SAVECONFIGTIM= E_SCT); + + err =3D ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGSAVECONFIGTIME), value); + if (err) + return err; + + if (dev_req_params->hs_rate =3D=3D PA_HS_MODE_A || + dev_req_params->hs_rate =3D=3D PA_HS_MODE_B) { + err =3D clk_set_rate(ufs->phy_clk, UFS_TEGRA_PHY_CLK_HS_RATE_HZ); + if (err) + return err; + } + + err =3D ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx, PA_INITI= AL_ADAPT); + if (err) + return err; + + return 0; +} + +static int ufs_tegra_set_dma_mask(struct ufs_hba *hba) +{ + return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); +} + +static const struct ufs_hba_variant_ops ufs_tegra_vops =3D { + .name =3D "ufs-tegra", + .init =3D ufs_tegra_init, + .exit =3D ufs_tegra_exit, + .suspend =3D ufs_tegra_suspend, + .resume =3D ufs_tegra_resume, + .hce_enable_notify =3D ufs_tegra_hce_enable_notify, + .negotiate_pwr_mode =3D ufs_tegra_negotiate_pwr_mode, + .pwr_change_notify =3D ufs_tegra_pwr_change_notify, + .link_startup_notify =3D ufs_tegra_link_startup_notify, + .set_dma_mask =3D ufs_tegra_set_dma_mask, +}; + +static int ufs_tegra_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int err; + + err =3D ufshcd_pltfrm_init(pdev, &ufs_tegra_vops); + if (err) + return dev_err_probe(dev, err, "ufshcd platform init failed\n"); + + return 0; +} + +static void ufs_tegra_remove(struct platform_device *pdev) +{ + ufshcd_pltfrm_remove(pdev); +} + +static const struct dev_pm_ops ufs_tegra_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) + SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) +}; + +static const struct of_device_id ufs_tegra_of_match[] =3D { + { .compatible =3D "nvidia,tegra264-ufs", }, + {} +}; +MODULE_DEVICE_TABLE(of, ufs_tegra_of_match); + +static struct platform_driver ufs_tegra_driver =3D { + .probe =3D ufs_tegra_probe, + .remove =3D ufs_tegra_remove, + .driver =3D { + .name =3D "ufs-tegra", + .pm =3D &ufs_tegra_pm_ops, + .of_match_table =3D ufs_tegra_of_match, + }, +}; +module_platform_driver(ufs_tegra_driver); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_AUTHOR("Kartik Rajput "); +MODULE_DESCRIPTION("NVIDIA Tegra UFS host controller driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0