From nobody Fri Sep 25 20:07:31 2026 Received: from mail-24416.protonmail.ch (mail-24416.protonmail.ch [109.224.244.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2D21345ED3; Wed, 9 Sep 2026 03:11:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788923485; cv=none; b=qo7FoT/bt3h+vFxtRF4UER7ki9wWxGYpLOHWiMEICpHyplLiDDwy1hqn/EUErLEBGRhnuXBB+rl29aZd6XO39e/QDLERa9fBg28WLCDELoep7WZ5NlmJ0E+sIlpKP2UCMUFnOP29L4gKYezOIRrJJwoM6E55/6q6KpD1V4U0xug= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788923485; c=relaxed/simple; bh=dLNKuhcrePHbBifLeDTkAyjnCHYYE/stTjBihrmk+bg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uM0p/kwYT49oRHlzi6MKjPbKHJXA9rGe5lwie5GgVmdxg3LQKSMG+fOzMn4+h3g5W+RNe1OJV6yGvPnpXvm3cfTwWlMUqRd4xf1mkFs+C0ttunaVLYe9jVnnjZhtJLMyK6MIKN2nBqfXRz/iSnsRiCud9/63XS8iOpaRN6Vsxqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=proton.me; spf=pass smtp.mailfrom=proton.me; dkim=pass (2048-bit key) header.d=proton.me header.i=@proton.me header.b=JS+ehv2o; arc=none smtp.client-ip=109.224.244.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=proton.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=proton.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=proton.me header.i=@proton.me header.b="JS+ehv2o" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1788923471; x=1789182671; bh=6V5vNBbkmNPezVZefxzahR0ftBgmoG/UPsu/x9aLVH4=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=JS+ehv2oFu9q3QePjIySoIdMB2f791dLteUPVv8SjxqnZE5+uD0+l7w5+9aU9Z/qn 8QjY3UVNfB5hLdF59Ug4dvrV6yNo0h7ibqmmkgwmbT7mxgzxMLOqZbtUZSxWeEE8G5 u0vXXN/v9dNH6WKcj+CiePsw3AmNWiXH+vufP+nicVpmxJb/jU3erfZQZoJO/BYaZh kPFoHhAePSg75xxWBtRD8R8KeWVrc8N8S9bc1eqy8OOMgHaZsrDRD1FWtmX0YuZV1t qCbcuv2oqCQCHlLNVK007cC5PnMVPONdbm6f57Kg8G4tbDqsil7xmDbW04HqMJMsTg PLyiCH/tnUsgw== Date: Wed, 09 Sep 2026 03:11:04 +0000 To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alex Elder , Bjorn Andersson , Konrad Dybcio From: Esteban Urrutia Cc: Esteban Urrutia , Nazar Kompanets , linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 1/3] dt-bindings: net: qcom,ipa: Add SM8450 compatible Message-ID: <20260909-sm8450-ipa-v2-1-2deb8b4e91a5@proton.me> In-Reply-To: <20260909-sm8450-ipa-v2-0-2deb8b4e91a5@proton.me> References: <20260909-sm8450-ipa-v2-0-2deb8b4e91a5@proton.me> Feedback-ID: 147889766:user:proton X-Pm-Message-ID: aba9c28308fded0664a4deff4d2b230bb8215508 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the SM8450 SoC, which uses IPA v5.1. Acked-by: Krzysztof Kozlowski Co-developed-by: Nazar Kompanets Signed-off-by: Nazar Kompanets Signed-off-by: Esteban Urrutia --- Documentation/devicetree/bindings/net/qcom,ipa.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml b/Document= ation/devicetree/bindings/net/qcom,ipa.yaml index 68ec76fe4473..db91bfaaf833 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipa.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipa.yaml @@ -53,6 +53,7 @@ properties: - qcom,sdx65-ipa - qcom,sm6350-ipa - qcom,sm8350-ipa + - qcom,sm8450-ipa - qcom,sm8550-ipa - items: - enum: --=20 2.55.0 From nobody Fri Sep 25 20:07:31 2026 Received: from mail-4322.protonmail.ch (mail-4322.protonmail.ch [185.70.43.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAE6A345ED9; Wed, 9 Sep 2026 03:11:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788923499; cv=none; b=DM0Z9kOdCbsicN6bDHxU4YeQTczj/QlqzWQ1a0+Gl6ijo2KILgk9Wn99FLWLI8nNY1VAhSPT4hLA44GZ9BHZi/Oun1t0JUc/DQdrsxVUZkVB8twuWB3oNM7cnMKSwGXsAqcvY1/3XJfPENhB12pJcITOVnYYrKn2oYmAaA7k79Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788923499; c=relaxed/simple; bh=BRwGrfU5Z0rAW7IvaEMnMp7b8lHMtIsZNJYMSdH1G9Y=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U2P1AIipn/Tjp96g0RwWbL72QAKglyFAFqPVoYaSTmgHLCPMGjxrprBeUm3FJzhV/mfDwtq13GjtRU6S2CHo5SynBmt4pieZvHxpKD42rdAmqNfikIfq6xDUscxy6Ad3ELXgXjRrsDU/FYHqtjOy58Xq7Bd2US0inMAf4ymJCBk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=proton.me; spf=pass smtp.mailfrom=proton.me; dkim=pass (2048-bit key) header.d=proton.me header.i=@proton.me header.b=IBqNukQs; arc=none smtp.client-ip=185.70.43.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=proton.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=proton.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=proton.me header.i=@proton.me header.b="IBqNukQs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1788923489; x=1789182689; bh=5nkK3I8dOESPdEnrk5253yGEG1lECIstukh3Bvwj5hI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=IBqNukQs7tEbaitXf+CRlBCmQ3akpJU8O0UFozqoXfpUTgmrvxeQcvLQ2se/Sp+YF hCLLVBpmMSfz5DomNbyZwvw1ci/8pAVJjARyl2+MxkOQcrQ1yrE+BNhRXkz4BoNZcx uK1FxYWzdKZ+XyX4WKiTsQgt163xtmDkL3u25dOibyqzHF5HMUTDuXAqGvMluJzqQX VkR4nb9kS3XDTL1efGRYxK8vNtanegiejYIAUzDedc4Zgn8GP6Vkh+UD6B6qLgKos9 fUJnl9qaRkiTjQCpryC/JSzhP50lVQhSklGCWOWDFbO+pBii7MfEdogqnZbf92NsUM 5TvZkJueGQxvg== Date: Wed, 09 Sep 2026 03:11:22 +0000 To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alex Elder , Bjorn Andersson , Konrad Dybcio From: Esteban Urrutia Cc: Esteban Urrutia , Nazar Kompanets , linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org Subject: [PATCH v2 2/3] net: ipa: Add IPA v5.1 configuration data Message-ID: <20260909-sm8450-ipa-v2-2-2deb8b4e91a5@proton.me> In-Reply-To: <20260909-sm8450-ipa-v2-0-2deb8b4e91a5@proton.me> References: <20260909-sm8450-ipa-v2-0-2deb8b4e91a5@proton.me> Feedback-ID: 147889766:user:proton X-Pm-Message-ID: 0a9f974822474a4b8d402165d845216a156a5f2f Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the configuration data required for IPA v5.1, which is used in the Qualcomm SM8450 SoC. Co-developed-by: Nazar Kompanets Signed-off-by: Nazar Kompanets Signed-off-by: Esteban Urrutia --- drivers/net/ipa/Makefile | 2 +- drivers/net/ipa/data/ipa_data-v5.1.c | 476 +++++++++++++++++++++++++++++++= ++++ drivers/net/ipa/gsi_reg.c | 1 + drivers/net/ipa/ipa_data.h | 1 + drivers/net/ipa/ipa_main.c | 4 + drivers/net/ipa/ipa_reg.c | 1 + 6 files changed, 484 insertions(+), 1 deletion(-) diff --git a/drivers/net/ipa/Makefile b/drivers/net/ipa/Makefile index e148ec3c1a10..d4995c2e8ca0 100644 --- a/drivers/net/ipa/Makefile +++ b/drivers/net/ipa/Makefile @@ -7,7 +7,7 @@ IPA_REG_VERSIONS :=3D 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0 5.5 # Some IPA versions can reuse another set of GSI register definitions. GSI_REG_VERSIONS :=3D 3.1 3.5.1 4.0 4.5 4.9 4.11 5.0 =20 -IPA_DATA_VERSIONS :=3D 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0 5.2 5.5 +IPA_DATA_VERSIONS :=3D 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0 5.1 5.2 5.5 =20 obj-$(CONFIG_QCOM_IPA) +=3D ipa.o =20 diff --git a/drivers/net/ipa/data/ipa_data-v5.1.c b/drivers/net/ipa/data/ip= a_data-v5.1.c new file mode 100644 index 000000000000..7d7bc193b774 --- /dev/null +++ b/drivers/net/ipa/data/ipa_data-v5.1.c @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2023-2024 Linaro Ltd. */ +/* Copyright (C) 2026 Nazar Kompanets */ +/* Copyright (C) 2026 Esteban Urrutia */ + +#include +#include + +#include "../ipa_data.h" +#include "../ipa_endpoint.h" +#include "../ipa_mem.h" +#include "../ipa_version.h" + +/** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.1= */ +enum ipa_resource_type { + /* Source resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS =3D 0, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_RESOURCE_TYPE_SRC_HPS_DMARS, + IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, + + /* Destination resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_DST_DATA_SECTORS =3D 0, + IPA_RESOURCE_TYPE_DST_DPS_DMARS, + IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS, +}; + +/* Resource groups used for an SoC having IPA v5.1 */ +enum ipa_rsrc_group_id { + /* Source resource group identifiers */ + IPA_RSRC_GROUP_SRC_UL =3D 0, + IPA_RSRC_GROUP_SRC_DL, + IPA_RSRC_GROUP_SRC_DMA, + IPA_RSRC_GROUP_SRC_QDSS, + IPA_RSRC_GROUP_SRC_URLLC, + IPA_RSRC_GROUP_SRC_U_RX_QC, + IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ + + /* Destination resource group identifiers */ + IPA_RSRC_GROUP_DST_UL =3D 0, + IPA_RSRC_GROUP_DST_DL, + IPA_RSRC_GROUP_DST_UNUSED_2, + IPA_RSRC_GROUP_DST_UNUSED_3, + IPA_RSRC_GROUP_DST_UNUSED_4, + IPA_RSRC_GROUP_DST_UC, + IPA_RSRC_GROUP_DST_DRB_IP, + IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ +}; + +/* QSB configuration data for an SoC having IPA v5.1 */ +static const struct ipa_qsb_data ipa_qsb_data[] =3D { + [IPA_QSB_MASTER_DDR] =3D { + .max_writes =3D 0, + .max_reads =3D 0, /* no limit (hardware max) */ + .max_reads_beats =3D 0, + }, + [IPA_QSB_MASTER_PCIE] =3D { + .max_writes =3D 0, + .max_reads =3D 0, /* no limit (hardware max) */ + .max_reads_beats =3D 0, + }, +}; + +/* Endpoint configuration data for an SoC having IPA v5.1 */ +static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] =3D { + [IPA_ENDPOINT_AP_COMMAND_TX] =3D { + .ee_id =3D GSI_EE_AP, + .channel_id =3D 12, + .endpoint_id =3D 14, + .toward_ipa =3D true, + .channel =3D { + .tre_count =3D 256, + .event_count =3D 256, + .tlv_count =3D 20, + }, + .endpoint =3D { + .config =3D { + .resource_group =3D IPA_RSRC_GROUP_SRC_UL, + .dma_mode =3D true, + .dma_endpoint =3D IPA_ENDPOINT_AP_LAN_RX, + .tx =3D { + .seq_type =3D IPA_SEQ_DMA, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_LAN_RX] =3D { + .ee_id =3D GSI_EE_AP, + .channel_id =3D 13, + .endpoint_id =3D 16, + .toward_ipa =3D false, + .channel =3D { + .tre_count =3D 256, + .event_count =3D 256, + .tlv_count =3D 9, + }, + .endpoint =3D { + .config =3D { + .resource_group =3D IPA_RSRC_GROUP_DST_UL, + .aggregation =3D true, + .status_enable =3D true, + .rx =3D { + .buffer_size =3D 8192, + .pad_align =3D ilog2(sizeof(u32)), + .aggr_time_limit =3D 500, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_TX] =3D { + .ee_id =3D GSI_EE_AP, + .channel_id =3D 11, + .endpoint_id =3D 2, + .toward_ipa =3D true, + .channel =3D { + .tre_count =3D 512, + .event_count =3D 512, + .tlv_count =3D 25, + }, + .endpoint =3D { + .filter_support =3D true, + .config =3D { + .resource_group =3D IPA_RSRC_GROUP_SRC_UL, + .checksum =3D true, + .qmap =3D true, + .status_enable =3D true, + .tx =3D { + .seq_type =3D IPA_SEQ_2_PASS_SKIP_LAST_UC, + .status_endpoint =3D + IPA_ENDPOINT_MODEM_AP_RX, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_RX] =3D { + .ee_id =3D GSI_EE_AP, + .channel_id =3D 1, + .endpoint_id =3D 23, + .toward_ipa =3D false, + .channel =3D { + .tre_count =3D 256, + .event_count =3D 256, + .tlv_count =3D 9, + }, + .endpoint =3D { + .config =3D { + .resource_group =3D IPA_RSRC_GROUP_DST_UL, + .checksum =3D true, + .qmap =3D true, + .aggregation =3D true, + .rx =3D { + .buffer_size =3D 8192, + .aggr_time_limit =3D 500, + .aggr_close_eof =3D true, + }, + }, + }, + }, + [IPA_ENDPOINT_MODEM_AP_TX] =3D { + .ee_id =3D GSI_EE_MODEM, + .channel_id =3D 0, + .endpoint_id =3D 12, + .toward_ipa =3D true, + .endpoint =3D { + .filter_support =3D true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_RX] =3D { + .ee_id =3D GSI_EE_MODEM, + .channel_id =3D 7, + .endpoint_id =3D 21, + .toward_ipa =3D false, + }, + [IPA_ENDPOINT_MODEM_DL_NLO_TX] =3D { + .ee_id =3D GSI_EE_MODEM, + .channel_id =3D 2, + .endpoint_id =3D 15, + .toward_ipa =3D true, + .endpoint =3D { + .filter_support =3D true, + }, + }, +}; + +/* Source resource configuration data for an SoC having IPA v5.1 */ +static const struct ipa_resource ipa_resource_src[] =3D { + [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] =3D { + .limits[IPA_RSRC_GROUP_SRC_UL] =3D { + .min =3D 7, .max =3D 12, + }, + .limits[IPA_RSRC_GROUP_SRC_URLLC] =3D { + .min =3D 1, .max =3D 63, + }, + .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] =3D { + .min =3D 0, .max =3D 63, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] =3D { + .limits[IPA_RSRC_GROUP_SRC_UL] =3D { + .min =3D 21, .max =3D 21, + }, + .limits[IPA_RSRC_GROUP_SRC_URLLC] =3D { + .min =3D 10, .max =3D 10, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] =3D { + .limits[IPA_RSRC_GROUP_SRC_UL] =3D { + .min =3D 33, .max =3D 33, + }, + .limits[IPA_RSRC_GROUP_SRC_URLLC] =3D { + .min =3D 20, .max =3D 20, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] =3D { + .limits[IPA_RSRC_GROUP_SRC_UL] =3D { + .min =3D 0, .max =3D 63, + }, + /* Marked as unused downstream */ + .limits[IPA_RSRC_GROUP_SRC_DMA] =3D { + .min =3D 0, .max =3D 63, + }, + /* Marked as unused downstream */ + .limits[IPA_RSRC_GROUP_SRC_QDSS] =3D { + .min =3D 0, .max =3D 63, + }, + .limits[IPA_RSRC_GROUP_SRC_URLLC] =3D { + .min =3D 1, .max =3D 63, + }, + .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] =3D { + .min =3D 0, .max =3D 63, + }, + }, + [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] =3D { + .limits[IPA_RSRC_GROUP_SRC_UL] =3D { + .min =3D 38, .max =3D 38, + }, + .limits[IPA_RSRC_GROUP_SRC_URLLC] =3D { + .min =3D 16, .max =3D 16, + }, + }, +}; + +/* Destination resource configuration data for an SoC having IPA v5.1 */ +static const struct ipa_resource ipa_resource_dst[] =3D { + [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] =3D { + .limits[IPA_RSRC_GROUP_DST_UL] =3D { + .min =3D 6, .max =3D 6, + }, + .limits[IPA_RSRC_GROUP_DST_DL] =3D { + .min =3D 5, .max =3D 5, + }, + .limits[IPA_RSRC_GROUP_DST_DRB_IP] =3D { + .min =3D 39, .max =3D 39, + }, + }, + [IPA_RESOURCE_TYPE_DST_DPS_DMARS] =3D { + .limits[IPA_RSRC_GROUP_DST_UL] =3D { + .min =3D 0, .max =3D 3, + }, + .limits[IPA_RSRC_GROUP_DST_DL] =3D { + .min =3D 0, .max =3D 3, + }, + }, + [IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] =3D { + .limits[IPA_RSRC_GROUP_DST_UL] =3D { + .min =3D 0, .max =3D 63, + }, + .limits[IPA_RSRC_GROUP_DST_DL] =3D { + .min =3D 0, .max =3D 63, + }, + }, +}; + +/* Resource configuration data for an SoC having IPA v5.1 */ +static const struct ipa_resource_data ipa_resource_data =3D { + .rsrc_group_dst_count =3D IPA_RSRC_GROUP_DST_COUNT, + .rsrc_group_src_count =3D IPA_RSRC_GROUP_SRC_COUNT, + .resource_src_count =3D ARRAY_SIZE(ipa_resource_src), + .resource_src =3D ipa_resource_src, + .resource_dst_count =3D ARRAY_SIZE(ipa_resource_dst), + .resource_dst =3D ipa_resource_dst, +}; + +/* IPA-resident memory region data for an SoC having IPA v5.1 */ +static const struct ipa_mem ipa_mem_local_data[] =3D { + { + .id =3D IPA_MEM_UC_EVENT_RING, + .offset =3D 0x0000, + .size =3D 0x1000, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_UC_SHARED, + .offset =3D 0x1000, + .size =3D 0x0080, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_UC_INFO, + .offset =3D 0x1080, + .size =3D 0x0200, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_V4_FILTER_HASHED, + .offset =3D 0x1288, + .size =3D 0x0078, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V4_FILTER, + .offset =3D 0x1308, + .size =3D 0x0078, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V6_FILTER_HASHED, + .offset =3D 0x1388, + .size =3D 0x0078, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V6_FILTER, + .offset =3D 0x1408, + .size =3D 0x0078, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V4_ROUTE_HASHED, + .offset =3D 0x1488, + .size =3D 0x0098, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V4_ROUTE, + .offset =3D 0x1528, + .size =3D 0x0098, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V6_ROUTE_HASHED, + .offset =3D 0x15c8, + .size =3D 0x0098, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V6_ROUTE, + .offset =3D 0x1668, + .size =3D 0x0098, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_MODEM_HEADER, + .offset =3D 0x1708, + .size =3D 0x0240, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_AP_HEADER, + .offset =3D 0x1948, + .size =3D 0x01e0, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_MODEM_PROC_CTX, + .offset =3D 0x1b40, + .size =3D 0x0b20, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_AP_PROC_CTX, + .offset =3D 0x2660, + .size =3D 0x0200, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_STATS_QUOTA_MODEM, + .offset =3D 0x2868, + .size =3D 0x0060, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_STATS_QUOTA_AP, + .offset =3D 0x28c8, + .size =3D 0x0048, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_STATS_TETHERING, + .offset =3D 0x2910, + .size =3D 0x03c0, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_STATS_FILTER_ROUTE, + .offset =3D 0x2cd0, + .size =3D 0x0ba0, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_STATS_DROP, + .offset =3D 0x3870, + .size =3D 0x0020, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_MODEM, + .offset =3D 0x3898, + .size =3D 0x0d48, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_NAT_TABLE, + .offset =3D 0x45e0, + .size =3D 0x0900, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_PDN_CONFIG, + .offset =3D 0x4ee8, + .size =3D 0x0100, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_MODEM_STATS_DROP, + .offset =3D 0x4fe8, + .size =3D 0x0018, + .canary_count =3D 0, + }, +}; + +/* Memory configuration data for an SoC having IPA v5.1 */ +static const struct ipa_mem_data ipa_mem_data =3D { + .local_count =3D ARRAY_SIZE(ipa_mem_local_data), + .local =3D ipa_mem_local_data, + .imem_addr =3D 0x146a8000, + .imem_size =3D 0x00002000, + .smem_size =3D 0x00009000, +}; + +/* Interconnect rates are in 1000 byte/second units */ +static const struct ipa_interconnect_data ipa_interconnect_data[] =3D { + { + .name =3D "memory", + .peak_bandwidth =3D 1900000, /* 1.9 GBps */ + .average_bandwidth =3D 590000, /* 590 MBps */ + }, + /* Average rate is unused for the next interconnect */ + { + .name =3D "config", + .peak_bandwidth =3D 76800, /* 76.8 MBps */ + .average_bandwidth =3D 0, /* unused */ + }, +}; + +/* Clock and interconnect configuration data for an SoC having IPA v5.1 */ +static const struct ipa_power_data ipa_power_data =3D { + .core_clock_rate =3D 120 * 1000 * 1000, /* Hz */ + .interconnect_count =3D ARRAY_SIZE(ipa_interconnect_data), + .interconnect_data =3D ipa_interconnect_data, +}; + +/* Configuration data for an SoC having IPA v5.1. */ +const struct ipa_data ipa_data_v5_1 =3D { + .version =3D IPA_VERSION_5_1, + .qsb_count =3D ARRAY_SIZE(ipa_qsb_data), + .qsb_data =3D ipa_qsb_data, + .modem_route_count =3D 11, + .endpoint_count =3D ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data =3D ipa_gsi_endpoint_data, + .resource_data =3D &ipa_resource_data, + .mem_data =3D &ipa_mem_data, + .power_data =3D &ipa_power_data, +}; diff --git a/drivers/net/ipa/gsi_reg.c b/drivers/net/ipa/gsi_reg.c index e13cf835a013..a57072ba4bef 100644 --- a/drivers/net/ipa/gsi_reg.c +++ b/drivers/net/ipa/gsi_reg.c @@ -110,6 +110,7 @@ static const struct regs *gsi_regs(struct gsi *gsi) return &gsi_regs_v4_11; =20 case IPA_VERSION_5_0: + case IPA_VERSION_5_1: case IPA_VERSION_5_2: case IPA_VERSION_5_5: return &gsi_regs_v5_0; diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h index 3eb9dc2ce339..fe6f7d5bfe88 100644 --- a/drivers/net/ipa/ipa_data.h +++ b/drivers/net/ipa/ipa_data.h @@ -253,6 +253,7 @@ extern const struct ipa_data ipa_data_v4_7; extern const struct ipa_data ipa_data_v4_9; extern const struct ipa_data ipa_data_v4_11; extern const struct ipa_data ipa_data_v5_0; +extern const struct ipa_data ipa_data_v5_1; extern const struct ipa_data ipa_data_v5_2; extern const struct ipa_data ipa_data_v5_5; =20 diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 14ac2d2faf7c..84bec461d22c 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -672,6 +672,10 @@ static const struct of_device_id ipa_match[] =3D { .compatible =3D "qcom,sdx65-ipa", .data =3D &ipa_data_v5_0, }, + { + .compatible =3D "qcom,sm8450-ipa", + .data =3D &ipa_data_v5_1, + }, { .compatible =3D "qcom,milos-ipa", .data =3D &ipa_data_v5_2, diff --git a/drivers/net/ipa/ipa_reg.c b/drivers/net/ipa/ipa_reg.c index 30bd69f4c147..5f22ca6295b1 100644 --- a/drivers/net/ipa/ipa_reg.c +++ b/drivers/net/ipa/ipa_reg.c @@ -125,6 +125,7 @@ static const struct regs *ipa_regs(enum ipa_version ver= sion) case IPA_VERSION_4_11: return &ipa_regs_v4_11; case IPA_VERSION_5_0: + case IPA_VERSION_5_1: case IPA_VERSION_5_2: return &ipa_regs_v5_0; case IPA_VERSION_5_5: --=20 2.55.0 From nobody Fri Sep 25 20:07:31 2026 Received: from mail-24418.protonmail.ch (mail-24418.protonmail.ch [109.224.244.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 479DB2BD587 for ; Wed, 9 Sep 2026 03:11:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788923518; cv=none; b=XXmX3zahCQcV6pm+3deCsLcS6kydWQsunUSLo6FanwuwRAbmanm6sinLnIz6ADM/+3qLOJt8KLIn9pBtGaPuWkbQezfbIKP7+udFcRrP/0OLtIeo9EzizJm3bP4/dy8AKg2s3CNpkUOq3cdszFT432tOCj0wCuhXGsau2xnLJQ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788923518; c=relaxed/simple; bh=X7A6ojzz9jLweLIbQWl37phoYRhtbnjKLl8m+DfmcRQ=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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b=ZewXl7t4iN6BherGDbIJyRFYRNdCqFL+LTB4QXlA+/Wz4aqmZfZY6Bed1oAmHT0Df bE3COl5Uo5nkh0prXonKuN/xAKJyEUhDDh1/Ct2aIngae8d7w5WLvAfG7FARa0glyQ 1E+4CIiswxP3AHiaQ4qQ/6nCj/AhSZccttTAs3jmDEh4dyFqqWABV1gBIz2p4l/R5X ELrWmQB05iXJBgnGdRYz/CTrMZ/e+j2s/eP3FCkHLsEuvAcP85tShknUNExMoBYup7 +4ihSw8ohw2iZEDKcYwDtYSVVLVNznD3P0xZ69OL+iAmlQdM8dn4NrQHAefuLQqJYW m7CMYgNir5BJA== Date: Wed, 09 Sep 2026 03:11:39 +0000 To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alex Elder , Bjorn Andersson , Konrad Dybcio From: Esteban Urrutia Cc: Esteban Urrutia , Nazar Kompanets , linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org Subject: [PATCH v2 3/3] arm64: dts: qcom: sm8450: Add IPA node Message-ID: <20260909-sm8450-ipa-v2-3-2deb8b4e91a5@proton.me> In-Reply-To: <20260909-sm8450-ipa-v2-0-2deb8b4e91a5@proton.me> References: <20260909-sm8450-ipa-v2-0-2deb8b4e91a5@proton.me> Feedback-ID: 147889766:user:proton X-Pm-Message-ID: 07fb0d36c9eba0c0c5ab037e212d75d3f31050e9 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the description of the IPA block in the SM8450 SoC. Co-developed-by: Nazar Kompanets Signed-off-by: Nazar Kompanets Signed-off-by: Esteban Urrutia --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 59 +++++++++++++++++++++++++++++++-= ---- 1 file changed, 52 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index b8793482b181..95b6fd22a846 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2625,6 +2625,47 @@ adreno_smmu: iommu@3da0000 { dma-coherent; }; =20 + ipa: ipa@3f40000 { + compatible =3D "qcom,sm8450-ipa"; + + reg =3D <0 0x3f40000 0 0x10000>, + <0 0x3f50000 0 0x5000>, + <0 0x3e04000 0 0xfc000>; + reg-names =3D "ipa-reg", + "ipa-shared", + "gsi"; + iommus =3D <&apps_smmu 0x5c0 0x0>, + <&apps_smmu 0x5c2 0x0>; + + interrupts-extended =3D <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks =3D <&rpmhcc RPMH_IPA_CLK>; + clock-names =3D "core"; + + interconnects =3D <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; + interconnect-names =3D "memory", + "config"; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names =3D "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + sram =3D <&ipa_modem_tables>; + + status =3D "disabled"; + }; + usb_1_hsphy: phy@88e3000 { compatible =3D "qcom,sm8450-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; @@ -4957,21 +4998,25 @@ cti@13900000 { clock-names =3D "apb_pclk"; }; =20 - sram@146aa000 { + sram@14680000 { compatible =3D "qcom,sm8450-imem", "syscon", "simple-mfd"; - reg =3D <0 0x146aa000 0 0x1000>; - ranges =3D <0 0 0x146aa000 0x1000>; + reg =3D <0 0x14680000 0 0x40000>; + ranges =3D <0 0 0x14680000 0x40000>; =20 #address-cells =3D <1>; #size-cells =3D <1>; =20 - minidump_config: minidump-sram@1c { - reg =3D <0x1c 0x4>; + ipa_modem_tables: modem-tables@28000 { + reg =3D <0x28000 0x2000>; + }; + + minidump_config: minidump-sram@2a01c { + reg =3D <0x2a01c 0x4>; }; =20 - pil-reloc@94c { + pil-reloc@2a94c { compatible =3D "qcom,pil-reloc-info"; - reg =3D <0x94c 0xc8>; + reg =3D <0x2a94c 0xc8>; }; }; =20 --=20 2.55.0