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The top-level node describes the IP wrapper, which owns the six shared IP clocks and the xlnx,num-priorities parameter, and has two children: - xlnx,tsn-ep-mac: the endpoint MAC, owning the host-side DMA channels (dmas / dma-names / tx-queues-config). - xlnx,tsn-switch: the three-port Ethernet switch covering the switch fabric and the two per-MAC register windows. The MDIO controllers and PTP register blocks sit at fixed offsets inside the per-MAC windows, accessed through the mdio-1 / mdio-2 children and per-MAC interrupt-names entries. Each external port@N references its PHY through a phy-handle in the matching mdio- child. Co-developed-by: Nagadheeraj Rottela Signed-off-by: Nagadheeraj Rottela Signed-off-by: Srinivas Neeli --- Changes in v2: - Describe only the Bridged Endpoint configuration. The IP has so far been simulated only as a bridged endpoint, so the binding and driver describe that configuration alone. Support for an Endpoint-only design will be add= ed once that IP variant is simulated. - Rename ep-mac@ to ethernet@ and mdio-mac1/mdio-mac2 to mdio-1/mdio-2, and anchor the node names (^ethernet@[0-9a-f]+$, ^switch@[0-9a-f]+$), per ethernet-controller.yaml and mdio.yaml. - Cap TX at 8 and RX at 8 channels. The IP exposes 8 priorities, so it drives at most 8 TX and 8 RX MCDMA channels. dma-names lists both directions, so its combined maxItems is 16 (8 TX + 8 RX). V1 allowed up to 16 per direction, which the hardware cannot use. - Set additionalProperties: false on tx-queues-config and its queue nodes. - Drop reg from the wrapper node. It has no registers of its own, ranges already describes the child windows. - Add minItems: 7 to the switch interrupts to match interrupt-names. - Use a ^(ethernet-)?ports$ container with additionalProperties: false and = its own #address-cells/#size-cells, and require either ports or ethernet-port= s. - Require ethernet on the CPU port@0. - Add reg (enum [1, 2]) on the external port@[1-2] ports and require reg, phy-mode and phy-handle. MAC1 and MAC2 use gmii/rgmii/rgmii-id. - Require port@0, port@1 and port@2. The IP is a fixed three-port bridged design (port@0 CPU, port@1 MAC1, port@2 MAC2), so a device tree missing any of them cannot describe working hardware. - Add #address-cells and #size-cells (both const 1) on the wrapper node, which the child ethernet@/switch@ windows need now that reg is dropped, and set unevaluatedProperties: false on the endpoint node. --- .../net/xlnx,tsn-endpoint-ethernet-mac.yaml | 364 +++++++++++++++++= ++++ MAINTAINERS | 7 + 2 files changed, 371 insertions(+) diff --git a/Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethern= et-mac.yaml b/Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ether= net-mac.yaml new file mode 100644 index 000000000000..4e65d1710da7 --- /dev/null +++ b/Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.= yaml @@ -0,0 +1,364 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/xlnx,tsn-endpoint-ethernet-mac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx TSN Endpoint Ethernet MAC + +description: + TSN Endpoint Ethernet MAC IP implements IEEE 802.1 Time-Sensitive + Networking (TSN) standards and provides low-latency network connectivity + in the Bridged Endpoint configuration. The IP integrates a three-port + switch, with two ports connected to the external network and one port + connected to an internal endpoint. It also supports GMII/RGMII interfaces + for connection to an external PHY, enabling full-duplex operation at + 100 Mb/s and 1 Gb/s speeds. + +maintainers: + - Srinivas Neeli + - Nagadheeraj Rottela + +properties: + compatible: + const: xlnx,tsn-endpoint-ethernet-mac-3.0 + + clocks: + items: + - description: GTX clock for transmitter logic and RTC + - description: GTX 90-degree phase shifted clock for RGMII + - description: Host RX FIFO clock + - description: Host TX FIFO clock + - description: Reference clock for IDELAY control + - description: AXI-Lite register interface clock + + clock-names: + items: + - const: gtx + - const: gtx90 + - const: host_rxfifo + - const: host_txfifo + - const: ref + - const: s_axi + + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + xlnx,num-priorities: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 2 + maximum: 8 + description: + Number of traffic classes (priorities) configured in the IP. + This is an IP configuration parameter that determines the number of + priority queues available for QoS scheduling. Traffic classes map to + IEEE 802.1Q priority levels (0-7). + +patternProperties: + "^ethernet@[0-9a-f]+$": + type: object + $ref: /schemas/net/ethernet-controller.yaml# + unevaluatedProperties: false + description: + Endpoint MAC sub-node. Provides the host-side data path through the + DMA channels described by its dmas / dma-names. + properties: + compatible: + const: xlnx,tsn-ep-mac + + reg: + maxItems: 1 + + dmas: + minItems: 2 + maxItems: 16 + + dma-names: + minItems: 2 + maxItems: 16 + items: + pattern: "^(tx|rx)_chan[0-7]$" + description: | + Names matching the entries in 'dmas', one per DMA channel and in + the same order. TX channel names use "tx_chan" and RX channel + names use "rx_chan", where N is 0..7. Example: "tx_chan0", + "tx_chan1", ..., "rx_chan0", "rx_chan1", .... + + tx-queues-config: + type: object + additionalProperties: false + description: + TX queue configuration node that maps IP priority queues to + DMA TX channels. The TSN IP supports multiple priority queues for + QoS scheduling, and each queue can be connected to a specific DMA + channel. This mapping defines which DMA TX channel is used to + transmit packets for each priority queue. For example, queue0 + with xlnx,dma-channel-num set to 5 means priority queue 0 uses + tx_chan5 for data transfer. + + patternProperties: + "^queue[0-7]$": + type: object + additionalProperties: false + + description: + Each subnode represents a priority queue. The + xlnx,dma-channel-num property specifies which DMA TX channel + (tx_chan0 to tx_chan7) is connected to this queue for + transmitting packets. + properties: + xlnx,dma-channel-num: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + DMA channel that transmits this priority queue, given as + the N of the tx_chanN entry in dma-names. + minimum: 0 + maximum: 7 + + required: + - xlnx,dma-channel-num + + required: + - compatible + - reg + - dmas + - dma-names + - tx-queues-config + + "^switch@[0-9a-f]+$": + type: object + $ref: /schemas/net/dsa/dsa.yaml#/$defs/ethernet-ports + description: + Three-port Ethernet switch sub-node. Contains the switch fabric + register window and the two per-MAC register windows. Each per-MAC + window houses an MDIO controller and a PTP register block at fixed + offsets. The IP's per-MAC and PTP-timer interrupts are exposed here. + + properties: + compatible: + const: xlnx,tsn-switch + + reg: + items: + - description: Switch fabric register window + - description: MAC1 register window (includes MDIO and PTP) + - description: MAC2 register window (includes MDIO and PTP) + + reg-names: + items: + - const: switch + - const: mac1 + - const: mac2 + + interrupts: + minItems: 7 + maxItems: 7 + + interrupt-names: + items: + - const: ptp_rx_mac1 + - const: ptp_tx_mac1 + - const: mac_irq_mac1 + - const: ptp_timer + - const: ptp_rx_mac2 + - const: ptp_tx_mac2 + - const: mac_irq_mac2 + + mdio-1: + $ref: /schemas/net/mdio.yaml# + description: + MDIO bus controller for MAC1. Registers reside inside the mac1 + reg-names window. + unevaluatedProperties: false + + mdio-2: + $ref: /schemas/net/mdio.yaml# + description: + MDIO bus controller for MAC2. Registers reside inside the mac2 + reg-names window. + unevaluatedProperties: false + + patternProperties: + "^(ethernet-)?ports$": + type: object + additionalProperties: false + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + unevaluatedProperties: true + description: + CPU port. Wired internally to the endpoint MAC sibling. + + properties: + reg: + const: 0 + + phy-mode: + const: internal + + required: + - ethernet + + patternProperties: + "^port@[1-2]$": + type: object + unevaluatedProperties: true + description: + External Ethernet port. port@1 is wired to MAC1 and reached + through the mdio-1 bus, port@2 is wired to MAC2 and reached + through the mdio-2 bus. + + properties: + reg: + enum: [1, 2] + + phy-mode: + enum: + - gmii + - rgmii + - rgmii-id + + required: + - reg + - phy-mode + - phy-handle + + required: + - port@0 + - port@1 + - port@2 + + required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + + oneOf: + - required: [ports] + - required: [ethernet-ports] + + unevaluatedProperties: false + +additionalProperties: false + +required: + - compatible + - clocks + - clock-names + - xlnx,num-priorities + - ranges + - '#address-cells' + - '#size-cells' + +examples: + - | + tsn@80040000 { + compatible =3D "xlnx,tsn-endpoint-ethernet-mac-3.0"; + clocks =3D <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_1>, <&misc_clk= _1>, + <&misc_clk_3>, <&misc_clk_0>; + clock-names =3D "gtx", "gtx90", "host_rxfifo", "host_txfifo", + "ref", "s_axi"; + xlnx,num-priorities =3D <8>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x80040000 0x40000>; + + ep_mac: ethernet@16000 { + compatible =3D "xlnx,tsn-ep-mac"; + reg =3D <0x16000 0xa000>; + dmas =3D <&axi_mcdma_0 0>, <&axi_mcdma_0 1>, <&axi_mcdma_0 2>, + <&axi_mcdma_0 3>, <&axi_mcdma_0 4>, <&axi_mcdma_0 5>, + <&axi_mcdma_0 6>, <&axi_mcdma_0 7>, <&axi_mcdma_0 16>, + <&axi_mcdma_0 17>, <&axi_mcdma_0 18>, <&axi_mcdma_0 19>, + <&axi_mcdma_0 20>, <&axi_mcdma_0 21>, <&axi_mcdma_0 22>, + <&axi_mcdma_0 23>; + dma-names =3D "tx_chan0", "tx_chan1", "tx_chan2", "tx_chan3", + "tx_chan4", "tx_chan5", "tx_chan6", "tx_chan7", + "rx_chan0", "rx_chan1", "rx_chan2", "rx_chan3", + "rx_chan4", "rx_chan5", "rx_chan6", "rx_chan7"; + tx-queues-config { + queue0 { xlnx,dma-channel-num =3D <0x7>; }; + queue1 { xlnx,dma-channel-num =3D <0x6>; }; + queue2 { xlnx,dma-channel-num =3D <0x5>; }; + queue3 { xlnx,dma-channel-num =3D <0x4>; }; + queue4 { xlnx,dma-channel-num =3D <0x3>; }; + queue5 { xlnx,dma-channel-num =3D <0x2>; }; + queue6 { xlnx,dma-channel-num =3D <0x1>; }; + queue7 { xlnx,dma-channel-num =3D <0x0>; }; + }; + }; + + switch@38000 { + compatible =3D "xlnx,tsn-switch"; + reg =3D <0x38000 0x8000>, + <0x00000 0x14000>, + <0x20000 0x14000>; + reg-names =3D "switch", "mac1", "mac2"; + + interrupt-parent =3D <&intc>; + interrupts =3D <0 2>, <2 2>, <4 2>, <6 2>, + <1 2>, <3 2>, <5 2>; + interrupt-names =3D "ptp_rx_mac1", "ptp_tx_mac1", + "mac_irq_mac1", "ptp_timer", + "ptp_rx_mac2", "ptp_tx_mac2", + "mac_irq_mac2"; + + mdio-1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; + + mdio-2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + phy1: ethernet-phy@1 { + reg =3D <1>; + }; + }; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + ethernet =3D <&ep_mac>; + phy-mode =3D "internal"; + + fixed-link { + speed =3D <1000>; + full-duplex; + }; + }; + + port@1 { + reg =3D <1>; + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + }; + + port@2 { + reg =3D <2>; + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index b23fb6f2f4ef..8f93f165a744 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -29911,6 +29911,13 @@ M: Harsh Jain S: Maintained F: drivers/char/hw_random/xilinx-trng.c =20 +XILINX TSN ENDPOINT ETHERNET MAC DRIVER +M: Nagadheeraj Rottela +M: Srinivas Neeli +L: netdev@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.ya= ml + XILINX UARTLITE SERIAL DRIVER M: Peter Korsgaard L: linux-serial@vger.kernel.org --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012030.outbound.protection.outlook.com [52.101.48.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC3F3523783; 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Each sub-node needs its own driver, and the shared clocks must be running before any of them probe. Add a thin wrapper platform driver for the IP node. Enable the IP-wide clocks from the device tree and bind each sub-node to its own driver. Co-developed-by: Nagadheeraj Rottela Signed-off-by: Nagadheeraj Rottela Signed-off-by: Srinivas Neeli --- Changes in v2: - Depend on OF_ADDRESS instead of OF && HAS_IOMEM. - Point the Kconfig help text at the companion DSA driver, not a symbol that does not exist yet at this patch. - Drop the mod_devicetable.h include, platform_device.h already pulls it in. --- MAINTAINERS | 1 + drivers/net/ethernet/xilinx/Kconfig | 1 + drivers/net/ethernet/xilinx/Makefile | 1 + drivers/net/ethernet/xilinx/tsn/Kconfig | 15 ++++ drivers/net/ethernet/xilinx/tsn/Makefile | 2 + drivers/net/ethernet/xilinx/tsn/xilinx_tsn_main.c | 104 ++++++++++++++++++= ++++ 6 files changed, 124 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8f93f165a744..ff94e314eeb1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -29917,6 +29917,7 @@ M: Srinivas Neeli L: netdev@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.ya= ml +F: drivers/net/ethernet/xilinx/tsn/ =20 XILINX UARTLITE SERIAL DRIVER M: Peter Korsgaard diff --git a/drivers/net/ethernet/xilinx/Kconfig b/drivers/net/ethernet/xil= inx/Kconfig index 7502214cc7d5..c6d704c8d3d4 100644 --- a/drivers/net/ethernet/xilinx/Kconfig +++ b/drivers/net/ethernet/xilinx/Kconfig @@ -41,4 +41,5 @@ config XILINX_LL_TEMAC This driver supports the Xilinx 10/100/1000 LocalLink TEMAC core used in Xilinx Spartan and Virtex FPGAs =20 +source "drivers/net/ethernet/xilinx/tsn/Kconfig" endif # NET_VENDOR_XILINX diff --git a/drivers/net/ethernet/xilinx/Makefile b/drivers/net/ethernet/xi= linx/Makefile index 7d7dc1771423..66dab012650b 100644 --- a/drivers/net/ethernet/xilinx/Makefile +++ b/drivers/net/ethernet/xilinx/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_XILINX_LL_TEMAC) +=3D ll_temac.o obj-$(CONFIG_XILINX_EMACLITE) +=3D xilinx_emaclite.o xilinx_emac-objs :=3D xilinx_axienet_main.o xilinx_axienet_mdio.o obj-$(CONFIG_XILINX_AXI_EMAC) +=3D xilinx_emac.o +obj-$(CONFIG_XILINX_TSN) +=3D tsn/ diff --git a/drivers/net/ethernet/xilinx/tsn/Kconfig b/drivers/net/ethernet= /xilinx/tsn/Kconfig new file mode 100644 index 000000000000..b8939d8a92ef --- /dev/null +++ b/drivers/net/ethernet/xilinx/tsn/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Xilinx TSN device configuration +# + +config XILINX_TSN + tristate "Xilinx TSN Ethernet driver" + depends on OF_ADDRESS + help + This driver supports the AMD/Xilinx Time-Sensitive Networking + (TSN) Endpoint Ethernet MAC IP. It provides the wrapper device + and the endpoint MAC that connects the IP to the host CPU. The + three-port switch is supported by the companion DSA driver. + + If unsure, say N. diff --git a/drivers/net/ethernet/xilinx/tsn/Makefile b/drivers/net/etherne= t/xilinx/tsn/Makefile new file mode 100644 index 000000000000..6f99226f3dc8 --- /dev/null +++ b/drivers/net/ethernet/xilinx/tsn/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_XILINX_TSN) +=3D xilinx_tsn.o +xilinx_tsn-y :=3D xilinx_tsn_main.o diff --git a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_main.c b/drivers/ne= t/ethernet/xilinx/tsn/xilinx_tsn_main.c new file mode 100644 index 000000000000..afe7609c67fb --- /dev/null +++ b/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_main.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Time Sensitive Networking (TSN) Ethernet MAC wrapper driver. + * + * Copyright (C) 2026 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define TSN_NUM_CLOCKS 6 + +/** + * struct xlnx_tsn_ip - wrapper-private IP state + * @clks: bulk-managed IP clocks + */ +struct xlnx_tsn_ip { + struct clk_bulk_data clks[TSN_NUM_CLOCKS]; +}; + +static const char * const tsn_clk_names[TSN_NUM_CLOCKS] =3D { + "gtx", + "gtx90", + "host_rxfifo", + "host_txfifo", + "ref", + "s_axi", +}; + +static void tsn_clk_bulk_disable(void *data) +{ + struct xlnx_tsn_ip *w =3D data; + + clk_bulk_disable_unprepare(TSN_NUM_CLOCKS, w->clks); +} + +static int tsn_ip_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct xlnx_tsn_ip *w; + int ret; + + w =3D devm_kzalloc(dev, sizeof(*w), GFP_KERNEL); + if (!w) + return -ENOMEM; + + for (int i =3D 0; i < TSN_NUM_CLOCKS; i++) + w->clks[i].id =3D tsn_clk_names[i]; + + ret =3D devm_clk_bulk_get(dev, TSN_NUM_CLOCKS, w->clks); + if (ret) + return dev_err_probe(dev, ret, "failed to get clocks\n"); + + ret =3D clk_bulk_prepare_enable(TSN_NUM_CLOCKS, w->clks); + if (ret) + return dev_err_probe(dev, ret, "failed to enable clocks\n"); + + ret =3D devm_add_action_or_reset(dev, tsn_clk_bulk_disable, w); + if (ret) + return ret; + + return devm_of_platform_populate(dev); +} + +static const struct of_device_id tsn_of_match[] =3D { + { .compatible =3D "xlnx,tsn-endpoint-ethernet-mac-3.0" }, + { } +}; +MODULE_DEVICE_TABLE(of, tsn_of_match); + +static struct platform_driver tsn_driver =3D { + .probe =3D tsn_ip_probe, + .driver =3D { + .name =3D "xilinx-tsn", + .of_match_table =3D tsn_of_match, + }, +}; + +static struct platform_driver * const tsn_drivers[] =3D { + &tsn_driver, +}; + +static int __init xlnx_tsn_init(void) +{ + return platform_register_drivers(tsn_drivers, ARRAY_SIZE(tsn_drivers)); +} +module_init(xlnx_tsn_init); + +static void __exit xlnx_tsn_exit(void) +{ + platform_unregister_drivers(tsn_drivers, ARRAY_SIZE(tsn_drivers)); +} +module_exit(xlnx_tsn_exit); + +MODULE_AUTHOR("Srinivas Neeli "); +MODULE_DESCRIPTION("AMD/Xilinx TSN Endpoint Ethernet MAC wrapper driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012054.outbound.protection.outlook.com [40.93.195.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 311B95A5159; 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The DSA switch needs this netdev to exist as its conduit. Add a platform driver (compatible "xlnx,tsn-ep-mac") for the endpoint. Register the netdev named "ep", set its MAC address, and provide minimal netdev and ethtool ops. ndo_open starts the queues and ndo_start_xmit drops frames. Co-developed-by: Nagadheeraj Rottela Signed-off-by: Nagadheeraj Rottela Signed-off-by: Srinivas Neeli --- Changes in v2: - Name the netdev ep%d with NET_NAME_ENUM instead of a fixed "ep", so a sec= ond IP instance does not clash on register_netdev(). The %d enumeration is wh= at NET_NAME_ENUM describes, and it matches the eth%d naming in net/dsa/user.= c. - Drop the mapped but unused register window (ep->regs and its ioremap). It was intended for QBV support, which is not part of this series, so the endpoint driver does not use it. The mapping will be re-added when QBV support lands. - Use dev_kfree_skb_any() on the drop path, not dev_kfree_skb(). - Drop the mod_devicetable.h include, platform_device.h already pulls it in. --- drivers/net/ethernet/xilinx/tsn/Makefile | 2 +- drivers/net/ethernet/xilinx/tsn/xilinx_tsn.h | 15 +++ drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c | 143 ++++++++++++++++++= ++++ drivers/net/ethernet/xilinx/tsn/xilinx_tsn_main.c | 3 + 4 files changed, 162 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/xilinx/tsn/Makefile b/drivers/net/etherne= t/xilinx/tsn/Makefile index 6f99226f3dc8..5886828b386f 100644 --- a/drivers/net/ethernet/xilinx/tsn/Makefile +++ b/drivers/net/ethernet/xilinx/tsn/Makefile @@ -1,2 +1,2 @@ obj-$(CONFIG_XILINX_TSN) +=3D xilinx_tsn.o -xilinx_tsn-y :=3D xilinx_tsn_main.o +xilinx_tsn-y :=3D xilinx_tsn_main.o xilinx_tsn_ep.o diff --git a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn.h b/drivers/net/eth= ernet/xilinx/tsn/xilinx_tsn.h new file mode 100644 index 000000000000..b0757e22d1fd --- /dev/null +++ b/drivers/net/ethernet/xilinx/tsn/xilinx_tsn.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * AMD/Xilinx TSN Endpoint Ethernet MAC driver, shared definitions. + * + * Copyright (C) 2026 Advanced Micro Devices, Inc. + */ + +#ifndef _XILINX_TSN_H +#define _XILINX_TSN_H + +#include + +extern struct platform_driver xlnx_tsn_ep_driver; + +#endif /* _XILINX_TSN_H */ diff --git a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c b/drivers/net/= ethernet/xilinx/tsn/xilinx_tsn_ep.c new file mode 100644 index 000000000000..089f17a126f5 --- /dev/null +++ b/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD/Xilinx TSN Endpoint MAC driver. + * + * Copyright (C) 2026 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xilinx_tsn.h" + +#define DRIVER_NAME "xilinx_tsn_ep" + +/** + * struct xlnx_tsn_ep - EP MAC private data, embedded in net_device priv a= rea + * @ndev: the conduit netdev ("ep0" for the first IP instance) + * @dev: backing device + */ +struct xlnx_tsn_ep { + struct net_device *ndev; + struct device *dev; +}; + +static netdev_tx_t ep_start_xmit(struct sk_buff *skb, struct net_device *n= dev) +{ + dev_kfree_skb_any(skb); + DEV_STATS_INC(ndev, tx_dropped); + return NETDEV_TX_OK; +} + +static int ep_open(struct net_device *ndev) +{ + netif_tx_start_all_queues(ndev); + + return 0; +} + +static int ep_stop(struct net_device *ndev) +{ + netif_tx_disable(ndev); + + return 0; +} + +static void ep_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo= *ed) +{ + strscpy(ed->driver, DRIVER_NAME, sizeof(ed->driver)); +} + +static const struct net_device_ops ep_netdev_ops =3D { + .ndo_open =3D ep_open, + .ndo_stop =3D ep_stop, + .ndo_start_xmit =3D ep_start_xmit, + .ndo_validate_addr =3D eth_validate_addr, + .ndo_set_mac_address =3D eth_mac_addr, +}; + +static const struct ethtool_ops ep_ethtool_ops =3D { + .get_drvinfo =3D ep_get_drvinfo, +}; + +static int xlnx_tsn_ep_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct net_device *ndev; + struct xlnx_tsn_ep *ep; + u8 mac_addr[ETH_ALEN]; + int ret; + + ndev =3D alloc_netdev(sizeof(*ep), "ep%d", NET_NAME_ENUM, ether_setup); + if (!ndev) + return -ENOMEM; + + SET_NETDEV_DEV(ndev, dev); + ndev->netdev_ops =3D &ep_netdev_ops; + ndev->ethtool_ops =3D &ep_ethtool_ops; + ndev->features =3D NETIF_F_SG; + + ep =3D netdev_priv(ndev); + ep->ndev =3D ndev; + ep->dev =3D dev; + + ret =3D of_get_mac_address(dev->of_node, mac_addr); + if (ret =3D=3D -EPROBE_DEFER) { + goto err_free_ndev; + } else if (!ret && is_valid_ether_addr(mac_addr)) { + eth_hw_addr_set(ndev, mac_addr); + } else { + eth_hw_addr_random(ndev); + dev_info(dev, "no valid MAC in DT, using random address %pM\n", + ndev->dev_addr); + } + + platform_set_drvdata(pdev, ep); + + ret =3D register_netdev(ndev); + if (ret) { + dev_err_probe(dev, ret, "failed to register net device\n"); + goto err_free_ndev; + } + + return 0; + +err_free_ndev: + free_netdev(ndev); + return ret; +} + +static void xlnx_tsn_ep_remove(struct platform_device *pdev) +{ + struct xlnx_tsn_ep *ep =3D platform_get_drvdata(pdev); + + if (!ep) + return; + + unregister_netdev(ep->ndev); + free_netdev(ep->ndev); +} + +static const struct of_device_id xlnx_tsn_ep_of_match[] =3D { + { .compatible =3D "xlnx,tsn-ep-mac" }, + { } +}; +MODULE_DEVICE_TABLE(of, xlnx_tsn_ep_of_match); + +struct platform_driver xlnx_tsn_ep_driver =3D { + .probe =3D xlnx_tsn_ep_probe, + .remove =3D xlnx_tsn_ep_remove, + .driver =3D { + .name =3D DRIVER_NAME, + .of_match_table =3D xlnx_tsn_ep_of_match, + }, +}; diff --git a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_main.c b/drivers/ne= t/ethernet/xilinx/tsn/xilinx_tsn_main.c index afe7609c67fb..d33a00dd6d15 100644 --- a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_main.c +++ b/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_main.c @@ -15,6 +15,8 @@ #include #include =20 +#include "xilinx_tsn.h" + #define TSN_NUM_CLOCKS 6 =20 /** @@ -85,6 +87,7 @@ static struct platform_driver tsn_driver =3D { =20 static struct platform_driver * const tsn_drivers[] =3D { &tsn_driver, + &xlnx_tsn_ep_driver, }; =20 static int __init xlnx_tsn_init(void) --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013039.outbound.protection.outlook.com [40.107.201.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4506F5A984F; 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Tue, 8 Sep 2026 14:20:30 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Tue, 8 Sep 2026 14:20:24 -0500 From: Srinivas Neeli Date: Wed, 9 Sep 2026 00:49:52 +0530 Subject: [PATCH net-next v2 4/8] net: xilinx: tsn: parse endpoint DMA channel configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-patches_v2_external-v2-4-3a40babaff4c@amd.com> References: <20260909-patches_v2_external-v2-0-3a40babaff4c@amd.com> In-Reply-To: <20260909-patches_v2_external-v2-0-3a40babaff4c@amd.com> To: Nagadheeraj Rottela , Andrew Lunn , "David S. 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The transmit path needs to know which physical DMA channel backs each logical TX queue. Count the TX and RX channels in "dma-names" and allocate the conduit netdev with that many hardware queues. Parse the "tx-queues-config" child node to map each logical TX queue to its physical DMA channel. Co-developed-by: Nagadheeraj Rottela Signed-off-by: Nagadheeraj Rottela Signed-off-by: Srinivas Neeli --- Changes in v2: - Check xlnx,dma-channel-num against the channels that dma-names actually lists, using a presence bitmask. Reject duplicates and out-of-range chann= els, and index the channel arrays by logical queue. - Require one queue node per tx_chan and num-priorities equal to the TX cha= nnel count. This also gives xlnx,num-priorities a consumer. - Cap TX and RX at 8 to match the binding. - Error out on an unknown dma-names entry instead of skipping it. - Drop the unreachable TX and RX count guards. The in-loop index and duplic= ate checks already bound the count, so the channel arrays cannot be over-inde= xed. --- drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c | 197 ++++++++++++++++++++= +++- 1 file changed, 196 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c b/drivers/net/= ethernet/xilinx/tsn/xilinx_tsn_ep.c index 089f17a126f5..24025b1f6e66 100644 --- a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c +++ b/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c @@ -5,9 +5,11 @@ * Copyright (C) 2026 Advanced Micro Devices, Inc. */ =20 +#include #include #include #include +#include #include #include #include @@ -21,14 +23,31 @@ =20 #define DRIVER_NAME "xilinx_tsn_ep" =20 +#define TSN_DMA_CH_INVALID 0xFFU +#define TSN_MAX_TX_QUEUE 8 +#define TSN_MAX_RX_QUEUE 8 + +#define TSN_MAX_VLAN_FRAME_SIZE (ETH_DATA_LEN + VLAN_ETH_HLEN + \ + ETH_FCS_LEN) + /** * struct xlnx_tsn_ep - EP MAC private data, embedded in net_device priv a= rea * @ndev: the conduit netdev ("ep0" for the first IP instance) * @dev: backing device + * @num_tx_queues: number of TX DMA channels (one per priority) + * @num_rx_queues: number of RX DMA channels + * @tx_dma_chan_map: logical TX queue index -> physical DMA channel number + * @rx_chan_num: RX ring index -> physical DMA channel number + * @max_frm_size: maximum frame size accepted on RX */ struct xlnx_tsn_ep { struct net_device *ndev; struct device *dev; + u32 num_tx_queues; + u32 num_rx_queues; + u32 tx_dma_chan_map[TSN_MAX_TX_QUEUE]; + u32 rx_chan_num[TSN_MAX_RX_QUEUE]; + u32 max_frm_size; }; =20 static netdev_tx_t ep_start_xmit(struct sk_buff *skb, struct net_device *n= dev) @@ -69,15 +88,173 @@ static const struct ethtool_ops ep_ethtool_ops =3D { .get_drvinfo =3D ep_get_drvinfo, }; =20 +/* + * Parse the "tx-queues-config" child of the EP node. The logical queue + * index is taken from the "queue" node name, so the mapping does not + * depend on the order the child nodes appear in the device tree. + */ +static int ep_parse_tx_queue_config(struct xlnx_tsn_ep *ep, + struct device_node *txcfg_np, u16 tx_present) +{ + DECLARE_BITMAP(queue_seen, TSN_MAX_TX_QUEUE) =3D {}; + DECLARE_BITMAP(chan_seen, TSN_MAX_TX_QUEUE) =3D {}; + unsigned int count =3D 0; + int ret; + + for_each_child_of_node_scoped(txcfg_np, qnode) { + u32 chan, queue; + + if (!str_has_prefix(qnode->name, "queue") || + kstrtou32(qnode->name + strlen("queue"), 10, &queue) || + queue >=3D ep->num_tx_queues) + return dev_err_probe(ep->dev, -EINVAL, + "tx-config: invalid queue node %pOFn (have %u queues)\n", + qnode, ep->num_tx_queues); + + if (test_and_set_bit(queue, queue_seen)) + return dev_err_probe(ep->dev, -EINVAL, + "tx-config: queue %u described twice\n", + queue); + + ret =3D of_property_read_u32(qnode, "xlnx,dma-channel-num", &chan); + if (ret) + return dev_err_probe(ep->dev, ret, + "tx-config: queue %u missing xlnx,dma-channel-num\n", + queue); + + if (chan >=3D TSN_MAX_TX_QUEUE || !(tx_present & BIT(chan))) + return dev_err_probe(ep->dev, -EINVAL, + "tx-config: queue %u maps to channel %u not present in dma-names= \n", + queue, chan); + + if (test_and_set_bit(chan, chan_seen)) + return dev_err_probe(ep->dev, -EINVAL, + "tx-config: channel %u already assigned to another queue\n", + chan); + + ep->tx_dma_chan_map[queue] =3D chan; + count++; + } + + if (count !=3D ep->num_tx_queues) + return dev_err_probe(ep->dev, -EINVAL, + "tx-config: described %u queues but expected %u\n", + count, ep->num_tx_queues); + + return 0; +} + +static int ep_count_dma_queues(struct device *dev, u32 *out_tx, u32 *out_r= x, + u16 *tx_present, u32 *rx_chan_num) +{ + u32 tx =3D 0, rx =3D 0; + u16 rx_present =3D 0; + int n, i, ret; + + n =3D of_property_count_strings(dev->of_node, "dma-names"); + if (n < 0) + return dev_err_probe(dev, n, "failed to read dma-names\n"); + + for (i =3D 0; i < n; i++) { + const char *name; + size_t plen; + u32 idx; + + ret =3D of_property_read_string_index(dev->of_node, "dma-names", + i, &name); + if (ret) + return dev_err_probe(dev, ret, + "failed to read dma-names[%d]\n", i); + + plen =3D str_has_prefix(name, "tx_chan"); + if (plen) { + if (kstrtou32(name + plen, 10, &idx) || + idx >=3D TSN_MAX_TX_QUEUE) + return dev_err_probe(dev, -EINVAL, + "invalid TX channel name %s\n", + name); + + if (*tx_present & BIT(idx)) + return dev_err_probe(dev, -EINVAL, + "duplicate TX channel %s\n", + name); + + *tx_present |=3D BIT(idx); + tx++; + continue; + } + + plen =3D str_has_prefix(name, "rx_chan"); + if (plen) { + if (kstrtou32(name + plen, 10, &idx) || + idx >=3D TSN_MAX_RX_QUEUE) + return dev_err_probe(dev, -EINVAL, + "invalid RX channel name %s\n", + name); + + if (rx_present & BIT(idx)) + return dev_err_probe(dev, -EINVAL, + "duplicate RX channel %s\n", + name); + + rx_present |=3D BIT(idx); + rx_chan_num[rx] =3D idx; + rx++; + continue; + } + + return dev_err_probe(dev, -EINVAL, + "unrecognised dma-names entry %s\n", name); + } + + if (!tx) + return dev_err_probe(dev, -EINVAL, + "no TX channels in dma-names\n"); + + if (!rx) + return dev_err_probe(dev, -EINVAL, + "no RX channels in dma-names\n"); + + *out_tx =3D tx; + *out_rx =3D rx; + + return 0; +} + static int xlnx_tsn_ep_probe(struct platform_device *pdev) { + u32 rx_chan_num[TSN_MAX_RX_QUEUE]; struct device *dev =3D &pdev->dev; + struct device_node *txcfg_np; + u32 num_tx, num_rx, num_prio; + struct device_node *ip_np; struct net_device *ndev; struct xlnx_tsn_ep *ep; u8 mac_addr[ETH_ALEN]; + u16 tx_present =3D 0; int ret; + int i; + + ret =3D ep_count_dma_queues(dev, &num_tx, &num_rx, &tx_present, rx_chan_n= um); + if (ret) + return ret; + + ip_np =3D of_get_parent(dev->of_node); + if (!ip_np) + return dev_err_probe(dev, -EINVAL, "missing parent IP node\n"); + + ret =3D of_property_read_u32(ip_np, "xlnx,num-priorities", &num_prio); + of_node_put(ip_np); + if (ret) + return dev_err_probe(dev, ret, "missing xlnx,num-priorities\n"); + + if (num_tx !=3D num_prio) + return dev_err_probe(dev, -EINVAL, + "TX channel count %u must equal num-priorities %u\n", + num_tx, num_prio); =20 - ndev =3D alloc_netdev(sizeof(*ep), "ep%d", NET_NAME_ENUM, ether_setup); + ndev =3D alloc_netdev_mqs(sizeof(*ep), "ep%d", NET_NAME_ENUM, + ether_setup, num_tx, num_rx); if (!ndev) return -ENOMEM; =20 @@ -89,6 +266,24 @@ static int xlnx_tsn_ep_probe(struct platform_device *pd= ev) ep =3D netdev_priv(ndev); ep->ndev =3D ndev; ep->dev =3D dev; + ep->num_tx_queues =3D num_tx; + ep->num_rx_queues =3D num_rx; + ep->max_frm_size =3D TSN_MAX_VLAN_FRAME_SIZE; + memcpy(ep->rx_chan_num, rx_chan_num, num_rx * sizeof(*rx_chan_num)); + + for (i =3D 0; i < TSN_MAX_TX_QUEUE; i++) + ep->tx_dma_chan_map[i] =3D TSN_DMA_CH_INVALID; + + txcfg_np =3D of_get_child_by_name(dev->of_node, "tx-queues-config"); + if (!txcfg_np) { + ret =3D dev_err_probe(dev, -EINVAL, + "missing tx-queues-config node\n"); + goto err_free_ndev; + } + ret =3D ep_parse_tx_queue_config(ep, txcfg_np, tx_present); + of_node_put(txcfg_np); + if (ret) + goto err_free_ndev; =20 ret =3D of_get_mac_address(dev->of_node, mac_addr); if (ret =3D=3D -EPROBE_DEFER) { --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010019.outbound.protection.outlook.com [52.101.193.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76B925A5145; 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Tue, 8 Sep 2026 14:20:35 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Tue, 8 Sep 2026 14:20:30 -0500 From: Srinivas Neeli Date: Wed, 9 Sep 2026 00:49:53 +0530 Subject: [PATCH net-next v2 5/8] net: xilinx: tsn: bring up the endpoint MCDMA channels Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-patches_v2_external-v2-5-3a40babaff4c@amd.com> References: <20260909-patches_v2_external-v2-0-3a40babaff4c@amd.com> In-Reply-To: <20260909-patches_v2_external-v2-0-3a40babaff4c@amd.com> To: Nagadheeraj Rottela , Andrew Lunn , "David S. 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Request every TX and RX channel named in the device tree when the interface opens, and give each one a ring of preallocated SKB descriptor slots. Reset the controller once at probe time through the first mapped TX channel, which also gates probe on the MCDMA provider being bound so -EPROBE_DEFER stays in the probe path and never reaches ndo_open. Release the channels on stop, where dmaengine_terminate_sync() returns them to a clean state. Add the XILINX_DMA dependency for the dmaengine and Xilinx DMA APIs. Co-developed-by: Nagadheeraj Rottela Signed-off-by: Nagadheeraj Rottela Signed-off-by: Srinivas Neeli --- Changes in v2: - Request a channel at probe time so -EPROBE_DEFER stays in the probe path = and ndo_open never hands a deferral back to userspace. - Request the channels by their real dma-names index, not a dense 0..N-1 sequence. - Reword the commit message so the reset reads as probe-time through the fi= rst mapped TX channel, not on open. --- drivers/net/ethernet/xilinx/tsn/Kconfig | 1 + drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c | 281 ++++++++++++++++++++= ++++ 2 files changed, 282 insertions(+) diff --git a/drivers/net/ethernet/xilinx/tsn/Kconfig b/drivers/net/ethernet= /xilinx/tsn/Kconfig index b8939d8a92ef..292f17694404 100644 --- a/drivers/net/ethernet/xilinx/tsn/Kconfig +++ b/drivers/net/ethernet/xilinx/tsn/Kconfig @@ -6,6 +6,7 @@ config XILINX_TSN tristate "Xilinx TSN Ethernet driver" depends on OF_ADDRESS + depends on XILINX_DMA help This driver supports the AMD/Xilinx Time-Sensitive Networking (TSN) Endpoint Ethernet MAC IP. It provides the wrapper device diff --git a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c b/drivers/net/= ethernet/xilinx/tsn/xilinx_tsn_ep.c index 24025b1f6e66..23a15df71baa 100644 --- a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c +++ b/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c @@ -6,16 +6,24 @@ */ =20 #include +#include +#include +#include +#include #include #include #include #include +#include #include #include #include #include #include #include +#include +#include +#include #include #include =20 @@ -30,6 +38,47 @@ #define TSN_MAX_VLAN_FRAME_SIZE (ETH_DATA_LEN + VLAN_ETH_HLEN + \ ETH_FCS_LEN) =20 +#define TX_BD_NUM_DEFAULT 64 +#define RX_BD_NUM_DEFAULT 128 + +/** + * struct skbuf_dma_descriptor - skb container for each in-flight DMA desc= riptor + * @sgl: scatter-gather list backing the DMA mapping + * @desc: dmaengine descriptor handle + * @dma_address: physical address of the first sgl entry (RX path) + * @skb: SKB owning the buffer + * @sg_len: number of valid entries in @sgl (TX path) + */ +struct skbuf_dma_descriptor { + struct scatterlist sgl[MAX_SKB_FRAGS + 1]; + struct dma_async_tx_descriptor *desc; + dma_addr_t dma_address; + struct sk_buff *skb; + int sg_len; +}; + +/** + * struct xlnx_tsn_ep_dma_chan - one DMA channel and its SKB ring + * @skb_ring: per-slot SKB descriptors + * @ep: pointer back to the owning EP instance + * @chan: dmaengine channel handle + * @dma_dev: device used for DMA mapping (the DMA engine, not the EP) + * @ring_head: producer index + * @ring_tail: consumer index + * @ring_size: number of slots in @skb_ring + * @is_tx: true for TX channels, false for RX + */ +struct xlnx_tsn_ep_dma_chan { + struct skbuf_dma_descriptor **skb_ring; + struct xlnx_tsn_ep *ep; + struct dma_chan *chan; + struct device *dma_dev; + u32 ring_head; + u32 ring_tail; + u32 ring_size; + bool is_tx; +}; + /** * struct xlnx_tsn_ep - EP MAC private data, embedded in net_device priv a= rea * @ndev: the conduit netdev ("ep0" for the first IP instance) @@ -39,6 +88,9 @@ * @tx_dma_chan_map: logical TX queue index -> physical DMA channel number * @rx_chan_num: RX ring index -> physical DMA channel number * @max_frm_size: maximum frame size accepted on RX + * @tx_chans: array of TX channels (size @num_tx_queues) + * @rx_chans: array of RX channels (size @num_rx_queues) + * @closing: set in ndo_stop so the RX completion callback stops re-arming */ struct xlnx_tsn_ep { struct net_device *ndev; @@ -48,8 +100,19 @@ struct xlnx_tsn_ep { u32 tx_dma_chan_map[TSN_MAX_TX_QUEUE]; u32 rx_chan_num[TSN_MAX_RX_QUEUE]; u32 max_frm_size; + + struct xlnx_tsn_ep_dma_chan **tx_chans; + struct xlnx_tsn_ep_dma_chan **rx_chans; + + bool closing; }; =20 +static inline struct skbuf_dma_descriptor * +ep_get_desc(struct xlnx_tsn_ep_dma_chan *xchan, int idx) +{ + return xchan->skb_ring[idx]; +} + static netdev_tx_t ep_start_xmit(struct sk_buff *skb, struct net_device *n= dev) { dev_kfree_skb_any(skb); @@ -57,8 +120,22 @@ static netdev_tx_t ep_start_xmit(struct sk_buff *skb, s= truct net_device *ndev) return NETDEV_TX_OK; } =20 +static int ep_init_dmaengine(struct xlnx_tsn_ep *ep); +static void ep_exit_dmaengine(struct xlnx_tsn_ep *ep); + static int ep_open(struct net_device *ndev) { + struct xlnx_tsn_ep *ep =3D netdev_priv(ndev); + int ret; + + WRITE_ONCE(ep->closing, false); + + ret =3D ep_init_dmaengine(ep); + if (ret) { + netdev_err(ndev, "failed to initialize DMA engine\n"); + return ret; + } + netif_tx_start_all_queues(ndev); =20 return 0; @@ -66,7 +143,11 @@ static int ep_open(struct net_device *ndev) =20 static int ep_stop(struct net_device *ndev) { + struct xlnx_tsn_ep *ep =3D netdev_priv(ndev); + netif_tx_disable(ndev); + WRITE_ONCE(ep->closing, true); + ep_exit_dmaengine(ep); =20 return 0; } @@ -88,6 +169,196 @@ static const struct ethtool_ops ep_ethtool_ops =3D { .get_drvinfo =3D ep_get_drvinfo, }; =20 +static struct xlnx_tsn_ep_dma_chan * +ep_alloc_dma_chan(struct xlnx_tsn_ep *ep, const char *name, bool is_tx, + int ring_size) +{ + struct xlnx_tsn_ep_dma_chan *chan; + struct dma_chan *err_chan; + int i; + + chan =3D kzalloc_obj(*chan); + if (!chan) + return ERR_PTR(-ENOMEM); + + chan->chan =3D dma_request_chan(ep->dev, name); + if (IS_ERR(chan->chan)) { + err_chan =3D chan->chan; + kfree(chan); + return ERR_CAST(err_chan); + } + + chan->skb_ring =3D kcalloc(ring_size, sizeof(*chan->skb_ring), GFP_KERNEL= ); + if (!chan->skb_ring) { + dma_release_channel(chan->chan); + kfree(chan); + return ERR_PTR(-ENOMEM); + } + + for (i =3D 0; i < ring_size; i++) { + chan->skb_ring[i] =3D kzalloc_obj(*chan->skb_ring[i]); + if (!chan->skb_ring[i]) { + while (--i >=3D 0) + kfree(chan->skb_ring[i]); + kfree(chan->skb_ring); + dma_release_channel(chan->chan); + kfree(chan); + return ERR_PTR(-ENOMEM); + } + } + + chan->is_tx =3D is_tx; + chan->ep =3D ep; + chan->ring_size =3D ring_size; + chan->dma_dev =3D dmaengine_get_dma_device(chan->chan); + + return chan; +} + +static void ep_free_dma_chan(struct xlnx_tsn_ep_dma_chan *chan) +{ + int i; + + if (!chan) + return; + + if (chan->chan) + dmaengine_terminate_sync(chan->chan); + + if (chan->is_tx) { + while (chan->ring_tail !=3D chan->ring_head) { + struct skbuf_dma_descriptor *skbuf_dma; + + skbuf_dma =3D chan->skb_ring[chan->ring_tail & + (chan->ring_size - 1)]; + if (skbuf_dma && skbuf_dma->skb) { + dma_unmap_sg(chan->dma_dev, skbuf_dma->sgl, + skbuf_dma->sg_len, DMA_TO_DEVICE); + dev_kfree_skb_any(skbuf_dma->skb); + skbuf_dma->skb =3D NULL; + } + chan->ring_tail++; + } + } + + if (chan->skb_ring) { + for (i =3D 0; i < chan->ring_size; i++) { + struct skbuf_dma_descriptor *skbuf_dma =3D chan->skb_ring[i]; + + if (skbuf_dma && !chan->is_tx && skbuf_dma->skb) { + dma_unmap_single(chan->dma_dev, + skbuf_dma->dma_address, + chan->ep->max_frm_size, + DMA_FROM_DEVICE); + dev_kfree_skb_any(skbuf_dma->skb); + } + kfree(chan->skb_ring[i]); + } + kfree(chan->skb_ring); + } + if (chan->chan) + dma_release_channel(chan->chan); + + kfree(chan); +} + +static void ep_exit_dmaengine(struct xlnx_tsn_ep *ep) +{ + int i; + + if (ep->tx_chans) { + for (i =3D 0; i < ep->num_tx_queues; i++) + ep_free_dma_chan(ep->tx_chans[i]); + kfree(ep->tx_chans); + ep->tx_chans =3D NULL; + } + if (ep->rx_chans) { + for (i =3D 0; i < ep->num_rx_queues; i++) + ep_free_dma_chan(ep->rx_chans[i]); + kfree(ep->rx_chans); + ep->rx_chans =3D NULL; + } +} + +static int ep_init_dmaengine(struct xlnx_tsn_ep *ep) +{ + int tx_allocated =3D 0, rx_allocated =3D 0; + char name[16]; + int i, ret; + + ep->tx_chans =3D kcalloc(ep->num_tx_queues, sizeof(*ep->tx_chans), + GFP_KERNEL); + if (!ep->tx_chans) + return -ENOMEM; + + ep->rx_chans =3D kcalloc(ep->num_rx_queues, sizeof(*ep->rx_chans), + GFP_KERNEL); + if (!ep->rx_chans) { + ret =3D -ENOMEM; + goto err_free_tx; + } + + for (i =3D 0; i < ep->num_tx_queues; i++) { + snprintf(name, sizeof(name), "tx_chan%u", ep->tx_dma_chan_map[i]); + ep->tx_chans[i] =3D ep_alloc_dma_chan(ep, name, true, + TX_BD_NUM_DEFAULT); + if (IS_ERR(ep->tx_chans[i])) { + ret =3D PTR_ERR(ep->tx_chans[i]); + ep->tx_chans[i] =3D NULL; + goto err_free_chans; + } + tx_allocated++; + } + + for (i =3D 0; i < ep->num_rx_queues; i++) { + snprintf(name, sizeof(name), "rx_chan%u", ep->rx_chan_num[i]); + ep->rx_chans[i] =3D ep_alloc_dma_chan(ep, name, false, + RX_BD_NUM_DEFAULT); + if (IS_ERR(ep->rx_chans[i])) { + ret =3D PTR_ERR(ep->rx_chans[i]); + ep->rx_chans[i] =3D NULL; + goto err_free_chans; + } + rx_allocated++; + } + + return 0; + +err_free_chans: + while (--rx_allocated >=3D 0) + ep_free_dma_chan(ep->rx_chans[rx_allocated]); + while (--tx_allocated >=3D 0) + ep_free_dma_chan(ep->tx_chans[tx_allocated]); + kfree(ep->rx_chans); + ep->rx_chans =3D NULL; +err_free_tx: + kfree(ep->tx_chans); + ep->tx_chans =3D NULL; + return ret; +} + +static int ep_reset_dma_controller(struct xlnx_tsn_ep *ep) +{ + struct xilinx_vdma_config cfg =3D { .reset =3D 1 }; + struct dma_chan *reset_chan; + char name[16]; + int ret; + + snprintf(name, sizeof(name), "tx_chan%u", ep->tx_dma_chan_map[0]); + reset_chan =3D dma_request_chan(ep->dev, name); + if (IS_ERR(reset_chan)) + return dev_err_probe(ep->dev, PTR_ERR(reset_chan), + "failed to request %s for reset\n", name); + + ret =3D xilinx_vdma_channel_set_config(reset_chan, &cfg); + dma_release_channel(reset_chan); + if (ret < 0) + return dev_err_probe(ep->dev, ret, + "failed to reset DMA controller\n"); + + return 0; +} + /* * Parse the "tx-queues-config" child of the EP node. The logical queue * index is taken from the "queue" node name, so the mapping does not @@ -285,6 +556,16 @@ static int xlnx_tsn_ep_probe(struct platform_device *p= dev) if (ret) goto err_free_ndev; =20 + /* + * Request one DMA channel at probe time to reset the controller and to + * gate on the MCDMA provider being bound. This keeps -EPROBE_DEFER in + * the probe path, so the netdev is only registered once the provider is + * available and ndo_open never sees a deferral. + */ + ret =3D ep_reset_dma_controller(ep); + if (ret) + goto err_free_ndev; + ret =3D of_get_mac_address(dev->of_node, mac_addr); if (ret =3D=3D -EPROBE_DEFER) { goto err_free_ndev; --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013040.outbound.protection.outlook.com [40.107.201.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFF8D598C09; Tue, 8 Sep 2026 19:20:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.201.40 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788895260; cv=fail; b=UH83unrz2EAOsw7cLvY+lufKLvmzTBA72waph0FBjaFpJq6JCKhEcQ3Td+ElB78rKQwW7czMwU285NHg6Y9zCPrTbFNdT8EGhQTN2p0lPIvb7QVdVXP2BNK2EqIrapyaosJlWsAe3giW/xi+sUa5HNznQQdhd1Spi8m3hCV+3h4= ARC-Message-Signature: i=2; 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Post RX buffers to every RX channel on open and reap them from the completion callback. Each inbound frame carries a TUSER port_id in the descriptor sideband. Accept frames from MAC1 (port_id 1) and MAC2 (port_id 2) and pass them up the stack. Drop any other port_id, since the bridged-only model never produces it. Drop and count frames with bad descriptor status, an invalid length or no metadata pointer. Refill each slot from the completion callback unless the interface is closing, which keeps the ring full without a separate refill worker. Serialise the RX refill against teardown. The completion callback re-arms the ring, so ndo_stop() sets a closing flag under the same per-channel lock the refill takes, and ep_free_dma_chan() takes that lock as a barrier before it terminates the channel. No descriptor is submitted once teardown has begun, so a single dmaengine_terminate_sync() is enough to quiesce the channel. The RX path uses __netif_rx() from the dmaengine completion callback rather than NAPI. dmaengine owns the RX interrupt and ring and delivers one descriptor per callback, so there is no poll context to run NAPI or GRO, and the per-packet counters use the dev->stats atomics. Co-developed-by: Nagadheeraj Rottela Signed-off-by: Nagadheeraj Rottela Signed-off-by: Srinivas Neeli --- Changes in v2: - Serialise the RX refill against teardown under a per-channel rx_lock. The completion callback re-arms the ring, so ndo_stop() sets a closing flag u= nder the same lock and ep_free_dma_chan() takes it as a barrier before termina= ting. - Recover a drained ring with a refill timer instead of leaving RX dead aft= er an allocation failure. - Fail ndo_open if a channel cannot arm any RX descriptor. - Set the closing flag on the ndo_open error path too, before tearing the channels down. - Take the ring size from the channel instead of a compile-time constant. - Note in the commit message why RX is not NAPI based. dmaengine owns the RX interrupt and ring and delivers one descriptor per callback, so there is = no poll context for NAPI or GRO, and the counters use the dev->stats atomics. - Shut the refill timer down with timer_shutdown_sync() at teardown rather = than relying on timer_delete_sync() plus the closing flag. - Return true from ep_rx_refill() when at least one descriptor is armed, fa= lse otherwise, following the usual bool convention. - Init the refill timer and rx_lock only for RX channels. --- drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c | 216 ++++++++++++++++++++= +++- 1 file changed, 215 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c b/drivers/net/= ethernet/xilinx/tsn/xilinx_tsn_ep.c index 23a15df71baa..9ed1170794e0 100644 --- a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c +++ b/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c @@ -5,6 +5,7 @@ * Copyright (C) 2026 Advanced Micro Devices, Inc. */ =20 +#include #include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include #include =20 #include "xilinx_tsn.h" @@ -41,6 +43,19 @@ #define TX_BD_NUM_DEFAULT 64 #define RX_BD_NUM_DEFAULT 128 =20 +#define EP_RX_REFILL_RETRY msecs_to_jiffies(10) + +/* + * The DMA descriptor sideband status word packs TID/TDEST/TUSER together; + * TUSER occupies the low byte, TID/TDEST sit in the upper bits. + */ +#define TSN_TUSER_MASK GENMASK(7, 0) +/* TUSER Input Port ID field (bits [5:4] of the TUSER field) */ +#define TSN_TUSER_PORT_ID_MASK GENMASK(5, 4) +#define TSN_TUSER_PORT_EP 0x0 +#define TSN_TUSER_PORT_MAC1 0x1 +#define TSN_TUSER_PORT_MAC2 0x2 + /** * struct skbuf_dma_descriptor - skb container for each in-flight DMA desc= riptor * @sgl: scatter-gather list backing the DMA mapping @@ -66,6 +81,8 @@ struct skbuf_dma_descriptor { * @ring_head: producer index * @ring_tail: consumer index * @ring_size: number of slots in @skb_ring + * @rx_lock: serialises @ring_head between the RX callback and the refill = timer + * @rx_refill_timer: retries RX refill after an allocation failure * @is_tx: true for TX channels, false for RX */ struct xlnx_tsn_ep_dma_chan { @@ -76,6 +93,8 @@ struct xlnx_tsn_ep_dma_chan { u32 ring_head; u32 ring_tail; u32 ring_size; + spinlock_t rx_lock; /* serialises @ring_head */ + struct timer_list rx_refill_timer; bool is_tx; }; =20 @@ -113,6 +132,174 @@ ep_get_desc(struct xlnx_tsn_ep_dma_chan *xchan, int i= dx) return xchan->skb_ring[idx]; } =20 +static void ep_dma_rx_cb(void *data, const struct dmaengine_result *result= ); + +static int ep_rx_submit_desc(struct xlnx_tsn_ep_dma_chan *xchan) +{ + struct dma_async_tx_descriptor *dma_rx_desc; + struct skbuf_dma_descriptor *skbuf_dma; + struct xlnx_tsn_ep *ep =3D xchan->ep; + struct sk_buff *skb; + dma_addr_t addr; + + skbuf_dma =3D ep_get_desc(xchan, xchan->ring_head & (xchan->ring_size - 1= )); + if (!skbuf_dma) + return -ENOSPC; + + skb =3D dev_alloc_skb(ep->max_frm_size); + if (!skb) + return -ENOMEM; + + sg_init_table(skbuf_dma->sgl, 1); + addr =3D dma_map_single(xchan->dma_dev, skb->data, ep->max_frm_size, + DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(xchan->dma_dev, addr))) { + if (net_ratelimit()) + dev_warn(ep->dev, "DMA mapping error on RX submit\n"); + + goto err_free_skb; + } + sg_dma_address(skbuf_dma->sgl) =3D addr; + sg_dma_len(skbuf_dma->sgl) =3D ep->max_frm_size; + dma_rx_desc =3D dmaengine_prep_slave_sg(xchan->chan, skbuf_dma->sgl, + 1, DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT); + if (!dma_rx_desc) + goto err_unmap_skb; + + skbuf_dma->skb =3D skb; + skbuf_dma->dma_address =3D sg_dma_address(skbuf_dma->sgl); + skbuf_dma->desc =3D dma_rx_desc; + dma_rx_desc->callback_param =3D xchan; + dma_rx_desc->callback_result =3D ep_dma_rx_cb; + xchan->ring_head++; + dmaengine_submit(dma_rx_desc); + + return 0; + +err_unmap_skb: + dma_unmap_single(xchan->dma_dev, addr, ep->max_frm_size, DMA_FROM_DEVICE); +err_free_skb: + dev_kfree_skb(skb); + return -ENOMEM; +} + +static bool ep_rx_refill(struct xlnx_tsn_ep_dma_chan *xchan, bool arm_time= r) +{ + int avail, i; + + guard(spinlock_bh)(&xchan->rx_lock); + + if (READ_ONCE(xchan->ep->closing)) + return false; + + avail =3D CIRC_SPACE(xchan->ring_head, READ_ONCE(xchan->ring_tail), + xchan->ring_size); + for (i =3D 0; i < avail; i++) { + if (ep_rx_submit_desc(xchan)) + break; + } + dma_async_issue_pending(xchan->chan); + + if (xchan->ring_head !=3D READ_ONCE(xchan->ring_tail)) + return true; + + if (arm_timer) + mod_timer(&xchan->rx_refill_timer, jiffies + EP_RX_REFILL_RETRY); + + return false; +} + +static void ep_rx_refill_timer(struct timer_list *t) +{ + struct xlnx_tsn_ep_dma_chan *xchan =3D timer_container_of(xchan, t, + rx_refill_timer); + + ep_rx_refill(xchan, true); +} + +static void ep_dma_rx_cb(void *data, const struct dmaengine_result *result) +{ + struct xlnx_tsn_ep_dma_chan *xchan =3D data; + struct skbuf_dma_descriptor *skbuf_dma; + size_t meta_len, meta_max_len, rx_len; + struct xlnx_tsn_ep *ep =3D xchan->ep; + struct net_device *ndev =3D ep->ndev; + struct sk_buff *skb; + u32 port_id, tuser; + u32 *metadata; + + skbuf_dma =3D ep_get_desc(xchan, xchan->ring_tail & (xchan->ring_size - 1= )); + WRITE_ONCE(xchan->ring_tail, xchan->ring_tail + 1); + skb =3D skbuf_dma->skb; + skbuf_dma->skb =3D NULL; + + dma_unmap_single(xchan->dma_dev, skbuf_dma->dma_address, + ep->max_frm_size, DMA_FROM_DEVICE); + + if (result->result !=3D DMA_TRANS_NOERROR) { + if (net_ratelimit()) + dev_warn(ep->dev, "RX DMA transfer error %d\n", + result->result); + + dev_kfree_skb_any(skb); + DEV_STATS_INC(ndev, rx_dropped); + DEV_STATS_INC(ndev, rx_errors); + goto submit_new; + } + + metadata =3D dmaengine_desc_get_metadata_ptr(skbuf_dma->desc, + &meta_len, + &meta_max_len); + if (IS_ERR_OR_NULL(metadata)) { + if (net_ratelimit()) + dev_warn(ep->dev, "Failed to get RX metadata pointer\n"); + + dev_kfree_skb_any(skb); + DEV_STATS_INC(ndev, rx_dropped); + DEV_STATS_INC(ndev, rx_errors); + goto submit_new; + } + + /* MCDMA metadata: [0] =3D status, [1] =3D sideband (TID/TDEST/TUSER), [2= ..] =3D app */ + tuser =3D metadata[1] & TSN_TUSER_MASK; + rx_len =3D ep->max_frm_size - result->residue; + + if (rx_len > ep->max_frm_size || rx_len < ETH_HLEN) { + if (net_ratelimit()) + dev_warn(ep->dev, "Invalid RX length %zu (max=3D%u, min=3D%u)\n", + rx_len, ep->max_frm_size, ETH_HLEN); + + dev_kfree_skb_any(skb); + DEV_STATS_INC(ndev, rx_dropped); + DEV_STATS_INC(ndev, rx_errors); + goto submit_new; + } + + port_id =3D FIELD_GET(TSN_TUSER_PORT_ID_MASK, tuser); + if (port_id !=3D TSN_TUSER_PORT_MAC1 && port_id !=3D TSN_TUSER_PORT_MAC2)= { + if (net_ratelimit()) + dev_dbg(ep->dev, "RX dropping unexpected TUSER port_id=3D%u\n", + port_id); + + dev_kfree_skb_any(skb); + DEV_STATS_INC(ndev, rx_dropped); + goto submit_new; + } + + skb_put(skb, rx_len); + skb->dev =3D ndev; + skb->protocol =3D eth_type_trans(skb, ndev); + skb->ip_summed =3D CHECKSUM_NONE; + __netif_rx(skb); + + DEV_STATS_INC(ndev, rx_packets); + DEV_STATS_ADD(ndev, rx_bytes, rx_len); + +submit_new: + ep_rx_refill(xchan, true); +} + static netdev_tx_t ep_start_xmit(struct sk_buff *skb, struct net_device *n= dev) { dev_kfree_skb_any(skb); @@ -211,6 +398,10 @@ ep_alloc_dma_chan(struct xlnx_tsn_ep *ep, const char *= name, bool is_tx, chan->ep =3D ep; chan->ring_size =3D ring_size; chan->dma_dev =3D dmaengine_get_dma_device(chan->chan); + if (!is_tx) { + spin_lock_init(&chan->rx_lock); + timer_setup(&chan->rx_refill_timer, ep_rx_refill_timer, 0); + } =20 return chan; } @@ -222,8 +413,21 @@ static void ep_free_dma_chan(struct xlnx_tsn_ep_dma_ch= an *chan) if (!chan) return; =20 - if (chan->chan) + if (chan->chan) { + if (!chan->is_tx) { + /* ep_stop() sets closing before teardown. Take rx_lock + * so any refill that already passed the closing check + * finishes and no later one submits or arms the timer, + * then shut down the timer so it cannot be rearmed + * before the channel is freed. + */ + spin_lock_bh(&chan->rx_lock); + spin_unlock_bh(&chan->rx_lock); + timer_shutdown_sync(&chan->rx_refill_timer); + } + dmaengine_terminate_sync(chan->chan); + } =20 if (chan->is_tx) { while (chan->ring_tail !=3D chan->ring_head) { @@ -322,9 +526,19 @@ static int ep_init_dmaengine(struct xlnx_tsn_ep *ep) rx_allocated++; } =20 + for (i =3D 0; i < ep->num_rx_queues; i++) { + if (!ep_rx_refill(ep->rx_chans[i], false)) { + dev_err(ep->dev, "RX channel %d: no descriptors armed\n", + i); + ret =3D -ENOMEM; + goto err_free_chans; + } + } + return 0; =20 err_free_chans: + WRITE_ONCE(ep->closing, true); while (--rx_allocated >=3D 0) ep_free_dma_chan(ep->rx_chans[rx_allocated]); while (--tx_allocated >=3D 0) --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010026.outbound.protection.outlook.com [52.101.201.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 450795AEC64; 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Tue, 8 Sep 2026 14:20:47 -0500 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb09.amd.com (10.181.42.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Tue, 8 Sep 2026 14:20:46 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Tue, 8 Sep 2026 14:20:41 -0500 From: Srinivas Neeli Date: Wed, 9 Sep 2026 00:49:55 +0530 Subject: [PATCH net-next v2 7/8] net: xilinx: tsn: add the endpoint TX data path Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-patches_v2_external-v2-7-3a40babaff4c@amd.com> References: <20260909-patches_v2_external-v2-0-3a40babaff4c@amd.com> In-Reply-To: <20260909-patches_v2_external-v2-0-3a40babaff4c@amd.com> To: Nagadheeraj Rottela , Andrew Lunn , "David S. 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Look up the physical DMA channel for the frame's queue through the map built at probe, map the frame and submit it to that channel. Stop the queue when the ring runs out of space, and wake it from the completion callback once a slot frees up. Co-developed-by: Nagadheeraj Rottela Signed-off-by: Nagadheeraj Rottela Signed-off-by: Srinivas Neeli --- Changes in v2: - Take the scatterlist entry count from skb_to_sgvec() instead of assuming nr_frags + 1, so dma_map_sg() cannot walk past the end of the list. - Check dmaengine_submit() with dma_submit_error() before advancing the ring head and charging BQL, and drop the frame if the submit fails. - Publish the ring head with WRITE_ONCE(), paired with the READ_ONCE() on t= he completion side. - Take the ring size from the channel instead of the compile-time constant. - Use dmaengine_prep_slave_sg() instead of calling the ops member directly. - Move tx_lock into the per-channel struct, mirroring rx_lock, so independe= nt TX queues do not serialise on one device-wide lock. - Narrow the tx_lock kernel-doc to what it actually protects. - Mark the ring_tail store in the completion callback with WRITE_ONCE() to match the READ_ONCE() readers. - Use the spinlock_bh guard class in the completion callback so it matches = the spin_lock_bh() in the xmit path. - Index tx_chans directly by logical queue in ep_start_xmit() and drop the phys_chan/dma_dev locals, so the transmit path no longer re-derives the channel through tx_dma_chan_map. --- drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c | 150 ++++++++++++++++++++= +++- 1 file changed, 149 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c b/drivers/net/= ethernet/xilinx/tsn/xilinx_tsn_ep.c index 9ed1170794e0..9e9a45169681 100644 --- a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c +++ b/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c @@ -29,6 +29,8 @@ #include #include =20 +#include + #include "xilinx_tsn.h" =20 #define DRIVER_NAME "xilinx_tsn_ep" @@ -82,6 +84,7 @@ struct skbuf_dma_descriptor { * @ring_tail: consumer index * @ring_size: number of slots in @skb_ring * @rx_lock: serialises @ring_head between the RX callback and the refill = timer + * @tx_lock: serialises @ring_head and @ring_tail between xmit and TX comp= letion * @rx_refill_timer: retries RX refill after an allocation failure * @is_tx: true for TX channels, false for RX */ @@ -94,6 +97,7 @@ struct xlnx_tsn_ep_dma_chan { u32 ring_tail; u32 ring_size; spinlock_t rx_lock; /* serialises @ring_head */ + spinlock_t tx_lock; /* serialises @ring_head and @ring_tail */ struct timer_list rx_refill_timer; bool is_tx; }; @@ -300,8 +304,147 @@ static void ep_dma_rx_cb(void *data, const struct dma= engine_result *result) ep_rx_refill(xchan, true); } =20 +static void ep_dma_tx_cb(void *data, const struct dmaengine_result *result) +{ + struct xlnx_tsn_ep_dma_chan *xchan =3D data; + struct skbuf_dma_descriptor *skbuf_dma; + struct netdev_queue *txq; + struct net_device *ndev; + struct scatterlist *sgl; + struct sk_buff *skb; + int sg_len; + int len; + + scoped_guard(spinlock_bh, &xchan->tx_lock) { + skbuf_dma =3D ep_get_desc(xchan, + xchan->ring_tail & (xchan->ring_size - 1)); + if (!skbuf_dma || !skbuf_dma->skb) + return; + + skb =3D skbuf_dma->skb; + sgl =3D skbuf_dma->sgl; + sg_len =3D skbuf_dma->sg_len; + + dma_unmap_sg(xchan->dma_dev, sgl, sg_len, DMA_TO_DEVICE); + + skbuf_dma->skb =3D NULL; + WRITE_ONCE(xchan->ring_tail, xchan->ring_tail + 1); + } + + ndev =3D skb->dev; + txq =3D netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); + len =3D skb->len; + + if (unlikely(result->result !=3D DMA_TRANS_NOERROR)) { + DEV_STATS_INC(ndev, tx_errors); + } else { + DEV_STATS_INC(ndev, tx_packets); + DEV_STATS_ADD(ndev, tx_bytes, len); + } + + dev_consume_skb_any(skb); + netif_txq_completed_wake(txq, 1, len, + CIRC_SPACE(READ_ONCE(xchan->ring_head), + READ_ONCE(xchan->ring_tail), + xchan->ring_size), 2); +} + static netdev_tx_t ep_start_xmit(struct sk_buff *skb, struct net_device *n= dev) { + struct dma_async_tx_descriptor *dma_tx_desc; + struct xlnx_tsn_ep *ep =3D netdev_priv(ndev); + struct skbuf_dma_descriptor *skbuf_dma; + int queue =3D skb_get_queue_mapping(skb); + struct xlnx_tsn_ep_dma_chan *xchan; + struct netdev_queue *txq; + int sg_len, nents, ret; + dma_cookie_t cookie; + + if (unlikely(queue >=3D ep->num_tx_queues)) { + if (net_ratelimit()) + netdev_warn(ndev, "Invalid TX queue %d (max %u)\n", + queue, ep->num_tx_queues); + goto err_drop_skb; + } + + if (ep->tx_dma_chan_map[queue] =3D=3D TSN_DMA_CH_INVALID) { + if (net_ratelimit()) + netdev_warn(ndev, "Logical TX queue %d has invalid DMA mapping\n", + queue); + goto err_drop_skb; + } + + xchan =3D ep->tx_chans[queue]; + + sg_len =3D skb_shinfo(skb)->nr_frags + 1; + txq =3D netdev_get_tx_queue(ndev, queue); + + spin_lock_bh(&xchan->tx_lock); + if (CIRC_SPACE(xchan->ring_head, READ_ONCE(xchan->ring_tail), + xchan->ring_size) <=3D 1) { + netif_txq_try_stop(txq, + CIRC_SPACE(xchan->ring_head, + READ_ONCE(xchan->ring_tail), + xchan->ring_size), + 2); + spin_unlock_bh(&xchan->tx_lock); + if (net_ratelimit()) + netdev_warn(ndev, "TSN TX ring full\n"); + + return NETDEV_TX_BUSY; + } + + skbuf_dma =3D ep_get_desc(xchan, xchan->ring_head & (xchan->ring_size - 1= )); + if (!skbuf_dma) { + spin_unlock_bh(&xchan->tx_lock); + goto err_drop_skb; + } + spin_unlock_bh(&xchan->tx_lock); + + sg_init_table(skbuf_dma->sgl, sg_len); + ret =3D skb_to_sgvec(skb, skbuf_dma->sgl, 0, skb->len); + if (ret < 0) + goto err_drop_skb; + sg_len =3D ret; + + nents =3D dma_map_sg(xchan->dma_dev, skbuf_dma->sgl, sg_len, DMA_TO_DEVIC= E); + if (!nents) + goto err_drop_skb; + + dma_tx_desc =3D dmaengine_prep_slave_sg(xchan->chan, skbuf_dma->sgl, + nents, DMA_MEM_TO_DEV, + DMA_PREP_INTERRUPT); + if (!dma_tx_desc) + goto err_unmap_sg; + + skbuf_dma->skb =3D skb; + skbuf_dma->sg_len =3D sg_len; + dma_tx_desc->callback_param =3D xchan; + dma_tx_desc->callback_result =3D ep_dma_tx_cb; + + spin_lock_bh(&xchan->tx_lock); + cookie =3D dmaengine_submit(dma_tx_desc); + if (dma_submit_error(cookie)) { + spin_unlock_bh(&xchan->tx_lock); + skbuf_dma->skb =3D NULL; + goto err_unmap_sg; + } + WRITE_ONCE(xchan->ring_head, xchan->ring_head + 1); + netdev_tx_sent_queue(txq, skb->len); + netif_txq_maybe_stop(txq, + CIRC_SPACE(xchan->ring_head, + READ_ONCE(xchan->ring_tail), + xchan->ring_size), + 2, 2); + spin_unlock_bh(&xchan->tx_lock); + + dma_async_issue_pending(xchan->chan); + + return NETDEV_TX_OK; + +err_unmap_sg: + dma_unmap_sg(xchan->dma_dev, skbuf_dma->sgl, sg_len, DMA_TO_DEVICE); +err_drop_skb: dev_kfree_skb_any(skb); DEV_STATS_INC(ndev, tx_dropped); return NETDEV_TX_OK; @@ -331,10 +474,13 @@ static int ep_open(struct net_device *ndev) static int ep_stop(struct net_device *ndev) { struct xlnx_tsn_ep *ep =3D netdev_priv(ndev); + unsigned int i; =20 netif_tx_disable(ndev); WRITE_ONCE(ep->closing, true); ep_exit_dmaengine(ep); + for (i =3D 0; i < ndev->num_tx_queues; i++) + netdev_tx_reset_subqueue(ndev, i); =20 return 0; } @@ -398,7 +544,9 @@ ep_alloc_dma_chan(struct xlnx_tsn_ep *ep, const char *n= ame, bool is_tx, chan->ep =3D ep; chan->ring_size =3D ring_size; chan->dma_dev =3D dmaengine_get_dma_device(chan->chan); - if (!is_tx) { + if (is_tx) { + spin_lock_init(&chan->tx_lock); + } else { spin_lock_init(&chan->rx_lock); timer_setup(&chan->rx_refill_timer, ep_rx_refill_timer, 0); } --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010014.outbound.protection.outlook.com [52.101.201.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46ED35AEC41; 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Tue, 8 Sep 2026 14:20:53 -0500 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb09.amd.com (10.181.42.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Tue, 8 Sep 2026 14:20:52 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Tue, 8 Sep 2026 14:20:47 -0500 From: Srinivas Neeli Date: Wed, 9 Sep 2026 00:49:56 +0530 Subject: [PATCH net-next v2 8/8] net: xilinx: tsn: deliver endpoint RX frames to DSA user ports Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-patches_v2_external-v2-8-3a40babaff4c@amd.com> References: <20260909-patches_v2_external-v2-0-3a40babaff4c@amd.com> In-Reply-To: <20260909-patches_v2_external-v2-0-3a40babaff4c@amd.com> To: Nagadheeraj Rottela , Andrew Lunn , "David S. Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Michal Simek , "Sebastian Andrzej Siewior" , Clark Williams , Steven Rostedt CC: , , , , , Srinivas Neeli , , X-Mailer: b4 0.16.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B072:EE_|CH2PR12MB4199:EE_ X-MS-Office365-Filtering-Correlation-Id: 53ecb8aa-7c7a-46da-3979-08df0dde4e1f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|1800799024|82310400026|23010399003|7416014|10067099003|3023799007|11063799006|56012099006|22082099003|18002099003|921020; X-Microsoft-Antispam-Message-Info: DHNbqNg5YhHEntQd6W1PTEPbYlDtR1+oGTohg2ECV2JceymRZDpqyR87O9ON8U3pfYAt8B43WT2k3U6I807ffwxG+yse0WFDnCbZcxR3GJG5CcA0DjCbs62k61JkU5Rbq1jjH7JNVVP7cWm9F/WN+M71tBxHzSYyDMAGXYG8u+7HjwPNgIbTw4ysdMaszo3uMZG0oRn6WDZCpIc6gSkN3S2Uql2BhGH6efz8YPhzUehOePwdGX+Z03VSWYinaXW41PYktmo74uh+pX+Etb7T2SqhXWSxq51FzMyAEdKuFkoic0nJi6TsKL+Id68AG0sivhbwKBmEk3s3s8+RRchlopbou8dHBsDx9X0eyD4JOK7AbwZWuYYSNgrP1GVnmIdDQI4WGJGDk7OwAs8XA6ocW3Epx/c4k2dgfb/MUGkLn8RCnvo68D/3RLQN4vfgylGJEpcZCdd7l8J8FbOJL9crG3b99yjIaHHNmV+qqjpQj7+55jAyk6GkiTsjR4tk1EHkUwBbMkKXp68EWqz+cJM3q+welwUAuh1pjHF+6NChBuVUmPwnFb8MDgwd/xo/xONEVBpmSnDBlOV2Zlipl//DlBjUxPmGCLDaxzYdBCAFmYDtrFqKCRrG9weLWK8CQwLlxIIB4lfbhkkHvAdVgHtNN8oaDTjnEYhomxo/Df9zfahgV1ws3d1JgFImrKl0GG+WhEKtJ6uJUlYdMdH7hoiXfyCxQ6/mBS9+nQoNTY4JUovIz48LFe+938ja/ojXrXq6 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700016)(1800799024)(82310400026)(23010399003)(7416014)(10067099003)(3023799007)(11063799006)(56012099006)(22082099003)(18002099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /qnnMjDeHSQ7AVag9dFL3ED6wyJfMc5rCzoWZcM+vj2rdltii651N1Riu3LcyqAbE9g1s8RR6Ke2aCY1hX6kBFfGH2AWkqC+vqAgGb59fzq041DanLR/hIOEZcbctkL2WwsIRQiBF2sJHBzooFqznsEpftdvBXEo5StSUp+qurSL30bFZsPgDxccO/f8elJYfWm1lOVfqM9G07/cO+VGhHVwxzDxYaQ7o1glcRhQUf0nCNghFaezyV/AUgnnK2s9XmF6ANJW2OHF8pgM1nCcZdqSQ7fclBuCZ3E4d+lSpFRNP2qLtpS/RoU5K4KTPkhriOWw0WR6oeeTS2ALpWTqunrs0yv/x7ooc8yY/v4HkU/GR8VDh1OI9nL5ymUTG1UrJ0u4wGb2PZJhIKZDBRtl4ftgDdQKJTA52WYcBK7ze3aum8i+ChRM7ADZNjrl42S7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2026 19:20:55.4039 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53ecb8aa-7c7a-46da-3979-08df0dde4e1f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B072.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4199 From: Nagadheeraj Rottela The DSA core routes an RX frame to a user port from the port metadata attached to the skb. Without that metadata, frames from the two MACs cannot reach their swpN netdevs. Allocate a METADATA_HW_PORT_MUX entry per MAC port at probe and attach the matching entry to each RX frame by its TUSER port_id. Frames from MAC1 and MAC2 now reach the correct user netdev, which completes the conduit data path. The RX callback runs in softirq and hands the frame to __netif_rx(), which queues it on the backlog instead of consuming it inline, so the attached dst must be a counted reference (dst_hold() + skb_dst_set()) to survive the handoff. Signed-off-by: Nagadheeraj Rottela Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli --- Changes in v2: - Attach the RX port metadata only when the netdev is a DSA conduit (netdev_uses_dsa()), so no dev-less dst leaks into the stack when no swit= ch is bound. - Take a real reference on the per-port metadata_dst with dst_hold() + skb_dst_set() before the __netif_rx() backlog handoff, instead of skb_dst_set_noref() + skb_dst_force(). The entries stay live for the driv= er lifetime, so this drops the rcu_read_lock() that skb_dst_force() would ne= ed in the softirq callback. - Release the per-port metadata_dst with dst_release() at teardown, not metadata_dst_free(), so an skb still referencing it is not freed early. --- drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c | 55 +++++++++++++++++++++= +++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c b/drivers/net/= ethernet/xilinx/tsn/xilinx_tsn_ep.c index 9e9a45169681..db7da26521d0 100644 --- a/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c +++ b/drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c @@ -29,6 +29,8 @@ #include #include =20 +#include +#include #include =20 #include "xilinx_tsn.h" @@ -58,6 +60,9 @@ #define TSN_TUSER_PORT_MAC1 0x1 #define TSN_TUSER_PORT_MAC2 0x2 =20 +/* Sized to index port_md[] by TUSER port_id (1 or 2, slot 0 unused) */ +#define XLNX_TSN_EP_PORT_MD_SLOTS (TSN_TUSER_PORT_MAC2 + 1) + /** * struct skbuf_dma_descriptor - skb container for each in-flight DMA desc= riptor * @sgl: scatter-gather list backing the DMA mapping @@ -114,6 +119,8 @@ struct xlnx_tsn_ep_dma_chan { * @tx_chans: array of TX channels (size @num_tx_queues) * @rx_chans: array of RX channels (size @num_rx_queues) * @closing: set in ndo_stop so the RX completion callback stops re-arming + * @port_md: per-TUSER-port METADATA_HW_PORT_MUX entries attached on RX, + * indexed by port_id (1 for MAC1, 2 for MAC2) */ struct xlnx_tsn_ep { struct net_device *ndev; @@ -128,6 +135,8 @@ struct xlnx_tsn_ep { struct xlnx_tsn_ep_dma_chan **rx_chans; =20 bool closing; + + struct metadata_dst *port_md[XLNX_TSN_EP_PORT_MD_SLOTS]; }; =20 static inline struct skbuf_dma_descriptor * @@ -292,6 +301,10 @@ static void ep_dma_rx_cb(void *data, const struct dmae= ngine_result *result) } =20 skb_put(skb, rx_len); + if (netdev_uses_dsa(ndev)) { + dst_hold(&ep->port_md[port_id]->dst); + skb_dst_set(skb, &ep->port_md[port_id]->dst); + } skb->dev =3D ndev; skb->protocol =3D eth_type_trans(skb, ndev); skb->ip_summed =3D CHECKSUM_NONE; @@ -854,6 +867,37 @@ static int ep_count_dma_queues(struct device *dev, u32= *out_tx, u32 *out_rx, return 0; } =20 +static void ep_free_port_md(struct xlnx_tsn_ep *ep) +{ + int i; + + for (i =3D 0; i < XLNX_TSN_EP_PORT_MD_SLOTS; i++) { + if (ep->port_md[i]) { + dst_release(&ep->port_md[i]->dst); + ep->port_md[i] =3D NULL; + } + } +} + +static int ep_alloc_port_md(struct xlnx_tsn_ep *ep) +{ + int i; + + for (i =3D TSN_TUSER_PORT_MAC1; i <=3D TSN_TUSER_PORT_MAC2; i++) { + struct metadata_dst *md; + + md =3D metadata_dst_alloc(0, METADATA_HW_PORT_MUX, GFP_KERNEL); + if (!md) { + ep_free_port_md(ep); + return -ENOMEM; + } + md->u.port_info.port_id =3D i; + ep->port_md[i] =3D md; + } + + return 0; +} + static int xlnx_tsn_ep_probe(struct platform_device *pdev) { u32 rx_chan_num[TSN_MAX_RX_QUEUE]; @@ -939,16 +983,24 @@ static int xlnx_tsn_ep_probe(struct platform_device *= pdev) ndev->dev_addr); } =20 + ret =3D ep_alloc_port_md(ep); + if (ret) { + dev_err_probe(dev, ret, "failed to allocate per-port metadata\n"); + goto err_free_ndev; + } + platform_set_drvdata(pdev, ep); =20 ret =3D register_netdev(ndev); if (ret) { dev_err_probe(dev, ret, "failed to register net device\n"); - goto err_free_ndev; + goto err_free_md; } =20 return 0; =20 +err_free_md: + ep_free_port_md(ep); err_free_ndev: free_netdev(ndev); return ret; @@ -962,6 +1014,7 @@ static void xlnx_tsn_ep_remove(struct platform_device = *pdev) return; =20 unregister_netdev(ep->ndev); + ep_free_port_md(ep); free_netdev(ep->ndev); } =20 --=20 2.43.0