From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B3515616C3; Wed, 9 Sep 2026 13:00:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958828; cv=none; b=QVF1SG6C86J1old3pw/sTTbjEITOBC3qdUHEz2wgCu98kqebMJae3yaiGBTpz2AqbBVauVpKWpp1zxL8YN1ZgEfJgpiQzWFByz5jrNb1RNZ+UfmUpAZpM+mzN0UsWccmoRIoOUNA0N5EYlkQztB+pd6NOf5Q+K7t/LZKZYdGQQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958828; c=relaxed/simple; bh=LhixG2fCAUNCT+8en6PrRgF6aAtHhOutp8kzJk8cL28=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=nEnedoygzJJbO5JJquD6p/2IxGxCDBuvuehFwYkSTCpucLYVKx++MEcsynPuvyCP0/k5kLSXrqXPwTH+/gd89CD+jv2SoudgxbYcsYSweweMT4iLeH4tyBTHpExxlDFMZ3PzMsBOyZvdD1qPDu6KZryIxb5M5viGz27NkdcPvM0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=dcyW9I/K; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="dcyW9I/K" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958826; x=1820494826; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=LhixG2fCAUNCT+8en6PrRgF6aAtHhOutp8kzJk8cL28=; b=dcyW9I/Kma41aACx98MisThHLJCjnJn+jz9+6s2TE3jyxTC9+l6FNLvr VlfaTQUJcHtByR5X1Mkv5GzVIZsc5EY7xM+Xkbr2GPE5wyo5mJUan6SoB I7XFxwBnRoyVaCiCfBGKIAiBjDxNBJh157/HWePt75ZPdPc7g+kssN/ID E5kiBQLZxluI53ArWd4c1EgYiGXb6RFajlw0M/BLy7djblgKGWJmWtuZf ua4c9NAjvL+i9J+PL6jpQZBNl5FTMwovbbkGgtwku9VykZYnlkJ9aaoNd +Ah6fi1CxDbpeOHDbFhdVYITpgJT6Ph/aJ6giKF8xNTgN5EDGZfIxQLb6 w==; X-CSE-ConnectionGUID: /e9uF4MCR3+eDjpTL/objg== X-CSE-MsgGUID: R3uDSJ5sSAClYKRzW4QWbQ== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="230464537" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Sep 2026 06:00:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 9 Sep 2026 06:00:25 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:00:21 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:03 +0200 Subject: [PATCH net-next v6 01/14] MAINTAINERS: add FDMA library to Sparx5 SoC entry Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-1-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 The FDMA library under drivers/net/ethernet/microchip/fdma/ is shared by the lan966x, sparx5 and lan969x drivers, but is not covered by an entry in the MAINTAINERS file. A subsequent patch will add new files to the FDMA library, so let's make sure it's covered. Add drivers/net/ethernet/microchip/fdma/ to the Sparx5 SoC entry, since I am already listed there. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index b23fb6f2f4ef..e41d4337136d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3214,6 +3214,7 @@ M: UNGLinuxDriver@microchip.com L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported F: arch/arm64/boot/dts/microchip/sparx* +F: drivers/net/ethernet/microchip/fdma/ F: drivers/net/ethernet/microchip/vcap/ F: drivers/pinctrl/pinctrl-microchip-sgpio.c N: sparx5 --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA8655616C8; Wed, 9 Sep 2026 13:00:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958832; cv=none; b=UpE1qLYas5c+/voG3Vf3yOKsEI9QX0oaEBQxW+Iu8EwtBz7hu3rylmCgwEJEQcA/9R4jEYeNFpS+N+qfuZXQ3uayS3nZ6gzYHFHIf0KTbejcLkip+O+aRQn7Q0oEzrM5bEu0dJ0XMWMoAx4D2AKj5ersMZ+260CshkB7Fj2JNtE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958832; c=relaxed/simple; bh=Iy12tCl7T6s6ZRBeoiQcoNoKALMADqPH0I/xSE+s2mQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=K9TU0fMd3g5QdQ8nmDeKkNZnkg7r1suCyXzrFZGzQTnhBcKI1KVoHpcCsUi5Oi+k51QIgMXfBDCeipGJN5khjKg7evxA42pyE90oLwKd7U+rEZgh3Na4hHqrAZbEqv7EHl7sYPuPDhD6rltuTWYvqzygjj2ZxhAZZpilwI6bEOQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=pdqsD3NH; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="pdqsD3NH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958831; x=1820494831; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=Iy12tCl7T6s6ZRBeoiQcoNoKALMADqPH0I/xSE+s2mQ=; b=pdqsD3NHPZ9x7y4RR2XLGnlck7dsBtNgyKteCvJjLGlzPnYTF/vzVIH7 yVaLa0S+67IRNYl4QzHOzWGGq67RVBcb3kktxcLLwUQRb7H7fJw8lgb/Y WLU781HjC8v5PrLzkuilQtgID+qiMKoXdLD75bbn+qmAD/XY7NeLnincF 0/zMHpCptIeyRqfG9owMu1cQfs8ac77CoKy8j3cFTZKXBADszkM330JaY 7TT1LQQsmxrJZ86sVuxuZb3PFdNInizEwaQOwxqsmNyDnEH9RCZTAT617 mAssGFjGou+JqMOzlKeSg+zCmhYmULSNKL5cl6S22uOSywjtyoZ6GTuk5 g==; X-CSE-ConnectionGUID: kfkBqir1QiKbPm1OTFvsfA== X-CSE-MsgGUID: 92zChvoSSgWM1SnRlbg6dw== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="63358622" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:00:29 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:00:29 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:00:25 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:04 +0200 Subject: [PATCH net-next v6 02/14] net: microchip: fdma: rename contiguous dataptr helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-2-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 When the FDMA library was introduced [1], two helpers to get the DMA and virtual address of a data buffer, in contiguous memory, were added. These helpers have had no callers until this series. I found the naming I initially used confusing and inconsistent. Rename fdma_dataptr_get_contiguous() and fdma_dataptr_virt_get_contiguous() to fdma_dataptr_dma_addr_contiguous() and fdma_dataptr_virt_addr_contiguous(). This makes the pair symmetric and clarifies what type of address each returns. [1]: commit 30e48a75df9c ("net: microchip: add FDMA library") Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/fdma/fdma_api.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.h b/drivers/net/e= thernet/microchip/fdma/fdma_api.h index d91affe8bd98..dea8e3cc155a 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.h +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.h @@ -197,8 +197,8 @@ static inline int fdma_nextptr_cb(struct fdma *fdma, in= t dcb_idx, u64 *nextptr) * if the dataptr addresses and DCB's are in contiguous memory and the dri= ver * supports XDP. */ -static inline u64 fdma_dataptr_get_contiguous(struct fdma *fdma, int dcb_i= dx, - int db_idx) +static inline u64 fdma_dataptr_dma_addr_contiguous(struct fdma *fdma, + int dcb_idx, int db_idx) { return fdma->dma + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + (dcb_idx * fdma->n_dbs + db_idx) * fdma->db_size + @@ -209,8 +209,8 @@ static inline u64 fdma_dataptr_get_contiguous(struct fd= ma *fdma, int dcb_idx, * applicable if the dataptr addresses and DCB's are in contiguous memory = and * the driver supports XDP. */ -static inline void *fdma_dataptr_virt_get_contiguous(struct fdma *fdma, - int dcb_idx, int db_idx) +static inline void *fdma_dataptr_virt_addr_contiguous(struct fdma *fdma, + int dcb_idx, int db_idx) { return (u8 *)fdma->dcbs + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + (dcb_idx * fdma->n_dbs + db_idx) * fdma->db_size + --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBCBD563293; Wed, 9 Sep 2026 13:00:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958837; cv=none; b=ja6IczdPbY/bP+pV0+TmlKuWF1G/Qqd/KL2fNrVoIlrppr0fsDmsa4SWjZ9RhVh5q0MVh7UQnpQfF+8VKzRqjr4+Dr9geCEz0pS6wcM/gw1W3NaR6v0YKGWvP0g5VbepBke0ADrRbiFh23ot8TdHpobNcGFBIMFNziJZusogC1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958837; c=relaxed/simple; bh=CkOwWYzIgRwk01MIAIjdFokeDHh82u6wTeIOqTaBdpY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=WC5ZB3TnrHVSugQY07cafnjJpQmq3sCgLUdgVRo+pdb80rXJEION1gB4lBYV2rljvgU28uugrV34GCC3ktzCncqh1AuO1O4QHcADevZbreO8SIzWMHIYx0KIx5nzgnudAuoRWcO8S6pLnYAJ2JIKIQxXlorVWnEJjFYrXpsW5Bw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=PC5tdlgT; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PC5tdlgT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958835; x=1820494835; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=CkOwWYzIgRwk01MIAIjdFokeDHh82u6wTeIOqTaBdpY=; b=PC5tdlgTo22SBViNek55ysP/QXuzgGsz6SmA+YwegwlDkFVDb/sSBiPP Wf0S6d4kmIEzt8iAhWVBlVcoER7COyJjhu3moKyXPHUklNtp5nGuJWV8f af/BrA+2Zs2uI+Zyxd5HDB5vzZ8DWpwV9f+FCd/StPKuwHvH1dUsUP2Nr f5nkTzaumTDZ7mPnKmG+oqeVffaVPmmo4GQHAuAPCcsogneqag1KlAxjo 964EUa3UHI7h0fQMn/maZ42v8Ep1scVRd60aHqyeXi6kpYszs2us/c6mB +5rtNxdqPpgTnTHE/46jKLclIIiInt0WBGLnt94fYkAUPM9tg4KlLKmk2 Q==; X-CSE-ConnectionGUID: BiDLrhlIQ/antAorFMGTMQ== X-CSE-MsgGUID: 2eu53TtqTTKS1sbX4f1Tvw== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="230464543" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Sep 2026 06:00:35 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 9 Sep 2026 06:00:34 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:00:29 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:05 +0200 Subject: [PATCH net-next v6 03/14] net: microchip: fdma: add PCIe ATU support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-3-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 When lan966x or lan969x operates as a PCIe endpoint, the internal FDMA engine cannot directly access host memory. Instead, DMA addresses must be translated through the PCIe Address Translation Unit (ATU). The ATU provides outbound windows that map internal addresses to PCIe bus addresses. The ATU outbound address space (0x10000000-0x1fffffff) is divided into six equally-sized regions (~42MB each). When FDMA buffers are allocated, a free ATU region is claimed and programmed with the DMA target address. The FDMA engine then uses the region's base address in its descriptors, and the ATU translates these to the actual DMA addresses on the PCIe bus. Add the required functions and helpers that combine the DMA allocation with the ATU region mapping, effectively adding support for PCIe FDMA. The ATU cannot express a limit finer than its 64KB region granularity, so pad the mapped allocation to that boundary; otherwise the outbound window would extend past the memory the host allocated for DMA. This implementation will also be used by the lan969x, when PCIe FDMA is added for that platform in the future. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/fdma/Makefile | 4 + drivers/net/ethernet/microchip/fdma/fdma_api.c | 44 ++++++ drivers/net/ethernet/microchip/fdma/fdma_api.h | 14 ++ drivers/net/ethernet/microchip/fdma/fdma_pci.c | 203 +++++++++++++++++++++= ++++ drivers/net/ethernet/microchip/fdma/fdma_pci.h | 52 +++++++ 5 files changed, 317 insertions(+) diff --git a/drivers/net/ethernet/microchip/fdma/Makefile b/drivers/net/eth= ernet/microchip/fdma/Makefile index cc9a736be357..910a10b33fb9 100644 --- a/drivers/net/ethernet/microchip/fdma/Makefile +++ b/drivers/net/ethernet/microchip/fdma/Makefile @@ -5,3 +5,7 @@ =20 obj-$(CONFIG_FDMA) +=3D fdma.o fdma-y +=3D fdma_api.o + +ifneq ($(CONFIG_MCHP_LAN966X_PCI),) +fdma-y +=3D fdma_pci.o +endif diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.c b/drivers/net/e= thernet/microchip/fdma/fdma_api.c index e78c3590da9e..a3c9e3097c5c 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.c +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.c @@ -127,6 +127,50 @@ void fdma_free_phys(struct fdma *fdma) } EXPORT_SYMBOL_GPL(fdma_free_phys); =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +/* Allocate coherent DMA memory and map it in the ATU. */ +int fdma_alloc_coherent_and_map(struct device *dev, struct fdma *fdma, + struct fdma_pci_atu *atu) +{ + struct fdma_pci_atu_region *region; + int err; + + if (WARN_ON(fdma->atu_region)) + return -EBUSY; + + /* The ATU cannot express a limit finer than the region granularity, so + * the hardware widens the programmed limit to that boundary. Pad the + * allocation to match, or the outbound window would extend past the + * memory we own. + */ + fdma->size =3D ALIGN(fdma->size, FDMA_PCI_ATU_REGION_ALIGN); + + err =3D fdma_alloc_coherent(dev, fdma); + if (err) + return err; + + region =3D fdma_pci_atu_region_map(atu, fdma->dma, fdma->size); + if (IS_ERR(region)) { + fdma_free_coherent(dev, fdma); + return PTR_ERR(region); + } + + fdma->atu_region =3D region; + + return 0; +} +EXPORT_SYMBOL_GPL(fdma_alloc_coherent_and_map); + +/* Free coherent DMA memory and unmap the memory in the ATU. */ +void fdma_free_coherent_and_unmap(struct device *dev, struct fdma *fdma) +{ + fdma_pci_atu_region_unmap(fdma->atu_region); + fdma->atu_region =3D NULL; + fdma_free_coherent(dev, fdma); +} +EXPORT_SYMBOL_GPL(fdma_free_coherent_and_unmap); +#endif + /* Get the size of the FDMA memory */ u32 fdma_get_size(struct fdma *fdma) { diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.h b/drivers/net/e= thernet/microchip/fdma/fdma_api.h index dea8e3cc155a..ccc30d506e89 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.h +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.h @@ -7,6 +7,8 @@ #include #include =20 +#include "fdma_pci.h" + /* This provides a common set of functions and data structures for interac= ting * with the Frame DMA engine on multiple Microchip switchcores. * @@ -109,6 +111,11 @@ struct fdma { u32 channel_id; =20 struct fdma_ops ops; + +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + /* PCI ATU region for this FDMA instance. */ + struct fdma_pci_atu_region *atu_region; +#endif }; =20 /* Advance the DCB index and wrap if required. */ @@ -233,9 +240,16 @@ int __fdma_dcb_add(struct fdma *fdma, int dcb_idx, u64= info, u64 status, =20 int fdma_alloc_coherent(struct device *dev, struct fdma *fdma); int fdma_alloc_phys(struct fdma *fdma); +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +int fdma_alloc_coherent_and_map(struct device *dev, struct fdma *fdma, + struct fdma_pci_atu *atu); +#endif =20 void fdma_free_coherent(struct device *dev, struct fdma *fdma); void fdma_free_phys(struct fdma *fdma); +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +void fdma_free_coherent_and_unmap(struct device *dev, struct fdma *fdma); +#endif =20 u32 fdma_get_size(struct fdma *fdma); u32 fdma_get_size_contiguous(struct fdma *fdma); diff --git a/drivers/net/ethernet/microchip/fdma/fdma_pci.c b/drivers/net/e= thernet/microchip/fdma/fdma_pci.c new file mode 100644 index 000000000000..bbfd3c67e03b --- /dev/null +++ b/drivers/net/ethernet/microchip/fdma/fdma_pci.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include + +#include "fdma_pci.h" + +/* When the switch operates as a PCIe endpoint, the FDMA engine needs to + * DMA to/from host memory. The FDMA writes to addresses within the endpoi= nt's + * internal Outbound (OB) address space, and the PCIe ATU translates these= to + * DMA addresses on the PCIe bus, targeting host memory. + * + * The ATU supports up to six outbound regions. This implementation divides + * the OB address space into six equally sized chunks. + * + * +-------------+------------+------------+-----+------------+ + * | Index | Region 0 | Region 1 | ... | Region 5 | + * +-------------+------------+------------+-----+------------+ + * | Base addr | 0x10000000 | 0x12aa0000 | ... | 0x1d520000 | + * | Limit addr | 0x12a9ffff | 0x1553ffff | ... | 0x1ffbffff | + * | Target addr | host dma | host dma | ... | host dma | + * +-------------+------------+------------+-----+------------+ + * + * Base addr is the start address of the region within the OB address spac= e. + * Limit addr is each region's own upper bound. The value actually + * programmed is set per-mapping as base_addr + mapped size - 1, and is + * usually smaller than this. + * Target addr is the host DMA address that the base addr translates to. + */ + +#define FDMA_PCI_ATU_OB_START 0x10000000 +#define FDMA_PCI_ATU_OB_END 0x1fffffff + +#define FDMA_PCI_ATU_ADDR 0x300000 +#define FDMA_PCI_ATU_IDX_SIZE 0x200 +#define FDMA_PCI_ATU_ENA_REG 0x4 +#define FDMA_PCI_ATU_ENA_BIT BIT(31) +#define FDMA_PCI_ATU_LWR_BASE_ADDR 0x8 +#define FDMA_PCI_ATU_UPP_BASE_ADDR 0xc +#define FDMA_PCI_ATU_LIMIT_ADDR 0x10 +#define FDMA_PCI_ATU_LWR_TARGET_ADDR 0x14 +#define FDMA_PCI_ATU_UPP_TARGET_ADDR 0x18 + +static u32 fdma_pci_atu_region_size(void) +{ + return round_down((FDMA_PCI_ATU_OB_END - FDMA_PCI_ATU_OB_START) / + FDMA_PCI_ATU_REGION_MAX, FDMA_PCI_ATU_REGION_ALIGN); +} + +static void __iomem *fdma_pci_atu_addr_get(void __iomem *addr, int offset, + int idx) +{ + return addr + FDMA_PCI_ATU_ADDR + FDMA_PCI_ATU_IDX_SIZE * idx + offset; +} + +static void fdma_pci_atu_region_enable(struct fdma_pci_atu_region *region) +{ + writel(FDMA_PCI_ATU_ENA_BIT, + fdma_pci_atu_addr_get(region->atu->addr, FDMA_PCI_ATU_ENA_REG, + region->idx)); +} + +static void fdma_pci_atu_region_disable(struct fdma_pci_atu_region *region) +{ + writel(0, fdma_pci_atu_addr_get(region->atu->addr, FDMA_PCI_ATU_ENA_REG, + region->idx)); +} + +/* Configure the address translation in the ATU. */ +static void +fdma_pci_atu_configure_translation(struct fdma_pci_atu_region *region) +{ + struct fdma_pci_atu *atu =3D region->atu; + int idx =3D region->idx; + + writel(lower_32_bits(region->base_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_LWR_BASE_ADDR, idx)); + + writel(upper_32_bits(region->base_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_UPP_BASE_ADDR, idx)); + + /* Upper limit register only needed with REGION_SIZE > 4GB. */ + writel(region->limit_addr, + fdma_pci_atu_addr_get(atu->addr, FDMA_PCI_ATU_LIMIT_ADDR, idx)); + + writel(lower_32_bits(region->target_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_LWR_TARGET_ADDR, idx)); + + writel(upper_32_bits(region->target_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_UPP_TARGET_ADDR, idx)); +} + +/* Find an unused ATU region. */ +static struct fdma_pci_atu_region * +fdma_pci_atu_region_get_free(struct fdma_pci_atu *atu) +{ + struct fdma_pci_atu_region *regions =3D atu->regions; + + for (int i =3D 0; i < FDMA_PCI_ATU_REGION_MAX; i++) { + if (regions[i].in_use) + continue; + + return ®ions[i]; + } + + return ERR_PTR(-ENOSPC); +} + +/* Unmap an ATU region, clearing its translation and disabling it. */ +void fdma_pci_atu_region_unmap(struct fdma_pci_atu_region *region) +{ + if (IS_ERR_OR_NULL(region)) + return; + + mutex_lock(®ion->atu->lock); + + region->target_addr =3D 0; + region->in_use =3D false; + + fdma_pci_atu_region_disable(region); + fdma_pci_atu_configure_translation(region); + + mutex_unlock(®ion->atu->lock); +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_region_unmap); + +/* Map a host DMA address into a free outbound region. */ +struct fdma_pci_atu_region * +fdma_pci_atu_region_map(struct fdma_pci_atu *atu, u64 target_addr, int siz= e) +{ + struct fdma_pci_atu_region *region; + + if (!atu) + return ERR_PTR(-EINVAL); + + if (size <=3D 0) + return ERR_PTR(-EINVAL); + + if (size > fdma_pci_atu_region_size()) + return ERR_PTR(-ERANGE); + + /* The ATU region base is only ever aligned to FDMA_PCI_ATU_REGION_ALIGN; + * require the same alignment of the host target address, since the ATU + * translates addr - target_addr + base_addr and any misalignment here + * would shift every translated address by the same amount. + */ + if (!IS_ALIGNED(target_addr, FDMA_PCI_ATU_REGION_ALIGN)) + return ERR_PTR(-EINVAL); + + mutex_lock(&atu->lock); + + region =3D fdma_pci_atu_region_get_free(atu); + if (IS_ERR(region)) { + mutex_unlock(&atu->lock); + return region; + } + + region->target_addr =3D target_addr; + region->limit_addr =3D region->base_addr + size - 1; + region->in_use =3D true; + + fdma_pci_atu_configure_translation(region); + fdma_pci_atu_region_enable(region); + + mutex_unlock(&atu->lock); + + return region; +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_region_map); + +/* Translate a host DMA address to the corresponding OB address. */ +u64 fdma_pci_atu_translate_addr(struct fdma_pci_atu_region *region, u64 ad= dr) +{ + return region->base_addr + (addr - region->target_addr); +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_translate_addr); + +/* Initialize ATU, dividing the OB space into equally sized regions. */ +void fdma_pci_atu_init(struct fdma_pci_atu *atu, void __iomem *addr) +{ + struct fdma_pci_atu_region *regions =3D atu->regions; + u32 region_size =3D fdma_pci_atu_region_size(); + + atu->addr =3D addr; + mutex_init(&atu->lock); + + for (int i =3D 0; i < FDMA_PCI_ATU_REGION_MAX; i++) { + regions[i].base_addr =3D + FDMA_PCI_ATU_OB_START + (i * region_size); + regions[i].idx =3D i; + regions[i].atu =3D atu; + + fdma_pci_atu_region_disable(®ions[i]); + } +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_init); diff --git a/drivers/net/ethernet/microchip/fdma/fdma_pci.h b/drivers/net/e= thernet/microchip/fdma/fdma_pci.h new file mode 100644 index 000000000000..60aa2d2a9af3 --- /dev/null +++ b/drivers/net/ethernet/microchip/fdma/fdma_pci.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _FDMA_PCI_H_ +#define _FDMA_PCI_H_ + +#include +#include +#include +#include + +#define FDMA_PCI_ATU_REGION_MAX 6 + +/* Outbound regions are 64KB granular (datasheet section 3.24.7.4.1), so b= oth + * the region base and the mapped size must be aligned to this. + */ +#define FDMA_PCI_ATU_REGION_ALIGN BIT(16) + +#define FDMA_PCI_DB_ALIGN 128 +#define FDMA_PCI_DB_SIZE(mtu) ALIGN(mtu, FDMA_PCI_DB_ALIGN) + +struct fdma_pci_atu; + +struct fdma_pci_atu_region { + struct fdma_pci_atu *atu; + u64 base_addr; /* Base addr of the OB window */ + u64 limit_addr; /* End addr of the active mapping (base_addr + size - 1) = */ + u64 target_addr; /* Host DMA address this region maps to */ + int idx; + bool in_use; +}; + +struct fdma_pci_atu { + void __iomem *addr; + struct mutex lock; /* Protects region alloc/free and ATU register access = */ + struct fdma_pci_atu_region regions[FDMA_PCI_ATU_REGION_MAX]; +}; + +/* Initialize ATU, dividing OB space into regions. */ +void fdma_pci_atu_init(struct fdma_pci_atu *atu, void __iomem *addr); + +/* Unmap an ATU region, clearing its translation and disabling it. */ +void fdma_pci_atu_region_unmap(struct fdma_pci_atu_region *region); + +/* Map a host DMA address into a free ATU region. */ +struct fdma_pci_atu_region *fdma_pci_atu_region_map(struct fdma_pci_atu *a= tu, + u64 target_addr, + int size); + +/* Translate a host DMA address to the OB address space. */ +u64 fdma_pci_atu_translate_addr(struct fdma_pci_atu_region *region, u64 ad= dr); + +#endif --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1DD25632A9; Wed, 9 Sep 2026 13:00:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958841; cv=none; b=D+gduX7nO/UaGMWj41g8ZiC7E/b4CruLuww+ro1tFagpLXv1pNH0vfKVIYnnfKVmD+LRhEQ3gOkqrf8ax/qTr7DSpOb+R1kbiToFWK/OSBQTXI/0VOFDrG9LxQ4UV9BQGPiDfDt9CBhjYpq5/fSJLKayl3H04xjggTNsGvXkGVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958841; c=relaxed/simple; bh=QYGrFqOkLMGg0egcUveRB4ur4cCoutEpPPiq+t5aHao=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=mphb0DOBdufX2uLeCBAt9ny6l+tVgAE60zxHEyR+pEDiWoPf6lV9VkCNciRXRSIvUX9JUQ5RMtzD+7693VS6Nfs52rFSH7NJlfCOpnFb78OMKr1p1Ws1tDg8cfIqSd1UO9VHYJQj4Tgu6KkLLLvjp864bla1UcNbfCRR262KLlc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=e3yVS4+/; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="e3yVS4+/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958844; x=1820494844; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=QYGrFqOkLMGg0egcUveRB4ur4cCoutEpPPiq+t5aHao=; b=e3yVS4+/YJvaE1rkfG0kWeH2oMB1a5OA4DCuxum8/6gpyutuLGpluORz KU7VSobBf3NaY9cKu0h9ANISfvchcTOHVY9itESHhnlOiVBfdi/QJCgDq E1z68kffI5a63uPCXtls5EcmEcibdVDKt1g5DWZmdoRVUatLIe+S/72hu rJT2DuB/1BPA3JobC/qwvPOcmLm04pwLE+CSH2EAal0dKCL9PLAtoMK0M 8dGUgGcKKfwIZcIicvAxm5YackOpoQQrkiVEYoFSoMwplUiDNVmlpCRMv KobBoZJKruitTAr2SZWsNsfbMYm4vLy08MElWyxMrzLtgcbA92kz10kaB w==; X-CSE-ConnectionGUID: CEuPzw+0Sni4lzeNQ638GQ== X-CSE-MsgGUID: 5THGDZdtSPa7Fp9QXOooNQ== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="62445205" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:00:43 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:00:38 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:00:34 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:06 +0200 Subject: [PATCH net-next v6 04/14] net: lan966x: add FDMA LLP register write helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-4-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 The FDMA Link List Pointer (LLP) register points to the first DCB in the chain and must be written before the channel is activated. This tells the FDMA engine where to begin DMA transfers. Move the LLP register writes from the channel start/activate functions into the allocation functions and introduce a shared lan966x_fdma_llp_configure() helper. This is needed because the upcoming PCIe FDMA path writes ATU-translated addresses to the LLP registers instead of DMA addresses. Keeping the writes in the shared start/activate path would overwrite these translated addresses. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 30 ++++++++++--------= ---- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 41d4ec7f2f57..b8344fd5e5ad 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -109,6 +109,13 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan9= 66x_rx *rx) return 0; } =20 +static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) +{ + lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); + lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); +} + static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; @@ -128,6 +135,8 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), FDMA_DCB_STATUS_INTR); =20 + lan966x_fdma_llp_configure(lan966x, fdma->dma, fdma->channel_id); + return 0; } =20 @@ -137,14 +146,6 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *r= x) struct fdma *fdma =3D &rx->fdma; u32 mask; =20 - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -215,6 +216,8 @@ static int lan966x_fdma_tx_alloc(struct lan966x_tx *tx) =20 fdma_dcbs_init(fdma, 0, 0); =20 + lan966x_fdma_llp_configure(lan966x, fdma->dma, fdma->channel_id); + return 0; =20 out: @@ -236,14 +239,6 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx= *tx) struct fdma *fdma =3D &tx->fdma; u32 mask; =20 - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -876,6 +871,9 @@ static int lan966x_fdma_reload(struct lan966x *lan966x,= int new_mtu) MEM_TYPE_PAGE_POOL, page_pool); } =20 + lan966x_fdma_llp_configure(lan966x, lan966x->rx.fdma.dma, + lan966x->rx.fdma.channel_id); + lan966x_fdma_rx_start(&lan966x->rx); =20 lan966x_fdma_wakeup_netdev(lan966x); --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAE3F560AB4; Wed, 9 Sep 2026 13:00:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958845; cv=none; b=tWcNE6fBQASuOfggLwbYTgjtLdJqn6A5645jlc/SB9/PzjbWuGAdBTeCkihBmPZj4QYniVJDzXKoqf8kDQML8hur+uoGuf7s8DATY0sOeo0t6StuWEU5P6VPDF6sCWOw9w8beAFUkC69ZMzSauGJ3cE48oYL+GtR1b3xpVu9RfE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958845; c=relaxed/simple; bh=GDJaLsAforcU9l7sYaMjbi5eINktR8k9y7Z6G10vv6o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=R6OWqJF20noxf+sJGqIlLie91Di4tLAfNfYf85aswe+ke2o5nZtQx++uK1SDc3pA6PLLQHvD46kWBZL53aiD05Jgv/ebMH4OsZ9SHTPv7fcDr07Wy2GX0K5o0ScrX9L+D5Oz8bwyL26VwnkW0CIexLoWzaiNjq7No3oKHgPn5A8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ZmRkEF4+; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ZmRkEF4+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958844; x=1820494844; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=GDJaLsAforcU9l7sYaMjbi5eINktR8k9y7Z6G10vv6o=; b=ZmRkEF4+Uxu8SXDUFXOWnjptC47LmbnzlgUnA/iaU0U3FEn/h+f/o5l9 Wpay6USnjZVtoxwbGDTS0OUULddzJdVbwjEV/fptgekG2Z6ZJzsLDOYjC YiPp29rQFO0FirossPvEjTyVfYi+Rykhqpgfif0EptRFL77Saq4S+Kfu5 KQCf30UFt3VnfVmZaLLvimEVo++FJQ5PkqirC1Z2VIAbLUI9xFmrHrezU 77C2OAzfCTNbkTOwxCqU3f5gdDi3LDNKdR0SdVffNt4n8PJKOVN7t+2Oa N+tu1I1QYtoVg7K7co9jHpJUnEIx3hnjuc1SUccjE+Bbp76YqYAKvWF5N g==; X-CSE-ConnectionGUID: VGLsUOARS32sPbXBsPgQIg== X-CSE-MsgGUID: Z16gsI4uRjaCcChh9orPIA== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="63358641" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:00:43 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:00:42 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:00:38 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:07 +0200 Subject: [PATCH net-next v6 05/14] net: lan966x: export FDMA helpers for reuse Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-5-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Make shared FDMA helpers non-static, so they can be reused by the PCIe FDMA implementation. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 22 +++++++++++-------= ---- .../net/ethernet/microchip/lan966x/lan966x_main.h | 11 +++++++++++ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index b8344fd5e5ad..1311b79bd11f 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -109,8 +109,8 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan96= 6x_rx *rx) return 0; } =20 -static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, - u8 channel_id) +void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) { lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); @@ -140,7 +140,7 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) return 0; } =20 -static void lan966x_fdma_rx_start(struct lan966x_rx *rx) +void lan966x_fdma_rx_start(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -171,7 +171,7 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *rx) lan966x, FDMA_CH_ACTIVATE); } =20 -static void lan966x_fdma_rx_disable(struct lan966x_rx *rx) +void lan966x_fdma_rx_disable(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -191,7 +191,7 @@ static void lan966x_fdma_rx_disable(struct lan966x_rx *= rx) lan966x, FDMA_CH_DB_DISCARD); } =20 -static void lan966x_fdma_rx_reload(struct lan966x_rx *rx) +void lan966x_fdma_rx_reload(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; =20 @@ -264,7 +264,7 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx = *tx) lan966x, FDMA_CH_ACTIVATE); } =20 -static void lan966x_fdma_tx_disable(struct lan966x_tx *tx) +void lan966x_fdma_tx_disable(struct lan966x_tx *tx) { struct lan966x *lan966x =3D tx->lan966x; struct fdma *fdma =3D &tx->fdma; @@ -296,7 +296,7 @@ static void lan966x_fdma_tx_reload(struct lan966x_tx *t= x) lan966x, FDMA_CH_RELOAD); } =20 -static void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x) +void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x) { struct lan966x_port *port; int i; @@ -470,7 +470,7 @@ static struct sk_buff *lan966x_fdma_rx_get_frame(struct= lan966x_rx *rx, return NULL; } =20 -static int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight) +int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight) { struct lan966x *lan966x =3D container_of(napi, struct lan966x, napi); struct lan966x_rx *rx =3D &lan966x->rx; @@ -583,7 +583,7 @@ static int lan966x_fdma_get_next_dcb(struct lan966x_tx = *tx) return -1; } =20 -static void lan966x_fdma_tx_start(struct lan966x_tx *tx) +void lan966x_fdma_tx_start(struct lan966x_tx *tx) { struct lan966x *lan966x =3D tx->lan966x; =20 @@ -801,7 +801,7 @@ static int lan966x_fdma_get_max_mtu(struct lan966x *lan= 966x) return max_mtu; } =20 -static int lan966x_qsys_sw_status(struct lan966x *lan966x) +int lan966x_qsys_sw_status(struct lan966x *lan966x) { return lan_rd(lan966x, QSYS_SW_STATUS(CPU_PORT)); } @@ -883,7 +883,7 @@ static int lan966x_fdma_reload(struct lan966x *lan966x,= int new_mtu) return err; } =20 -static int lan966x_fdma_get_max_frame(struct lan966x *lan966x) +int lan966x_fdma_get_max_frame(struct lan966x *lan966x) { return lan966x_fdma_get_max_mtu(lan966x) + IFH_LEN_BYTES + diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index eea286c29474..83c361abb789 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -561,6 +561,17 @@ int lan966x_fdma_init(struct lan966x *lan966x); void lan966x_fdma_deinit(struct lan966x *lan966x); irqreturn_t lan966x_fdma_irq_handler(int irq, void *args); int lan966x_fdma_reload_page_pool(struct lan966x *lan966x); +int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight); +void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id); +void lan966x_fdma_rx_start(struct lan966x_rx *rx); +void lan966x_fdma_rx_disable(struct lan966x_rx *rx); +void lan966x_fdma_rx_reload(struct lan966x_rx *rx); +void lan966x_fdma_tx_start(struct lan966x_tx *tx); +void lan966x_fdma_tx_disable(struct lan966x_tx *tx); +void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x); +int lan966x_fdma_get_max_frame(struct lan966x *lan966x); +int lan966x_qsys_sw_status(struct lan966x *lan966x); =20 int lan966x_lag_port_join(struct lan966x_port *port, struct net_device *brport_dev, --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EE4C5650E1; Wed, 9 Sep 2026 13:00:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958850; cv=none; b=LYfPUgrKRLJzcLaOYoaz5aQAM8v6MPHm9ySAUFW8qhuLBItVg5h7/C/T9Jgae95XBvzT/NuAdxhrNH4ZaVFFnTGyX/yaICPfXySokkmxrUBif0B7YmF9dNM0DlqZIkFXlh4FtJh9UZ8Mm19voSJj1D/bJ3ql5JjZRDiieVhHroM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958850; c=relaxed/simple; bh=zBov56ra9TQQ0Btxz615KJ63MNaEZMJU8uYgTEPF1Xs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=SCs1oY6VVAUWeJH2Alsv8N35SKI5xJX+LTqtOXjgODyhWFJF69NM9Lb2HV7OMQe3+ND6OQjAMWuoPqc2gjU2AxBDhzBsE6OQLKbaCjoWf2vMyfg34RMoDgpymRQtwvWyr/+KbxN6xgdGiPjJEWSkpb9ezhJEmBfCxvWIiyvSpu0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=wRK5zFa0; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="wRK5zFa0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958848; x=1820494848; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=zBov56ra9TQQ0Btxz615KJ63MNaEZMJU8uYgTEPF1Xs=; b=wRK5zFa0oAZoDqz68iTn5IQaR/BTKEd1jCtQyOUOiuQPksyT4WdQ6DAK hoN3JhcMckm7akNM/d/OF4cWIFott2u6trXcoNoQNlJmP1RbjIRgz8qW7 ERpCAvWbaX6ArRqeFT3WvSSJiPFe3ZYG0O/CM6XNH9ja+LMf0DhvV+8Ly xUgdIZKJ285AZJC2oSmdl0s7+ZFd/MhIVLonguebFbVowmeskTXWR5itz R7soORuGgDBNdjeopQNr/ONrAhLvgNaetKXXC4rO1q/Ok5jsnqF/Njcps N2K5Q35MTCKhlV7kSWdeF1eZgJlZOVsGu47AC2ltLCd8WmCY186Y32SxZ A==; X-CSE-ConnectionGUID: I/1DwU+2QTOlLSGotqcmmA== X-CSE-MsgGUID: pqqg6biRSSeOKYoaJ41BmQ== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="73307779" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:00:47 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:00:46 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:00:42 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:08 +0200 Subject: [PATCH net-next v6 06/14] net: lan966x: use a dedicated device for DMA operations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-6-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 In preparation for the PCIe FDMA implementation, add lan966x->dma_dev, resolved once at probe time, and use it for every DMA operation the FDMA path performs: coherent allocations, streaming mappings and the RX page pool. Natively, dma_dev is lan966x->dev, so there is no functional change. Since dma_dev differs from dev only on the PCIe path, add lan966x_is_pci() on top of it, for the later PCIe patches to key off. Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 30 +++++++++++-------= ---- .../net/ethernet/microchip/lan966x/lan966x_main.c | 16 ++++++++++++ .../net/ethernet/microchip/lan966x/lan966x_main.h | 10 ++++++++ 3 files changed, 41 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 1311b79bd11f..15fc59cb4ad7 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -80,7 +80,7 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan966x= _rx *rx) .flags =3D PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, .pool_size =3D rx->fdma.n_dcbs, .nid =3D NUMA_NO_NODE, - .dev =3D lan966x->dev, + .dev =3D lan966x->dma_dev, .dma_dir =3D DMA_FROM_DEVICE, .offset =3D XDP_PACKET_HEADROOM, .max_len =3D rx->max_mtu - @@ -126,7 +126,7 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) if (err) return err; =20 - err =3D fdma_alloc_coherent(lan966x->dev, fdma); + err =3D fdma_alloc_coherent(lan966x->dma_dev, fdma); if (err) { page_pool_destroy(rx->page_pool); return err; @@ -210,7 +210,7 @@ static int lan966x_fdma_tx_alloc(struct lan966x_tx *tx) if (!tx->dcbs_buf) return -ENOMEM; =20 - err =3D fdma_alloc_coherent(lan966x->dev, fdma); + err =3D fdma_alloc_coherent(lan966x->dma_dev, fdma); if (err) goto out; =20 @@ -230,7 +230,7 @@ static void lan966x_fdma_tx_free(struct lan966x_tx *tx) struct lan966x *lan966x =3D tx->lan966x; =20 kfree(tx->dcbs_buf); - fdma_free_coherent(lan966x->dev, &tx->fdma); + fdma_free_coherent(lan966x->dma_dev, &tx->fdma); } =20 static void lan966x_fdma_tx_activate(struct lan966x_tx *tx) @@ -355,7 +355,7 @@ static void lan966x_fdma_tx_clear_buf(struct lan966x *l= an966x, int weight) =20 dcb_buf->used =3D false; if (dcb_buf->use_skb) { - dma_unmap_single(lan966x->dev, + dma_unmap_single(lan966x->dma_dev, dcb_buf->dma_addr, dcb_buf->len, DMA_TO_DEVICE); @@ -364,7 +364,7 @@ static void lan966x_fdma_tx_clear_buf(struct lan966x *l= an966x, int weight) napi_consume_skb(dcb_buf->data.skb, weight); } else { if (dcb_buf->xdp_ndo) - dma_unmap_single(lan966x->dev, + dma_unmap_single(lan966x->dma_dev, dcb_buf->dma_addr, dcb_buf->len, DMA_TO_DEVICE); @@ -400,7 +400,7 @@ static int lan966x_fdma_rx_check_frame(struct lan966x_r= x *rx, u64 *src_port) if (unlikely(!page)) return FDMA_ERROR; =20 - dma_sync_single_for_cpu(lan966x->dev, + dma_sync_single_for_cpu(lan966x->dma_dev, (dma_addr_t)db->dataptr + XDP_PACKET_HEADROOM, FDMA_DCB_STATUS_BLOCKL(db->status), DMA_FROM_DEVICE); @@ -635,11 +635,11 @@ int lan966x_fdma_xmit_xdpf(struct lan966x_port *port,= void *ptr, u32 len) lan966x_ifh_set_bypass(ifh, 1); lan966x_ifh_set_port(ifh, BIT_ULL(port->chip_port)); =20 - dma_addr =3D dma_map_single(lan966x->dev, + dma_addr =3D dma_map_single(lan966x->dma_dev, xdpf->data - IFH_LEN_BYTES, xdpf->len + IFH_LEN_BYTES, DMA_TO_DEVICE); - if (dma_mapping_error(lan966x->dev, dma_addr)) { + if (dma_mapping_error(lan966x->dma_dev, dma_addr)) { ret =3D NETDEV_TX_OK; goto out; } @@ -655,7 +655,7 @@ int lan966x_fdma_xmit_xdpf(struct lan966x_port *port, v= oid *ptr, u32 len) lan966x_ifh_set_port(ifh, BIT_ULL(port->chip_port)); =20 dma_addr =3D page_pool_get_dma_addr(page); - dma_sync_single_for_device(lan966x->dev, + dma_sync_single_for_device(lan966x->dma_dev, dma_addr + XDP_PACKET_HEADROOM, len + IFH_LEN_BYTES, DMA_TO_DEVICE); @@ -734,9 +734,9 @@ int lan966x_fdma_xmit(struct sk_buff *skb, __be32 *ifh,= struct net_device *dev) memcpy(skb->data, ifh, IFH_LEN_BYTES); skb_put(skb, 4); =20 - dma_addr =3D dma_map_single(lan966x->dev, skb->data, skb->len, + dma_addr =3D dma_map_single(lan966x->dma_dev, skb->data, skb->len, DMA_TO_DEVICE); - if (dma_mapping_error(lan966x->dev, dma_addr)) { + if (dma_mapping_error(lan966x->dma_dev, dma_addr)) { dev->stats.tx_dropped++; err =3D NETDEV_TX_OK; goto release; @@ -842,7 +842,7 @@ static int lan966x_fdma_reload(struct lan966x *lan966x,= int new_mtu) page_pool_put_full_page(page_pool, old_pages[i][j], false); =20 - fdma_free_coherent(lan966x->dev, &fdma_rx_old); + fdma_free_coherent(lan966x->dma_dev, &fdma_rx_old); =20 page_pool_destroy(page_pool); =20 @@ -992,7 +992,7 @@ int lan966x_fdma_init(struct lan966x *lan966x) =20 err =3D lan966x_fdma_tx_alloc(&lan966x->tx); if (err) { - fdma_free_coherent(lan966x->dev, &lan966x->rx.fdma); + fdma_free_coherent(lan966x->dma_dev, &lan966x->rx.fdma); page_pool_destroy(lan966x->rx.page_pool); return err; } @@ -1014,7 +1014,7 @@ void lan966x_fdma_deinit(struct lan966x *lan966x) napi_disable(&lan966x->napi); =20 lan966x_fdma_rx_free_pages(&lan966x->rx); - fdma_free_coherent(lan966x->dev, &lan966x->rx.fdma); + fdma_free_coherent(lan966x->dma_dev, &lan966x->rx.fdma); page_pool_destroy(lan966x->rx.page_pool); lan966x_fdma_tx_free(&lan966x->tx); } diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 1179a6e127c5..2741f7c9fa4c 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1081,6 +1082,20 @@ static int lan966x_reset_switch(struct lan966x *lan9= 66x) return 0; } =20 +/* When enumerated over PCIe, dev is a platform device with no + * iommus/dma-ranges of its own, so DMA must target the PCIe endpoint inst= ead. + * The result differs from dev only in that case; lan966x_is_pci() relies = on it. + */ +static struct device *lan966x_get_dma_dev(struct device *dev) +{ + for (struct device *p =3D dev->parent; p; p =3D p->parent) { + if (dev_is_pci(p)) + return p; + } + + return dev; +} + static int lan966x_probe(struct platform_device *pdev) { struct fwnode_handle *ports, *portnp; @@ -1094,6 +1109,7 @@ static int lan966x_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, lan966x); lan966x->dev =3D &pdev->dev; + lan966x->dma_dev =3D lan966x_get_dma_dev(lan966x->dev); =20 if (!device_get_mac_address(&pdev->dev, mac_addr)) { ether_addr_copy(lan966x->base_mac, mac_addr); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index 83c361abb789..3f09f8ddf620 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -270,6 +270,9 @@ struct lan966x_skb_cb { struct lan966x { struct device *dev; =20 + /* Device used for DMA; the PCIe endpoint when enumerated over PCIe. */ + struct device *dma_dev; + u8 num_phys_ports; struct lan966x_port **ports; =20 @@ -573,6 +576,13 @@ void lan966x_fdma_wakeup_netdev(struct lan966x *lan966= x); int lan966x_fdma_get_max_frame(struct lan966x *lan966x); int lan966x_qsys_sw_status(struct lan966x *lan966x); =20 +/* dma_dev differs from dev only on the PCIe path. */ +static inline bool lan966x_is_pci(struct lan966x *lan966x) +{ + return IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) && + lan966x->dma_dev !=3D lan966x->dev; +} + int lan966x_lag_port_join(struct lan966x_port *port, struct net_device *brport_dev, struct net_device *bond, --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B3945592E7; Wed, 9 Sep 2026 13:00:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958854; cv=none; b=RdU4igtNlvGmQntood8F11LXuPi3o8YAPB4AdIBMnb/mxHjX4xMafHHJWOgOugeVmpQulMeX6b+UNN3ZkJPrynlBoBEaZTJe11up46nhkA7ZM3wa8wfQC0YAIGmowiHhZnBB4LerLz9lGzLjQjSyvSlZ/dudDS85pkTx4q83JAA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958854; c=relaxed/simple; bh=4zQqj5itNYOGWNPkAW/1oif6pIwVusHfQCh/CqcaFw0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=maqUh9u1b+tv4Gp3UrIWhNWvPpLfxWtsjjXrqxc5lOS6tNWVlkJTbdRRNBR0RUTbBOUD/wkv+0QR0cRQW2q3BuLmlugBdtmzK/a2Aholna3aY4oUkN1NAdifQ/QiGMa2Rt/J/I3rzE+A7FUuuWWjMnqhzZWcVldfB9jyEo6fCe8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=eMpC0GIO; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="eMpC0GIO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958852; x=1820494852; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=4zQqj5itNYOGWNPkAW/1oif6pIwVusHfQCh/CqcaFw0=; b=eMpC0GIOAHd2EpWt7KaseBkCkYMFA6g4WmfzTJ3L046gSjjaILYBW/fe Z1MN0AJwJLMFXNNk8izGugSNHFK/JkuKsokBEKgnp0Un9as2DKHbmh8wt BHgP3+iNbQ62HEbU5QZniCH+rLRL7YS5FrUdAxGo5fnYuVx/GHH2akiRq m5HNBIEwxapSo0LAyk/o7WJKYXBOzx+n08yvhnbWIPMogR01GklJujIuH y1ILiRczbnDtZRpAZk3UZVBwx2+p+NhMR6vyqTTt68YqlIAtSnAskxqzn gJZenjDn9yzTnyw9KJIP+8zTiskEgUJvbEG7iQKdazESf8OVVH0OGUST5 A==; X-CSE-ConnectionGUID: iYGeOhmHQL2cPXQA5KfGlg== X-CSE-MsgGUID: jPrkB7qUQsGqkhw/ZCKNKQ== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="63358653" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:00:51 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:00:50 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:00:47 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:09 +0200 Subject: [PATCH net-next v6 07/14] net: lan966x: add FDMA ops dispatch for PCIe support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-7-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Introduce lan966x_fdma_ops to support different FDMA implementations for platform and PCIe. Plumb fdma_init, fdma_deinit, fdma_xmit, fdma_poll and fdma_resize through the ops table, and select the implementation at probe time. Only the platform implementation exists at this point; the PCIe implementation is added in a later patch. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 2 +- .../net/ethernet/microchip/lan966x/lan966x_main.c | 20 +++++++++++++++-= ---- .../net/ethernet/microchip/lan966x/lan966x_main.h | 13 +++++++++++++ 3 files changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 15fc59cb4ad7..2695bc41e52a 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -947,7 +947,7 @@ void lan966x_fdma_netdev_init(struct lan966x *lan966x, = struct net_device *dev) return; =20 lan966x->fdma_ndev =3D dev; - netif_napi_add(dev, &lan966x->napi, lan966x_fdma_napi_poll); + netif_napi_add(dev, &lan966x->napi, lan966x->ops->fdma_poll); napi_enable(&lan966x->napi); } =20 diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 2741f7c9fa4c..6e6c08bb8eea 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -27,6 +27,14 @@ =20 #define IO_RANGES 2 =20 +static const struct lan966x_fdma_ops lan966x_fdma_ops =3D { + .fdma_init =3D &lan966x_fdma_init, + .fdma_deinit =3D &lan966x_fdma_deinit, + .fdma_xmit =3D &lan966x_fdma_xmit, + .fdma_poll =3D &lan966x_fdma_napi_poll, + .fdma_resize =3D &lan966x_fdma_change_mtu, +}; + static const struct of_device_id lan966x_match[] =3D { { .compatible =3D "microchip,lan966x-switch" }, { } @@ -392,7 +400,7 @@ static netdev_tx_t lan966x_port_xmit(struct sk_buff *sk= b, =20 spin_lock(&lan966x->tx_lock); if (port->lan966x->fdma) - err =3D lan966x_fdma_xmit(skb, ifh, dev); + err =3D lan966x->ops->fdma_xmit(skb, ifh, dev); else err =3D lan966x_port_ifh_xmit(skb, ifh, dev); spin_unlock(&lan966x->tx_lock); @@ -414,7 +422,7 @@ static int lan966x_port_change_mtu(struct net_device *d= ev, int new_mtu) if (!lan966x->fdma) return 0; =20 - err =3D lan966x_fdma_change_mtu(lan966x); + err =3D lan966x->ops->fdma_resize(lan966x); if (err) { lan_wr(DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(LAN966X_HW_MTU(old_mtu)), lan966x, DEV_MAC_MAXLEN_CFG(port->chip_port)); @@ -1111,6 +1119,8 @@ static int lan966x_probe(struct platform_device *pdev) lan966x->dev =3D &pdev->dev; lan966x->dma_dev =3D lan966x_get_dma_dev(lan966x->dev); =20 + lan966x->ops =3D &lan966x_fdma_ops; + if (!device_get_mac_address(&pdev->dev, mac_addr)) { ether_addr_copy(lan966x->base_mac, mac_addr); } else { @@ -1250,7 +1260,7 @@ static int lan966x_probe(struct platform_device *pdev) if (err) goto cleanup_fdb; =20 - err =3D lan966x_fdma_init(lan966x); + err =3D lan966x->ops->fdma_init(lan966x); if (err) goto cleanup_ptp; =20 @@ -1263,7 +1273,7 @@ static int lan966x_probe(struct platform_device *pdev) return 0; =20 cleanup_fdma: - lan966x_fdma_deinit(lan966x); + lan966x->ops->fdma_deinit(lan966x); =20 cleanup_ptp: lan966x_ptp_deinit(lan966x); @@ -1291,7 +1301,7 @@ static void lan966x_remove(struct platform_device *pd= ev) =20 lan966x_taprio_deinit(lan966x); lan966x_vcap_deinit(lan966x); - lan966x_fdma_deinit(lan966x); + lan966x->ops->fdma_deinit(lan966x); lan966x_cleanup_ports(lan966x); =20 cancel_delayed_work_sync(&lan966x->stats_work); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index 3f09f8ddf620..aab5e53ed059 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -193,6 +193,17 @@ enum vcap_is1_port_sel_rt { VCAP_IS1_PS_RT_FOLLOW_OTHER =3D 7, }; =20 +struct lan966x; + +struct lan966x_fdma_ops { + int (*fdma_init)(struct lan966x *lan966x); + void (*fdma_deinit)(struct lan966x *lan966x); + int (*fdma_xmit)(struct sk_buff *skb, __be32 *ifh, + struct net_device *dev); + int (*fdma_poll)(struct napi_struct *napi, int weight); + int (*fdma_resize)(struct lan966x *lan966x); +}; + struct lan966x_port; =20 struct lan966x_rx { @@ -273,6 +284,8 @@ struct lan966x { /* Device used for DMA; the PCIe endpoint when enumerated over PCIe. */ struct device *dma_dev; =20 + const struct lan966x_fdma_ops *ops; + u8 num_phys_ports; struct lan966x_port **ports; =20 --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84D5A56511C; Wed, 9 Sep 2026 13:00:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958858; cv=none; b=M7MlA4AfFDBId4xSBgVKgZGRo0wgim0utSe48QZlhvNxi4+gjTL4NP9HVZant4F75kfdzFUkmXXMFGJWAyOc22wOdexlE12s8l5tY93sWE3Mqf4+yn816ZL5vVFJW376bIaT/NzfPfPGIuXJeH4ugSN0S5wqdSHiRCvwXT0uEoQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958858; c=relaxed/simple; bh=rVpMMDlK7E+NlpQ9MahYaWBp6KhJAh4OQm2tWvl9qOI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=J7U8uHzW2UULnRySNhUirRMvHKChdIxp4R8zAJldECcJiklZpjuwW/ek2/xWkXOj0TUPN8WK9GtRAvn+ALexkKyhQZ2DAF4gEQ0g3OGSJ+xcoTDN9d+hGD9WS6xje+DR0Z9QDIUnEoVjZEMWc17R4ixA2KzJ1VUnZyPL0/gpPmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=2FkZwUvF; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="2FkZwUvF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958861; x=1820494861; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=rVpMMDlK7E+NlpQ9MahYaWBp6KhJAh4OQm2tWvl9qOI=; b=2FkZwUvFokaV/y4QWc7Evpa8JdChZppvjZ264DV9iCf4qLi8SQY0O7ur ML6zAq0lGbK/RPuY7zhditc0DuEbrWk4ZNv4rSL/rjgB7OZfgGvNdvwJR O0VtjTJqqtzUuSrFbpm3Wf7MJbjGp0w82lIdMDrJonDPL7l+Dk+x+7JN8 Izkgj5eGaRK5u/Gl3wc1NHH7EsEtBcoRmYt5UkF0nOTmksZpJK9KJHYf8 f0HTwo2Q9VBHa5DDV6V8gEQjA7a1sfcdfyuRZ9WTaj0YHrofDx/TexeGg Zi6Y6hSjDbNmAg+TJzE293ydss3gRVcU5TDffsF6gF+Qo4OsOKfWgrbT6 w==; X-CSE-ConnectionGUID: wSoHObMlRVyHWvIVKL+mDQ== X-CSE-MsgGUID: OvS619mMSi+yHy3DRCpW4w== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="63658691" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Sep 2026 06:01:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 9 Sep 2026 06:00:55 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:00:51 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:10 +0200 Subject: [PATCH net-next v6 08/14] net: lan966x: clear FDMA interrupt stickies after switch reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-8-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 When in PCI mode, the GCB soft reset issued by the reset controller can latch spurious bits in the FDMA error stickies. The latched bits sit in FDMA_INTR_ERR until the FDMA IRQ is requested later in probe, at which point the handler fires immediately and WARNs. Clear FDMA_ERRORS, FDMA_INTR_ERR and FDMA_INTR_DB right after the switch reset so the FDMA comes out clean and the IRQ handler does not see ghost errors on probe. The clear runs on both the PCI and platform paths. On the platform path it has no effect =E2=80=94 there are no spurious stickies to clear =E2= =80=94 but keeping it unconditional avoids a PCI-specific code path here. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan966x/lan966x_main.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 6e6c08bb8eea..11094a381ec2 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -1067,6 +1067,15 @@ static int lan966x_reset_switch(struct lan966x *lan9= 66x) =20 reset_control_reset(switch_reset); =20 + /* When in PCI mode, the GCB soft reset issued by the reset + * controller can latch spurious bits in the FDMA error stickies. + * Clear them before request_irq hooks up the FDMA IRQ line, + * otherwise the handler fires immediately on probe. + */ + lan_wr(lan_rd(lan966x, FDMA_ERRORS), lan966x, FDMA_ERRORS); + lan_wr(lan_rd(lan966x, FDMA_INTR_ERR), lan966x, FDMA_INTR_ERR); + lan_wr(lan_rd(lan966x, FDMA_INTR_DB), lan966x, FDMA_INTR_DB); + /* Don't reinitialize the switch core, if it is already initialized. In * case it is initialized twice, some pointers inside the queue system * in HW will get corrupted and then after a while the queue system gets --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2113566C78; Wed, 9 Sep 2026 13:01:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958862; cv=none; b=ARkrCncKjB3gRXVBFZQHTsura7TJYQqxmId6anmPY9oC2Awo2npMRhN5Xt7pQSy4lVUqOcBKNDlVSb8NLSVDZCnga/pykH5l2/JsSZwkzVHri2MjRd9r1Cbp7Xw1jFiN6BBkOvVqZiD+Kqj6SLXvbTrzmTyFT7B7O3hNEuRba1s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958862; c=relaxed/simple; bh=//1Sej3ygsAUOeV8Xbw9m53S52nHYA3SXR8Urfm05bw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=iotObJt4TtJKJUQZyZSx/DyZlSk/Nepf8HSUf6GDjzYdDBlZSLVbaHaNUWgOcxm1aITq+2KezgWKhcUOEwDtx2++K8mtGxpqzunTPYWFHbMNz1I9pBOmdHQ3flbGaiqvwaHa+wFa0pb1iWWTTdaoSGDQnxNAXBkRxJlFZwYGBb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Vo/gdgSb; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Vo/gdgSb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958861; x=1820494861; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=//1Sej3ygsAUOeV8Xbw9m53S52nHYA3SXR8Urfm05bw=; b=Vo/gdgSbsWzeFrPfmsq7L8QyhoiKN77V8WWR56PQkYd/sATFWyYOgPNh IPvDfQuM4FkKVPZdvM8cPzDyLtnqOYZHbQfBBY2vLVgQd9ESrqoCx7c/U HEh6ltop7mBbgV3FKjiPWiDr2+ktyb/800XiVYF/aMwhClb0AOvOkhj22 v6DgoogRrUYjtEGDaTEXicpMetQmnrQNuej/qKBu4g+ZVWQ396TWY9A8r rxPJFCrQZQDgxGuAbT8fWpJHaoRT1t+0vThAYocdrpn2S6z4zDyzxX+C2 SS8r9TDokZGND3BM2wpWbxDnGJwT1gfqjTnXKrMrQZR9nARX3qVn1AOUn A==; X-CSE-ConnectionGUID: 7eRe6HgDTF2R+8/Z6zeXFg== X-CSE-MsgGUID: 7LG8u9CqT2SlIST+25QDLA== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="294759147" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:01:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:00:59 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:00:55 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:11 +0200 Subject: [PATCH net-next v6 09/14] net: lan966x: add shutdown callback to stop FDMA on reboot Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-9-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 When lan966x is used as a PCIe endpoint, the FDMA engine runs on the card and survives a host reboot. Without a shutdown callback, channels stay active and interrupt sources stay armed across the reset, causing the shared PCIe INTx to assert before the driver has re-probed. Add a shutdown callback, shared by the platform and PCI paths, that disables NAPI and stops the netdev TX queues, then disables the RX and TX channels, and finally masks the interrupt sources that share the PCIe INTx: FDMA (FDMA_INTR_ENA and FDMA_INTR_DB_ENA) and the analyzer (ANA_ANAINTR), which lan966x_init() arms unconditionally. Masking is only required on this path: on reboot the kernel calls device_shutdown(), so shutdown() is the only callback that runs. On unbind, fdma_deinit() disables both channels and waits for them to go idle before lan966x_cleanup_ports() releases the FDMA interrupt handler, so the engine cannot assert the shared line once the handler is gone. FDMA_INTR_ENA persists on the card across a warm reboot, so also restore the full enable in lan966x_fdma_rx_start() to re-arm interrupts after a previous shutdown(). rx_start() runs after both the RX and TX rings are allocated, so the same single-site re-arm works for both the platform and PCIe backends. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 19 ++++++++++++++++ .../net/ethernet/microchip/lan966x/lan966x_main.c | 26 ++++++++++++++++++= ++++ .../net/ethernet/microchip/lan966x/lan966x_main.h | 1 + .../net/ethernet/microchip/lan966x/lan966x_regs.h | 15 +++++++++++++ 4 files changed, 61 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 2695bc41e52a..5793a83268fc 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -146,6 +146,10 @@ void lan966x_fdma_rx_start(struct lan966x_rx *rx) struct fdma *fdma =3D &rx->fdma; u32 mask; =20 + lan_wr(FDMA_INTR_ENA_INTR_PORT_ENA_SET(GENMASK(1, 0)) | + FDMA_INTR_ENA_INTR_CH_ENA_SET(GENMASK(7, 0)), + lan966x, FDMA_INTR_ENA); + lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -325,6 +329,21 @@ static void lan966x_fdma_stop_netdev(struct lan966x *l= an966x) } } =20 +/* Drain in-flight xmit callers and stop all TX queues on every port. */ +void lan966x_fdma_tx_disable_netdev(struct lan966x *lan966x) +{ + struct lan966x_port *port; + int i; + + for (i =3D 0; i < lan966x->num_phys_ports; ++i) { + port =3D lan966x->ports[i]; + if (!port) + continue; + + netif_tx_disable(port->dev); + } +} + static void lan966x_fdma_tx_clear_buf(struct lan966x *lan966x, int weight) { struct lan966x_tx *tx =3D &lan966x->tx; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 11094a381ec2..d6ce1e3e373f 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -1324,9 +1324,35 @@ static void lan966x_remove(struct platform_device *p= dev) debugfs_remove_recursive(lan966x->debugfs_root); } =20 +static void lan966x_shutdown(struct platform_device *pdev) +{ + struct lan966x *lan966x =3D platform_get_drvdata(pdev); + + if (!lan966x->fdma) + return; + + /* The reload paths disable this NAPI under rtnl; serialize with them. */ + rtnl_lock(); + + if (lan966x->fdma_ndev) + napi_disable(&lan966x->napi); + + lan966x_fdma_tx_disable_netdev(lan966x); + + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + + lan_wr(0, lan966x, FDMA_INTR_ENA); + lan_wr(0, lan966x, FDMA_INTR_DB_ENA); + lan_wr(0, lan966x, ANA_ANAINTR); + + rtnl_unlock(); +} + static struct platform_driver lan966x_driver =3D { .probe =3D lan966x_probe, .remove =3D lan966x_remove, + .shutdown =3D lan966x_shutdown, .driver =3D { .name =3D "lan966x-switch", .of_match_table =3D lan966x_match, diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index aab5e53ed059..b7e3ce4f0355 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -586,6 +586,7 @@ void lan966x_fdma_rx_reload(struct lan966x_rx *rx); void lan966x_fdma_tx_start(struct lan966x_tx *tx); void lan966x_fdma_tx_disable(struct lan966x_tx *tx); void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x); +void lan966x_fdma_tx_disable_netdev(struct lan966x *lan966x); int lan966x_fdma_get_max_frame(struct lan966x *lan966x); int lan966x_qsys_sw_status(struct lan966x *lan966x); =20 diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_regs.h index 4b553927d2e0..aba0d36ae6b5 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h @@ -1039,6 +1039,21 @@ enum lan966x_target { /* FDMA:FDMA:FDMA_INTR_ERR */ #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 00, 0, 1, 4) =20 +/* FDMA:FDMA:FDMA_INTR_ENA */ +#define FDMA_INTR_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 04, 0, 1, 4) + +#define FDMA_INTR_ENA_INTR_PORT_ENA GENMASK(9, 8) +#define FDMA_INTR_ENA_INTR_PORT_ENA_SET(x)\ + FIELD_PREP(FDMA_INTR_ENA_INTR_PORT_ENA, x) +#define FDMA_INTR_ENA_INTR_PORT_ENA_GET(x)\ + FIELD_GET(FDMA_INTR_ENA_INTR_PORT_ENA, x) + +#define FDMA_INTR_ENA_INTR_CH_ENA GENMASK(7, 0) +#define FDMA_INTR_ENA_INTR_CH_ENA_SET(x)\ + FIELD_PREP(FDMA_INTR_ENA_INTR_CH_ENA, x) +#define FDMA_INTR_ENA_INTR_CH_ENA_GET(x)\ + FIELD_GET(FDMA_INTR_ENA_INTR_CH_ENA, x) + /* FDMA:FDMA:FDMA_ERRORS */ #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 12, 0, 1, 4) =20 --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF950566C7A; Wed, 9 Sep 2026 13:01:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958867; cv=none; b=pMRGMQ2tDW2RQUNvrEWZblN8a/mP2Zn0g0sCnTPHp4E/ZQlrcBNuPz/BXjpqXNqBiBz6iMRciTxhVK0tqSzGO7GsmWGndM2hTcV+13S1oShaZJkQK63OMYWHz2nHagET8er1wP7CyH0aY2j2tpL/OT7dtzICI72hKerQoj4AriQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958867; c=relaxed/simple; bh=b7nkWWg9H4K4PT6b6lRMFPDXbmtAk4BBT2qgpFb9Eqc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=kKqrLYS1aqysxYjzcG8t4tEXRvQFYI6mb4yUH+oLrC1NRZXR184CGi0P6efrkiIt3C74Oy4wH2n6iJOBuLz3FRp0S4tyJ3TcLh+IhGaQIYmj5TT67sp8lyOKHURjEQuDR3aHh9l1JYX+YUDsV67oqBm6DH6o7IdvZqMujR+KGL4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=MBSXKy/9; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="MBSXKy/9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958864; x=1820494864; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=b7nkWWg9H4K4PT6b6lRMFPDXbmtAk4BBT2qgpFb9Eqc=; b=MBSXKy/9hriaFO3Ws8XUoswauk/RU1PufKXv+vMsU5T6j8uzhGFITPHE K6VygI16EQrtOq6XbtEjbe3u5RI2rXwG8s7a9Q3z0uZBhEXYJ9evpsTlp 5W71V8r43k2bYw8BBDNNDMoVMONjTnQNNe/ivxIXmaWswi6AMGGhht8Dl ueaESRN13jaF/9u5/MaEVqLvJ4PNB3yYk1rl0rFQP1p6+/lhA1IFqqsLt YPlOOjJlTa9QENWJMAGoqUY1xkuC5eD6ibioVwr6zzq14056itIYMNpPq +JyEgjhMLM41jDSO4NCQA+8yz1wgayxEbzm/v/+Zcg/AWD6tnHuMHZw2R A==; X-CSE-ConnectionGUID: BiZMwvF+QV6EJjQHYW0fxg== X-CSE-MsgGUID: GbEP4hSZSAWx62Hun73A/A== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="73307806" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Sep 2026 06:01:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 9 Sep 2026 06:01:03 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:00:59 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:12 +0200 Subject: [PATCH net-next v6 10/14] net: lan966x: add PCIe FDMA support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-10-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Add PCIe FDMA support for lan966x. The PCIe FDMA path uses contiguous DMA buffers mapped through the endpoint's ATU, with memcpy-based frame transfer instead of per-page DMA mappings. With PCIe FDMA, throughput increases from ~33 Mbps (register-based I/O) to ~620 Mbps on an Intel x86 host with a lan966x PCIe card. XDP is not supported on this path yet, so do not advertise xdp_features and reject program attach for PCIe instances. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan966x/Makefile | 4 + .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 404 +++++++++++++++++= ++++ .../net/ethernet/microchip/lan966x/lan966x_main.c | 11 +- .../net/ethernet/microchip/lan966x/lan966x_main.h | 7 + .../net/ethernet/microchip/lan966x/lan966x_regs.h | 10 + .../net/ethernet/microchip/lan966x/lan966x_xdp.c | 6 + 6 files changed, 439 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/Makefile b/drivers/net/= ethernet/microchip/lan966x/Makefile index 4cdbe263502c..02db4d4d9826 100644 --- a/drivers/net/ethernet/microchip/lan966x/Makefile +++ b/drivers/net/ethernet/microchip/lan966x/Makefile @@ -18,6 +18,10 @@ lan966x-switch-objs :=3D lan966x_main.o lan966x_phylink= .o lan966x_port.o \ lan966x-switch-$(CONFIG_LAN966X_DCB) +=3D lan966x_dcb.o lan966x-switch-$(CONFIG_DEBUG_FS) +=3D lan966x_vcap_debugfs.o =20 +ifneq ($(CONFIG_MCHP_LAN966X_PCI),) +lan966x-switch-y +=3D lan966x_fdma_pci.o +endif + # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/vcap ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/fdma diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c new file mode 100644 index 000000000000..f1f3c789d3a6 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "fdma_api.h" +#include "lan966x_main.h" + +static int lan966x_fdma_pci_dataptr_cb(struct fdma *fdma, int dcb, int db, + u64 *dataptr) +{ + u64 addr; + + addr =3D fdma_dataptr_dma_addr_contiguous(fdma, dcb, db); + + *dataptr =3D fdma_pci_atu_translate_addr(fdma->atu_region, addr); + + return 0; +} + +static int lan966x_fdma_pci_nextptr_cb(struct fdma *fdma, int dcb, u64 *ne= xtptr) +{ + u64 addr; + + fdma_nextptr_cb(fdma, dcb, &addr); + + *nextptr =3D fdma_pci_atu_translate_addr(fdma->atu_region, addr); + + return 0; +} + +static int lan966x_fdma_pci_rx_alloc(struct lan966x_rx *rx) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + int err; + + err =3D fdma_alloc_coherent_and_map(lan966x->dma_dev, fdma, + &lan966x->atu); + if (err) + return err; + + err =3D fdma_dcbs_init(fdma, + FDMA_DCB_INFO_DATAL(fdma->db_size - XDP_PACKET_HEADROOM), + FDMA_DCB_STATUS_INTR); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dma_dev, fdma); + return err; + } + + lan966x_fdma_llp_configure(lan966x, + fdma->atu_region->base_addr, + fdma->channel_id); + + return 0; +} + +static int lan966x_fdma_pci_tx_alloc(struct lan966x_tx *tx) +{ + struct lan966x *lan966x =3D tx->lan966x; + struct fdma *fdma =3D &tx->fdma; + int err; + + err =3D fdma_alloc_coherent_and_map(lan966x->dma_dev, fdma, + &lan966x->atu); + if (err) + return err; + + err =3D fdma_dcbs_init(fdma, + FDMA_DCB_INFO_DATAL(fdma->db_size), + FDMA_DCB_STATUS_DONE); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dma_dev, fdma); + return err; + } + + lan966x_fdma_llp_configure(lan966x, + fdma->atu_region->base_addr, + fdma->channel_id); + + return 0; +} + +static int lan966x_fdma_pci_get_next_dcb(struct fdma *fdma) +{ + struct fdma_db *db; + + for (int i =3D 0; i < fdma->n_dcbs; i++) { + db =3D fdma_db_get(fdma, i, 0); + + if (!fdma_db_is_done(db)) + continue; + if (fdma_is_last(fdma, &fdma->dcbs[i])) + continue; + + return i; + } + + return -ENOSPC; +} + +/* TX slot layout (sizes in bytes): + * + * +---------------------+-----+---------+-----+ + * | XDP_PACKET_HEADROOM | IFH | payload | FCS | + * | 256 | 28 | len | 4 | + * +---------------------+-----+---------+-----+ + * |<---------------- db_size ----------------->| + * + * Return true if the frame plus required overhead fits. + */ +static bool lan966x_fdma_pci_tx_size_fits(struct fdma *fdma, u32 len) +{ + return XDP_PACKET_HEADROOM + IFH_LEN_BYTES + len + ETH_FCS_LEN <=3D + fdma->db_size; +} + +/* Return true if blockl is a valid RX frame size. */ +static bool lan966x_fdma_pci_rx_size_fits(struct fdma *fdma, u32 blockl) +{ + return blockl >=3D IFH_LEN_BYTES + ETH_HLEN + ETH_FCS_LEN && + blockl <=3D fdma->db_size - XDP_PACKET_HEADROOM; +} + +static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + struct lan966x_port *port; + struct fdma_db *db; + void *virt_addr; + u32 blockl; + + /* virt_addr points to the IFH. */ + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, + fdma->dcb_index, + fdma->db_index); + + lan966x_ifh_get_src_port(virt_addr, src_port); + + if (*src_port >=3D lan966x->num_phys_ports) + return FDMA_ERROR; + + port =3D lan966x->ports[*src_port]; + if (!port) + return FDMA_ERROR; + + db =3D fdma_db_next_get(fdma); + + /* BLOCKL is a 16-bit HW-populated field; reject obviously-bad + * values before they feed memcpy/XDP sizes. + */ + blockl =3D FDMA_DCB_STATUS_BLOCKL(db->status); + if (!lan966x_fdma_pci_rx_size_fits(fdma, blockl)) + return FDMA_ERROR; + + return FDMA_PASS; +} + +static struct sk_buff *lan966x_fdma_pci_rx_get_frame(struct lan966x_rx *rx, + u64 src_port) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + struct sk_buff *skb; + struct fdma_db *db; + u32 data_len; + + /* Get the received frame and create an SKB for it. */ + db =3D fdma_db_next_get(fdma); + data_len =3D FDMA_DCB_STATUS_BLOCKL(db->status); + + skb =3D napi_alloc_skb(&lan966x->napi, data_len); + if (unlikely(!skb)) + return NULL; + + memcpy(skb->data, + fdma_dataptr_virt_addr_contiguous(fdma, + fdma->dcb_index, + fdma->db_index), + data_len); + + skb_put(skb, data_len); + + skb->dev =3D lan966x->ports[src_port]->dev; + skb_pull(skb, IFH_LEN_BYTES); + + skb_trim(skb, skb->len - ETH_FCS_LEN); + + skb->protocol =3D eth_type_trans(skb, skb->dev); + + if (lan966x->bridge_mask & BIT(src_port)) { + skb->offload_fwd_mark =3D 1; + + skb_reset_network_header(skb); + if (!lan966x_hw_offload(lan966x, src_port, skb)) + skb->offload_fwd_mark =3D 0; + } + + skb->dev->stats.rx_bytes +=3D skb->len; + skb->dev->stats.rx_packets++; + + return skb; +} + +static int lan966x_fdma_pci_xmit(struct sk_buff *skb, __be32 *ifh, + struct net_device *dev) +{ + struct lan966x_port *port =3D netdev_priv(dev); + struct lan966x *lan966x =3D port->lan966x; + struct lan966x_tx *tx =3D &lan966x->tx; + struct fdma *fdma =3D &tx->fdma; + int next_to_use; + void *virt_addr; + + next_to_use =3D lan966x_fdma_pci_get_next_dcb(fdma); + + if (next_to_use < 0) { + netif_stop_queue(dev); + return NETDEV_TX_BUSY; + } + + if (skb_put_padto(skb, ETH_ZLEN)) { + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + + if (!lan966x_fdma_pci_tx_size_fits(fdma, skb->len)) { + dev_kfree_skb_any(skb); + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + + skb_tx_timestamp(skb); + + /* virt_addr points to the IFH. */ + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, next_to_use, 0); + memcpy(virt_addr, ifh, IFH_LEN_BYTES); + memcpy(virt_addr + IFH_LEN_BYTES, skb->data, skb->len); + + /* Order frame write before DCB status write below. */ + dma_wmb(); + + fdma_dcb_add(fdma, + next_to_use, + 0, + FDMA_DCB_STATUS_INTR | + FDMA_DCB_STATUS_SOF | + FDMA_DCB_STATUS_EOF | + FDMA_DCB_STATUS_BLOCKO(0) | + FDMA_DCB_STATUS_BLOCKL(IFH_LEN_BYTES + skb->len + ETH_FCS_LEN)); + + /* Start the transmission. */ + lan966x_fdma_tx_start(tx); + + dev->stats.tx_bytes +=3D skb->len; + dev->stats.tx_packets++; + + /* Safe to free: PTP is not supported on the PCIe path yet, + * so lan966x->ptp is always 0 here. + */ + dev_consume_skb_any(skb); + + return NETDEV_TX_OK; +} + +static int lan966x_fdma_pci_napi_poll(struct napi_struct *napi, int weight) +{ + struct lan966x *lan966x =3D container_of(napi, struct lan966x, napi); + struct lan966x_rx *rx =3D &lan966x->rx; + struct fdma *fdma =3D &rx->fdma; + int dcb_reload, old_dcb; + struct sk_buff *skb; + int counter =3D 0; + u64 src_port; + + /* Wake any stopped TX queues if a TX DCB is available. */ + spin_lock(&lan966x->tx_lock); + if (lan966x_fdma_pci_get_next_dcb(&lan966x->tx.fdma) >=3D 0) + lan966x_fdma_wakeup_netdev(lan966x); + spin_unlock(&lan966x->tx_lock); + + dcb_reload =3D fdma->dcb_index; + + /* Get all received skbs. */ + while (counter < weight) { + if (!fdma_has_frames(fdma)) + break; + /* Order DONE read before DCB/frame reads below. */ + dma_rmb(); + counter++; + switch (lan966x_fdma_pci_rx_check_frame(rx, &src_port)) { + case FDMA_PASS: + break; + case FDMA_ERROR: + /* No rx_dropped increment here because src_port is + * invalid. + */ + fdma_dcb_advance(fdma); + continue; + } + skb =3D lan966x_fdma_pci_rx_get_frame(rx, src_port); + fdma_dcb_advance(fdma); + if (!skb) { + lan966x->ports[src_port]->dev->stats.rx_dropped++; + continue; + } + + napi_gro_receive(&lan966x->napi, skb); + } + while (dcb_reload !=3D fdma->dcb_index) { + old_dcb =3D dcb_reload; + dcb_reload++; + dcb_reload &=3D fdma->n_dcbs - 1; + + fdma_dcb_add(fdma, + old_dcb, + FDMA_DCB_INFO_DATAL(fdma->db_size - XDP_PACKET_HEADROOM), + FDMA_DCB_STATUS_INTR); + + lan966x_fdma_rx_reload(rx); + } + + if (counter < weight && napi_complete_done(napi, counter)) + lan_wr(0xff, lan966x, FDMA_INTR_DB_ENA); + + return counter; +} + +static int lan966x_fdma_pci_init(struct lan966x *lan966x) +{ + struct fdma *rx_fdma =3D &lan966x->rx.fdma; + struct fdma *tx_fdma =3D &lan966x->tx.fdma; + int err; + + if (!lan966x->fdma) + return 0; + + lan_wr(FDMA_CTRL_NRESET_SET(0), lan966x, FDMA_CTRL); + lan_wr(FDMA_CTRL_NRESET_SET(1), lan966x, FDMA_CTRL); + + fdma_pci_atu_init(&lan966x->atu, lan966x->regs[TARGET_PCIE_DBI]); + + lan966x->rx.lan966x =3D lan966x; + lan966x->rx.max_mtu =3D lan966x_fdma_get_max_frame(lan966x); + rx_fdma->channel_id =3D FDMA_XTR_CHANNEL; + rx_fdma->n_dcbs =3D FDMA_DCB_MAX; + rx_fdma->n_dbs =3D FDMA_RX_DCB_MAX_DBS; + rx_fdma->priv =3D lan966x; + rx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + rx_fdma->size =3D fdma_get_size_contiguous(rx_fdma); + rx_fdma->ops.nextptr_cb =3D &lan966x_fdma_pci_nextptr_cb; + rx_fdma->ops.dataptr_cb =3D &lan966x_fdma_pci_dataptr_cb; + + lan966x->tx.lan966x =3D lan966x; + tx_fdma->channel_id =3D FDMA_INJ_CHANNEL; + tx_fdma->n_dcbs =3D FDMA_DCB_MAX; + tx_fdma->n_dbs =3D FDMA_TX_DCB_MAX_DBS; + tx_fdma->priv =3D lan966x; + tx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + tx_fdma->size =3D fdma_get_size_contiguous(tx_fdma); + tx_fdma->ops.nextptr_cb =3D &lan966x_fdma_pci_nextptr_cb; + tx_fdma->ops.dataptr_cb =3D &lan966x_fdma_pci_dataptr_cb; + + err =3D lan966x_fdma_pci_rx_alloc(&lan966x->rx); + if (err) + return err; + + err =3D lan966x_fdma_pci_tx_alloc(&lan966x->tx); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dma_dev, rx_fdma); + return err; + } + + lan966x_fdma_rx_start(&lan966x->rx); + + return 0; +} + +static int lan966x_fdma_pci_resize(struct lan966x *lan966x) +{ + return -EOPNOTSUPP; +} + +static void lan966x_fdma_pci_deinit(struct lan966x *lan966x) +{ + if (!lan966x->fdma) + return; + + if (lan966x->fdma_ndev) + napi_disable(&lan966x->napi); + + lan966x_fdma_tx_disable_netdev(lan966x); + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + + fdma_free_coherent_and_unmap(lan966x->dma_dev, &lan966x->rx.fdma); + fdma_free_coherent_and_unmap(lan966x->dma_dev, &lan966x->tx.fdma); +} + +const struct lan966x_fdma_ops lan966x_fdma_pci_ops =3D { + .fdma_init =3D &lan966x_fdma_pci_init, + .fdma_deinit =3D &lan966x_fdma_pci_deinit, + .fdma_xmit =3D &lan966x_fdma_pci_xmit, + .fdma_poll =3D &lan966x_fdma_pci_napi_poll, + .fdma_resize =3D &lan966x_fdma_pci_resize, +}; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index d6ce1e3e373f..e089c08b9c37 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -50,6 +50,7 @@ struct lan966x_main_io_resource { static const struct lan966x_main_io_resource lan966x_main_iomap[] =3D { { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ + { TARGET_PCIE_DBI, 0x400000, 0 }, /* 0xe0400000 */ { TARGET_ORG, 0, 1 }, /* 0xe2000000 */ { TARGET_GCB, 0x4000, 1 }, /* 0xe2004000 */ { TARGET_QS, 0x8000, 1 }, /* 0xe2008000 */ @@ -873,7 +874,8 @@ static int lan966x_probe_port(struct lan966x *lan966x, = u32 p, =20 port->phylink =3D phylink; =20 - if (lan966x->fdma) + /* XDP is not supported on the PCIe FDMA path. */ + if (lan966x->fdma && !lan966x_is_pci(lan966x)) dev->xdp_features =3D NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | NETDEV_XDP_ACT_NDO_XMIT; @@ -1128,7 +1130,8 @@ static int lan966x_probe(struct platform_device *pdev) lan966x->dev =3D &pdev->dev; lan966x->dma_dev =3D lan966x_get_dma_dev(lan966x->dev); =20 - lan966x->ops =3D &lan966x_fdma_ops; + lan966x->ops =3D lan966x_is_pci(lan966x) ? &lan966x_fdma_pci_ops : + &lan966x_fdma_ops; =20 if (!device_get_mac_address(&pdev->dev, mac_addr)) { ether_addr_copy(lan966x->base_mac, mac_addr); @@ -1187,7 +1190,9 @@ static int lan966x_probe(struct platform_device *pdev) if (err) return dev_err_probe(&pdev->dev, err, "Unable to use ptp irq"); =20 - lan966x->ptp =3D 1; + /* PTP is not supported on the PCIe path yet. */ + if (!lan966x_is_pci(lan966x)) + lan966x->ptp =3D 1; } =20 lan966x->fdma_irq =3D platform_get_irq_byname(pdev, "fdma"); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index b7e3ce4f0355..48c7527845fb 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -17,6 +17,7 @@ #include =20 #include +#include #include #include =20 @@ -291,6 +292,10 @@ struct lan966x { =20 void __iomem *regs[NUM_TARGETS]; =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + struct fdma_pci_atu atu; +#endif + int shared_queue_sz; =20 u8 base_mac[ETH_ALEN]; @@ -590,6 +595,8 @@ void lan966x_fdma_tx_disable_netdev(struct lan966x *lan= 966x); int lan966x_fdma_get_max_frame(struct lan966x *lan966x); int lan966x_qsys_sw_status(struct lan966x *lan966x); =20 +extern const struct lan966x_fdma_ops lan966x_fdma_pci_ops; + /* dma_dev differs from dev only on the PCIe path. */ static inline bool lan966x_is_pci(struct lan966x *lan966x) { diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_regs.h index aba0d36ae6b5..4778ea217673 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h @@ -20,6 +20,7 @@ enum lan966x_target { TARGET_FDMA =3D 21, TARGET_GCB =3D 27, TARGET_ORG =3D 36, + TARGET_PCIE_DBI =3D 40, TARGET_PTP =3D 41, TARGET_QS =3D 42, TARGET_QSYS =3D 46, @@ -1009,6 +1010,15 @@ enum lan966x_target { #define FDMA_CH_CFG_CH_MEM_GET(x)\ FIELD_GET(FDMA_CH_CFG_CH_MEM, x) =20 +/* FDMA:FDMA:FDMA_CTRL */ +#define FDMA_CTRL __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 24, 0, 1, 4) + +#define FDMA_CTRL_NRESET BIT(0) +#define FDMA_CTRL_NRESET_SET(x)\ + FIELD_PREP(FDMA_CTRL_NRESET, x) +#define FDMA_CTRL_NRESET_GET(x)\ + FIELD_GET(FDMA_CTRL_NRESET, x) + /* FDMA:FDMA:FDMA_PORT_CTRL */ #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 3= 76, r, 2, 4) =20 diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c b/drivers= /net/ethernet/microchip/lan966x/lan966x_xdp.c index 9ee61db8690b..e63634887f64 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c @@ -20,6 +20,12 @@ static int lan966x_xdp_setup(struct net_device *dev, str= uct netdev_bpf *xdp) return -EOPNOTSUPP; } =20 + if (lan966x_is_pci(lan966x)) { + NL_SET_ERR_MSG_MOD(xdp->extack, + "XDP is not supported on the PCIe FDMA path"); + return -EOPNOTSUPP; + } + old_xdp =3D lan966x_xdp_present(lan966x); old_prog =3D xchg(&port->xdp_prog, xdp->prog); new_xdp =3D lan966x_xdp_present(lan966x); --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB6BE5616A8; Wed, 9 Sep 2026 13:01:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958871; cv=none; b=OalHTJZk2d8A5tEnq2bgVdfKKtlut2WTx5v8zsw/jHYUw+svlSAqW/AU7c72zFNmdBClv7jUQ1B0IQQEIBlKbDudS/7uZGFE1GROt8OSwm8MUDkB8uk3DhtV3UqvzcnKfjTBX9/zAlRyLOm+Kv/0VmN6yw9u1MzMunUlrRf006A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958871; c=relaxed/simple; bh=b2dGVJTd0yHdTgyW6Eaws6C1vM3i3wCLqxj+jxHi9Vw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ebPEjjlyowE9AOy1ydh5TOiINXJE15qpix06HT3PJS6eusttzUPHxec9Vw636NG/kVkW7pq4RO2OZve/WZewP3cLWNB+K9nAQSvxn8qkIAhKIaXL31QVR8oGfmpKPs4hnbVX1hZR6iaGp2FiQMdtXNmET/EP5DFOI3kf0UIHFHU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=pny5lrGw; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="pny5lrGw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958869; x=1820494869; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=b2dGVJTd0yHdTgyW6Eaws6C1vM3i3wCLqxj+jxHi9Vw=; b=pny5lrGw4nbI9Oza9DVsNdTk++MDWOourECVZWSuBCQDeBLoljIx61Fj QVdZxEOb20mQBbyFywF8zL492v2bNYxIsdbaefSCLj+AtpbBAKAIjI7iR N0mcVkrfNmexN0o1sAa55QVhyRjVgKBptJaVhpSDLkQ3HPZ/SKgziPDEL SmZ/yzdFeIQ7gUevUjcbzFoFfkem3eMEYsXbZRwm1K3U/4NXEFWX/EYaL JAOgQ7jZcmqYpcb1yAmtwVK7rUZoenRaKcBpn8W8dLm15ofJ6S+Go9Z46 HRLNqEcbEAMgBd2biTT8jl2Jn2hfR7yW2I0V16VHAAPdX78oCYYE/7S26 A==; X-CSE-ConnectionGUID: hVe6ykYaTLaF3yn7jHyvvA== X-CSE-MsgGUID: W1Z8YWMeStGxhRQODZM2NQ== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="230464594" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:01:08 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:01:08 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:01:03 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:13 +0200 Subject: [PATCH net-next v6 11/14] net: lan966x: add PCIe FDMA MTU change support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-11-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Add MTU change support for the PCIe FDMA path. When the MTU changes, the contiguous ATU-mapped RX and TX buffers are reallocated with the new size. On allocation failure, the existing buffers are reused after being reset. Cap the PCIe DCB ring at 256 (FDMA_PCI_DCB_MAX) to keep the entire contiguous allocation under MAX_PAGE_ORDER at jumbo MTU, which 512 DCBs would overflow. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 168 +++++++++++++++++= +++- 1 file changed, 165 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c index f1f3c789d3a6..6cabbb8b47f2 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -1,8 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ =20 +#include + #include "fdma_api.h" #include "lan966x_main.h" =20 +/* Ring must fit in one MAX_PAGE_ORDER DMA block; 512 DCBs overflows + * at jumbo MTU. + */ +#define FDMA_PCI_DCB_MAX 256 + static int lan966x_fdma_pci_dataptr_cb(struct fdma *fdma, int dcb, int db, u64 *dataptr) { @@ -341,7 +348,7 @@ static int lan966x_fdma_pci_init(struct lan966x *lan966= x) lan966x->rx.lan966x =3D lan966x; lan966x->rx.max_mtu =3D lan966x_fdma_get_max_frame(lan966x); rx_fdma->channel_id =3D FDMA_XTR_CHANNEL; - rx_fdma->n_dcbs =3D FDMA_DCB_MAX; + rx_fdma->n_dcbs =3D FDMA_PCI_DCB_MAX; rx_fdma->n_dbs =3D FDMA_RX_DCB_MAX_DBS; rx_fdma->priv =3D lan966x; rx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); @@ -351,7 +358,7 @@ static int lan966x_fdma_pci_init(struct lan966x *lan966= x) =20 lan966x->tx.lan966x =3D lan966x; tx_fdma->channel_id =3D FDMA_INJ_CHANNEL; - tx_fdma->n_dcbs =3D FDMA_DCB_MAX; + tx_fdma->n_dcbs =3D FDMA_PCI_DCB_MAX; tx_fdma->n_dbs =3D FDMA_TX_DCB_MAX_DBS; tx_fdma->priv =3D lan966x; tx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); @@ -374,9 +381,164 @@ static int lan966x_fdma_pci_init(struct lan966x *lan9= 66x) return 0; } =20 +/* Reset existing rx and tx buffers. */ +static void lan966x_fdma_pci_reset_mem(struct lan966x *lan966x) +{ + struct lan966x_rx *rx =3D &lan966x->rx; + struct lan966x_tx *tx =3D &lan966x->tx; + + memset(rx->fdma.dcbs, 0, rx->fdma.size); + memset(tx->fdma.dcbs, 0, tx->fdma.size); + + fdma_dcbs_init(&rx->fdma, + FDMA_DCB_INFO_DATAL(rx->fdma.db_size - XDP_PACKET_HEADROOM), + FDMA_DCB_STATUS_INTR); + + fdma_dcbs_init(&tx->fdma, + FDMA_DCB_INFO_DATAL(tx->fdma.db_size), + FDMA_DCB_STATUS_DONE); + + lan966x_fdma_llp_configure(lan966x, + tx->fdma.atu_region->base_addr, + tx->fdma.channel_id); + lan966x_fdma_llp_configure(lan966x, + rx->fdma.atu_region->base_addr, + rx->fdma.channel_id); +} + +/* Wake all TX queues on every port (undoes lan966x_fdma_tx_disable_netdev= ). */ +static void lan966x_fdma_pci_wakeup_netdev(struct lan966x *lan966x) +{ + for (int i =3D 0; i < lan966x->num_phys_ports; ++i) { + struct lan966x_port *port =3D lan966x->ports[i]; + + if (port) + netif_tx_wake_all_queues(port->dev); + } +} + +static int lan966x_fdma_pci_reload(struct lan966x *lan966x, int new_mtu) +{ + struct fdma tx_fdma_old =3D lan966x->tx.fdma; + struct fdma rx_fdma_old =3D lan966x->rx.fdma; + u32 old_mtu =3D lan966x->rx.max_mtu; + int err; + + napi_disable(&lan966x->napi); + lan966x_fdma_tx_disable_netdev(lan966x); + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + + lan966x->rx.max_mtu =3D new_mtu; + + /* Must be NULL'ed in order to realloc them. */ + lan966x->rx.fdma.atu_region =3D NULL; + lan966x->tx.fdma.atu_region =3D NULL; + + lan966x->tx.fdma.db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + lan966x->tx.fdma.size =3D fdma_get_size_contiguous(&lan966x->tx.fdma); + lan966x->rx.fdma.db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + lan966x->rx.fdma.size =3D fdma_get_size_contiguous(&lan966x->rx.fdma); + + err =3D lan966x_fdma_pci_rx_alloc(&lan966x->rx); + if (err) + goto restore; + + err =3D lan966x_fdma_pci_tx_alloc(&lan966x->tx); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dma_dev, + &lan966x->rx.fdma); + goto restore; + } + + /* Free and unmap old memory. */ + fdma_free_coherent_and_unmap(lan966x->dma_dev, &rx_fdma_old); + fdma_free_coherent_and_unmap(lan966x->dma_dev, &tx_fdma_old); + + napi_enable(&lan966x->napi); + lan966x_fdma_rx_start(&lan966x->rx); + lan966x_fdma_pci_wakeup_netdev(lan966x); + + return err; +restore: + + /* No new buffers are allocated at this point. Use the old buffers, + * but reset them before starting the FDMA again. + */ + + memcpy(&lan966x->tx.fdma, &tx_fdma_old, sizeof(struct fdma)); + memcpy(&lan966x->rx.fdma, &rx_fdma_old, sizeof(struct fdma)); + + lan966x->rx.max_mtu =3D old_mtu; + + lan966x_fdma_pci_reset_mem(lan966x); + + napi_enable(&lan966x->napi); + lan966x_fdma_rx_start(&lan966x->rx); + lan966x_fdma_pci_wakeup_netdev(lan966x); + + return err; +} + +static int __lan966x_fdma_pci_reload(struct lan966x *lan966x, int max_mtu) +{ + int err; + u32 val; + + /* Disable the CPU port. */ + lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(0), + QSYS_SW_PORT_MODE_PORT_ENA, + lan966x, QSYS_SW_PORT_MODE(CPU_PORT)); + + /* Flush the CPU queues. */ + readx_poll_timeout(lan966x_qsys_sw_status, + lan966x, + val, + !(QSYS_SW_STATUS_EQ_AVAIL_GET(val)), + READL_SLEEP_US, READL_TIMEOUT_US); + + /* Add a sleep in case there are frames between the queues and the CPU + * port + */ + usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); + + err =3D lan966x_fdma_pci_reload(lan966x, max_mtu); + + /* Enable back the CPU port. */ + lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(1), + QSYS_SW_PORT_MODE_PORT_ENA, + lan966x, QSYS_SW_PORT_MODE(CPU_PORT)); + + return err; +} + static int lan966x_fdma_pci_resize(struct lan966x *lan966x) { - return -EOPNOTSUPP; + struct fdma rx_fdma; + int max_mtu; + + max_mtu =3D lan966x_fdma_get_max_frame(lan966x); + if (max_mtu =3D=3D lan966x->rx.max_mtu) + return 0; + + /* rx and tx have n_dbs =3D=3D 1, so both rings need the same contiguous + * dma_alloc_coherent() block, which can't exceed MAX_PAGE_ORDER. The + * allocation is padded to the ATU region granularity, so test the + * padded size. + */ + rx_fdma =3D lan966x->rx.fdma; + rx_fdma.db_size =3D FDMA_PCI_DB_SIZE(max_mtu); + if (ALIGN(fdma_get_size_contiguous(&rx_fdma), + FDMA_PCI_ATU_REGION_ALIGN) > (PAGE_SIZE << MAX_PAGE_ORDER)) + return -ERANGE; + + /* db_size is also handed to the FDMA in the 16-bit DCB DATAL field, + * where a larger value would be silently truncated. + */ + if (rx_fdma.db_size > GENMASK(15, 0)) + return -ERANGE; + + return __lan966x_fdma_pci_reload(lan966x, max_mtu); } =20 static void lan966x_fdma_pci_deinit(struct lan966x *lan966x) --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02714568539; Wed, 9 Sep 2026 13:01:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958876; cv=none; b=nYtwV2NN4zyQdkRQg8Cdkwu5HXb4OyWmD4u5g7lUW/njP08nWZgMBYxK5479DQjfFDdBbxl0iRPZM3B76g8PZlp30VyQGs0ybAuZVkl8fg2Y2hOND4JmSeEen/sZTBn0snR5LRlKRpB1fqyi98/GJiqGNpnLhL6d0Il0d/9+KTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958876; c=relaxed/simple; bh=saI5xc9/H+CA4hkm0hDilkBJ4KXx8mRVjY11FTkM3y8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=HMYNVD4ojlrwl6S7EgR9Oy5I+fjp8bcKMU4thoCGjXgcVK8sw8ihN1KWLCeIB8hMLo1ATavONoBtDJpRlpzrOS+FfjCwE1f7CKuEnL4QhuISawYMTGjC7yZ7QWEVBhoRqIZrpQGiPgxv7VpPb+iG+7rmSUqpBzI11btEvExvu1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=0EuvuYGW; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="0EuvuYGW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958878; x=1820494878; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=saI5xc9/H+CA4hkm0hDilkBJ4KXx8mRVjY11FTkM3y8=; b=0EuvuYGWkVwfIjVaOtD6UyKoSi0v/mGPfHx53DwgoQ2tTUtzchtBGU1+ W0xt/hzGeXxlwtxQz/MrNQYPPqhVA0Mur3uZKNcsBXYqVq9aeYHZml+f4 s5CT3nGKxedGwieV5mBqzLjBhkQ908Igp4rFPPN+VY6iMgky3Kr0qXY0H wT/2yxR0ux2VRx00wBDTciK10evuukEsQNQ4D2RYUO/U/I6ZcgVwD0X+8 aRC15bk5yPhbGOwTf1sTjpDRBMBnO67MR3T7QJlvntOIJBBDHyWOk+6/d CZuvG2LreLSr1HCbv568x6Q5j/yOrp2CdTORYKeUqEblcZBHprEPcTsMn w==; X-CSE-ConnectionGUID: EGJ7SlzESWykJ+vdG9FzNw== X-CSE-MsgGUID: UfRaa20AQGKZ0ep0d1oSMg== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="63658729" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:01:17 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:01:12 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:01:08 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:14 +0200 Subject: [PATCH net-next v6 12/14] net: lan966x: add PCIe FDMA XDP support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-12-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Add XDP support for the PCIe FDMA path. The implementation operates on contiguous ATU-mapped buffers with memcpy-based XDP_TX, unlike the platform path which uses page_pool. XDP sees the frame with IFH and FCS stripped. These are removed in lan966x_fdma_pci_rx_check_frame() before the BPF program runs, because after the program returns the driver cannot tell whether the tail region was modified. The skb_pull/skb_trim previously done in lan966x_fdma_pci_rx_get_frame() are removed for the same reason; the frame pointer and length are pre-computed by rx_check_frame() and passed through rx_get_frame() and lan966x_xdp_pci_run() to the caller. lan966x_fdma_pci_xmit_xdpf() handles XDP_TX: it rebuilds a fresh IFH in the TX slot, copies the post-XDP frame after it, and lets HW insert a new FCS. lan966x_xdp_setup() is extended so the PCIe path skips the page_pool reload that the platform path needs. Only XDP_ACT_BASIC is supported. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 166 +++++++++++++++++= +--- .../net/ethernet/microchip/lan966x/lan966x_main.c | 12 +- .../net/ethernet/microchip/lan966x/lan966x_xdp.c | 12 +- 3 files changed, 159 insertions(+), 31 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c index 6cabbb8b47f2..02c021617a3e 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ =20 +#include #include =20 #include "fdma_api.h" @@ -126,7 +127,123 @@ static bool lan966x_fdma_pci_rx_size_fits(struct fdma= *fdma, u32 blockl) blockl <=3D fdma->db_size - XDP_PACKET_HEADROOM; } =20 -static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port) +static int lan966x_fdma_pci_xmit_xdpf(struct lan966x_port *port, + void *ptr, u32 len) +{ + struct lan966x *lan966x =3D port->lan966x; + struct lan966x_tx *tx =3D &lan966x->tx; + struct fdma *fdma =3D &tx->fdma; + int next_to_use, ret =3D 0; + void *virt_addr; + + spin_lock(&lan966x->tx_lock); + + next_to_use =3D lan966x_fdma_pci_get_next_dcb(fdma); + + if (next_to_use < 0) { + netif_stop_queue(port->dev); + port->dev->stats.tx_dropped++; + ret =3D NETDEV_TX_BUSY; + goto out; + } + + /* Only the upper bound is enforced: XDP owns the frame contents and + * length, so a program that shrinks below ETH_ZLEN gets what it asked + * for. + */ + if (!lan966x_fdma_pci_tx_size_fits(fdma, len)) { + port->dev->stats.tx_dropped++; + ret =3D -EINVAL; + goto out; + } + + /* virt_addr points to the IFH. */ + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, next_to_use, 0); + + /* Construct a fresh IFH. */ + memset(virt_addr, 0, IFH_LEN_BYTES); + lan966x_ifh_set_bypass(virt_addr, 1); + lan966x_ifh_set_port(virt_addr, BIT_ULL(port->chip_port)); + + /* Copy the (post-XDP) frame after the IFH. */ + memcpy(virt_addr + IFH_LEN_BYTES, ptr, len); + + /* Order frame write before DCB status write below. */ + dma_wmb(); + + /* Reserve ETH_FCS_LEN for the HW-inserted FCS (len is FCS-stripped). */ + fdma_dcb_add(fdma, + next_to_use, + 0, + FDMA_DCB_STATUS_INTR | + FDMA_DCB_STATUS_SOF | + FDMA_DCB_STATUS_EOF | + FDMA_DCB_STATUS_BLOCKO(0) | + FDMA_DCB_STATUS_BLOCKL(IFH_LEN_BYTES + len + ETH_FCS_LEN)); + + /* Start the transmission. */ + lan966x_fdma_tx_start(tx); + + port->dev->stats.tx_bytes +=3D len; + port->dev->stats.tx_packets++; + +out: + spin_unlock(&lan966x->tx_lock); + + return ret; +} + +static int lan966x_xdp_pci_run(struct lan966x_port *port, void *data, + u32 data_len, void **xdp_data, u32 *xdp_len) +{ + /* Read once so the NULL check and bpf_prog_run_xdp() see the same + * pointer. + */ + struct bpf_prog *xdp_prog =3D READ_ONCE(port->xdp_prog); + struct lan966x *lan966x =3D port->lan966x; + struct fdma *fdma =3D &lan966x->rx.fdma; + struct xdp_buff xdp; + u32 act; + + if (!xdp_prog) + return FDMA_PASS; + + xdp_init_buff(&xdp, fdma->db_size, &port->xdp_rxq); + + /* hard_start is set to slot start (virt_addr is XDP_PACKET_HEADROOM + * into the slot). Headroom includes the IFH; BPF may grow into it + * via adjust_head. IFH is rebuilt on XDP_TX and unread on XDP_PASS. + */ + xdp_prepare_buff(&xdp, + data - XDP_PACKET_HEADROOM, + XDP_PACKET_HEADROOM + IFH_LEN_BYTES, + data_len, + false); + + act =3D bpf_prog_run_xdp(xdp_prog, &xdp); + + *xdp_data =3D xdp.data; + *xdp_len =3D xdp.data_end - xdp.data; + + switch (act) { + case XDP_PASS: + return FDMA_PASS; + case XDP_TX: + return lan966x_fdma_pci_xmit_xdpf(port, *xdp_data, *xdp_len) ? + FDMA_DROP : FDMA_TX; + default: + bpf_warn_invalid_xdp_action(port->dev, xdp_prog, act); + fallthrough; + case XDP_ABORTED: + trace_xdp_exception(port->dev, xdp_prog, act); + fallthrough; + case XDP_DROP: + return FDMA_DROP; + } +} + +static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port, + void **data, u32 *data_len) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -158,38 +275,33 @@ static int lan966x_fdma_pci_rx_check_frame(struct lan= 966x_rx *rx, u64 *src_port) if (!lan966x_fdma_pci_rx_size_fits(fdma, blockl)) return FDMA_ERROR; =20 - return FDMA_PASS; + /* Present the Ethernet frame (no IFH, no FCS). HW re-inserts the + * FCS on TX; see lan966x_fdma_pci_xmit_xdpf(). May be overridden + * by XDP. The FCS strip is unconditional because NETIF_F_RXFCS + * is not advertised in hw_features. + */ + *data =3D virt_addr + IFH_LEN_BYTES; + *data_len =3D blockl - IFH_LEN_BYTES - ETH_FCS_LEN; + + return lan966x_xdp_pci_run(port, virt_addr, *data_len, data, data_len); } =20 static struct sk_buff *lan966x_fdma_pci_rx_get_frame(struct lan966x_rx *rx, - u64 src_port) + u64 src_port, void *data, + u32 data_len) { struct lan966x *lan966x =3D rx->lan966x; - struct fdma *fdma =3D &rx->fdma; struct sk_buff *skb; - struct fdma_db *db; - u32 data_len; - - /* Get the received frame and create an SKB for it. */ - db =3D fdma_db_next_get(fdma); - data_len =3D FDMA_DCB_STATUS_BLOCKL(db->status); =20 skb =3D napi_alloc_skb(&lan966x->napi, data_len); if (unlikely(!skb)) return NULL; =20 - memcpy(skb->data, - fdma_dataptr_virt_addr_contiguous(fdma, - fdma->dcb_index, - fdma->db_index), - data_len); + memcpy(skb->data, data, data_len); =20 skb_put(skb, data_len); =20 skb->dev =3D lan966x->ports[src_port]->dev; - skb_pull(skb, IFH_LEN_BYTES); - - skb_trim(skb, skb->len - ETH_FCS_LEN); =20 skb->protocol =3D eth_type_trans(skb, skb->dev); =20 @@ -277,6 +389,8 @@ static int lan966x_fdma_pci_napi_poll(struct napi_struc= t *napi, int weight) struct sk_buff *skb; int counter =3D 0; u64 src_port; + u32 data_len; + void *data; =20 /* Wake any stopped TX queues if a TX DCB is available. */ spin_lock(&lan966x->tx_lock); @@ -293,7 +407,10 @@ static int lan966x_fdma_pci_napi_poll(struct napi_stru= ct *napi, int weight) /* Order DONE read before DCB/frame reads below. */ dma_rmb(); counter++; - switch (lan966x_fdma_pci_rx_check_frame(rx, &src_port)) { + switch (lan966x_fdma_pci_rx_check_frame(rx, + &src_port, + &data, + &data_len)) { case FDMA_PASS: break; case FDMA_ERROR: @@ -302,8 +419,17 @@ static int lan966x_fdma_pci_napi_poll(struct napi_stru= ct *napi, int weight) */ fdma_dcb_advance(fdma); continue; + case FDMA_TX: + fdma_dcb_advance(fdma); + continue; + case FDMA_DROP: + fdma_dcb_advance(fdma); + continue; } - skb =3D lan966x_fdma_pci_rx_get_frame(rx, src_port); + skb =3D lan966x_fdma_pci_rx_get_frame(rx, + src_port, + data, + data_len); fdma_dcb_advance(fdma); if (!skb) { lan966x->ports[src_port]->dev->stats.rx_dropped++; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index e089c08b9c37..9ada497767c6 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -874,11 +874,13 @@ static int lan966x_probe_port(struct lan966x *lan966x= , u32 p, =20 port->phylink =3D phylink; =20 - /* XDP is not supported on the PCIe FDMA path. */ - if (lan966x->fdma && !lan966x_is_pci(lan966x)) - dev->xdp_features =3D NETDEV_XDP_ACT_BASIC | - NETDEV_XDP_ACT_REDIRECT | - NETDEV_XDP_ACT_NDO_XMIT; + if (lan966x->fdma) { + dev->xdp_features =3D NETDEV_XDP_ACT_BASIC; + + if (!lan966x_is_pci(lan966x)) + dev->xdp_features |=3D NETDEV_XDP_ACT_REDIRECT | + NETDEV_XDP_ACT_NDO_XMIT; + } =20 err =3D register_netdev(dev); if (err) { diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c b/drivers= /net/ethernet/microchip/lan966x/lan966x_xdp.c index e63634887f64..b98426afc785 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c @@ -20,16 +20,16 @@ static int lan966x_xdp_setup(struct net_device *dev, st= ruct netdev_bpf *xdp) return -EOPNOTSUPP; } =20 - if (lan966x_is_pci(lan966x)) { - NL_SET_ERR_MSG_MOD(xdp->extack, - "XDP is not supported on the PCIe FDMA path"); - return -EOPNOTSUPP; - } - old_xdp =3D lan966x_xdp_present(lan966x); old_prog =3D xchg(&port->xdp_prog, xdp->prog); new_xdp =3D lan966x_xdp_present(lan966x); =20 + /* PCIe FDMA uses contiguous buffers, so no page_pool reload + * is needed. + */ + if (lan966x_is_pci(lan966x)) + goto out; + if (old_xdp =3D=3D new_xdp) goto out; =20 --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87007568543; Wed, 9 Sep 2026 13:01:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958880; cv=none; b=cy6ioZGSTNwDIp9/gzETBlC/UTpSYURK+bPItSJPzoWgUTfp0fZK9x1N5PSanRdUARfu417RvrobVbfeO/2Zz9V/lk2mZyA3Rt1jZSSc+QlKeyDzckiHgWDVIR92vJ7n+WfN9WGArIT7mLm6FgyxCZUl8wPanQQWcZAE6YKdLIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958880; c=relaxed/simple; bh=pLLUnpsQHk0XLLoB+wBplrU8A7WIjOzUca/wCfOw6mw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Fwf3T4JC2lfiRbYNkV6Kn5xB5oC0T4bSGKrJWRck8+fiSP54Qj4Ro4zwNK+r+E7IUaORa4KAeEMU+vD0XYmjlHkb4dyXtGdj8gW7aA5TnIQAohSQzp/xT5oOIHbptu2ufuAb6Mu1ykpbwFL3kxI2KclQlCCk0O+j+0ssjWMhqxM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=PTFl0Xv8; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PTFl0Xv8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958878; x=1820494878; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=pLLUnpsQHk0XLLoB+wBplrU8A7WIjOzUca/wCfOw6mw=; b=PTFl0Xv88rfW2RFHgvGEhk4+F5A/o2MbG9Jlp5UE07/Y0xoHXxry5etu QuIEMv+v2o43ywcNtUPnjQiidMBQkzXSZsrGUsaeRMXDMsG9SOPm9iQz+ rdYKxP/4HMpfXH6NpGOvVdkDNmiuI6Dffhu1H/zeK3fj+eQeDk88fYr7p 8HHZ+oHlHVxp0qmZJtU9uRgNb1d4yEX8qTAQy5bLPT+xDvV2e8xtYMJrp +NJPHGK6jhTm+2CQOP6M1ayJFX3SOb+JDDnpmr9Oe9HWXSZs1zs6j6lAN oJHvp13KdX/yDEVfnh+qzAHNuFamKhWzkq/4yStZyeYHhJZXO0fukRYBs g==; X-CSE-ConnectionGUID: E/ZtF3FyRom806v0oaXIxg== X-CSE-MsgGUID: WCrG0WACS7iGeteB5+Hh4g== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="230464608" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:01:17 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:01:17 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:01:13 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:15 +0200 Subject: [PATCH net-next v6 13/14] misc: lan966x-pci: dts: extend cpu reg to cover PCIE DBI space Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-13-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 The ATU outbound windows used by the FDMA engine are programmed through registers at offset 0x400000+, which falls outside the current cpu reg mapping. Extend the cpu reg size from 0x100000 (1MB) to 0x800000 (8MB) to cover the full PCIE DBI and iATU register space. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/misc/lan966x_pci.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7b196b0a0eb6..7bb726550caf 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -135,7 +135,7 @@ lan966x_phy1: ethernet-lan966x_phy@2 { =20 switch: switch@e0000000 { compatible =3D "microchip,lan966x-switch"; - reg =3D <0xe0000000 0x0100000>, + reg =3D <0xe0000000 0x0800000>, <0xe2000000 0x0800000>; reg-names =3D "cpu", "gcb"; =20 --=20 2.34.1 From nobody Fri Sep 25 19:20:05 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15EAA568FB8; Wed, 9 Sep 2026 13:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958884; cv=none; b=uvlionBQJ741sQpCmiP3gnelHYwDxDpcWGfWsiuvTk+mu/zLXtGpLwkAjWH3WRANgovx+NyVVIFgKL8PwGBDN+ZZZDHzLE3d+bnrbJ/hBTlviHdkmjow1+Pi1R1IygH5jWMA+5Lmd4OIRLgoGciUrdPjhwJqYUKlPwUP8/ynaFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788958884; c=relaxed/simple; bh=wGxs+F/+5Vrhuyz2y5uEWLeuFrAw1YPbFSMnjR0PIic=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=N+iR/tR2s0dqNx3HcJlDucp2MtFU4oRH6vGuzxwFqviC+ZVmo97wZnH3/57evOmucYdgECmrKDlcUQ9yy6m1OIsL5ul83v5CvOFQGySMr3Gl+UuyhniW/DBV5ArS+HkyRYkKt5Dfh6a9wQIdhdoE0g/nIb6961rhDCSvljSMBs0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=kIdAIrlX; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="kIdAIrlX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1788958883; x=1820494883; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=wGxs+F/+5Vrhuyz2y5uEWLeuFrAw1YPbFSMnjR0PIic=; b=kIdAIrlX2i5Ws4OKInvWaC8eZ2mFBm7uI3tf2xzKq1aqtRBRgeXVamXU ExlJIcW9aEr/th0kBileXEGtM+XO773hqhLeVKn8iCPllq7cDMqczEdfC LixEkNQRs71VLOnYQYingw0dJB18dd0D+0+xczoCd74/oaKlb2ZjUL5uB aWSlcBSkBQW+wa4399yUZJ9dMqFMRnAzpszSbcfd1xUP4KfrVwfKJsgO7 ceKl4UkmSo+0O1CcQV5my8s4GkNimP//enqZjD4FwmCFySWhYethnjA3i h1KWGBZV2QnBPbNgvNaX3pPAODoWll+oQ7VyaOT8FSbogLTq7E/tTmQ/D g==; X-CSE-ConnectionGUID: m9VhaSUDSZCeuWHFixm3Lw== X-CSE-MsgGUID: UKhMqLabSB+23J0chCn83Q== X-IronPort-AV: E=Sophos;i="6.25,270,1779174000"; d="scan'208";a="294759204" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 06:01:22 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Wed, 9 Sep 2026 06:01:21 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 9 Sep 2026 06:01:17 -0700 From: Daniel Machon Date: Wed, 9 Sep 2026 15:00:16 +0200 Subject: [PATCH net-next v6 14/14] misc: lan966x-pci: dts: add fdma interrupt to overlay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260909-lan966x-pci-fdma-v6-14-6f48dab9d671@microchip.com> References: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> In-Reply-To: <20260909-lan966x-pci-fdma-v6-0-6f48dab9d671@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 Add the fdma interrupt (OIC interrupt 14) to the lan966x PCI device tree overlay, enabling FDMA-based frame injection/extraction when the switch is connected over PCIe. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/misc/lan966x_pci.dtso | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7bb726550caf..5bb12dbc0843 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -141,8 +141,9 @@ switch: switch@e0000000 { =20 interrupt-parent =3D <&oic>; interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names =3D "xtr", "ana"; + interrupt-names =3D "xtr", "fdma", "ana"; =20 resets =3D <&reset 0>; reset-names =3D "switch"; --=20 2.34.1