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- compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x000>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x000>; + enable-method =3D "psci"; + clock-frequency =3D <2400000000>; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl0_1: cpu@1 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x001>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x001>; + enable-method =3D "psci"; + clock-frequency =3D <2400000000>; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl0_2: cpu@2 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x002>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x002>; + enable-method =3D "psci"; + clock-frequency =3D <2400000000>; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl0_3: cpu@3 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x003>; - enable-method =3D "psci"; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x003>; + enable-method =3D "psci"; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 /* Cluster 1 */ cpucl1_0: cpu@100 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x100>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + clock-frequency =3D <2400000000>; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl1_1: cpu@101 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x101>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x101>; + enable-method =3D "psci"; + clock-frequency =3D <2400000000>; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl1_2: cpu@102 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x102>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x102>; + enable-method =3D "psci"; + clock-frequency =3D <2400000000>; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl1_3: cpu@103 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x103>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x103>; + enable-method =3D "psci"; + clock-frequency =3D <2400000000>; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 /* Cluster 2 */ cpucl2_0: cpu@200 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x200>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + clock-frequency =3D <2400000000>; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl2_1: cpu@201 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x201>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x201>; + enable-method =3D "psci"; + clock-frequency =3D <2400000000>; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl2_2: cpu@202 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x202>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x0 0x202>; + enable-method =3D "psci"; + clock-frequency =3D <2400000000>; + cpu-idle-states =3D <&cpu_sleep>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl2_3: cpu@203 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a72"; - reg =3D <0x0 0x203>; - enable-method =3D "psci"; - clock-frequency =3D <2400000000>; - cpu-idle-states =3D <&cpu_sleep>; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&cpucl_l2>; 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Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar --- arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 16 +- arch/arm64/boot/dts/tesla/fsd.dtsi | 798 ++++++++++++++-----------= ---- 2 files changed, 407 insertions(+), 407 deletions(-) diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/d= ts/tesla/fsd-pinctrl.dtsi index 6f4658f57453..ab25433e9b32 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -27,14 +27,6 @@ gpf1: gpf1-gpio-bank { #interrupt-cells =3D <2>; }; =20 - gpf6: gpf6-gpio-bank { - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-controller; - #interrupt-cells =3D <2>; - }; - gpf4: gpf4-gpio-bank { gpio-controller; #gpio-cells =3D <2>; @@ -51,6 +43,14 @@ gpf5: gpf5-gpio-bank { #interrupt-cells =3D <2>; }; =20 + gpf6: gpf6-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + ufs_rst_n: ufs-rst-n-pins { samsung,pins =3D "gpf5-0"; samsung,pin-function =3D ; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla= /fsd.dtsi index acbe93756a76..22b997880d65 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -34,6 +34,12 @@ aliases { spi2 =3D &spi_2; }; =20 + fin_pll: clock { + compatible =3D "fixed-clock"; + clock-output-names =3D "fin_pll"; + #clock-cells =3D <0>; + }; + cpus { #address-cells =3D <2>; #size-cells =3D <0>; @@ -312,7 +318,7 @@ cpu_sleep: cpu-sleep { }; }; =20 - arm-pmu { + pmu { compatible =3D "arm,cortex-a72-pmu"; interrupts =3D , , @@ -337,20 +343,6 @@ psci { method =3D "smc"; }; =20 - timer { - compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; - }; - - fin_pll: clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "fin_pll"; - #clock-cells =3D <0>; - }; - reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; @@ -370,14 +362,88 @@ soc: soc@0 { ranges =3D <0x0 0x0 0x0 0x0 0x0 0x18000000>; dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; =20 - gic: interrupt-controller@10400000 { - compatible =3D "arm,gic-v3"; - #address-cells =3D <0>; - #interrupt-cells =3D <3>; - interrupt-controller; - reg =3D <0x0 0x10400000 0x0 0x10000>, /* GICD */ - <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ - interrupts =3D ; + clock_imem: clock-controller@10010000 { + compatible =3D "tesla,fsd-clock-imem"; + reg =3D <0x0 0x10010000 0x0 0x3000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, + <&clock_cmu DOUT_CMU_IMEM_ACLK>, + <&clock_cmu DOUT_CMU_IMEM_DMACLK>; + clock-names =3D "fin_pll", + "dout_cmu_imem_tcuclk", + "dout_cmu_imem_aclk", + "dout_cmu_imem_dmaclk"; + }; + + timer@10040000 { + compatible =3D "tesla,fsd-mct", "samsung,exynos4210-mct"; + reg =3D <0x0 0x10040000 0x0 0x800>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; + clock-names =3D "fin_pll", "mct"; + }; + + watchdog_0: watchdog@100a0000 { + compatible =3D "tesla,fsd-wdt", "samsung,exynos7-wdt"; + reg =3D <0x0 0x100a0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&fin_pll>; + clock-names =3D "watchdog"; + samsung,syscon-phandle =3D <&pmu_system_controller>; + }; + + watchdog_1: watchdog@100b0000 { + compatible =3D "tesla,fsd-wdt", "samsung,exynos7-wdt"; + reg =3D <0x0 0x100b0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&fin_pll>; + clock-names =3D "watchdog"; + samsung,syscon-phandle =3D <&pmu_system_controller>; + }; + + watchdog_2: watchdog@100c0000 { + compatible =3D "tesla,fsd-wdt", "samsung,exynos7-wdt"; + reg =3D <0x0 0x100c0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&fin_pll>; + clock-names =3D "watchdog"; + samsung,syscon-phandle =3D <&pmu_system_controller>; + }; + + mdma0: dma-controller@10100000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0x10100000 0x0 0x1000>; + interrupts =3D ; + #dma-cells =3D <1>; + clocks =3D <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; + clock-names =3D "apb_pclk"; + iommus =3D <&smmu_imem 0x800 0x0>; + }; + + mdma1: dma-controller@10110000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0x10110000 0x0 0x1000>; + interrupts =3D ; + #dma-cells =3D <1>; + clocks =3D <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; + clock-names =3D "apb_pclk"; + iommus =3D <&smmu_imem 0x801 0x0>; }; =20 smmu_imem: iommu@10200000 { @@ -400,6 +466,34 @@ smmu_imem: iommu@10200000 { ; /* for CONTEXT_3 */ }; =20 + gic: interrupt-controller@10400000 { + compatible =3D "arm,gic-v3"; + #address-cells =3D <0>; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0x0 0x10400000 0x0 0x10000>, /* GICD */ + <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ + interrupts =3D ; + }; + + pmu_system_controller: system-controller@11400000 { + compatible =3D "tesla,fsd-pmu", "samsung,exynos7-pmu", "syscon"; + reg =3D <0x0 0x11400000 0x0 0x5000>; + }; + + pinctrl_pmu: pinctrl@114f0000 { + compatible =3D "tesla,fsd-pinctrl"; + reg =3D <0x0 0x114f0000 0x0 0x1000>; + }; + + clock_cmu: clock-controller@11c10000 { + compatible =3D "tesla,fsd-clock-cmu"; + reg =3D <0x0 0x11c10000 0x0 0x3000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>; + clock-names =3D "fin_pll"; + }; + smmu_isp: iommu@12100000 { compatible =3D "arm,mmu-500"; reg =3D <0x0 0x12100000 0x0 0x10000>; @@ -428,60 +522,6 @@ smmu_isp: iommu@12100000 { ; /* for CONTEXT_7 */ }; =20 - smmu_peric: iommu@14900000 { - compatible =3D "arm,mmu-500"; - reg =3D <0x0 0x14900000 0x0 0x10000>; - #iommu-cells =3D <2>; - #global-interrupts =3D <5>; - interrupts =3D , /* Global secure faul= t */ - , /* Global non-secure fault */ - , /* Combined secure interrupt */ - , /* Combined non-secure interru= pt */ - /* Performance counter interrupts */ - , /* for PERIC */ - /* Per context non-secure context interrupts, 0-1 interrupts */ - , /* for CONTEXT_0 */ - ; /* for CONTEXT_1 */ - }; - - smmu_fsys0: iommu@15450000 { - compatible =3D "arm,mmu-500"; - reg =3D <0x0 0x15450000 0x0 0x10000>; - #iommu-cells =3D <2>; - #global-interrupts =3D <5>; - interrupts =3D , /* Global secure faul= t */ - , /* Global non-secure fault */ - , /* Combined secure interrupt */ - , /* Combined non-secure interrup= t */ - /* Performance counter interrupts */ - , /* for FSYS0 */ - /* Per context non-secure context interrupts, 0-1 interrupts */ - , /* for CONTEXT_0 */ - ; /* for CONTEXT_1 */ - }; - - clock_imem: clock-controller@10010000 { - compatible =3D "tesla,fsd-clock-imem"; - reg =3D <0x0 0x10010000 0x0 0x3000>; - #clock-cells =3D <1>; - clocks =3D <&fin_pll>, - <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, - <&clock_cmu DOUT_CMU_IMEM_ACLK>, - <&clock_cmu DOUT_CMU_IMEM_DMACLK>; - clock-names =3D "fin_pll", - "dout_cmu_imem_tcuclk", - "dout_cmu_imem_aclk", - "dout_cmu_imem_dmaclk"; - }; - - clock_cmu: clock-controller@11c10000 { - compatible =3D "tesla,fsd-clock-cmu"; - reg =3D <0x0 0x11c10000 0x0 0x3000>; - #clock-cells =3D <1>; - clocks =3D <&fin_pll>; - clock-names =3D "fin_pll"; - }; - clock_csi: clock-controller@12610000 { compatible =3D "tesla,fsd-clock-cam_csi"; reg =3D <0x0 0x12610000 0x0 0x3000>; @@ -503,6 +543,15 @@ clock_mfc: clock-controller@12810000 { clock-names =3D "fin_pll"; }; =20 + mfc: mfc@12880000 { + compatible =3D "tesla,fsd-mfc"; + reg =3D <0x0 0x12880000 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>; + clock-names =3D "mfc"; + memory-region =3D <&mfc_left>; + }; + clock_peric: clock-controller@14010000 { compatible =3D "tesla,fsd-clock-peric"; reg =3D <0x0 0x14010000 0x0 0x3000>; @@ -526,80 +575,191 @@ sysreg_peric: system-controller@14030000 { reg =3D <0x0 0x14030000 0x0 0x1000>; }; =20 - clock_fsys0: clock-controller@15010000 { - compatible =3D "tesla,fsd-clock-fsys0"; - reg =3D <0x0 0x15010000 0x0 0x3000>; + m_can0: can@14088000 { + compatible =3D "bosch,m_can"; + reg =3D <0x0 0x14088000 0x0 0x0200>, + <0x0 0x14080000 0x0 0x8000>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + pinctrl-0 =3D <&m_can0_bus>; + pinctrl-names =3D "default"; + clocks =3D <&clock_peric PERIC_MCAN0_IPCLKPORT_PCLK>, + <&clock_peric PERIC_MCAN0_IPCLKPORT_CCLK>; + clock-names =3D "hclk", "cclk"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + + status =3D "disabled"; + }; + + m_can1: can@14098000 { + compatible =3D "bosch,m_can"; + reg =3D <0x0 0x14098000 0x0 0x0200>, + <0x0 0x14090000 0x0 0x8000>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + pinctrl-0 =3D <&m_can1_bus>; + pinctrl-names =3D "default"; + clocks =3D <&clock_peric PERIC_MCAN1_IPCLKPORT_PCLK>, + <&clock_peric PERIC_MCAN1_IPCLKPORT_CCLK>; + clock-names =3D "hclk", "cclk"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + + status =3D "disabled"; + }; + + m_can2: can@140a8000 { + compatible =3D "bosch,m_can"; + reg =3D <0x0 0x140a8000 0x0 0x0200>, + <0x0 0x140a0000 0x0 0x8000>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + pinctrl-0 =3D <&m_can2_bus>; + pinctrl-names =3D "default"; + clocks =3D <&clock_peric PERIC_MCAN2_IPCLKPORT_PCLK>, + <&clock_peric PERIC_MCAN2_IPCLKPORT_CCLK>; + clock-names =3D "hclk", "cclk"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + + status =3D "disabled"; + }; + + m_can3: can@140b8000 { + compatible =3D "bosch,m_can"; + reg =3D <0x0 0x140b8000 0x0 0x0200>, + <0x0 0x140b0000 0x0 0x8000>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + pinctrl-0 =3D <&m_can3_bus>; + pinctrl-names =3D "default"; + clocks =3D <&clock_peric PERIC_MCAN3_IPCLKPORT_PCLK>, + <&clock_peric PERIC_MCAN3_IPCLKPORT_CCLK>; + clock-names =3D "hclk", "cclk"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + + status =3D "disabled"; + }; + + i2s_0: i2s@140e0000 { + compatible =3D "tesla,fsd-i2s"; + reg =3D <0x0 0x140e0000 0x0 0x100>; + interrupts =3D ; + dmas =3D <&pdma1 14>, <&pdma1 13>, <&pdma1 12>; + dma-names =3D "tx", "rx", "tx-sec"; #clock-cells =3D <1>; - clocks =3D <&fin_pll>, - <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, - <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, - <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; - clock-names =3D "fin_pll", - "dout_cmu_pll_shared0_div6", - "dout_cmu_fsys0_shared1div4", - "dout_cmu_fsys0_shared0div4"; + clocks =3D <&clock_peric PERIC_PCLK_TDM0>, + <&clock_peric PERIC_HCLK_TDM0>, + <&clock_peric PERIC_HCLK_TDM0>; + clock-names =3D "iis", "i2s_opclk0", "i2s_opclk1"; + pinctrl-0 =3D <&i2s0_bus>; + pinctrl-names =3D "default"; + #sound-dai-cells =3D <1>; + + status =3D "disabled"; }; =20 - sysreg_fsys0: system-controller@15030000 { - compatible =3D "tesla,fsd-fsys0-sysreg", "syscon"; - reg =3D <0x0 0x15030000 0x0 0x1000>; - }; - - clock_fsys1: clock-controller@16810000 { - compatible =3D "tesla,fsd-clock-fsys1"; - reg =3D <0x0 0x16810000 0x0 0x3000>; + i2s_1: i2s@140f0000 { + compatible =3D "tesla,fsd-i2s"; + reg =3D <0x0 0x140f0000 0x0 0x100>; + interrupts =3D ; + dmas =3D <&pdma1 17>, <&pdma1 16>, <&pdma1 15>; + dma-names =3D "tx", "rx", "tx-sec"; #clock-cells =3D <1>; - clocks =3D <&fin_pll>, - <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, - <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; - clock-names =3D "fin_pll", - "dout_cmu_fsys1_shared0div8", - "dout_cmu_fsys1_shared0div4"; + clocks =3D <&clock_peric PERIC_PCLK_TDM1>, + <&clock_peric PERIC_HCLK_TDM1>, + <&clock_peric PERIC_HCLK_TDM1>; + clock-names =3D "iis", "i2s_opclk0", "i2s_opclk1"; + pinctrl-0 =3D <&i2s1_bus>; + pinctrl-names =3D "default"; + #sound-dai-cells =3D <1>; + + status =3D "disabled"; }; =20 - sysreg_fsys1: system-controller@16830000 { - compatible =3D "tesla,fsd-fsys1-sysreg", "syscon"; - reg =3D <0x0 0x16830000 0x0 0x1000>; + pwm_0: pwm@14100000 { + compatible =3D "tesla,fsd-pwm", "samsung,exynos4210-pwm"; + reg =3D <0x0 0x14100000 0x0 0x100>; + samsung,pwm-outputs =3D <0>, <1>, <2>, <3>; + #pwm-cells =3D <3>; + clocks =3D <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; + clock-names =3D "timers"; + + status =3D "disabled"; }; =20 - mdma0: dma-controller@10100000 { - compatible =3D "arm,pl330", "arm,primecell"; - reg =3D <0x0 0x10100000 0x0 0x1000>; - interrupts =3D ; - #dma-cells =3D <1>; - clocks =3D <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; - clock-names =3D "apb_pclk"; - iommus =3D <&smmu_imem 0x800 0x0>; + pwm_1: pwm@14110000 { + compatible =3D "tesla,fsd-pwm", "samsung,exynos4210-pwm"; + reg =3D <0x0 0x14110000 0x0 0x100>; + samsung,pwm-outputs =3D <0>, <1>, <2>, <3>; + #pwm-cells =3D <3>; + clocks =3D <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; + clock-names =3D "timers"; + + status =3D "disabled"; }; =20 - mdma1: dma-controller@10110000 { - compatible =3D "arm,pl330", "arm,primecell"; - reg =3D <0x0 0x10110000 0x0 0x1000>; - interrupts =3D ; - #dma-cells =3D <1>; - clocks =3D <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; - clock-names =3D "apb_pclk"; - iommus =3D <&smmu_imem 0x801 0x0>; + spi_0: spi@14140000 { + compatible =3D "tesla,fsd-spi"; + reg =3D <0x0 0x14140000 0x0 0x100>; + interrupts =3D ; + dmas =3D <&pdma1 4>, <&pdma1 5>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clock_peric PERIC_PCLK_SPI0>, + <&clock_peric PERIC_SCLK_SPI0>; + clock-names =3D "spi", "spi_busclk0"; + pinctrl-0 =3D <&spi0_bus>; + pinctrl-names =3D "default"; + num-cs =3D <1>; + samsung,spi-src-clk =3D <0>; + + status =3D "disabled"; }; =20 - pdma0: dma-controller@14280000 { - compatible =3D "arm,pl330", "arm,primecell"; - reg =3D <0x0 0x14280000 0x0 0x1000>; - interrupts =3D ; - #dma-cells =3D <1>; - clocks =3D <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; - clock-names =3D "apb_pclk"; - iommus =3D <&smmu_peric 0x2 0x0>; + spi_1: spi@14150000 { + compatible =3D "tesla,fsd-spi"; + reg =3D <0x0 0x14150000 0x0 0x100>; + interrupts =3D ; + dmas =3D <&pdma1 6>, <&pdma1 7>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clock_peric PERIC_PCLK_SPI1>, + <&clock_peric PERIC_SCLK_SPI1>; + clock-names =3D "spi", "spi_busclk0"; + pinctrl-0 =3D <&spi1_bus>; + pinctrl-names =3D "default"; + num-cs =3D <1>; + samsung,spi-src-clk =3D <0>; + + status =3D "disabled"; }; =20 - pdma1: dma-controller@14290000 { - compatible =3D "arm,pl330", "arm,primecell"; - reg =3D <0x0 0x14290000 0x0 0x1000>; - interrupts =3D ; - #dma-cells =3D <1>; - clocks =3D <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; - clock-names =3D "apb_pclk"; - iommus =3D <&smmu_peric 0x1 0x0>; + spi_2: spi@14160000 { + compatible =3D "tesla,fsd-spi"; + reg =3D <0x0 0x14160000 0x0 0x100>; + interrupts =3D ; + dmas =3D <&pdma1 8>, <&pdma1 9>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clock_peric PERIC_PCLK_SPI2>, + <&clock_peric PERIC_SCLK_SPI2>; + clock-names =3D "spi", "spi_busclk0"; + pinctrl-0 =3D <&spi2_bus>; + pinctrl-names =3D "default"; + num-cs =3D <1>; + samsung,spi-src-clk =3D <0>; + + status =3D "disabled"; }; =20 serial_0: serial@14180000 { @@ -630,58 +790,10 @@ serial_1: serial@14190000 { status =3D "disabled"; }; =20 - pmu_system_controller: system-controller@11400000 { - compatible =3D "tesla,fsd-pmu", "samsung,exynos7-pmu", "syscon"; - reg =3D <0x0 0x11400000 0x0 0x5000>; - }; - - watchdog_0: watchdog@100a0000 { - compatible =3D "tesla,fsd-wdt", "samsung,exynos7-wdt"; - reg =3D <0x0 0x100a0000 0x0 0x100>; - interrupts =3D ; - samsung,syscon-phandle =3D <&pmu_system_controller>; - clocks =3D <&fin_pll>; - clock-names =3D "watchdog"; - }; - - watchdog_1: watchdog@100b0000 { - compatible =3D "tesla,fsd-wdt", "samsung,exynos7-wdt"; - reg =3D <0x0 0x100b0000 0x0 0x100>; - interrupts =3D ; - samsung,syscon-phandle =3D <&pmu_system_controller>; - clocks =3D <&fin_pll>; - clock-names =3D "watchdog"; - }; - - watchdog_2: watchdog@100c0000 { - compatible =3D "tesla,fsd-wdt", "samsung,exynos7-wdt"; - reg =3D <0x0 0x100c0000 0x0 0x100>; - interrupts =3D ; - samsung,syscon-phandle =3D <&pmu_system_controller>; - clocks =3D <&fin_pll>; - clock-names =3D "watchdog"; - }; - - pwm_0: pwm@14100000 { - compatible =3D "tesla,fsd-pwm", "samsung,exynos4210-pwm"; - reg =3D <0x0 0x14100000 0x0 0x100>; - samsung,pwm-outputs =3D <0>, <1>, <2>, <3>; - #pwm-cells =3D <3>; - clocks =3D <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; - clock-names =3D "timers"; - - status =3D "disabled"; - }; - - pwm_1: pwm@14110000 { - compatible =3D "tesla,fsd-pwm", "samsung,exynos4210-pwm"; - reg =3D <0x0 0x14110000 0x0 0x100>; - samsung,pwm-outputs =3D <0>, <1>, <2>, <3>; - #pwm-cells =3D <3>; - clocks =3D <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; - clock-names =3D "timers"; - - status =3D "disabled"; + pinctrl_peric: pinctrl@141f0000 { + compatible =3D "tesla,fsd-pinctrl"; + reg =3D <0x0 0x141f0000 0x0 0x1000>; + interrupts =3D ; }; =20 hsi2c_0: i2c@14200000 { @@ -796,218 +908,24 @@ hsi2c_7: i2c@14270000 { status =3D "disabled"; }; =20 - i2s_0: i2s@140e0000 { - compatible =3D "tesla,fsd-i2s"; - reg =3D <0x0 0x140e0000 0x0 0x100>; - interrupts =3D ; - dmas =3D <&pdma1 14>, <&pdma1 13>, <&pdma1 12>; - dma-names =3D "tx", "rx", "tx-sec"; - #clock-cells =3D <1>; - clocks =3D <&clock_peric PERIC_PCLK_TDM0>, - <&clock_peric PERIC_HCLK_TDM0>, - <&clock_peric PERIC_HCLK_TDM0>; - clock-names =3D "iis", "i2s_opclk0", "i2s_opclk1"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&i2s0_bus>; - #sound-dai-cells =3D <1>; - - status =3D "disabled"; + pdma0: dma-controller@14280000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0x14280000 0x0 0x1000>; + interrupts =3D ; + #dma-cells =3D <1>; + clocks =3D <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; + clock-names =3D "apb_pclk"; + iommus =3D <&smmu_peric 0x2 0x0>; }; =20 - i2s_1: i2s@140f0000 { - compatible =3D "tesla,fsd-i2s"; - reg =3D <0x0 0x140f0000 0x0 0x100>; - interrupts =3D ; - dmas =3D <&pdma1 17>, <&pdma1 16>, <&pdma1 15>; - dma-names =3D "tx", "rx", "tx-sec"; - #clock-cells =3D <1>; - clocks =3D <&clock_peric PERIC_PCLK_TDM1>, - <&clock_peric PERIC_HCLK_TDM1>, - <&clock_peric PERIC_HCLK_TDM1>; - clock-names =3D "iis", "i2s_opclk0", "i2s_opclk1"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&i2s1_bus>; - #sound-dai-cells =3D <1>; - - status =3D "disabled"; - }; - - pinctrl_pmu: pinctrl@114f0000 { - compatible =3D "tesla,fsd-pinctrl"; - reg =3D <0x0 0x114f0000 0x0 0x1000>; - }; - - pinctrl_peric: pinctrl@141f0000 { - compatible =3D "tesla,fsd-pinctrl"; - reg =3D <0x0 0x141f0000 0x0 0x1000>; - interrupts =3D ; - }; - - pinctrl_fsys0: pinctrl@15020000 { - compatible =3D "tesla,fsd-pinctrl"; - reg =3D <0x0 0x15020000 0x0 0x1000>; - interrupts =3D ; - }; - - m_can0: can@14088000 { - compatible =3D "bosch,m_can"; - reg =3D <0x0 0x14088000 0x0 0x0200>, - <0x0 0x14080000 0x0 0x8000>; - reg-names =3D "m_can", "message_ram"; - interrupts =3D , - ; - interrupt-names =3D "int0", "int1"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&m_can0_bus>; - clocks =3D <&clock_peric PERIC_MCAN0_IPCLKPORT_PCLK>, - <&clock_peric PERIC_MCAN0_IPCLKPORT_CCLK>; - clock-names =3D "hclk", "cclk"; - bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; - - status =3D "disabled"; - }; - - m_can1: can@14098000 { - compatible =3D "bosch,m_can"; - reg =3D <0x0 0x14098000 0x0 0x0200>, - <0x0 0x14090000 0x0 0x8000>; - reg-names =3D "m_can", "message_ram"; - interrupts =3D , - ; - interrupt-names =3D "int0", "int1"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&m_can1_bus>; - clocks =3D <&clock_peric PERIC_MCAN1_IPCLKPORT_PCLK>, - <&clock_peric PERIC_MCAN1_IPCLKPORT_CCLK>; - clock-names =3D "hclk", "cclk"; - bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; - - status =3D "disabled"; - }; - - m_can2: can@140a8000 { - compatible =3D "bosch,m_can"; - reg =3D <0x0 0x140a8000 0x0 0x0200>, - <0x0 0x140a0000 0x0 0x8000>; - reg-names =3D "m_can", "message_ram"; - interrupts =3D , - ; - interrupt-names =3D "int0", "int1"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&m_can2_bus>; - clocks =3D <&clock_peric PERIC_MCAN2_IPCLKPORT_PCLK>, - <&clock_peric PERIC_MCAN2_IPCLKPORT_CCLK>; - clock-names =3D "hclk", "cclk"; - bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; - - status =3D "disabled"; - }; - - m_can3: can@140b8000 { - compatible =3D "bosch,m_can"; - reg =3D <0x0 0x140b8000 0x0 0x0200>, - <0x0 0x140b0000 0x0 0x8000>; - reg-names =3D "m_can", "message_ram"; - interrupts =3D , - ; - interrupt-names =3D "int0", "int1"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&m_can3_bus>; - clocks =3D <&clock_peric PERIC_MCAN3_IPCLKPORT_PCLK>, - <&clock_peric PERIC_MCAN3_IPCLKPORT_CCLK>; - clock-names =3D "hclk", "cclk"; - bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; - - status =3D "disabled"; - }; - - spi_0: spi@14140000 { - compatible =3D "tesla,fsd-spi"; - reg =3D <0x0 0x14140000 0x0 0x100>; - interrupts =3D ; - dmas =3D <&pdma1 4>, <&pdma1 5>; - dma-names =3D "tx", "rx"; - #address-cells =3D <1>; - #size-cells =3D <0>; - clocks =3D <&clock_peric PERIC_PCLK_SPI0>, - <&clock_peric PERIC_SCLK_SPI0>; - clock-names =3D "spi", "spi_busclk0"; - samsung,spi-src-clk =3D <0>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&spi0_bus>; - num-cs =3D <1>; - - status =3D "disabled"; - }; - - spi_1: spi@14150000 { - compatible =3D "tesla,fsd-spi"; - reg =3D <0x0 0x14150000 0x0 0x100>; - interrupts =3D ; - dmas =3D <&pdma1 6>, <&pdma1 7>; - dma-names =3D "tx", "rx"; - #address-cells =3D <1>; - #size-cells =3D <0>; - clocks =3D <&clock_peric PERIC_PCLK_SPI1>, - <&clock_peric PERIC_SCLK_SPI1>; - clock-names =3D "spi", "spi_busclk0"; - samsung,spi-src-clk =3D <0>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&spi1_bus>; - num-cs =3D <1>; - - status =3D "disabled"; - }; - - spi_2: spi@14160000 { - compatible =3D "tesla,fsd-spi"; - reg =3D <0x0 0x14160000 0x0 0x100>; - interrupts =3D ; - dmas =3D <&pdma1 8>, <&pdma1 9>; - dma-names =3D "tx", "rx"; - #address-cells =3D <1>; - #size-cells =3D <0>; - clocks =3D <&clock_peric PERIC_PCLK_SPI2>, - <&clock_peric PERIC_SCLK_SPI2>; - clock-names =3D "spi", "spi_busclk0"; - samsung,spi-src-clk =3D <0>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&spi2_bus>; - num-cs =3D <1>; - - status =3D "disabled"; - }; - - timer@10040000 { - compatible =3D "tesla,fsd-mct", "samsung,exynos4210-mct"; - reg =3D <0x0 0x10040000 0x0 0x800>; - interrupts =3D , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks =3D <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; - clock-names =3D "fin_pll", "mct"; - }; - - mfc: mfc@12880000 { - compatible =3D "tesla,fsd-mfc"; - reg =3D <0x0 0x12880000 0x0 0x10000>; - interrupts =3D ; - clock-names =3D "mfc"; - clocks =3D <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>; - memory-region =3D <&mfc_left>; + pdma1: dma-controller@14290000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0x14290000 0x0 0x1000>; + interrupts =3D ; + #dma-cells =3D <1>; + clocks =3D <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; + clock-names =3D "apb_pclk"; + iommus =3D <&smmu_peric 0x1 0x0>; }; =20 ethernet1: ethernet@14300000 { @@ -1041,6 +959,47 @@ ethernet1: ethernet@14300000 { status =3D "disabled"; }; =20 + smmu_peric: iommu@14900000 { + compatible =3D "arm,mmu-500"; + reg =3D <0x0 0x14900000 0x0 0x10000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <5>; + interrupts =3D , /* Global secure faul= t */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interru= pt */ + /* Performance counter interrupts */ + , /* for PERIC */ + /* Per context non-secure context interrupts, 0-1 interrupts */ + , /* for CONTEXT_0 */ + ; /* for CONTEXT_1 */ + }; + + clock_fsys0: clock-controller@15010000 { + compatible =3D "tesla,fsd-clock-fsys0"; + reg =3D <0x0 0x15010000 0x0 0x3000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, + <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, + <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; + clock-names =3D "fin_pll", + "dout_cmu_pll_shared0_div6", + "dout_cmu_fsys0_shared1div4", + "dout_cmu_fsys0_shared0div4"; + }; + + pinctrl_fsys0: pinctrl@15020000 { + compatible =3D "tesla,fsd-pinctrl"; + reg =3D <0x0 0x15020000 0x0 0x1000>; + interrupts =3D ; + }; + + sysreg_fsys0: system-controller@15030000 { + compatible =3D "tesla,fsd-fsys0-sysreg", "syscon"; + reg =3D <0x0 0x15030000 0x0 0x1000>; + }; + ufs: ufs@15120000 { compatible =3D "tesla,fsd-ufs"; reg =3D <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */ @@ -1091,6 +1050,47 @@ ethernet0: ethernet@15300000 { =20 status =3D "disabled"; }; + + smmu_fsys0: iommu@15450000 { + compatible =3D "arm,mmu-500"; + reg =3D <0x0 0x15450000 0x0 0x10000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <5>; + interrupts =3D , /* Global secure faul= t */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrup= t */ + /* Performance counter interrupts */ + , /* for FSYS0 */ + /* Per context non-secure context interrupts, 0-1 interrupts */ + , /* for CONTEXT_0 */ + ; /* for CONTEXT_1 */ + }; + + clock_fsys1: clock-controller@16810000 { + compatible =3D "tesla,fsd-clock-fsys1"; + reg =3D <0x0 0x16810000 0x0 0x3000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; + clock-names =3D "fin_pll", + "dout_cmu_fsys1_shared0div8", + "dout_cmu_fsys1_shared0div4"; + }; + + sysreg_fsys1: system-controller@16830000 { + compatible =3D "tesla,fsd-fsys1-sysreg", "syscon"; + reg =3D <0x0 0x16830000 0x0 0x1000>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; }; }; =20 --=20 2.53.0 From nobody Fri Sep 25 18:24:35 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6EF5580383 for ; Wed, 9 Sep 2026 14:18:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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=20 reserved-memory { + ranges; #address-cells =3D <2>; #size-cells =3D <2>; - ranges; =20 mfc_left: region@84000000 { compatible =3D "shared-dma-pool"; - no-map; reg =3D <0 0x84000000 0 0x8000000>; + no-map; }; }; =20 soc: soc@0 { compatible =3D "simple-bus"; - #address-cells =3D <2>; - #size-cells =3D <2>; ranges =3D <0x0 0x0 0x0 0x0 0x0 0x18000000>; dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + #address-cells =3D <2>; + #size-cells =3D <2>; =20 clock_imem: clock-controller@10010000 { compatible =3D "tesla,fsd-clock-imem"; @@ -468,11 +468,11 @@ smmu_imem: iommu@10200000 { =20 gic: interrupt-controller@10400000 { compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x10400000 0x0 0x10000>, /* GICD */ + <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ #address-cells =3D <0>; #interrupt-cells =3D <3>; interrupt-controller; - reg =3D <0x0 0x10400000 0x0 0x10000>, /* GICD */ - <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ interrupts =3D ; }; =20 @@ -686,10 +686,10 @@ i2s_1: i2s@140f0000 { pwm_0: pwm@14100000 { compatible =3D "tesla,fsd-pwm", "samsung,exynos4210-pwm"; reg =3D <0x0 0x14100000 0x0 0x100>; - samsung,pwm-outputs =3D <0>, <1>, <2>, <3>; #pwm-cells =3D <3>; clocks =3D <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; clock-names =3D "timers"; + samsung,pwm-outputs =3D <0>, <1>, <2>, <3>; =20 status =3D "disabled"; }; @@ -697,10 +697,10 @@ pwm_0: pwm@14100000 { pwm_1: pwm@14110000 { compatible =3D "tesla,fsd-pwm", "samsung,exynos4210-pwm"; reg =3D <0x0 0x14110000 0x0 0x100>; - samsung,pwm-outputs =3D <0>, <1>, <2>, <3>; #pwm-cells =3D <3>; clocks =3D <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; clock-names =3D "timers"; + samsung,pwm-outputs =3D <0>, <1>, <2>, <3>; =20 status =3D "disabled"; }; @@ -802,8 +802,8 @@ hsi2c_0: i2c@14200000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&hs_i2c0_bus>; + pinctrl-names =3D "default"; clocks =3D <&clock_peric PERIC_PCLK_HSI2C0>; clock-names =3D "hsi2c"; =20 @@ -816,8 +816,8 @@ hsi2c_1: i2c@14210000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&hs_i2c1_bus>; + pinctrl-names =3D "default"; clocks =3D <&clock_peric PERIC_PCLK_HSI2C1>; clock-names =3D "hsi2c"; =20 @@ -830,8 +830,8 @@ hsi2c_2: i2c@14220000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&hs_i2c2_bus>; + pinctrl-names =3D "default"; clocks =3D <&clock_peric PERIC_PCLK_HSI2C2>; clock-names =3D "hsi2c"; =20 @@ -844,8 +844,8 @@ hsi2c_3: i2c@14230000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&hs_i2c3_bus>; + pinctrl-names =3D "default"; clocks =3D <&clock_peric PERIC_PCLK_HSI2C3>; clock-names =3D "hsi2c"; =20 @@ -858,8 +858,8 @@ hsi2c_4: i2c@14240000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&hs_i2c4_bus>; + pinctrl-names =3D "default"; clocks =3D <&clock_peric PERIC_PCLK_HSI2C4>; clock-names =3D "hsi2c"; =20 @@ -872,8 +872,8 @@ hsi2c_5: i2c@14250000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&hs_i2c5_bus>; + pinctrl-names =3D "default"; clocks =3D <&clock_peric PERIC_PCLK_HSI2C5>; clock-names =3D "hsi2c"; =20 @@ -886,8 +886,8 @@ hsi2c_6: i2c@14260000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&hs_i2c6_bus>; + pinctrl-names =3D "default"; clocks =3D <&clock_peric PERIC_PCLK_HSI2C6>; clock-names =3D "hsi2c"; =20 @@ -900,8 +900,8 @@ hsi2c_7: i2c@14270000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&hs_i2c7_bus>; + pinctrl-names =3D "default"; clocks =3D <&clock_peric PERIC_PCLK_HSI2C7>; clock-names =3D "hsi2c"; =20 @@ -949,10 +949,10 @@ ethernet1: ethernet@14300000 { assigned-clocks =3D <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>, <&clock_peric PERIC_EQOS_PHYRXCLK>; assigned-clock-parents =3D <&clock_peric PERIC_EQOS_PHYRXCLK>; - pinctrl-names =3D "default"; pinctrl-0 =3D <ð1_tx_clk>, <ð1_tx_data>, <ð1_tx_ctrl>, <ð1_phy_intr>, <ð1_rx_clk>, <ð1_rx_data>, <ð1_rx_ctrl>, <ð1_mdio>; + pinctrl-names =3D "default"; local-mac-address =3D [00 00 00 00 00 00]; iommus =3D <&smmu_peric 0x0 0x1>; =20 @@ -1012,8 +1012,8 @@ ufs: ufs@15120000 { <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>; clock-names =3D "core_clk", "sclk_unipro_main"; freq-table-hz =3D <0 0>, <0 0>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&ufs_rst_n &ufs_refclk_out>; + pinctrl-names =3D "default"; phys =3D <&ufs_phy>; phy-names =3D "ufs-phy"; =20 @@ -1024,10 +1024,10 @@ ufs_phy: ufs-phy@15124000 { compatible =3D "tesla,fsd-ufs-phy"; reg =3D <0x0 0x15124000 0x0 0x800>; reg-names =3D "phy-pma"; - samsung,pmu-syscon =3D <&pmu_system_controller>; #phy-cells =3D <0>; clocks =3D <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>; clock-names =3D "ref_clk"; + samsung,pmu-syscon =3D <&pmu_system_controller>; }; =20 ethernet0: ethernet@15300000 { @@ -1041,10 +1041,10 @@ ethernet0: ethernet@15300000 { <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I>, <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I>; clock-names =3D "ptp_ref", "master_bus", "slave_bus", "tx", "rx"; - pinctrl-names =3D "default"; pinctrl-0 =3D <ð0_tx_clk>, <ð0_tx_data>, <ð0_tx_ctrl>, <ð0_phy_intr>, <ð0_rx_clk>, <ð0_rx_data>, <ð0_rx_ctrl>, <ð0_mdio>; + pinctrl-names =3D "default"; local-mac-address =3D [00 00 00 00 00 00]; iommus =3D <&smmu_fsys0 0x0 0x1>; =20 --=20 2.53.0