From nobody Fri Sep 25 18:27:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6E8C56E064; Wed, 9 Sep 2026 14:14:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788963263; cv=none; b=R/qHXZQ5BMj5uAWfVqMjNQa/5SFvRL+14XG5/ph653nHCN6G9hkOKHMcv+IbB8oV/hJSQexhLH90/Kft6kIEWUf+yd2qFzKaGBysfYl5heGmhaBXGXO/+kjhjhTXf3uyI/WHohzBWkFlQ9DM4S8oYD6TIcC/TGNgiUMqBXC2CEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788963263; c=relaxed/simple; bh=9/hL1L/RgVcYwPOX97dzhmc2ixM8V+eqpLWH0ghP9Mk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eaXObDabwui0PrFECHj3HrkPIsUbJkaaHRTKZt/pY/L8KcHHeY+WaIhBrZujBZMoCK/zmYqYTAcYOFA9ykrAEcbSd01sdWmgI1COOQpqFybAp7LzVN5EjOSc3MTuSPkuSLH9ePNAb3cpSgT4SvDup15lODduNOES+nG12SHhFXw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HHp3TTjG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HHp3TTjG" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4564FC2BCB9; Wed, 9 Sep 2026 14:14:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788963263; bh=9/hL1L/RgVcYwPOX97dzhmc2ixM8V+eqpLWH0ghP9Mk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HHp3TTjGCsSmUkLNpPve5n1n/X9evKMmtERHHUnOsMQ3AIxGmQbNQs2EEn5BysWnc PJ08B6wBNy2TTEf4OifrpQIwRXXOdxh4mdcOmjKI0vmBQN/ReZnnbAVTJ/3naQlvBw YrEJ1Ul2Q0RKmkt2jDsDf+0BZDYKeiyFfSYmrXPcHS+pSAtI9TgEfaLcfgUScDpewI zJoJU/HNucGQw7xhw/lf/HCE35SMWcvoQzrdlwRBbhS2yb0kNp+bvGeZPbh2oPOuoV 8gtLQQ9fl800VIoAINY4Jzj3Fdr5tIWDSawfAKs689v3Lo0PWkZ+SJ3DHlEV85FL3t GXHxQlTE+kAQQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F9D7C79FB6; Wed, 9 Sep 2026 14:14:23 +0000 (UTC) From: Roman Vivchar via B4 Relay Date: Wed, 09 Sep 2026 17:14:05 +0300 Subject: [PATCH 1/3] dt-bindings: iommu: mediatek: add mt6572 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260909-6572-iommu-v1-1-de261da09fb2@protonmail.com> References: <20260909-6572-iommu-v1-0-de261da09fb2@protonmail.com> In-Reply-To: <20260909-6572-iommu-v1-0-de261da09fb2@protonmail.com> To: Yong Wu , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: iommu@lists.linux.dev, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roman Vivchar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788963261; l=2837; i=rva333@protonmail.com; s=20260510; h=from:subject:message-id; bh=dwxNgLWUiyagGRngvUTXF8Q3mn0Z/8Gp90+ec/HbfQE=; b=8zBKc+fTvUi9pPpdPzfAzxaZDGX72EAiENZ4TSMrwd7adwi6lVA7T1qT0eczdmcib3XGbCsMi +DXU9U7VFidBMcOTDMSr/H823ERdWDuT6q9iwd0tD/LuitQr5U+vqO4 X-Developer-Key: i=rva333@protonmail.com; a=ed25519; pk=zww/nWjBGoQ4POXCG0BV6fx2iuXK6jx77rsKPA5YK5Y= X-Endpoint-Received: by B4 Relay for rva333@protonmail.com/20260510 with auth_id=777 X-Original-From: Roman Vivchar Reply-To: rva333@protonmail.com From: Roman Vivchar Add compatible string and header file for mt6572 IOMMU support. Signed-off-by: Roman Vivchar Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/iommu/mediatek,iommu.yaml | 3 +++ .../memory/mediatek,mt6572-memory-port.h | 26 ++++++++++++++++++= ++++ 2 files changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/= Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 79c573c47b08..d0ac4bd71911 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -72,6 +72,7 @@ properties: - enum: - mediatek,mt2701-m4u # generation one - mediatek,mt2712-m4u # generation two + - mediatek,mt6572-m4u # generation one - mediatek,mt6779-m4u # generation two - mediatek,mt6795-m4u # generation two - mediatek,mt6893-iommu-mm # generation two @@ -134,6 +135,7 @@ properties: dt-binding/memory/mediatek,mt8189-memory-port.h for mt8189, dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, dt-binding/memory/mt2712-larb-port.h for mt2712, + dt-binding/memory/mediatek,mt6572-memory-port.h for mt6572, dt-binding/memory/mt6779-larb-port.h for mt6779, dt-binding/memory/mt6795-larb-port.h for mt6795, dt-binding/memory/mediatek,mt6893-memory-port.h for mt6893, @@ -162,6 +164,7 @@ allOf: enum: - mediatek,mt2701-m4u - mediatek,mt2712-m4u + - mediatek,mt6572-m4u - mediatek,mt6795-m4u - mediatek,mt6893-iommu-mm - mediatek,mt8173-m4u diff --git a/include/dt-bindings/memory/mediatek,mt6572-memory-port.h b/inc= lude/dt-bindings/memory/mediatek,mt6572-memory-port.h new file mode 100644 index 000000000000..6f8ddc98f1b1 --- /dev/null +++ b/include/dt-bindings/memory/mediatek,mt6572-memory-port.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2026 Roman Vivchar + */ + +#ifndef _DT_BINDINGS_MEMORY_MT6572_MEMORY_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT6572_MEMORY_PORT_H_ + +#define M4U_PORT_DISP_OVL 0 +#define M4U_PORT_DISP_RDMA 1 +#define M4U_PORT_DISP_WDMA 2 +#define M4U_PORT_DISP_DBI 3 +#define M4U_PORT_CAM_WDMA 4 +#define M4U_PORT_CMDQ 5 +#define M4U_PORT_VENC_BSDMA_VDEC_POST0 6 +#define M4U_PORT_MDP_RDMA 7 +#define M4U_PORT_MDP_WDMA 8 +#define M4U_PORT_MDP_ROTO 9 +#define M4U_PORT_MDP_ROTCO 10 +#define M4U_PORT_MDP_ROTVO 11 +#define M4U_PORT_VENC_MVQP 12 +#define M4U_PORT_VENC_MC 13 +#define M4U_PORT_VENC_CDMA_VDEC_CDMA 14 +#define M4U_PORT_VENC_REC_VDEC_WDMA 15 + +#endif --=20 2.55.0 From nobody Fri Sep 25 18:27:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7152572695; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260909-6572-iommu-v1-2-de261da09fb2@protonmail.com> References: <20260909-6572-iommu-v1-0-de261da09fb2@protonmail.com> In-Reply-To: <20260909-6572-iommu-v1-0-de261da09fb2@protonmail.com> To: Yong Wu , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: iommu@lists.linux.dev, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roman Vivchar , stable@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788963261; l=4888; i=rva333@protonmail.com; s=20260510; h=from:subject:message-id; bh=EcGIcOox9foAPPSzCZAPzZ4As2FunuolmFilHRQ5qcg=; b=soNtO8zKf8oyMiaDfTmWSrvH5R6+Rzyfb/MHjpHC1PLcyTcvCY4+RsyYiRV/GmHNQ5XuEQcZL 2eh4Z8weCS2AwlTxK5SzzdxX4aW+pOYoocewtcaUIK+KIP3UxUMNLTs X-Developer-Key: i=rva333@protonmail.com; a=ed25519; pk=zww/nWjBGoQ4POXCG0BV6fx2iuXK6jx77rsKPA5YK5Y= X-Endpoint-Received: by B4 Relay for rva333@protonmail.com/20260510 with auth_id=777 X-Original-From: Roman Vivchar Reply-To: rva333@protonmail.com From: Roman Vivchar Currently the driver silently fails to bind devices and DRM subsystem (which is the primary IOMMU user on MediaTek SoCs) falls back to PA mode. Fix this by providing of_xlate callback, which lets the driver actually bind devices and use VA mode. The fix can be verified by reading overlay engine input address. Before: ~ # devmem 0x14007040 32 0xBB900000 After: ~ # devmem 0x14007040 32 0x00000000 Fixes: b17336c55d89 ("iommu/mediatek: add support for mtk iommu generation = one HW") Cc: stable@vger.kernel.org Signed-off-by: Roman Vivchar --- Untested on mt2701. --- drivers/iommu/mtk_iommu_v1.c | 86 ++++++++++++++++++++--------------------= ---- 1 file changed, 39 insertions(+), 47 deletions(-) diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c index ac97dd2868d4..72355f41c36a 100644 --- a/drivers/iommu/mtk_iommu_v1.c +++ b/drivers/iommu/mtk_iommu_v1.c @@ -413,38 +413,10 @@ static const struct iommu_ops mtk_iommu_v1_ops; * MTK generation one iommu HW only support one iommu domain, and all the = client * sharing the same iova address space. */ -static int mtk_iommu_v1_create_mapping(struct device *dev, - const struct of_phandle_args *args) +static int mtk_iommu_v1_create_mapping(struct device *dev) { struct mtk_iommu_v1_data *data; - struct platform_device *m4updev; struct dma_iommu_mapping *mtk_mapping; - int ret; - - if (args->args_count !=3D 1) { - dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", - args->args_count); - return -EINVAL; - } - - ret =3D iommu_fwspec_init(dev, of_fwnode_handle(args->np)); - if (ret) - return ret; - - if (!dev_iommu_priv_get(dev)) { - /* Get the m4u device */ - m4updev =3D of_find_device_by_node(args->np); - if (WARN_ON(!m4updev)) - return -EINVAL; - - dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); - - put_device(&m4updev->dev); - } - - ret =3D iommu_fwspec_add_ids(dev, args->args, 1); - if (ret) - return ret; =20 data =3D dev_iommu_priv_get(dev); mtk_mapping =3D data->mapping; @@ -462,27 +434,12 @@ static int mtk_iommu_v1_create_mapping(struct device = *dev, =20 static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev) { - struct iommu_fwspec *fwspec =3D NULL; - struct of_phandle_args iommu_spec; + struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); struct mtk_iommu_v1_data *data; - int err, idx =3D 0, larbid, larbidx; + int idx, larbid, larbidx; struct device_link *link; struct device *larbdev; =20 - while (!of_parse_phandle_with_args(dev->of_node, "iommus", - "#iommu-cells", - idx, &iommu_spec)) { - - err =3D mtk_iommu_v1_create_mapping(dev, &iommu_spec); - of_node_put(iommu_spec.np); - if (err) - return ERR_PTR(err); - - /* dev->iommu_fwspec might have changed */ - fwspec =3D dev_iommu_fwspec_get(dev); - idx++; - } - if (!fwspec) return ERR_PTR(-ENODEV); =20 @@ -519,9 +476,15 @@ static void mtk_iommu_v1_probe_finalize(struct device = *dev) __maybe_unused struct mtk_iommu_v1_data *data =3D dev_iommu_priv_get(dev); int err; =20 + err =3D mtk_iommu_v1_create_mapping(dev); + if (err) { + dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); + return; + } + err =3D arm_iommu_attach_device(dev, data->mapping); if (err) - dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); + dev_err(dev, "Can't attach to IOMMU mapping - DMA-OPS will not work\n"); } =20 static void mtk_iommu_v1_release_device(struct device *dev) @@ -537,6 +500,34 @@ static void mtk_iommu_v1_release_device(struct device = *dev) device_link_remove(dev, larbdev); } =20 +static int mtk_iommu_v1_of_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct platform_device *m4updev; + int ret; + + if (args->args_count !=3D 1) { + dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", + args->args_count); + return -EINVAL; + } + + ret =3D iommu_fwspec_init(dev, of_fwnode_handle(args->np)); + if (ret) + return ret; + + if (!dev_iommu_priv_get(dev)) { + m4updev =3D of_find_device_by_node(args->np); + if (WARN_ON(!m4updev)) + return -EINVAL; + + dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); + put_device(&m4updev->dev); + } + + return iommu_fwspec_add_ids(dev, args->args, 1); +} + static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data) { u32 regval; @@ -585,6 +576,7 @@ static const struct iommu_ops mtk_iommu_v1_ops =3D { .probe_finalize =3D mtk_iommu_v1_probe_finalize, .release_device =3D mtk_iommu_v1_release_device, .device_group =3D generic_device_group, + .of_xlate =3D mtk_iommu_v1_of_xlate, .owner =3D THIS_MODULE, .default_domain_ops =3D &(const struct iommu_domain_ops) { .attach_dev =3D mtk_iommu_v1_attach_device, --=20 2.55.0 From nobody Fri Sep 25 18:27:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A702D572692; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260909-6572-iommu-v1-3-de261da09fb2@protonmail.com> References: <20260909-6572-iommu-v1-0-de261da09fb2@protonmail.com> In-Reply-To: <20260909-6572-iommu-v1-0-de261da09fb2@protonmail.com> To: Yong Wu , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: iommu@lists.linux.dev, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roman Vivchar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788963261; l=5880; i=rva333@protonmail.com; s=20260510; h=from:subject:message-id; bh=Q9DENazAgwi3T2qykCPLy9Ktvy2jjfeMJUql9cSW4PY=; b=8+P8cpShisgwoJq0VZRjZTKZLtcBmRIMxKVIDut/OQ5H+DuS0IRCr8OkGmuFQBBntJL5u+eAM gSO9ctW66BlAB6sGh2wQRaETyPAsSTIhioXn1Gf/IaQj0ZaS0FCL5+k X-Developer-Key: i=rva333@protonmail.com; a=ed25519; pk=zww/nWjBGoQ4POXCG0BV6fx2iuXK6jx77rsKPA5YK5Y= X-Endpoint-Received: by B4 Relay for rva333@protonmail.com/20260510 with auth_id=777 X-Original-From: Roman Vivchar Reply-To: rva333@protonmail.com From: Roman Vivchar mt6572 SoC utilizes an earlier version of the IOMMU, that shares the same v1 architecture, but has minor hardware differences compared to mt2701. Introduce mtk_iommu_type to distinguish between mt2701 and mt6572 variant and apply the necessary logic. Finally, add a platform data for the mt6572 SoC. Signed-off-by: Roman Vivchar --- Based on my downstream findings, this change may also support mt6582 SoC, but I don't have the hardware to test if it actually works. --- drivers/iommu/mtk_iommu_v1.c | 72 +++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 55 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c index 72355f41c36a..b6f547b100d1 100644 --- a/drivers/iommu/mtk_iommu_v1.c +++ b/drivers/iommu/mtk_iommu_v1.c @@ -7,6 +7,7 @@ * * Based on driver/iommu/mtk_iommu.c */ +#include #include #include #include @@ -85,6 +86,13 @@ struct dma_iommu_mapping { #define F_DESC_NONSEC BIT(3) #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) + +#define MT6572_MMU_INT_ID_PORT_ID GENMASK(12, 8) +#define MT6572_MMU_INT_ID_LARB_ID GENMASK(14, 13) + +#define MT6572_M4U_TF_PORT(TF) FIELD_GET(MT6572_MMU_INT_ID_PORT_ID, TF) +#define MT6572_M4U_TF_LARB(TF) (FIELD_GET(MT6572_MMU_INT_ID_LARB_ID, TF)= - 1) + /* MTK generation one iommu HW only support 4K size mapping */ #define MT2701_IOMMU_PAGE_SHIFT 12 #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) @@ -96,6 +104,11 @@ struct dma_iommu_mapping { */ #define M2701_IOMMU_PGT_SIZE SZ_4M =20 +enum mtk_iommu_type { + MTK_IOMMU_MT6572, + MTK_IOMMU_V1, +}; + struct mtk_iommu_v1_suspend_reg { u32 standard_axi_mode; u32 dcm_dis; @@ -116,6 +129,8 @@ struct mtk_iommu_v1_data { struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; =20 struct mtk_iommu_v1_suspend_reg reg; + + enum mtk_iommu_type type; }; =20 struct mtk_iommu_v1_domain { @@ -170,8 +185,12 @@ static inline int mt2701_m4u_to_port(int id) =20 static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data) { - writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, - data->base + REG_MMU_INV_SEL); + u32 val =3D F_INVLD_EN0; + + if (data->type =3D=3D MTK_IOMMU_V1) + val |=3D F_INVLD_EN1; + + writel_relaxed(val, data->base + REG_MMU_INV_SEL); writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); wmb(); /* Make sure the tlb flush all done */ } @@ -180,25 +199,33 @@ static void mtk_iommu_v1_tlb_flush_range(struct mtk_i= ommu_v1_data *data, unsigned long iova, size_t size) { int ret; - u32 tmp; + u32 tmp, val =3D F_INVLD_EN0; =20 - writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, - data->base + REG_MMU_INV_SEL); + if (data->type =3D=3D MTK_IOMMU_V1) + val |=3D F_INVLD_EN1; + + writel_relaxed(val, data->base + REG_MMU_INV_SEL); writel_relaxed(iova & F_MMU_FAULT_VA_MSK, data->base + REG_MMU_INVLD_START_A); writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, data->base + REG_MMU_INVLD_END_A); writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); =20 - ret =3D readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, - tmp, tmp !=3D 0, 10, 100000); - if (ret) { - dev_warn(data->dev, - "Partial TLB flush timed out, falling back to full flush\n"); - mtk_iommu_v1_tlb_flush_all(data); + if (data->type =3D=3D MTK_IOMMU_V1) { + ret =3D readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, + tmp, tmp !=3D 0, 10, 100000); + if (ret) { + dev_warn(data->dev, + "Partial TLB flush timed out, falling back to full flush\n"); + mtk_iommu_v1_tlb_flush_all(data); + } + + /* Clear the CPE status */ + writel_relaxed(0, data->base + REG_MMU_CPE_DONE); + } else { + /* Make sure the TLB flush is done */ + wmb(); } - /* Clear the CPE status */ - writel_relaxed(0, data->base + REG_MMU_CPE_DONE); } =20 static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id) @@ -215,8 +242,14 @@ static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev= _id) fault_iova &=3D F_MMU_FAULT_VA_MSK; fault_pa =3D readl_relaxed(data->base + REG_MMU_INVLD_PA); regval =3D readl_relaxed(data->base + REG_MMU_INT_ID); - fault_larb =3D MT2701_M4U_TF_LARB(regval); - fault_port =3D MT2701_M4U_TF_PORT(regval); + + if (data->type =3D=3D MTK_IOMMU_V1) { + fault_larb =3D MT2701_M4U_TF_LARB(regval); + fault_port =3D MT2701_M4U_TF_PORT(regval); + } else { + fault_larb =3D MT6572_M4U_TF_LARB(regval); + fault_port =3D MT6572_M4U_TF_PORT(regval); + } =20 /* * MTK v1 iommu HW could not determine whether the fault is read or @@ -539,7 +572,10 @@ static int mtk_iommu_v1_hw_init(const struct mtk_iommu= _v1_data *data) return ret; } =20 - regval =3D F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); + regval =3D F_MMU_TF_PROTECT_SEL(2); + if (data->type =3D=3D MTK_IOMMU_V1) + regval |=3D F_MMU_CTRL_COHERENT_EN; + writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); =20 regval =3D F_INT_TRANSLATION_FAULT | @@ -588,7 +624,8 @@ static const struct iommu_ops mtk_iommu_v1_ops =3D { }; =20 static const struct of_device_id mtk_iommu_v1_of_ids[] =3D { - { .compatible =3D "mediatek,mt2701-m4u", }, + { .compatible =3D "mediatek,mt2701-m4u", .data =3D (void *)MTK_IOMMU_V1 }, + { .compatible =3D "mediatek,mt6572-m4u", .data =3D (void *)MTK_IOMMU_MT65= 72 }, {} }; MODULE_DEVICE_TABLE(of, mtk_iommu_v1_of_ids); @@ -612,6 +649,7 @@ static int mtk_iommu_v1_probe(struct platform_device *p= dev) return -ENOMEM; =20 data->dev =3D dev; + data->type =3D (enum mtk_iommu_type)(uintptr_t)of_device_get_match_data(d= ev); =20 /* Protect memory. HW will access here while translation fault.*/ protect =3D devm_kcalloc(dev, 2, MTK_PROTECT_PA_ALIGN, --=20 2.55.0