From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 010E057269D; Tue, 8 Sep 2026 16:22:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884574; cv=none; b=FdI8O3JMHCYUrrf9ggrNz5s3enBNwPZZZnao7f5ThZJ51oBkiC+S7lPhJiQZZTsEbzQoVidL+mZdZ+qJmVcyG5OK+24zk5Tm6UtvvfP90H2mv0SNEX1ZFLZot+e3jzudnbdRrlxU8+W1oESGZ8ZAVlE6L38ZkPicV1EtgqREWuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884574; c=relaxed/simple; bh=47zEMqoqsoiKg7tbbReEvjkQybQ6brogsshUzI3uxgI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PKOHaStaW7g4raqETWKiYUIjp+kwmyEOQABwNIBiF1lH9rFWH+/LvtLEqKXIudoYyM/k7hhhk0691XbuM5ifIVsTI8svEUn0yka0itgRHvHzL0I2nLeCiSUqjo3WIGr13XefbpVV40y0UJJAKBZPK+//DVK3WmrIjTdYeE7Stnc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Zkm0kuXC; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Zkm0kuXC" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A84B41476; Tue, 8 Sep 2026 09:22:48 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 09F5E3F7B4; Tue, 8 Sep 2026 09:22:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884572; bh=47zEMqoqsoiKg7tbbReEvjkQybQ6brogsshUzI3uxgI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zkm0kuXCVncAhb9UUgYK2b7cVO8si3BlyMJs6aPsW75YScuqTSRlIH5dMhibU9M61 9pM4xW6fVfGUzar49dIF5QCBLZfZVIwshV7yc3kCQSgH24ytR8ee/pfZWR7Qx0ro60 OF5ptgRlVFuwddDxLVh29GDtvuzN8UXmVmw/ZhOQ= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 01/20] KVM: arm64: Include kvm_emulate.h in kvm/arm_psci.h Date: Tue, 8 Sep 2026 17:22:04 +0100 Message-ID: <20260908162223.1683432-2-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Fix a potential build error (like below, when asm/kvm_emulate.h gets included after the kvm/arm_psci.h) by including the missing header file in kvm/arm_psci.h: ./include/kvm/arm_psci.h: In function =E2=80=98kvm_psci_version=E2=80=99: ./include/kvm/arm_psci.h:29:13: error: implicit declaration of function =E2=80=98vcpu_has_feature=E2=80=99; did you mean =E2=80=98cpu_have_featu= re=E2=80=99? [-Werror=3Dimplicit-function-declaration] 29 | if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PSCI_0_2)) { | ^~~~~~~~~~~~~~~~ | cpu_have_feature Reviewed-by: Gavin Shan Signed-off-by: Suzuki K Poulose Signed-off-by: Steven Price Reviewed-by: Fuad Tabba --- include/kvm/arm_psci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kvm/arm_psci.h b/include/kvm/arm_psci.h index f86a006d67136..06c20612e9e7d 100644 --- a/include/kvm/arm_psci.h +++ b/include/kvm/arm_psci.h @@ -10,6 +10,8 @@ #include #include =20 +#include + #define KVM_ARM_PSCI_0_1 PSCI_VERSION(0, 1) #define KVM_ARM_PSCI_0_2 PSCI_VERSION(0, 2) #define KVM_ARM_PSCI_1_0 PSCI_VERSION(1, 0) --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 880C0572666; Tue, 8 Sep 2026 16:22:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884578; cv=none; b=gFyvqennF4CI8KzXUVVTitfpGDKtrZeIEsTNDYUr8Koc2oT+HMYi/9TEJjl5a2N+4jt562Vsx3n/gQR52vqGfDh3NcCKOSz7hnXGkr+K28itjXgIpwb7Q9dTT0vaFEeF9HUyeqSMWo7BujGRd6MnF9FFEqffTbgHogSwMDLS/sQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884578; c=relaxed/simple; bh=rxCr9R5U5X3xLczY0WAuwie4AKdeSbZI/m5eSPs9xkQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AKVpBAhxlEU5axaBjcFKN9FxyjnyD/+OjztXfHB6YEibWl6llC/ikh5XYMHl/oQU4aUxoGarBerbovBWIb9YMGKTJxy2n63vv4VV2RK6vuIZ2+AcFPtO20UeMxDYgLhXq4SVt0PYbS1rLPQsFF0j7mlA0EwZ1y0Ly43NJ8mSnfY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=VF4W3WIZ; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="VF4W3WIZ" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2B2E11477; Tue, 8 Sep 2026 09:22:52 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AC4D13F7B4; Tue, 8 Sep 2026 09:22:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884575; bh=rxCr9R5U5X3xLczY0WAuwie4AKdeSbZI/m5eSPs9xkQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VF4W3WIZ7ACCk84wyYk+Iv17qPotZPa5um0f4J7gS9pEVKIIqbLaLSnj2xotYfXJN wFjcTTwXGa1EB0n/Nys5EQe0v/1t8WyV9HMx4UK1bx+lHBxptXYLY09lwXleNXpYlI EEyHN+Y8ONACqRVYvJy26YLTgj5Q1w+VN9LlzfAs= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com Subject: [PATCH v17 02/20] KVM: arm64: Avoid including linux/kvm_host.h in kvm_pgtable.h Date: Tue, 8 Sep 2026 17:22:05 +0100 Message-ID: <20260908162223.1683432-3-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Steven Price To avoid future include cycles, drop the linux/kvm_host.h include in kvm_pgtable.h and include the lightweight headers required for the types and inline helpers used there. Additionally provide a forward declaration for struct kvm_s2_mmu as it's only used as a pointer in this file. Both pgtable.c and kvm_pkvm.h relied on the indirect inclusion of kvm_host.h, so make that explicit. Signed-off-by: Steven Price Reviewed-by: Fuad Tabba Reviewed-by: Gavin Shan --- New patch in v13 --- arch/arm64/include/asm/kvm_pgtable.h | 6 +++++- arch/arm64/include/asm/kvm_pkvm.h | 2 +- arch/arm64/kvm/hyp/pgtable.c | 1 + 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/= kvm_pgtable.h index 41a8687938eb6..c2e4b29e605fc 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -8,9 +8,13 @@ #define __ARM64_KVM_PGTABLE_H__ =20 #include -#include +#include +#include +#include #include =20 +struct kvm_s2_mmu; + #define KVM_PGTABLE_FIRST_LEVEL -1 #define KVM_PGTABLE_LAST_LEVEL 3 =20 diff --git a/arch/arm64/include/asm/kvm_pkvm.h b/arch/arm64/include/asm/kvm= _pkvm.h index beea00e693a0a..54a618d887fa4 100644 --- a/arch/arm64/include/asm/kvm_pkvm.h +++ b/arch/arm64/include/asm/kvm_pkvm.h @@ -7,9 +7,9 @@ #define __ARM64_KVM_PKVM_H__ =20 #include +#include #include #include -#include #include =20 /* Maximum number of VMs that can co-exist under pKVM. */ diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index b74dd5ce1efd3..f48253b9d88b5 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include =20 --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3EE91559CA0; Tue, 8 Sep 2026 16:23:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884582; cv=none; b=WmFMo3BTKt7KtRKWpcPg5I1MIYoOKPlcTftTHCEsR252IkmbTkc26IVVkc9f1EAx5c8JITOzju1nZBNPgBNXH+nSyjKSEdKxIoiXkHil0qMGXovJoDAD+FHG9ly2edFg/9K8WRuGYjB/beFDn801P/cRqGwNp4lxamoLAsMJHkw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884582; c=relaxed/simple; bh=8GFagwRPNrqblRIlYkC7acPkqx1bS3/JF6XjcUKUqO0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T+boo1XenhrJ3rcnR5EP/PpBbXeeWB7aDziaQXIUQWEKQtyrwZyWBEX+LcN+d9bOdI+pN4Urk660KEFrBnCVgvqHBuCBRi3IbL3pgRi1FMNT/lWL2itWvPc9xlDeqbgS5Z7gcQ4Afxk0eBD5A97BADyupydBNO+TmHYD7QpUwMg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=E6wgGKzz; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="E6wgGKzz" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C73C11476; Tue, 8 Sep 2026 09:22:55 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 309E03F7B4; Tue, 8 Sep 2026 09:22:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884579; bh=8GFagwRPNrqblRIlYkC7acPkqx1bS3/JF6XjcUKUqO0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E6wgGKzzvkAm7qWkNdDzcTLCWVILzEKx8FaZ55mPGxTS3qkHmTWVG3qKp6ztR3IlV u0NaBfDDwmEShoghB3FHOFJV4gF01ilq8hSHP3wz8F0aBv0+uUK9gKv0WXiGsjnog2 tweZ+2Ah9PwinwedbxAeXSah3eu7w5xAn5PX0b8w= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 03/20] KVM: arm64: Track the type of VM in kvm_arch Date: Tue, 8 Sep 2026 17:22:06 +0100 Message-ID: <20260908162223.1683432-4-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM arm64 has different types of VMs with all the different modes in which = the hypervisor code can be run. e.g., VHE, nVHE, PKVM etc. Then there is protec= ted VM and normal VMs with PKVM. We might soon add other types, e.g., Arm CCA R= ealm. So in an effort to make the handling of these different types of VMs a bit = more friendlier to the eyes, add a VM flavor to the kvm_arch and we could then a= dd handlers for different operations based on the VM type. Keep the flavor initialisation at the beginning to allow for the detection early enough and fail out on any unsupported requests. (e.g., protected on = !PKVM) With that, use the vm_flavor to detect if a VM is protected VM on PKVM. Based on a patch by Marc Zyngier Suggested-by: Marc Zyngier Signed-off-by: Suzuki K Poulose Reviewed-by: Fuad Tabba Reviewed-by: Gavin Shan --- arch/arm64/include/asm/kvm_host.h | 12 ++++++++++-- arch/arm64/kvm/arm.c | 27 ++++++++++++++++++++++++--- arch/arm64/kvm/hyp/nvhe/pkvm.c | 2 +- arch/arm64/kvm/pkvm.c | 1 - 4 files changed, 35 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 27fe0cd5b2d7a..d0dccc9ad6aa8 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -257,7 +257,6 @@ struct kvm_protected_vm { pkvm_handle_t handle; struct kvm_hyp_memcache teardown_mc; struct kvm_hyp_memcache stage2_teardown_mc; - bool is_protected; bool is_created; =20 /* @@ -306,9 +305,18 @@ enum fgt_group_id { __NR_FGT_GROUP_IDS__ }; =20 +enum kvm_arm_vm_flavor { + VM_NVHE, + VM_VHE, + VM_PKVM, /* Normal guests on PKVM */ + VM_PROTECTED_PKVM, /* Protected VM */ + VM_FLAVOR_MAX, +}; + struct kvm_arch { struct kvm_s2_mmu mmu; =20 + enum kvm_arm_vm_flavor vm_flavor; /* * Fine-Grained UNDEF, mimicking the FGT layout defined by the * architecture. We track them globally, as we present the @@ -1504,7 +1512,7 @@ struct kvm *kvm_arch_alloc_vm(void); =20 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE =20 -#define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arc= h.pkvm.is_protected) +#define kvm_vm_is_protected(kvm) ((kvm)->arch.vm_flavor =3D=3D VM_PROTECTE= D_PKVM) =20 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) =20 diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 8b080804bc90b..67f1ff9bc4fbe 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -214,6 +214,26 @@ static int kvm_arm_default_max_vcpus(void) return vgic_present ? kvm_vgic_get_max_vcpus() : KVM_MAX_VCPUS; } =20 +static int kvm_init_vm_flavor(struct kvm *kvm, unsigned long type) +{ + bool protected =3D type & KVM_VM_TYPE_ARM_PROTECTED; + + if (is_protected_kvm_enabled()) { + if (protected) + kvm->arch.vm_flavor =3D VM_PROTECTED_PKVM; + else + kvm->arch.vm_flavor =3D VM_PKVM; + } else if (protected) { + return -EINVAL; + } else if (has_vhe()) { + kvm->arch.vm_flavor =3D VM_VHE; + } else { + kvm->arch.vm_flavor =3D VM_NVHE; + } + + return 0; +} + /** * kvm_arch_init_vm - initializes a VM data structure * @kvm: pointer to the KVM struct @@ -236,6 +256,10 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long ty= pe) mutex_unlock(&kvm->lock); #endif =20 + ret =3D kvm_init_vm_flavor(kvm, type); + if (ret) + return ret; + kvm_init_nested(kvm); =20 ret =3D kvm_share_hyp(kvm, kvm + 1); @@ -260,9 +284,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long typ= e) ret =3D pkvm_init_host_vm(kvm, type); if (ret) goto err_uninit_mmu; - } else if (type & KVM_VM_TYPE_ARM_PROTECTED) { - ret =3D -EINVAL; - goto err_uninit_mmu; } =20 kvm_vgic_early_init(kvm); diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 459bd9eb7e4bc..09961c0056f2b 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -432,7 +432,7 @@ static void init_pkvm_hyp_vm(struct kvm *host_kvm, stru= ct pkvm_hyp_vm *hyp_vm, =20 hyp_vm->host_kvm =3D host_kvm; hyp_vm->kvm.created_vcpus =3D nr_vcpus; - hyp_vm->kvm.arch.pkvm.is_protected =3D READ_ONCE(host_kvm->arch.pkvm.is_p= rotected); + hyp_vm->kvm.arch.vm_flavor =3D READ_ONCE(host_kvm->arch.vm_flavor); hyp_vm->kvm.arch.flags =3D 0; pkvm_init_features_from_host(hyp_vm, host_kvm); =20 diff --git a/arch/arm64/kvm/pkvm.c b/arch/arm64/kvm/pkvm.c index 8e4c6e4bec123..3948fa46f4d75 100644 --- a/arch/arm64/kvm/pkvm.c +++ b/arch/arm64/kvm/pkvm.c @@ -240,7 +240,6 @@ int pkvm_init_host_vm(struct kvm *kvm, unsigned long ty= pe) return ret; =20 kvm->arch.pkvm.handle =3D ret; - kvm->arch.pkvm.is_protected =3D protected; if (protected) { pr_warn_once("kvm: protected VMs are experimental and for development on= ly, tainting kernel\n"); add_taint(TAINT_USER, LOCKDEP_STILL_OK); --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DE18B57982B; Tue, 8 Sep 2026 16:23:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="WR4raCcN" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6A6AC1477; Tue, 8 Sep 2026 09:22:59 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C9DFE3F7B4; Tue, 8 Sep 2026 09:22:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884583; bh=jyx0bzcdch/5rk8pWYJvVqWJSVIwEZRSvU35/MZxUBs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WR4raCcNCHMMsmR6jIuN361aK8JL0wDc7B6vVu7a+jtkd2SqUt1BagULHtdkKIXke j4loINdiOoC9x9OsQrOOVX1Zmk1tkzeyxAj0ScUiHWYwBln1qIblMOr8QRX3XErJ3w Bs62fwD73ouJEskpEnlwqHSyN4yeQHyj6jOjct6w= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 04/20] KVM: arm64: Refactor the vcpu_load to allow for VM specific callbacks Date: Tue, 8 Sep 2026 17:22:07 +0100 Message-ID: <20260908162223.1683432-5-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Based on a work by Marc Zyngier To keep the VCPU load/put handling cleaner with the different kinds of VM t= ypes, we are about to introduce VM specific callbacks to do just the right thing. In preparation for that, make some refactoring to add the change easier. No functional changes intended. Signed-off-by: Suzuki K Poulose Reviewed-by: Gavin Shan --- arch/arm64/kvm/arm.c | 46 +++++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 67f1ff9bc4fbe..51fc651267157 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -683,14 +683,11 @@ static bool kvm_vcpu_should_clear_twe(struct kvm_vcpu= *vcpu) return single_task_running(); } =20 -void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +static void vcpu_prepare_mmu(struct kvm_vcpu *vcpu) { struct kvm_s2_mmu *mmu; int *last_ran; =20 - if (is_protected_kvm_enabled()) - goto nommu; - if (vcpu_has_nv(vcpu)) kvm_vcpu_load_hw_mmu(vcpu); =20 @@ -720,10 +717,33 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cp= u) kvm_call_hyp(__kvm_flush_cpu_context, mmu); *last_ran =3D vcpu->vcpu_idx; } +} + +static void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu) +{ + if (kvm_vcpu_should_clear_twe(vcpu)) + vcpu->arch.hcr_el2 &=3D ~HCR_TWE; + else + vcpu->arch.hcr_el2 |=3D HCR_TWE; + + if (kvm_vcpu_should_clear_twi(vcpu)) + vcpu->arch.hcr_el2 &=3D ~HCR_TWI; + else + vcpu->arch.hcr_el2 |=3D HCR_TWI; +} + +static void vcpu_load_pvtime(struct kvm_vcpu *vcpu) +{ + if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) + kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); +} + +void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +{ + if (!is_protected_kvm_enabled()) + vcpu_prepare_mmu(vcpu); =20 -nommu: vcpu->cpu =3D cpu; - /* * The timer must be loaded before the vgic to correctly set up physical * interrupt deactivation in nested state (e.g. timer interrupt). @@ -736,19 +756,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_vcpu_load_vhe(vcpu); kvm_arch_vcpu_load_fp(vcpu); kvm_vcpu_pmu_restore_guest(vcpu); - if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) - kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); - - if (kvm_vcpu_should_clear_twe(vcpu)) - vcpu->arch.hcr_el2 &=3D ~HCR_TWE; - else - vcpu->arch.hcr_el2 |=3D HCR_TWE; - - if (kvm_vcpu_should_clear_twi(vcpu)) - vcpu->arch.hcr_el2 &=3D ~HCR_TWI; - else - vcpu->arch.hcr_el2 |=3D HCR_TWI; =20 + vcpu_load_pvtime(vcpu); + vcpu_set_wfx_traps(vcpu); vcpu_set_pauth_traps(vcpu); =20 if (is_protected_kvm_enabled()) { --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 872D43403E8; Tue, 8 Sep 2026 16:23:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884589; cv=none; b=t9QDbIhKMOm9IZPa/CDlqqIy0H+d+gL0m97M0yUFOhL/VawBk+NEj1y5y+N/OnQOcKzWM9qjXck/2gFx5323k2G/Ur71N2CMLH6BVs/o+bqST8/aOVa+6E9bTGPjKrLfQN7pe30S+O2ZcYGsaSobpcID4ZUSExBycJp0S17XF6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884589; c=relaxed/simple; bh=mLztz2bBk7TLJ4RrXB4VtymPwt7FFyDvGQ4i4G6/fAI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r0bdcWXjm4NS6acmyyRIwD00K+TUcQyL53amNWObdAomnckxKnFEXSydO+HRkshnBXDRR6MkzaO3E3f7MQDV0k8DXnbwpnQOb2ci5NEfFGj/RYR0696029T3Oz0Gg+00DcVW1fSn07M9rCjVAv7k0YGR1zXn/rVaG1MZwT3/Co4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=eaIQgo5h; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="eaIQgo5h" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0FCC91476; Tue, 8 Sep 2026 09:23:03 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6F7C03F7B4; Tue, 8 Sep 2026 09:23:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884586; bh=mLztz2bBk7TLJ4RrXB4VtymPwt7FFyDvGQ4i4G6/fAI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eaIQgo5hBEEoJPSXq8eOfnpVZ9hoy+eyEOWyvsMlm6F7y4OObvw3ThRmunGdVM/Tj wubuJZuG9I8FjOsEvAO/j0UL+iyYle9ZohLPtEHu198+T0Y5FYGqPgBP6wYaf6VHJw fD8KsXbUoum959SFUPhh0KM1aDbRqCytG7dNLHFI= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 05/20] KVM: arm64: Add vcpu load/put call backs for flavors Date: Tue, 8 Sep 2026 17:22:08 +0100 Message-ID: <20260908162223.1683432-6-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add VM flavor specific handlers for VCPU load/put, in an effort to make it easier to follow the code. Based on a patch by Marc Zyngier Suggested-by: Marc Zyngier Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/kvm_host.h | 6 ++ arch/arm64/kvm/arm.c | 156 ++++++++++++++++++++++-------- 2 files changed, 123 insertions(+), 39 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index d0dccc9ad6aa8..b2e99c5cb1cd3 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -150,6 +150,11 @@ struct kvm_vmid { atomic64_t id; }; =20 +struct kvm_vcpu_ops { + void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); + void (*vcpu_put)(struct kvm_vcpu *vcpu); +}; + struct kvm_s2_mmu { struct kvm_vmid vmid; =20 @@ -854,6 +859,7 @@ struct vncr_tlb; =20 struct kvm_vcpu_arch { struct kvm_cpu_context ctxt; + const struct kvm_vcpu_ops *vcpu_ops; =20 /* * Guest floating point state diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 51fc651267157..9af3bbb2f8c24 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -74,6 +74,8 @@ struct kvm_ioctl_cap_map { long ext; }; =20 +static const struct kvm_vcpu_ops *arm64_vcpu_ops[VM_FLAVOR_MAX]; + /* Make KVM_CAP_NR_VCPUS the reference for features we always supported */ #define KVM_CAP_ARM_BASIC KVM_CAP_NR_VCPUS =20 @@ -569,6 +571,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) mutex_unlock(&vcpu->mutex); #endif =20 + vcpu->arch.vcpu_ops =3D arm64_vcpu_ops[vcpu->kvm->arch.vm_flavor]; + /* Force users to call KVM_ARM_VCPU_INIT */ vcpu_clear_flag(vcpu, VCPU_INITIALIZED); =20 @@ -738,36 +742,72 @@ static void vcpu_load_pvtime(struct kvm_vcpu *vcpu) kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); } =20 +static void vhe_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +{ + vcpu_prepare_mmu(vcpu); + /* + * The timer must be loaded before the vgic to correctly set up physical + * interrupt deactivation in nested state (e.g. timer interrupt). + */ + kvm_timer_vcpu_load(vcpu); + kvm_vgic_load(vcpu); + kvm_vcpu_load_debug(vcpu); + kvm_vcpu_load_fgt(vcpu); + kvm_vcpu_load_vhe(vcpu); + kvm_arch_vcpu_load_fp(vcpu); + kvm_vcpu_pmu_restore_guest(vcpu); + + vcpu_load_pvtime(vcpu); + vcpu_set_wfx_traps(vcpu); + vcpu_set_pauth_traps(vcpu); +} + +static void nvhe_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +{ + vcpu_prepare_mmu(vcpu); + /* + * The timer must be loaded before the vgic to correctly set up physical + * interrupt deactivation in nested state (e.g. timer interrupt). + */ + kvm_timer_vcpu_load(vcpu); + kvm_vgic_load(vcpu); + kvm_vcpu_load_debug(vcpu); + kvm_vcpu_load_fgt(vcpu); + kvm_arch_vcpu_load_fp(vcpu); + kvm_vcpu_pmu_restore_guest(vcpu); + + vcpu_load_pvtime(vcpu); + vcpu_set_wfx_traps(vcpu); + vcpu_set_pauth_traps(vcpu); +} + +static void pkvm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +{ + /* + * The timer must be loaded before the vgic to correctly set up physical + * interrupt deactivation in nested state (e.g. timer interrupt). + */ + kvm_timer_vcpu_load(vcpu); + kvm_vgic_load(vcpu); + kvm_vcpu_load_debug(vcpu); + kvm_vcpu_load_fgt(vcpu); + kvm_arch_vcpu_load_fp(vcpu); + kvm_vcpu_pmu_restore_guest(vcpu); + + vcpu_load_pvtime(vcpu); + vcpu_set_wfx_traps(vcpu); + + kvm_call_hyp_nvhe(__pkvm_vcpu_load, + vcpu->kvm->arch.pkvm.handle, + vcpu->vcpu_idx, vcpu->arch.hcr_el2); + kvm_call_hyp(__vgic_v3_restore_vmcr_aprs, + &vcpu->arch.vgic_cpu.vgic_v3); +} + void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { - if (!is_protected_kvm_enabled()) - vcpu_prepare_mmu(vcpu); - vcpu->cpu =3D cpu; - /* - * The timer must be loaded before the vgic to correctly set up physical - * interrupt deactivation in nested state (e.g. timer interrupt). - */ - kvm_timer_vcpu_load(vcpu); - kvm_vgic_load(vcpu); - kvm_vcpu_load_debug(vcpu); - kvm_vcpu_load_fgt(vcpu); - if (has_vhe()) - kvm_vcpu_load_vhe(vcpu); - kvm_arch_vcpu_load_fp(vcpu); - kvm_vcpu_pmu_restore_guest(vcpu); - - vcpu_load_pvtime(vcpu); - vcpu_set_wfx_traps(vcpu); - vcpu_set_pauth_traps(vcpu); - - if (is_protected_kvm_enabled()) { - kvm_call_hyp_nvhe(__pkvm_vcpu_load, - vcpu->kvm->arch.pkvm.handle, - vcpu->vcpu_idx, vcpu->arch.hcr_el2); - kvm_call_hyp(__vgic_v3_restore_vmcr_aprs, - &vcpu->arch.vgic_cpu.vgic_v3); - } + vcpu->arch.vcpu_ops->vcpu_load(vcpu, cpu); =20 if (!cpumask_test_cpu(cpu, vcpu->kvm->arch.supported_cpus)) vcpu_set_on_unsupported_cpu(vcpu); @@ -775,28 +815,44 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cp= u) vcpu->arch.pid =3D pid_nr(vcpu->pid); } =20 -void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) +static void vhe_vcpu_put(struct kvm_vcpu *vcpu) { - if (is_protected_kvm_enabled()) { - kvm_call_hyp(__vgic_v3_save_aprs, &vcpu->arch.vgic_cpu.vgic_v3); - kvm_call_hyp_nvhe(__pkvm_vcpu_put); - - /* __pkvm_vcpu_put implies a sync of the state */ - if (!kvm_vm_is_protected(vcpu->kvm)) - vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY); - } - kvm_vcpu_put_debug(vcpu); kvm_arch_vcpu_put_fp(vcpu); - if (has_vhe()) - kvm_vcpu_put_vhe(vcpu); + kvm_vcpu_put_vhe(vcpu); kvm_timer_vcpu_put(vcpu); kvm_vgic_put(vcpu); kvm_vcpu_pmu_restore_host(vcpu); if (vcpu_has_nv(vcpu)) kvm_vcpu_put_hw_mmu(vcpu); kvm_arm_vmid_clear_active(); +} =20 +static void nvhe_vcpu_put(struct kvm_vcpu *vcpu) +{ + kvm_vcpu_put_debug(vcpu); + kvm_arch_vcpu_put_fp(vcpu); + kvm_timer_vcpu_put(vcpu); + kvm_vgic_put(vcpu); + kvm_vcpu_pmu_restore_host(vcpu); + kvm_arm_vmid_clear_active(); +} + +static void pkvm_vcpu_put(struct kvm_vcpu *vcpu) +{ + kvm_call_hyp(__vgic_v3_save_aprs, &vcpu->arch.vgic_cpu.vgic_v3); + kvm_call_hyp_nvhe(__pkvm_vcpu_put); + + /* __pkvm_vcpu_put implies a sync of the state */ + if (!kvm_vm_is_protected(vcpu->kvm)) + vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY); + + nvhe_vcpu_put(vcpu); +} + +void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) +{ + vcpu->arch.vcpu_ops->vcpu_put(vcpu); vcpu_clear_on_unsupported_cpu(vcpu); vcpu->cpu =3D -1; } @@ -2136,6 +2192,28 @@ int kvm_arch_vm_ioctl(struct file *filp, unsigned in= t ioctl, unsigned long arg) } } =20 +static const struct kvm_vcpu_ops vhe_vcpu_ops =3D { + .vcpu_load =3D vhe_vcpu_load, + .vcpu_put =3D vhe_vcpu_put, +}; + +static const struct kvm_vcpu_ops nvhe_vcpu_ops =3D { + .vcpu_load =3D nvhe_vcpu_load, + .vcpu_put =3D nvhe_vcpu_put, +}; + +static const struct kvm_vcpu_ops pkvm_vcpu_ops =3D { + .vcpu_load =3D pkvm_vcpu_load, + .vcpu_put =3D pkvm_vcpu_put, +}; + +static const struct kvm_vcpu_ops *arm64_vcpu_ops[] =3D { + [VM_VHE] =3D &vhe_vcpu_ops, + [VM_NVHE] =3D &nvhe_vcpu_ops, + [VM_PKVM] =3D &pkvm_vcpu_ops, + [VM_PROTECTED_PKVM] =3D &pkvm_vcpu_ops, +}; + static unsigned long nvhe_percpu_size(void) { return (unsigned long)CHOOSE_NVHE_SYM(__per_cpu_end) - --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4907357C73E; Tue, 8 Sep 2026 16:23:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884593; cv=none; b=P83xSV8qWE9a0p5iGncVldkFKjYEyxGSMoklhCDHsfrRFA3270ceBXQtq3udzawIo/TOs32XpZe9GPWg84h/mCYiTmzXjZngxcSb/mrbGjJARb5WdkN44yCfHXwR38a5m8xurfYXvZif99pM3blWRsYtiF8oADcNlc1Lol1hxkI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884593; c=relaxed/simple; bh=ZXNl0PkFseGSY5buvrG1RYaRc9Peh83P91M3YTJ/q/Y=; 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Tue, 8 Sep 2026 09:23:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884590; bh=ZXNl0PkFseGSY5buvrG1RYaRc9Peh83P91M3YTJ/q/Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fQ/PWbCRCJxNZW9mZlnwtLp96PicpPSWvkBuSjtvLiq+v2y1JOIltaVICN4VpnDm+ n/oDhxt/bescAX+eRFZ01VaPwUFZ3phCo7w0tNQ92feUf8jerq3nGcgjkRynriOh/f iYXhG4mosucDzy+Ie9e9T1T/mtddQgvnlxCOnT5A= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 06/20] KVM: arm64: CCA: Add a new mode for supporting Realm guests Date: Tue, 8 Sep 2026 17:22:09 +0100 Message-ID: <20260908162223.1683432-7-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an explicit mode to support Arm CCA guests. Signed-off-by: Suzuki K Poulose --- Documentation/admin-guide/kernel-parameters.txt | 3 +++ arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/arm.c | 5 +++++ 3 files changed, 9 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 68647ff4bdd24..1afe3df3b923e 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3256,6 +3256,9 @@ Kernel parameters nested: VHE-based mode with support for nested virtualization. Requires at least ARMv8.4 hardware (with FEAT_NV2). + rmm: Support for running confidential guests in Realm + world using RMM, as defined by Arm Confidential + Compute Architecture (CCA) =20 Defaults to VHE/nVHE based on hardware support. Setting mode to "protected" will disable kexec and hibernation diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index b2e99c5cb1cd3..31ae9d8d8e92f 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -69,6 +69,7 @@ enum kvm_mode { KVM_MODE_DEFAULT, KVM_MODE_PROTECTED, KVM_MODE_NV, + KVM_MODE_RMM, KVM_MODE_NONE, }; #ifdef CONFIG_KVM diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 9af3bbb2f8c24..50f0adfadab38 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -3264,6 +3264,11 @@ static int __init early_kvm_mode_cfg(char *arg) return 0; } =20 + if (strcmp(arg, "rmm") =3D=3D 0 && !WARN_ON(!is_kernel_in_hyp_mode())) { + kvm_mode =3D KVM_MODE_RMM; + return 0; + } + return -EINVAL; } early_param("kvm-arm.mode", early_kvm_mode_cfg); --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9DEAC57D210; Tue, 8 Sep 2026 16:23:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884597; cv=none; b=pGgeUsFVtZua5ROPao/YxLz9RgAcUqtVvdkAcIe3RmTQkWhVH59bEn/HyJMlmCU5hIzRPUqehgvYLXxHF/zo1a2RAX+SSWQDVZ2cohyKJVMXLRq1Bb1Om9nBMqEsctRaHUB8/G3HyF4SGh8Df+zTGf1RlC3B+5J0SSHLqES8fcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884597; c=relaxed/simple; bh=UbCe8E6AdE5loYzr31Otwq81TkSXS5gjT1Eg8pSlEEY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YdH0oukXpapmqBvx2beXpToxKt7ybJHT9aXHPvV/8lVsZrrbyY4AuoTTcTOOQwUugXridBwPZEq6u56KM7erBMGyBxhLOdFeuBuSnAXJvZwcFTFs05f9qEE/OdxcG/UKD71fo9MmGmvwzmiutLNyjTjt8xhN4h+5koyPuAu7YBE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=k9KT5tS3; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="k9KT5tS3" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E11E1476; Tue, 8 Sep 2026 09:23:10 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AC6FB3F7B4; Tue, 8 Sep 2026 09:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884594; bh=UbCe8E6AdE5loYzr31Otwq81TkSXS5gjT1Eg8pSlEEY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k9KT5tS3qLeAfSBtDzdbTKObWsO5E8CM3//xQQ/nB2Zip8gSp8UzE0JlzqXCntwYW +/XlfXl3DBYMa4YPlaqZFK6RzL8BkqOHxGbTfvnMA5oLa1UcKdd7KgfXw4g+oOBOCE ykwDkxqTdYLgkMIgbQUpGSlXsQ2c5rqbXch2Divk= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 07/20] KVM: arm64: CCA: Introduce Realms Date: Tue, 8 Sep 2026 17:22:10 +0100 Message-ID: <20260908162223.1683432-8-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Steven Price Add foundational work for supporting Realms. - Add a new VM flavor. - At KVM init, check if the KVM can support Realms (though not functional = yet) and will be advertised by static key kvm_rmi_is_available. This will be turned on in a later patches, once we have all the bits and pieces ready. For now check if we are blessed with KVM_MODE_RMM. - Add realm specific tracking in kvm_arch. Since Realm and protected pKVM states are mutually exclusive, move them into a union. Signed-off-by: Steven Price Co-Developed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose --- Changes since v16: * Share mutually exclusive pKVM and Realm per-VM storage in a union. * Move to the new VM flavor infrastructure, split bits out. Trimmed down * Move in Realm state and basic boiler plates Changes since v13: * Most of the init has been moved out of the 'kvm' directory so this is much more basic now. Changes since v12: * Drop check for 4k page size. Changes since v11: * Reword slightly the comments on the realm states. Changes since v10: * kvm_is_realm() no longer has a NULL check. * Rename from "rme" to "rmi" when referring to the RMM interface. * Check for RME (hardware) support before probing for RMI support. Changes since v8: * No need to guard kvm_init_rme() behind 'in_hyp_mode'. Changes since v6: * Improved message for an unsupported RMI ABI version. Changes since v5: * Reword "unsupported" message from "host supports" to "we want" to clarify that 'we' are the 'host'. Changes since v2: * Drop return value from kvm_init_rme(), it was always 0. * Rely on the RMM return value to identify whether the RSI ABI is compatible. --- arch/arm64/include/asm/kvm_emulate.h | 16 ++++++++ arch/arm64/include/asm/kvm_host.h | 17 +++++--- arch/arm64/include/asm/kvm_rmi.h | 61 ++++++++++++++++++++++++++++ arch/arm64/include/asm/virt.h | 1 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/arm.c | 5 +++ arch/arm64/kvm/rmi.c | 18 ++++++++ 7 files changed, 114 insertions(+), 6 deletions(-) create mode 100644 arch/arm64/include/asm/kvm_rmi.h create mode 100644 arch/arm64/kvm/rmi.c diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index a3c1928bdf743..d360a8b05b8bf 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -793,4 +793,20 @@ static inline void kvm_reset_vcpu_psci(struct kvm_vcpu= *vcpu, vcpu_set_reg(vcpu, 0, reset_state->r0); } =20 +static inline enum realm_state kvm_realm_state(struct kvm *kvm) +{ + return READ_ONCE(kvm->arch.realm.state); +} + +static inline void kvm_set_realm_state(struct kvm *kvm, + enum realm_state new_state) +{ + WRITE_ONCE(kvm->arch.realm.state, new_state); +} + +static inline bool kvm_realm_is_created(struct kvm *kvm) +{ + return kvm_vm_is_realm(kvm) && kvm_realm_state(kvm) !=3D REALM_STATE_NONE; +} + #endif /* __ARM64_KVM_EMULATE_H__ */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 31ae9d8d8e92f..824a3383409c8 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -27,6 +27,7 @@ #include #include #include +#include #include =20 #define __KVM_HAVE_ARCH_INTC_INITIALIZED @@ -316,6 +317,7 @@ enum kvm_arm_vm_flavor { VM_VHE, VM_PKVM, /* Normal guests on PKVM */ VM_PROTECTED_PKVM, /* Protected VM */ + VM_REALM, /* CCA */ VM_FLAVOR_MAX, }; =20 @@ -431,11 +433,14 @@ struct kvm_arch { /* Count the number of VNCR_EL2 TLBs */ atomic_t vncr_tlb_count; =20 - /* - * For an untrusted host VM, 'pkvm.handle' is used to lookup - * the associated pKVM instance in the hypervisor. - */ - struct kvm_protected_vm pkvm; + union { + /* + * For an untrusted host VM, 'pkvm.handle' is used to lookup + * the associated pKVM instance in the hypervisor. + */ + struct kvm_protected_vm pkvm; + struct realm realm; + }; =20 #ifdef CONFIG_PTDUMP_STAGE2_DEBUGFS /* Nested virtualization info */ @@ -1520,8 +1525,10 @@ struct kvm *kvm_arch_alloc_vm(void); #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE =20 #define kvm_vm_is_protected(kvm) ((kvm)->arch.vm_flavor =3D=3D VM_PROTECTE= D_PKVM) +#define kvm_vm_is_realm(kvm) ((kvm)->arch.vm_flavor =3D=3D VM_REALM) =20 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) +#define vcpu_is_rec(vcpu) kvm_vm_is_realm((vcpu)->kvm) =20 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h new file mode 100644 index 0000000000000..44f5c75a27b5b --- /dev/null +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023-2026 ARM Ltd. + */ + +#ifndef __ASM_KVM_RMI_H +#define __ASM_KVM_RMI_H + +/** + * enum realm_state - State of a Realm + * + * Mirrors the RMM's Realm lifecycle states where they are meaningful to K= VM, + * with REALM_STATE_DYING being a KVM-internal state used to prevent furth= er + * requests while teardown is in progress. KVM does not track REALM_SYSTEM= _OFF + * or REALM_ZOMBIE separately as they naturally lead to teardown. + */ +enum realm_state { + /** + * @REALM_STATE_NONE: + * Realm has not yet been created. rmi_realm_create() has not + * yet been called. + */ + REALM_STATE_NONE, + /** + * @REALM_STATE_NEW: + * Realm is under construction, rmi_realm_create() has been + * called, but it is not yet activated. Pages may be populated. + */ + REALM_STATE_NEW, + /** + * @REALM_STATE_ACTIVE: + * Realm has been created and is eligible for execution with + * rmi_rec_enter(). Pages may no longer be populated with + * rmi_data_create(). + */ + REALM_STATE_ACTIVE, + /** + * @REALM_STATE_DYING: + * Realm is in the process of being destroyed or has already been + * destroyed. + */ + REALM_STATE_DYING, + /** + * @REALM_STATE_DEAD: + * Realm has been destroyed. + */ + REALM_STATE_DEAD +}; + +/** + * struct realm - Additional per VM data for a Realm + * + * @state: The lifetime state machine for the realm + */ +struct realm { + enum realm_state state; +}; + +void kvm_init_rmi(void); + +#endif /* __ASM_KVM_RMI_H */ diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h index b546703c3ab9a..92cec42952f42 100644 --- a/arch/arm64/include/asm/virt.h +++ b/arch/arm64/include/asm/virt.h @@ -87,6 +87,7 @@ void __hyp_reset_vectors(void); bool is_kvm_arm_initialised(void); =20 DECLARE_STATIC_KEY_FALSE(kvm_protected_mode_initialized); +DECLARE_STATIC_KEY_FALSE(kvm_rmi_is_available); =20 static inline bool is_pkvm_initialized(void) { diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 59612d2f277c1..ed3cf30eb06e7 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -16,7 +16,7 @@ CFLAGS_handle_exit.o +=3D -Wno-override-init kvm-y +=3D arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \ inject_fault.o va_layout.o handle_exit.o config.o \ guest.o debug.o reset.o sys_regs.o stacktrace.o \ - vgic-sys-reg-v3.o fpsimd.o pkvm.o \ + vgic-sys-reg-v3.o fpsimd.o pkvm.o rmi.o \ arch_timer.o trng.o vmid.o emulate-nested.o nested.o at.o \ vgic/vgic.o vgic/vgic-init.o \ vgic/vgic-irqfd.o vgic/vgic-v2.o \ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 50f0adfadab38..2ecd92156f7cc 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include =20 @@ -113,6 +114,8 @@ long kvm_get_cap_for_kvm_ioctl(unsigned int ioctl, long= *ext) return -EINVAL; } =20 +DEFINE_STATIC_KEY_FALSE(kvm_rmi_is_available); + DECLARE_KVM_HYP_PER_CPU(unsigned long, kvm_hyp_vector); =20 DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_base); @@ -3159,6 +3162,8 @@ static __init int kvm_arm_init(void) =20 in_hyp_mode =3D is_kernel_in_hyp_mode(); =20 + kvm_init_rmi(); + if (cpus_have_final_cap(ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) || cpus_have_final_cap(ARM64_WORKAROUND_1508412)) kvm_info("Guests without required CPU erratum workarounds can deadlock s= ystem!\n" \ diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c new file mode 100644 index 0000000000000..5ecc8b3498698 --- /dev/null +++ b/arch/arm64/kvm/rmi.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023-2026 ARM Ltd. + */ + +#include + +#include + +void kvm_init_rmi(void) +{ + if (kvm_get_mode() !=3D KVM_MODE_RMM) + return; + + /* TODO: Check if the RMI is available */ + + /* Future patch will enable static branch kvm_rmi_is_available */ +} --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5E19457266C; Tue, 8 Sep 2026 16:23:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884600; cv=none; b=YMNIsfmDJRYbFCFZV9wuPMhRIrzIsOqlm3SvEZqithIrKBpQoFanE50CPZ3Bphbekapz5Ed2fE8vny7HlzkA71vRlPNHSdzlRJX2RADauPQ7whUxuAAWka/x2vPleY6eDxyXv5pMzPs3aRzp/UoA6kxACmOM0JNDX3CPWjUseh4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884600; c=relaxed/simple; bh=CgnhUkjRCuK5Hn3XRTDM/Af/LZ4kv2s2gn1J+cXjimM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ngMVcrpKuSRzuFeWjxz7iZHQQvXMmATziW2vp7v/bInaZeu5iJULYQBu5KoOrI689sVaMbZutDuFbiPYMU4AalymqLi1DwDsxNjRtA6382/r92GlSz01uTixwbSy+OQ3464+aFj6dwaxcwAsWDtSXjBlXWKTm+SqNahjnN5KPx4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=vfFLvsGB; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="vfFLvsGB" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E6C791476; Tue, 8 Sep 2026 09:23:13 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 526EB3F7B4; Tue, 8 Sep 2026 09:23:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884597; bh=CgnhUkjRCuK5Hn3XRTDM/Af/LZ4kv2s2gn1J+cXjimM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vfFLvsGBSaN2oezQYfkot3Y+FXdmwUIVuwYRthDibzcWmcx2Frlxv4hVZczohPmB/ y4mjeTNNINippo3RnXpp+1FIM87EkCd6qbR8ywk2NgCHN7lLREQf5b2ji+VIf666KR 9V0EM0n9MnrdzvudZDiIvBAezfm9jn1NPqQ+uDmY= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 08/20] KVM: arm64: coco: Add a helper to check if a VM is confidential compute guest Date: Tue, 8 Sep 2026 17:22:11 +0100 Message-ID: <20260908162223.1683432-9-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Both protected VMs and Realms are additionally secured by the trusted hyper= visor guarantees. Add a helper to detect if a given VM is a coco guest. Base this= off the ordering of the VM flavor type. Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/kvm_host.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 824a3383409c8..020aef5a1b698 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -316,6 +316,7 @@ enum kvm_arm_vm_flavor { VM_NVHE, VM_VHE, VM_PKVM, /* Normal guests on PKVM */ + MARKER(__VM_CONFIDENTIAL), VM_PROTECTED_PKVM, /* Protected VM */ VM_REALM, /* CCA */ VM_FLAVOR_MAX, @@ -1524,9 +1525,11 @@ struct kvm *kvm_arch_alloc_vm(void); =20 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE =20 +#define kvm_vm_is_confidential(kvm) ((kvm)->arch.vm_flavor >=3D __VM_CONFI= DENTIAL) #define kvm_vm_is_protected(kvm) ((kvm)->arch.vm_flavor =3D=3D VM_PROTECTE= D_PKVM) #define kvm_vm_is_realm(kvm) ((kvm)->arch.vm_flavor =3D=3D VM_REALM) =20 +#define vcpu_is_confidential(vcpu) kvm_vm_is_confidential((vcpu)->kvm) #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) #define vcpu_is_rec(vcpu) kvm_vm_is_realm((vcpu)->kvm) =20 --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BEF7A57F729; Tue, 8 Sep 2026 16:23:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884603; cv=none; b=V9FdJ4X3qAUW+/PsZw2MZyIt6eMoRZ01njxi2vWZTWX2p0i9GbG6iKnjhniAHEom326SVtnE0ANf4+7mQkhH6pa9vQSHkkSTmJTP2/KFqFask0tnjaTYZYK5HnOsq7eutfEoMwEdkJpZM1GmWaeKolMtTNLvXhYPy48gkXrpLeI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884603; c=relaxed/simple; bh=vmaUB5iSk6lw4qSBLxzzmbDWNLrO7NOzUFjs3zuKsbA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Qny8KFvtUKiIkwvNQVEKfDTGzGVD+rdlGS20VRWib/YKbYiwjU+5jld1LpWiUYgqqDDkc5mvK/bm3a9eeTpvx2VZdErf1P18RMYOh+lcvdCj+nPeCkAG+Gs8pWeTPCL9S8fXrHrt5xbZgFN2et11w/hvgizAPg/jRCYZaIE0dIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=gFF+ippZ; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="gFF+ippZ" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A4B11477; Tue, 8 Sep 2026 09:23:17 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EAFB73F7B4; Tue, 8 Sep 2026 09:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884601; bh=vmaUB5iSk6lw4qSBLxzzmbDWNLrO7NOzUFjs3zuKsbA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gFF+ippZOn+9Uh847NfrGv7hLhfT9mTDUoj1KbLPPfGTkup8rmKO7Jw7hVAGDMrQD wxSOeR0i0hFa1EcjDfZMqcMzRvX0H20hpKhsFr4GgPP87Edk0jAVNt+rLTWyhvMMUs /iH9YsBkJRlD0mjkS++BmEGtrgVUrTf4LuqMrgYY= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 09/20] KVM: arm64: coco: arch_timer: Prevent timer offset configuration Date: Tue, 8 Sep 2026 17:22:12 +0100 Message-ID: <20260908162223.1683432-10-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Confidential guests, including protected PKVM guests and Arm CCA Realms, al= ways runs with 0 timer offset. Prevent the configuration for them. Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/arch_timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 6ac3321f4c575..eba84cab95d01 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -1079,7 +1079,7 @@ static void timer_context_init(struct kvm_vcpu *vcpu,= int timerid) =20 ctxt->timer_id =3D timerid; =20 - if (!kvm_vm_is_protected(vcpu->kvm)) { + if (!vcpu_is_confidential(vcpu)) { if (timerid =3D=3D TIMER_VTIMER) ctxt->offset.vm_offset =3D &kvm->arch.timer_data.voffset; else @@ -1110,7 +1110,7 @@ void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) timer_context_init(vcpu, i); =20 /* Synchronize offsets across timers of a VM if not already provided */ - if (!vcpu_is_protected(vcpu) && + if (!vcpu_is_confidential(vcpu) && !test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) { timer_set_offset(vcpu_vtimer(vcpu), kvm_phys_timer_read()); timer_set_offset(vcpu_ptimer(vcpu), 0); @@ -1736,7 +1736,7 @@ int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, if (offset->reserved) return -EINVAL; =20 - if (kvm_vm_is_protected(kvm)) + if (kvm_vm_is_confidential(kvm)) return -EINVAL; =20 mutex_lock(&kvm->lock); --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7CB8D580385; Tue, 8 Sep 2026 16:23:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884607; cv=none; b=H5jvBs0QYnP8KGU218lhdHbaIeuwgvVCBC97ew2dvis9unsWBlUH1Bfd85mExZ/83othyYjjgMc73XknnVBuXhwwH0WkGkzxtzKt76etUqKL896CVCkyKgBR093cFJBnCLt0F5wKqv4yitQIas4cAc6ZfOQ6/ovKB+MxdEW1d4E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884607; c=relaxed/simple; bh=X91qpxlmCb+RcASVwWsSL4AP+f2WCekRe8JKe4PKM9Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cbOIP2K82Dv0+VFUTSB/shKMIHILlqZB+14jbdrWnk9JWMpjKYCo0qKvVWcoAJ0HNH1V8pOFj7REXSnYfit3EKnShPD+4DnL+e4f4r8IvvL7Qbd5GzwSsuIca8HXNnZrqbcM2TaBScxhdLonPhLKhwaoLroZeQdsjCeZqznXnH8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=OH674DE6; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="OH674DE6" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 32B571476; Tue, 8 Sep 2026 09:23:21 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9009E3F7B4; Tue, 8 Sep 2026 09:23:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884604; bh=X91qpxlmCb+RcASVwWsSL4AP+f2WCekRe8JKe4PKM9Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OH674DE6RzZ1E5TLddbpKAdwRgPW35U59OH0+ZgFxiyjHnqexeWj+Ks77CBOV+pin cydpWohwNRxiQunWmrmtkKMCFzbW9949shwjmdj4SlY4utGeaBpEgF1ZLB4lag4Esc gzStEowg3HcQ76Uk2j8IHe3RHWEOJZzf4yS8VTRU= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 10/20] KVM: arm64: coco: Disable Steal time accounting for coco guests Date: Tue, 8 Sep 2026 17:22:13 +0100 Message-ID: <20260908162223.1683432-11-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" PVTIME support is advertised by KVM_CAP_STEAL_TIME, which doesn't take into account the kvm instance. Even with that, a VMM could skip the CAP check and proceed to configure the PVTIME as we don't do further check on the DEVICE_= CTRL. Tighten this up by passing the KVM instance around wherever possible and catch things early Signed-off-by: Suzuki K Poulose Reviewed-by: Fuad Tabba --- arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/kvm/arm.c | 2 +- arch/arm64/kvm/pvtime.c | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 020aef5a1b698..0f258f16fdf81 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1367,7 +1367,7 @@ long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); void kvm_update_stolen_time(struct kvm_vcpu *vcpu); =20 -bool kvm_arm_pvtime_supported(void); +bool kvm_arm_pvtime_supported(struct kvm *kvm); int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 2ecd92156f7cc..b5e0893ea16f1 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -473,7 +473,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) r =3D system_supports_mte(); break; case KVM_CAP_STEAL_TIME: - r =3D kvm_arm_pvtime_supported(); + r =3D kvm_arm_pvtime_supported(kvm); break; case KVM_CAP_ARM_EL1_32BIT: r =3D cpus_have_final_cap(ARM64_HAS_32BIT_EL1); diff --git a/arch/arm64/kvm/pvtime.c b/arch/arm64/kvm/pvtime.c index 4ceabaa4c30bd..41fbfd92cd292 100644 --- a/arch/arm64/kvm/pvtime.c +++ b/arch/arm64/kvm/pvtime.c @@ -67,9 +67,9 @@ gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu) return base; } =20 -bool kvm_arm_pvtime_supported(void) +bool kvm_arm_pvtime_supported(struct kvm *kvm) { - return !!sched_info_on(); + return !!sched_info_on() && (!kvm || !kvm_vm_is_confidential(kvm)); } =20 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, @@ -81,7 +81,7 @@ int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, int ret =3D 0; int idx; =20 - if (!kvm_arm_pvtime_supported() || + if (!kvm_arm_pvtime_supported(kvm) || attr->attr !=3D KVM_ARM_VCPU_PVTIME_IPA) return -ENXIO; =20 @@ -110,7 +110,7 @@ int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, u64 __user *user =3D (u64 __user *)attr->addr; u64 ipa; =20 - if (!kvm_arm_pvtime_supported() || + if (!kvm_arm_pvtime_supported(vcpu->kvm) || attr->attr !=3D KVM_ARM_VCPU_PVTIME_IPA) return -ENXIO; =20 @@ -126,7 +126,7 @@ int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, { switch (attr->attr) { case KVM_ARM_VCPU_PVTIME_IPA: - if (kvm_arm_pvtime_supported()) + if (kvm_arm_pvtime_supported(vcpu->kvm)) return 0; } return -ENXIO; --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2859A5803B7; Tue, 8 Sep 2026 16:23:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884611; cv=none; b=a1YnhgRJRK05ZkgpWgcYjRyjjWUNrptlOUlr6siTaaiFsodHpxd1r/1XyPM8oVaIg8XOd61QtIscRvdsXlsbBHiZRHkOl7+vAtI++jIz4pceCSPflFgk3fPKlKyPGCXTpZrWIPgF6XK7T8wVhMqxOXtBd+YVUuuRXtzf+cFYjFY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 8 Sep 2026 09:23:24 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 356B33F7B4; Tue, 8 Sep 2026 09:23:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884608; bh=W2yWocIjX/1lSG41m89vduKUKYOsNpQW6LsSskrDhH8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C/02/NQ71e7kEfL+DYbaJceFhyRvQa7eVvAYwvfxkW3wXxUNeydtcGDoxcGzimu2b f0rnHpbKFLqCBQrtJ/a7dn+aEA3mMqvBmxQcYvLKLq/7ImxMPMkj1tY4SqXkxyEMEV rLo3UfobC5k9KyJtN8fQpcyleSowUCWy8shC18nw= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 11/20] KVM: arm64: coco: Don't handle MMIO with no ISV Date: Tue, 8 Sep 2026 17:22:14 +0100 Message-ID: <20260908162223.1683432-12-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Generalize the MMIO with no ISV handling to confidential guests. Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/mmio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/mmio.c b/arch/arm64/kvm/mmio.c index d1c3a352d5a22..bbcf52f01e912 100644 --- a/arch/arm64/kvm/mmio.c +++ b/arch/arm64/kvm/mmio.c @@ -168,14 +168,14 @@ int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t f= ault_ipa) * No valid syndrome? Ask userspace for help if it has * volunteered to do so, and bail out otherwise. * - * In the protected VM case, there isn't much userspace can do + * In the protected/Realm VM case, there isn't much userspace can do * though, so directly deliver an exception to the guest. */ if (!kvm_vcpu_dabt_isvalid(vcpu)) { trace_kvm_mmio_nisv(*vcpu_pc(vcpu), esr, kvm_vcpu_get_hfar(vcpu), fault_ipa); =20 - if (vcpu_is_protected(vcpu)) + if (vcpu_is_confidential(vcpu)) return kvm_inject_sea_dabt(vcpu, kvm_vcpu_get_hfar(vcpu)); =20 if (test_bit(KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER, --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B6F2C58125A; Tue, 8 Sep 2026 16:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884614; cv=none; b=u8H59vCPsowOJOIVDOQCqmCEVjyOWkMcMwcvp4xpRUBGFJQMiLNdz+AN4gIGkPx78n7LXjgykls4/xbyNkCTkloloJLMF4yww7SQgBm5QVEtKZQXWQlPIN3KdAgWtiIlzZgYIGqRX6lVDYzzqUZxZqKcuncIuS9WWa3lhN+XR8M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884614; c=relaxed/simple; bh=cQ58Yv70roVo81q8YhrC7/X6t1/ZhRn2w2WWnNS8nhw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UtxDtO6F9ewJthXsF1ZCnWOSnYj1GAQgbkpWsMxbVHil62aFI0OeqBQjc/PA+X7j2ZR/05RhvLZKRXtKdOfZeYWU1TXBskaouAprIFk/PmX5SYMu7tuqZbLIBenc2BYXNYVsFSEHGqch3gAWABK/TfGEqL+7sncrCkubnjFRRhU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=kClYRytW; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="kClYRytW" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 779011477; Tue, 8 Sep 2026 09:23:28 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D775D3F7B4; Tue, 8 Sep 2026 09:23:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884612; bh=cQ58Yv70roVo81q8YhrC7/X6t1/ZhRn2w2WWnNS8nhw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kClYRytWqQQBGNNWIWxVmskQVHDgFyIpVPJJUOmWcU0B+eJcM90R/uSvItvNW5ufv 37Ffp+qeitSORtr+HhQuh4ELTvScMnd6b7Lm0elsysioOlx/w0VCzZGeYMcRiyDI63 ScAk2LSkj5PGLVJRp3pAWyoRIOX5ikoQAAyB/oxM= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 12/20] KVM: arm64: CCA: Support timers in realm RECs Date: Tue, 8 Sep 2026 17:22:15 +0100 Message-ID: <20260908162223.1683432-13-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Steven Price The RMM keeps track of the timer while the realm REC is running, but on exit to the normal world KVM is responsible for handling the timers. A later patch adds the support for propagating the timer values from the exit data structure and makeing sure the values are in sync for KVM. Also, RMM doesn't support injecting virtual interrupts backed by Physical interrupts. So, use the existing software resampling mechanims for Realm timer interrupts. Signed-off-by: Steven Price Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/arch_timer.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index eba84cab95d01..3eddf44f7b1dd 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -56,11 +56,25 @@ static unsigned long kvm_arch_timer_get_irq_flags(void) return kvm_vgic_global_state.no_hw_deactivation ? VGIC_IRQ_SW_RESAMPLE : = 0; } =20 +static unsigned long kvm_realm_timer_get_irq_flags(void) +{ + /* + * RMI_REC_ENTER rejects LRs with the HW bit set, so use the existing + * software resampling mechanism for Realm timer interrupts. + */ + return VGIC_IRQ_SW_RESAMPLE; +} + static const struct irq_ops arch_timer_irq_ops =3D { .get_flags =3D kvm_arch_timer_get_irq_flags, .get_input_level =3D kvm_arch_timer_get_input_level, }; =20 +static const struct irq_ops realm_timer_irq_ops =3D { + .get_flags =3D kvm_realm_timer_get_irq_flags, + .get_input_level =3D kvm_arch_timer_get_input_level, +}; + static const struct irq_ops arch_timer_irq_ops_vgic_v5 =3D { .get_input_level =3D kvm_arch_timer_get_input_level, .queue_irq_unlock =3D vgic_v5_ppi_queue_irq_unlock, @@ -1609,8 +1623,12 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) =20 get_timer_map(vcpu, &map); =20 - ops =3D vgic_is_v5(vcpu->kvm) ? &arch_timer_irq_ops_vgic_v5 : - &arch_timer_irq_ops; + if (vcpu_is_rec(vcpu)) + ops =3D &realm_timer_irq_ops; + else if (vgic_is_v5(vcpu->kvm)) + ops =3D &arch_timer_irq_ops_vgic_v5; + else + ops =3D &arch_timer_irq_ops; =20 for (int i =3D 0; i < nr_timers(vcpu); i++) kvm_vgic_set_irq_ops(vcpu, timer_irq(vcpu_get_timer(vcpu, i)), ops); --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 872AB582BAC; Tue, 8 Sep 2026 16:23:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884619; cv=none; b=ueIJ1mT2C2m2bA/trT8IX7TN8ltcrVNhDovukcfpvjhU/+TDCjdYli5Ef/gibu7Tgy0CDobnf1bTuNpD9uRqLZ0khAm21MlIWCpXhuRRU8QywK2O0un4CJlv5uc9JULklcyhoLeRKz/deCP5EvcXjXv7v7nw3qAJ+LDHzNlYMos= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884619; c=relaxed/simple; bh=rcvFiEHuSI+iYZssP4YUoc0XZJr7UrWElOyPy2d1u6g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pXUPS4q7yHcjZSK1dLGTBvjBb5vF5KSNt+wizUNy5gEhaLLnpPfyJuLodamOtRz/Q6SGup/8qa/pjRovgpiLLIRz2rkVehnWDk5M0spEEG+vFOn9VXAT9ibYivVhzZZWefJykytBKVYDxvpAdEFxtysc6XOnCatJjTz3oFXDAK0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=WMDCslfU; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="WMDCslfU" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1FA6A1C01; Tue, 8 Sep 2026 09:23:32 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7C4D23F7B4; Tue, 8 Sep 2026 09:23:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884615; bh=rcvFiEHuSI+iYZssP4YUoc0XZJr7UrWElOyPy2d1u6g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WMDCslfUN1dre+HAmE9X1Q55Ii1XoTfcKIVPrHjrgsDViNunXcJ4JIobAh6hKTNAJ ZGIcMsTnSSv9IWkenAEfgbsztp3S0KUdK6wB59Vh4pTkb7qGjsYDIfK46kUEG+/jLb GByUP/siteS2s9n4sz1vR7apwihT9vs85j+0VOpI= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 13/20] KVM: arm64: CCA: Add VCPU load/put for Realms Date: Tue, 8 Sep 2026 17:22:16 +0100 Message-ID: <20260908162223.1683432-14-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RMM controls the VCPU settings and most are hidden from the KVM, except for= the VGIC and timer bits. A later patch would add syncing the VCPU state into the Realm REC related S= MC parameters. Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/arm.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index b5e0893ea16f1..3dfe0e03fab7a 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -807,6 +807,13 @@ static void pkvm_vcpu_load(struct kvm_vcpu *vcpu, int = cpu) &vcpu->arch.vgic_cpu.vgic_v3); } =20 +static void realm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +{ + kvm_timer_vcpu_load(vcpu); + kvm_vgic_load(vcpu); + vcpu_set_wfx_traps(vcpu); +} + void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { vcpu->cpu =3D cpu; @@ -853,6 +860,12 @@ static void pkvm_vcpu_put(struct kvm_vcpu *vcpu) nvhe_vcpu_put(vcpu); } =20 +static void realm_vcpu_put(struct kvm_vcpu *vcpu) +{ + kvm_timer_vcpu_put(vcpu); + kvm_vgic_put(vcpu); +} + void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) { vcpu->arch.vcpu_ops->vcpu_put(vcpu); @@ -2210,11 +2223,17 @@ static const struct kvm_vcpu_ops pkvm_vcpu_ops =3D { .vcpu_put =3D pkvm_vcpu_put, }; =20 +static const struct kvm_vcpu_ops realm_vcpu_ops =3D { + .vcpu_load =3D realm_vcpu_load, + .vcpu_put =3D realm_vcpu_put, +}; + static const struct kvm_vcpu_ops *arm64_vcpu_ops[] =3D { [VM_VHE] =3D &vhe_vcpu_ops, [VM_NVHE] =3D &nvhe_vcpu_ops, [VM_PKVM] =3D &pkvm_vcpu_ops, [VM_PROTECTED_PKVM] =3D &pkvm_vcpu_ops, + [VM_REALM] =3D &realm_vcpu_ops, }; =20 static unsigned long nvhe_percpu_size(void) --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EEC0956C64A; Tue, 8 Sep 2026 16:23:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884622; cv=none; b=GOLmINGRnbn84q3S7d8uD5ZziY0weruzd7/7KVWF3Sgtz4UNBD2lU8SUYDeBXwWy6m/dX3Jkwhf3m0ahgWeAEVj/5FgSZobeUb7S/kcRbBqCNnhaOxVGlHxIxOcf5rTIy2NerHgINAMcmcZFHG1JMmFXIe3PKD7oV3WOf3UBE4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884622; c=relaxed/simple; bh=CUFNiF/5y947+lSyvlccR1MDxDZzW2BioQzrsrm2Qto=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ap7lVY3nKXhUWOz70wlO9MN2tMduoMYKJptuu8Kb6RVoD4l8WD86JUYnPCg8ypgUJ75Cv+deCazfHCiQGJ3nv9+eb5lVFSAJA6s2rvEiQ3byNcyv4gP2tN+Z5qGIAfE/hRPpCgLVwZP89mos/NtZzdVmUWXFFoOYoEjR5aD5brY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=N6Ry4fTc; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="N6Ry4fTc" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B414C1477; Tue, 8 Sep 2026 09:23:35 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 214D83F7B4; Tue, 8 Sep 2026 09:23:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884619; bh=CUFNiF/5y947+lSyvlccR1MDxDZzW2BioQzrsrm2Qto=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N6Ry4fTcgU4eQHixy+4BGrZC4KulzSrwnQRFnZuaZnzv3hbjGqjznzcXXzFGmkHvi gQyjgIenUiTiXfhXLGAtGBnB4tMUuSLlgVK5HsvokijC3TAv7PNxdVT3PjconnGMPV f568LLkwgJJoBsNFGLYhaxXkIf48eErUA0lRbHxs= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 14/20] KVM: arm64: CCA: Don't expose unsupported capabilities for realm guests Date: Tue, 8 Sep 2026 17:22:17 +0100 Message-ID: <20260908162223.1683432-15-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RMM v2.0 provides no mechanism for the host to perform debug operations on the guest. So limit the extensions that are visible to an allowlist so that only those capabilities we can support are advertised. Signed-off-by: Suzuki K Poulose Signed-off-by: Steven Price --- Changes since v13: * Add missing check in kvm_vm_ioctl_enable_cap(). Changes since v10: * Add a kvm_realm_ext_allowed() function which limits which extensions are exposed to an allowlist. This removes the need for special casing various extensions. Changes since v7: * Remove the helper functions and inline the kvm_is_realm() check with a ternary operator. * Rewrite the commit message to explain this patch. --- arch/arm64/kvm/arm.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 3dfe0e03fab7a..fbb4d6651ab51 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -137,6 +137,25 @@ int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) return kvm_vcpu_exiting_guest_mode(vcpu) =3D=3D IN_GUEST_MODE; } =20 +static bool kvm_realm_ext_allowed(long ext) +{ + switch (ext) { + case KVM_CAP_IRQCHIP: + case KVM_CAP_ARM_PSCI: + case KVM_CAP_ARM_PSCI_0_2: + case KVM_CAP_NR_VCPUS: + case KVM_CAP_MAX_VCPUS: + case KVM_CAP_MAX_VCPU_ID: + case KVM_CAP_MSI_DEVID: + case KVM_CAP_ARM_VM_IPA_SIZE: + case KVM_CAP_ARM_PTRAUTH_ADDRESS: + case KVM_CAP_ARM_PTRAUTH_GENERIC: + case KVM_CAP_SYNC_MMU: + return true; + } + return false; +} + int kvm_vm_ioctl_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap) { @@ -148,6 +167,9 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, if (is_protected_kvm_enabled() && !kvm_pkvm_ext_allowed(kvm, cap->cap)) return -EINVAL; =20 + if (kvm && kvm_vm_is_realm(kvm) && !kvm_realm_ext_allowed(cap->cap)) + return -EINVAL; + switch (cap->cap) { case KVM_CAP_ARM_NISV_TO_USER: r =3D 0; @@ -407,6 +429,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) if (is_protected_kvm_enabled() && !kvm_pkvm_ext_allowed(kvm, ext)) return 0; =20 + if (kvm && kvm_vm_is_realm(kvm) && !kvm_realm_ext_allowed(ext)) + return 0; + switch (ext) { case KVM_CAP_IRQCHIP: r =3D vgic_present; --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AF32D577E41; Tue, 8 Sep 2026 16:23:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884625; cv=none; b=Ao+p0PeRQ/FABW7D/t8RmZAGOpS3n3RjuQv2C8rhWBoK6tbupaScMA79px3ryEYZgnEeWpd0WQbJMUR7wNvEX1maYJNb/FB/ZiDF3pxT9OoQw65ugkpMy3UWkv8/bUtmWDnCMDzkvFfIoAMWunDN6EzTntUFiR9s+49YlO9+dRY= ARC-Message-Signature: i=1; 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Tue, 8 Sep 2026 09:23:39 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BA6643F7D8; Tue, 8 Sep 2026 09:23:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884622; bh=rO1Aepg+ZPdfUbjznCSF+LW5fDa0Tz1f7cbp73DbIAA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TREfTy4DfvUOhrBPONa+KEhnkj0+0n2gCSA15H2mLGooirGLP4ip4tXpKvb0vB9VK 17XwONb5gU/G3yWRcnK0dY4n2Pm8cN1rZNLqGOA12+bQeLm+ntA+OpLrk2OuWfrlio ZG2oDGaY1ItLsEVvmLjdlVtp3fmqC1yvfiugSxXc= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com Subject: [PATCH v17 15/20] KVM: arm64: CCA: WARN on injected undef exceptions Date: Tue, 8 Sep 2026 17:22:18 +0100 Message-ID: <20260908162223.1683432-16-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Steven Price The RMM doesn't allow injection of a undefined exception into a realm guest. Add a WARN to catch if this ever happens. Signed-off-by: Steven Price --- Changes since v15: * Switch to KVM_BUG() to mark the VM as bugged as well. Changes since v6: * if (x) WARN(1, ...) makes no sense, just WARN(x, ...)! --- arch/arm64/kvm/inject_fault.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c index d6c4fc16f8795..d61a3ff04fabb 100644 --- a/arch/arm64/kvm/inject_fault.c +++ b/arch/arm64/kvm/inject_fault.c @@ -317,6 +317,7 @@ void kvm_inject_size_fault(struct kvm_vcpu *vcpu) */ void kvm_inject_undefined(struct kvm_vcpu *vcpu) { + KVM_BUG(vcpu_is_rec(vcpu), vcpu->kvm, "Unexpected undefined exception inj= ection to REC"); if (vcpu_el1_is_32bit(vcpu)) inject_undef32(vcpu); else --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 89646584952; Tue, 8 Sep 2026 16:23:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884629; cv=none; b=Az0JmT4sktcpVoNjVmNNjQnj/TVQzIx7I1aNUY6oPgtkFmiFvYucT3roFExArQ3bsDJw3qW42aE5b8Zg91ZJVe/n/SL//cCLqt4NR25W+gCaArJ7jlHGc2gtCh2krS3Z7ey3T/XqpACJlR6gTIXjFzywm2HRkYFhVcVUqMNFiPk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884629; c=relaxed/simple; bh=S77v1BDbvfQaK2gnhv9ZUvhfNvS6strceig1vPocSBw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e8pkx5vYcWHceQ01Res59sJR7A65bGZNubZgwKTeeudeioQtWo7Uac11n9SJNqpZThJv8dcu6i7+y6Mh6Gur/kYasGDXUOLRE+UXEUA4vXAghBbymyaM1/IkMbwcgLyEC793j9SxMMrOg1lB9TLWNWuOmY4cYx3zfQGNf2ZW/HA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=ZrgX2Fl8; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="ZrgX2Fl8" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0828E1C01; Tue, 8 Sep 2026 09:23:43 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 491C43F7B4; Tue, 8 Sep 2026 09:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884626; bh=S77v1BDbvfQaK2gnhv9ZUvhfNvS6strceig1vPocSBw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZrgX2Fl8MhqU/CcGK6RgBT06B4x2UojJLSg1+Vkgu/tAthB79yuNwIXm1/DqfWxH5 fhKk9UEMmYwCf567408u6vmM4aLe2J/mJudjrcgCqqcvPRVnf4CWLNOP4PyTZV6Gyb 1hw/OQ9/PF09AoSuwAK8nzqxCa1lG7Dij9B6I+UA= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Jean-Philippe Brucker , Suzuki K Poulose Subject: [PATCH v17 16/20] KVM: arm64: CCA: Provide register list for unfinalized RECs Date: Tue, 8 Sep 2026 17:22:19 +0100 Message-ID: <20260908162223.1683432-17-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker KVM_GET_REG_LIST should not be called before SVE is finalized. The ioctl handler currently returns -EPERM in this case. But because it uses kvm_arm_vcpu_is_finalized(), it now also rejects the call for unfinalized REC even though finalizing the REC can only be done late, after Realm descriptor creation. Move the check to copy_sve_reg_indices(). One adverse side effect of this change is that a KVM_GET_REG_LIST call that only probes for the array size will now succeed even if SVE is not finalized, but that seems harmless since the following KVM_GET_REG_LIST with the full array will fail. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Steven Price Reviewed-by: Gavin Shan Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/arm.c | 14 +++++++++++++- arch/arm64/kvm/guest.c | 10 +++++----- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index fbb4d6651ab51..3fe5a4f77738e 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1980,6 +1980,18 @@ static int kvm_arm_vcpu_set_events(struct kvm_vcpu *= vcpu, return __kvm_arm_vcpu_set_events(vcpu, events); } =20 +/* + * Realm VCPUs can be finalized after the Realm descriptor is created. + * Allow the register list for RECs before the VCPUs are finalized, but + * after the SVE is finalized. + */ +static bool kvm_arm_vcpu_reg_list_allowed(struct kvm_vcpu *vcpu) +{ + if (kvm_arm_vcpu_is_finalized(vcpu)) + return true; + return vcpu_is_rec(vcpu); +} + long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { @@ -2035,7 +2047,7 @@ long kvm_arch_vcpu_ioctl(struct file *filp, break; =20 r =3D -EPERM; - if (!kvm_arm_vcpu_is_finalized(vcpu)) + if (!kvm_arm_vcpu_reg_list_allowed(vcpu)) break; =20 r =3D -EFAULT; diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index b01d6622b8720..c3ca369882273 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -598,8 +598,8 @@ static unsigned long num_sve_regs(const struct kvm_vcpu= *vcpu) if (!vcpu_has_sve(vcpu)) return 0; =20 - /* Policed by KVM_GET_REG_LIST: */ - WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu)); + if (!kvm_arm_vcpu_sve_finalized(vcpu)) + return 1; /* KVM_REG_ARM64_SVE_VLS */ =20 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) + 1; /* KVM_REG_ARM64_SVE_VLS */ @@ -616,9 +616,6 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, if (!vcpu_has_sve(vcpu)) return 0; =20 - /* Policed by KVM_GET_REG_LIST: */ - WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu)); - /* * Enumerate this first, so that userspace can save/restore in * the order reported by KVM_GET_REG_LIST: @@ -628,6 +625,9 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, return -EFAULT; ++num_regs; =20 + if (!kvm_arm_vcpu_sve_finalized(vcpu)) + return num_regs; + for (i =3D 0; i < slices; i++) { for (n =3D 0; n < SVE_NUM_ZREGS; n++) { reg =3D KVM_REG_ARM64_SVE_ZREG(n, i); --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4B65658496F; Tue, 8 Sep 2026 16:23:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884633; cv=none; b=sESh9K3ZE3Zyr8WpScId0RazHC7CWd36Zmd+3x/xIZcKVwxZl1msdZgIaT0nMReOKmWrbIHbbleY5Scpu6wUSyzC6YezbgzW33fmVk1rxKTACwZ7opYWA9K4CEnzGVQkm96yZOOLzgyirWKMh+QKZRReLCgBazDArh2S8HI49t8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884633; c=relaxed/simple; bh=sxqATCHsr6tDZCNJ0dXA6hDL+Vb7A5QKPzZqFLIQVuY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kLMfAF+lGTt1d3RZy0UIBwJkpnWtbqB0Q5L6BH27cSLIBzBSOsY4TClPPt5R2Jr6/IgDpxnAjitwBghh97mX+8gxUmJqz9P/KnWy8X3pMBOlAU2FFfzQrbss266F9oIMv0bD9id2NOLycIQl79b4QY8ce1dApun62P+/8ceac0o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=ZlgHLavd; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="ZlgHLavd" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C25B71477; Tue, 8 Sep 2026 09:23:46 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0E4E73F7B4; Tue, 8 Sep 2026 09:23:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884630; bh=sxqATCHsr6tDZCNJ0dXA6hDL+Vb7A5QKPzZqFLIQVuY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZlgHLavdZXg3AvqytPc25joZuVXCcPWZp31rAgA1bTU8mTy3eGWJPoXxp2TJcwZEt pnJo4Ug/lXc+Nc3QFLjBkZpSf44PcXAZ/2kG460yfTUDxwVoAMTkRBZoVu3Noo5MjV 5ey+3dk99XU/ZDt9asbYPkVJrzTse8TODk/LOnGk= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Jean-Philippe Brucker , Suzuki K Poulose Subject: [PATCH v17 17/20] KVM: arm64: CCA: Provide an accurate register list Date: Tue, 8 Sep 2026 17:22:20 +0100 Message-ID: <20260908162223.1683432-18-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker Userspace can set a few registers with KVM_SET_ONE_REG (9 GP registers at runtime, and 3 system registers during initialization). Update the register list returned by KVM_GET_REG_LIST. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Steven Price Signed-off-by: Suzuki K Poulose --- arch/arm64/kvm/guest.c | 6 ++++++ arch/arm64/kvm/hypercalls.c | 4 ++-- arch/arm64/kvm/sys_regs.c | 27 +++++++++++++++++++++------ 3 files changed, 29 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index c3ca369882273..6bec73d1ee050 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -601,6 +601,9 @@ static unsigned long num_sve_regs(const struct kvm_vcpu= *vcpu) if (!kvm_arm_vcpu_sve_finalized(vcpu)) return 1; /* KVM_REG_ARM64_SVE_VLS */ =20 + if (kvm_vm_is_realm(vcpu->kvm)) + return 1; /* KVM_REG_ARM64_SVE_VLS */ + return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) + 1; /* KVM_REG_ARM64_SVE_VLS */ } @@ -628,6 +631,9 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, if (!kvm_arm_vcpu_sve_finalized(vcpu)) return num_regs; =20 + if (kvm_vm_is_realm(vcpu->kvm)) + return num_regs; + for (i =3D 0; i < slices; i++) { for (n =3D 0; n < SVE_NUM_ZREGS; n++) { reg =3D KVM_REG_ARM64_SVE_ZREG(n, i); diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index b11b8821c9fbc..2b1e6fdeb4d5c 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -414,14 +414,14 @@ void kvm_arm_teardown_hypercalls(struct kvm *kvm) =20 int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) { - return ARRAY_SIZE(kvm_arm_fw_reg_ids); + return vcpu_is_rec(vcpu) ? 0 : ARRAY_SIZE(kvm_arm_fw_reg_ids); } =20 int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) { int i; =20 - for (i =3D 0; i < ARRAY_SIZE(kvm_arm_fw_reg_ids); i++) { + for (i =3D 0; i < kvm_arm_get_fw_num_regs(vcpu); i++) { if (put_user(kvm_arm_fw_reg_ids[i], uindices++)) return -EFAULT; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 44aae52c473d7..a58c1fc13ea17 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -5638,18 +5638,18 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, = const struct kvm_one_reg *reg sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); } =20 -static unsigned int num_demux_regs(void) +static inline unsigned int num_demux_regs(struct kvm_vcpu *vcpu) { - return CSSELR_MAX; + return vcpu_is_rec(vcpu) ? 0 : CSSELR_MAX; } =20 -static int write_demux_regids(u64 __user *uindices) +static int write_demux_regids(struct kvm_vcpu *vcpu, u64 __user *uindices) { u64 val =3D KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; unsigned int i; =20 val |=3D KVM_REG_ARM_DEMUX_ID_CCSIDR; - for (i =3D 0; i < CSSELR_MAX; i++) { + for (i =3D 0; i < num_demux_regs(vcpu); i++) { if (put_user(val | i, uindices)) return -EFAULT; uindices++; @@ -5693,11 +5693,26 @@ static bool copy_reg_to_user(const struct sys_reg_d= esc *reg, u64 __user **uind) return true; } =20 +static inline bool kvm_realm_sys_reg_hidden_user(const struct kvm_vcpu *vc= pu, + u64 reg) +{ + switch (reg) { + case SYS_ID_AA64DFR0_EL1: + case SYS_PMCR_EL0: + return false; + } + return true; +} + static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 __user **uind, unsigned int *total) { + if (vcpu_is_rec(vcpu) && + kvm_realm_sys_reg_hidden_user(vcpu, reg_to_encoding(rd))) + return 0; + /* * Ignore registers we trap but don't save, * and for which no custom user accessor is provided. @@ -5735,7 +5750,7 @@ static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 _= _user *uind) =20 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) { - return num_demux_regs() + return num_demux_regs(vcpu) + walk_sys_regs(vcpu, (u64 __user *)NULL); } =20 @@ -5748,7 +5763,7 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcp= u, u64 __user *uindices) return err; uindices +=3D err; =20 - return write_demux_regids(uindices); + return write_demux_regids(vcpu, uindices); } =20 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D87C257C712; Tue, 8 Sep 2026 16:23:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Xk9L4HoP" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6F5F61C01; Tue, 8 Sep 2026 09:23:50 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C90673F7B4; Tue, 8 Sep 2026 09:23:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884634; bh=4dJcz7Ui6l+RUG6SvRhjywJMQzx66cIRrcDMmHTUl6w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Xk9L4HoPqQR3OWVdrHMS46rx1HZ9nOwVn3L6/b1ETu0ntTEaRrCnntL2V9WhXDKRS qpDRirgQESNLkXnlmH8YCb0QnVJVkCNvKchEChb/2yHzBTxJZ7lBmYQYI32s8p9ckL sBk/PFi15aSwyMgoAHm30r74g6USmZXA2rdMs52Q= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 18/20] KVM: arm64: Reuse kvm_stage2_unmap_range in kvm_unmap_gfn_range Date: Tue, 8 Sep 2026 17:22:21 +0100 Message-ID: <20260908162223.1683432-19-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding VM specific backends for stage2 operation, switch to kvm_stage2_unmap_range() instead of __unmap_stage2_range() from the kvm_unmap_gfn_range(). Drop the bail out check for protected VMs and defer that to the one in kvm_stage2_unmap_range(). Later we would replace the logic in kvm_stage2_unmap_range() with VM specific backends. No functional changes intended. Signed-off-by: Suzuki K Poulose Reviewed-by: Fuad Tabba --- arch/arm64/kvm/mmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 9ba86450fe4af..67852acf7a6f8 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -2436,12 +2436,12 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) =20 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range) { - if (!kvm->arch.mmu.pgt || kvm_vm_is_protected(kvm)) + if (!kvm->arch.mmu.pgt) return false; =20 - __unmap_stage2_range(&kvm->arch.mmu, range->start << PAGE_SHIFT, - (range->end - range->start) << PAGE_SHIFT, - range->may_block); + kvm_stage2_unmap_range(&kvm->arch.mmu, range->start << PAGE_SHIFT, + (range->end - range->start) << PAGE_SHIFT, + range->may_block); =20 kvm_nested_s2_unmap(kvm, range->may_block); return false; --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6C44856C63F; Tue, 8 Sep 2026 16:23:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884640; cv=none; b=noLAuC7UT1v3W5lQVHynT5y4miASOchgyWr58jyi6zAE6GuFLGx9dQe89L7iRkxYnC3qkXyp5284jiLTmxEYeQNUbLqgJH/dwlV54fL4WqewqM+N48J95SVwzQMuFvKPxlO5vzXlMw3VmLzytGUhHIUMaKixrA2Z+f/XqNe1W3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788884640; c=relaxed/simple; bh=CAoe+UJNr/YaTbgVkWUXMV8SFhy8nVi8Z6d99vH1yu8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DcQYjBPfVaBXeWJH1btEMzfKv+7wJquuMPkRnx4JgbAoi+JkRYpXoTj6sZCISqY4jptpW/fbe77HI6CwK2HoSBG9iJexmXo88ntQMz2VsUzDhL79gjhoHo/AqBJOwQ9Vzay/wSm5QqTK9J1pb0gB+tNafvR+b8+JmtakykAuYIg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=cwoywZnZ; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="cwoywZnZ" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1A6F31477; Tue, 8 Sep 2026 09:23:54 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 789233F7B4; Tue, 8 Sep 2026 09:23:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884637; bh=CAoe+UJNr/YaTbgVkWUXMV8SFhy8nVi8Z6d99vH1yu8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cwoywZnZLsPBL+em+VMWV/vvuE9O4SK1hce/S1YOp1HG9gc5qtzCUJF2Bl7DAAm8N POt+OedpPtZfxaus4aEEeIi8V9bUbqN0wyzDarEMrNkr8Pt4SYBxwaaQnDX9WmGfbu 2cy/lPGFjDLaUumGQJyrxu+QJ9bZsaMELaVm+wBY= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 19/20] KVM: arm64: Add VM specific callback for S2 MMU operations Date: Tue, 8 Sep 2026 17:22:22 +0100 Message-ID: <20260908162223.1683432-20-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add VM type specific S2 MMU operation backends which can be initialized per= VM flavor, to keep the handling cleaner. Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/kvm_host.h | 15 ++++ arch/arm64/kvm/mmu.c | 129 +++++++++++++++++++++++++----- 2 files changed, 124 insertions(+), 20 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 0f258f16fdf81..e3c308b6e319f 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -157,6 +157,19 @@ struct kvm_vcpu_ops { void (*vcpu_put)(struct kvm_vcpu *vcpu); }; =20 +struct kvm_gfn_range; + +struct kvm_vm_s2_ops { + bool (*vm_age_gfn)(struct kvm *kvm, struct kvm_gfn_range *range); + bool (*vm_test_age_gfn)(struct kvm *kvm, struct kvm_gfn_range *range); + int (*vm_flush_remote_tlbs)(struct kvm *kvm); + int (*vm_flush_remote_tlbs_range)(struct kvm *kvm, gfn_t gfn, + u64 nr_pages); + void (*vm_stage2_unmap_range)(struct kvm_s2_mmu *mmu, + phys_addr_t start, u64 size, + bool may_block); +}; + struct kvm_s2_mmu { struct kvm_vmid vmid; =20 @@ -335,6 +348,8 @@ struct kvm_arch { */ u64 fgu[__NR_FGT_GROUP_IDS__]; =20 + const struct kvm_vm_s2_ops *vm_s2_ops; + /* * Stage 2 paging state for VMs with nested S2 using a virtual * VMID. diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 67852acf7a6f8..e78a56fb73696 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -37,6 +37,10 @@ static unsigned long __ro_after_init io_map_base; =20 #define KVM_PGT_FN(fn) (!is_protected_kvm_enabled() ? fn : p ## fn) =20 +static const struct kvm_vm_s2_ops protected_pkvm_s2_ops; +static const struct kvm_vm_s2_ops unprotected_pkvm_s2_ops; +static const struct kvm_vm_s2_ops kvm_default_vm_s2_ops; + static phys_addr_t __stage2_range_addr_end(phys_addr_t addr, phys_addr_t e= nd, phys_addr_t size) { @@ -166,6 +170,18 @@ static bool memslot_is_logging(struct kvm_memory_slot = *memslot) return memslot->dirty_bitmap && !(memslot->flags & KVM_MEM_READONLY); } =20 +static int pkvm_flush_remote_tlbs(struct kvm *kvm) +{ + kvm_call_hyp_nvhe(__pkvm_tlb_flush_vmid, kvm->arch.pkvm.handle); + return 0; +} + +static int kvm_vm_flush_remote_tlbs(struct kvm *kvm) +{ + kvm_call_hyp(__kvm_tlb_flush_vmid, &kvm->arch.mmu); + return 0; +} + /** * kvm_arch_flush_remote_tlbs() - flush all VM TLB entries for v7/8 * @kvm: pointer to kvm structure. @@ -174,26 +190,36 @@ static bool memslot_is_logging(struct kvm_memory_slot= *memslot) */ int kvm_arch_flush_remote_tlbs(struct kvm *kvm) { - if (is_protected_kvm_enabled()) - kvm_call_hyp_nvhe(__pkvm_tlb_flush_vmid, kvm->arch.pkvm.handle); - else - kvm_call_hyp(__kvm_tlb_flush_vmid, &kvm->arch.mmu); - return 0; + if (!kvm->arch.vm_s2_ops->vm_flush_remote_tlbs) + return 0; + return kvm->arch.vm_s2_ops->vm_flush_remote_tlbs(kvm); } =20 -int kvm_arch_flush_remote_tlbs_range(struct kvm *kvm, - gfn_t gfn, u64 nr_pages) +static int pkvm_flush_remote_tlbs_range(struct kvm *kvm, + gfn_t gfn, u64 nr_pages) +{ + return pkvm_flush_remote_tlbs(kvm); +} + +static int kvm_vm_flush_remote_tlbs_range(struct kvm *kvm, + gfn_t gfn, u64 nr_pages) { u64 size =3D nr_pages << PAGE_SHIFT; u64 addr =3D gfn << PAGE_SHIFT; =20 - if (is_protected_kvm_enabled()) - kvm_call_hyp_nvhe(__pkvm_tlb_flush_vmid, kvm->arch.pkvm.handle); - else - kvm_tlb_flush_vmid_range(&kvm->arch.mmu, addr, size); + kvm_tlb_flush_vmid_range(&kvm->arch.mmu, addr, size); return 0; } =20 +int kvm_arch_flush_remote_tlbs_range(struct kvm *kvm, + gfn_t gfn, u64 nr_pages) +{ + if (!kvm->arch.vm_s2_ops->vm_flush_remote_tlbs_range) + return 0; + + return kvm->arch.vm_s2_ops->vm_flush_remote_tlbs_range(kvm, gfn, nr_pages= ); +} + static void *stage2_memcache_zalloc_page(void *arg) { struct kvm_mmu_memory_cache *mc =3D arg; @@ -337,13 +363,20 @@ static void __unmap_stage2_range(struct kvm_s2_mmu *m= mu, phys_addr_t start, u64 may_block)); } =20 +static void kvm_vm_stage2_unmap_range(struct kvm_s2_mmu *mmu, + phys_addr_t start, + u64 size, bool may_block) +{ + __unmap_stage2_range(mmu, start, size, may_block); +} + void kvm_stage2_unmap_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 size, bool may_block) { - if (kvm_vm_is_protected(kvm_s2_mmu_to_kvm(mmu))) - return; + struct kvm *kvm =3D kvm_s2_mmu_to_kvm(mmu); =20 - __unmap_stage2_range(mmu, start, size, may_block); + if (kvm->arch.vm_s2_ops->vm_stage2_unmap_range) + kvm->arch.vm_s2_ops->vm_stage2_unmap_range(mmu, start, size, may_block); } =20 void kvm_stage2_flush_range(struct kvm_s2_mmu *mmu, phys_addr_t addr, phys= _addr_t end) @@ -963,6 +996,18 @@ static void kvm_stage2_destroy(struct kvm_pgtable *pgt) KVM_PGT_FN(kvm_pgtable_stage2_destroy_pgd)(pgt); } =20 +static const struct kvm_vm_s2_ops *arm64_vm_s2_ops[VM_FLAVOR_MAX] =3D { + [VM_VHE] =3D &kvm_default_vm_s2_ops, + [VM_NVHE] =3D &kvm_default_vm_s2_ops, + [VM_PKVM] =3D &unprotected_pkvm_s2_ops, + [VM_PROTECTED_PKVM] =3D &protected_pkvm_s2_ops, +}; + +static void kvm_vm_init_vm_s2_ops(struct kvm *kvm, unsigned long type) +{ + kvm->arch.vm_s2_ops =3D arm64_vm_s2_ops[kvm->arch.vm_flavor]; +} + /** * kvm_init_stage2_mmu - Initialise a S2 MMU structure * @kvm: The pointer to the KVM structure @@ -983,6 +1028,9 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2= _mmu *mmu, unsigned long t int cpu, err; struct kvm_pgtable *pgt; =20 + /* Initialize the VM ops for the VM instance for the first time */ + if (mmu =3D=3D &kvm->arch.mmu) + kvm_vm_init_vm_s2_ops(kvm, type); /* * If we already have our page tables in place, and that the * MMU context is the canonical one, we have a bug somewhere, @@ -2447,27 +2495,32 @@ bool kvm_unmap_gfn_range(struct kvm *kvm, struct kv= m_gfn_range *range) return false; } =20 -bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) +static bool kvm_vm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) { u64 size =3D (range->end - range->start) << PAGE_SHIFT; =20 - if (!kvm->arch.mmu.pgt || kvm_vm_is_protected(kvm)) - return false; - return KVM_PGT_FN(kvm_pgtable_stage2_test_clear_young)(kvm->arch.mmu.pgt, range->start << PAGE_SHIFT, size, true); +} + +bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) +{ + if (!kvm->arch.mmu.pgt || !kvm->arch.vm_s2_ops->vm_age_gfn) + return false; + + return kvm->arch.vm_s2_ops->vm_age_gfn(kvm, range); /* * TODO: Handle nested_mmu structures here using the reverse mapping in * a later version of patch series. */ } =20 -bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) +static bool kvm_vm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *ran= ge) { u64 size =3D (range->end - range->start) << PAGE_SHIFT; =20 - if (!kvm->arch.mmu.pgt || kvm_vm_is_protected(kvm)) + if (!kvm->arch.mmu.pgt) return false; =20 return KVM_PGT_FN(kvm_pgtable_stage2_test_clear_young)(kvm->arch.mmu.pgt, @@ -2475,6 +2528,15 @@ bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gf= n_range *range) size, false); } =20 +bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) +{ + + if (!kvm->arch.mmu.pgt || !kvm->arch.vm_s2_ops->vm_test_age_gfn) + return false; + + return kvm->arch.vm_s2_ops->vm_test_age_gfn(kvm, range); +} + phys_addr_t kvm_mmu_get_httbr(void) { return __pa(hyp_pgtable->pgd); @@ -2796,3 +2858,30 @@ void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool wa= s_enabled) =20 trace_kvm_toggle_cache(*vcpu_pc(vcpu), was_enabled, now_enabled); } + +static const struct kvm_vm_s2_ops protected_vm_s2_ops =3D { + .vm_flush_remote_tlbs =3D pkvm_flush_remote_tlbs, + .vm_flush_remote_tlbs_range =3D pkvm_flush_remote_tlbs_range, + /* + * Not supported for Protected VMs under pKVM + * .vm_age_gfn + * .vm_test_age_gfn + * .vm_stage2_unmap_range + */ +}; + +static const struct kvm_vm_s2_ops pkvm_vm_s2_ops =3D { + .vm_flush_remote_tlbs =3D pkvm_flush_remote_tlbs, + .vm_flush_remote_tlbs_range =3D pkvm_flush_remote_tlbs_range, + .vm_age_gfn =3D kvm_vm_age_gfn, + .vm_test_age_gfn =3D kvm_vm_test_age_gfn, + .vm_stage2_unmap_range =3D kvm_vm_stage2_unmap_range, +}; + +static const struct kvm_vm_s2_ops kvm_default_vm_s2_ops =3D { + .vm_flush_remote_tlbs =3D kvm_vm_flush_remote_tlbs, + .vm_flush_remote_tlbs_range =3D kvm_vm_flush_remote_tlbs_range, + .vm_age_gfn =3D kvm_vm_age_gfn, + .vm_test_age_gfn =3D kvm_vm_test_age_gfn, + .vm_stage2_unmap_range =3D kvm_vm_stage2_unmap_range, +}; --=20 2.43.0 From nobody Fri Sep 25 20:48:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 15583585998; Tue, 8 Sep 2026 16:24:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="E1dF61eh" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B2B2F1C01; Tue, 8 Sep 2026 09:23:57 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.2.197.99]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1CF153F7B4; Tue, 8 Sep 2026 09:23:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1788884641; bh=TV5sgn3MU+BPdCIki4A9TOoFrWpKgF21nYvxFenyEoY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E1dF61ehF0Jpq3xi78ZC73lgGaUWuVrilGM/A/R6a9qU20SNBdHpNU6+IM6Cettf/ 3ZDdDIAxveVZWA0EAl2mV93ntq1IOGR/Z7Qin1deIxA7V+xDAuXZwUAzDEgRaTWiHe xuJL4vbQ+E8tJSkL/+StD+21yJRsRgADwXGtgYzc= From: Suzuki K Poulose To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, Suzuki K Poulose Subject: [PATCH v17 20/20] KVM: arm64: Abstract out memory abort handling Date: Tue, 8 Sep 2026 17:22:23 +0100 Message-ID: <20260908162223.1683432-21-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908162223.1683432-1-suzuki.poulose@arm.com> References: <20260908162223.1683432-1-suzuki.poulose@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the memory abort handling under VM specific s2 operation. Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/mmu.c | 36 +++++++++++++++++++------------ 2 files changed, 24 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index e3c308b6e319f..fbfd85dc999ef 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -158,6 +158,7 @@ struct kvm_vcpu_ops { }; =20 struct kvm_gfn_range; +struct kvm_s2_fault_desc; =20 struct kvm_vm_s2_ops { bool (*vm_age_gfn)(struct kvm *kvm, struct kvm_gfn_range *range); @@ -168,6 +169,7 @@ struct kvm_vm_s2_ops { void (*vm_stage2_unmap_range)(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 size, bool may_block); + int (*vm_mem_abort)(const struct kvm_s2_fault_desc *s2fd); }; =20 struct kvm_s2_mmu { diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index e78a56fb73696..5e7cdbe310fc8 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1753,7 +1753,7 @@ struct kvm_s2_fault_vma_info { bool map_non_cacheable; }; =20 -static int pkvm_mem_abort(const struct kvm_s2_fault_desc *s2fd) +static int protected_vm_mem_abort(const struct kvm_s2_fault_desc *s2fd) { unsigned int flags =3D FOLL_HWPOISON | FOLL_LONGTERM | FOLL_WRITE; struct kvm_vcpu *vcpu =3D s2fd->vcpu; @@ -2191,6 +2191,22 @@ static int user_mem_abort(const struct kvm_s2_fault_= desc *s2fd) return kvm_s2_fault_map(s2fd, &s2vi, prot, memcache); } =20 +static int kvm_vm_mem_abort(const struct kvm_s2_fault_desc *s2fd) +{ + int ret; + struct kvm_vcpu *vcpu =3D s2fd->vcpu; + + VM_WARN_ON_ONCE(kvm_vcpu_trap_is_permission_fault(vcpu) && + !kvm_is_write_fault(vcpu) && + !kvm_vcpu_trap_is_exec_fault(vcpu)); + + if (kvm_slot_has_gmem(s2fd->memslot)) + ret =3D gmem_abort(s2fd); + else + ret =3D user_mem_abort(s2fd); + return ret; +} + /* Resolve the access fault by making the page young again. */ static void handle_access_fault(struct kvm_vcpu *vcpu, phys_addr_t fault_i= pa) { @@ -2298,6 +2314,7 @@ int kvm_handle_guest_sea(struct kvm_vcpu *vcpu) int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) { struct kvm_s2_trans nested_trans, *nested =3D NULL; + struct kvm *kvm =3D vcpu->kvm; unsigned long esr; phys_addr_t fault_ipa; /* The address we faulted on */ phys_addr_t ipa; /* Always the IPA in the L1 guest phys space */ @@ -2459,19 +2476,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) .hva =3D hva, }; =20 - if (kvm_vm_is_protected(vcpu->kvm)) { - ret =3D pkvm_mem_abort(&s2fd); - } else { - VM_WARN_ON_ONCE(kvm_vcpu_trap_is_permission_fault(vcpu) && - !write_fault && - !kvm_vcpu_trap_is_exec_fault(vcpu)); - - if (kvm_slot_has_gmem(memslot)) - ret =3D gmem_abort(&s2fd); - else - ret =3D user_mem_abort(&s2fd); - } - + ret =3D kvm->arch.vm_s2_ops->vm_mem_abort(&s2fd); if (ret =3D=3D 0) ret =3D 1; out: @@ -2868,6 +2873,7 @@ static const struct kvm_vm_s2_ops protected_vm_s2_ops= =3D { * .vm_test_age_gfn * .vm_stage2_unmap_range */ + .vm_mem_abort =3D protected_vm_mem_abort, }; =20 static const struct kvm_vm_s2_ops pkvm_vm_s2_ops =3D { @@ -2876,6 +2882,7 @@ static const struct kvm_vm_s2_ops pkvm_vm_s2_ops =3D { .vm_age_gfn =3D kvm_vm_age_gfn, .vm_test_age_gfn =3D kvm_vm_test_age_gfn, .vm_stage2_unmap_range =3D kvm_vm_stage2_unmap_range, + .vm_mem_abort =3D kvm_vm_mem_abort, }; =20 static const struct kvm_vm_s2_ops kvm_default_vm_s2_ops =3D { @@ -2884,4 +2891,5 @@ static const struct kvm_vm_s2_ops kvm_default_vm_s2_o= ps =3D { .vm_age_gfn =3D kvm_vm_age_gfn, .vm_test_age_gfn =3D kvm_vm_test_age_gfn, .vm_stage2_unmap_range =3D kvm_vm_stage2_unmap_range, + .vm_mem_abort =3D kvm_vm_mem_abort, }; --=20 2.43.0