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[35.229.176.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08cacbb0sm31999240a91.13.2026.09.08.02.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:40:41 -0700 (PDT) From: Kuan-Wei Chiu To: geert@linux-m68k.org, tglx@kernel.org, miodrag.dinic@mips.com Cc: radu@rendec.net, zewenchen@google.com, jamiechen@google.com, edwardwchen@google.com, marscheng@google.com, eleanor15x@gmail.com, jserv@ccns.ncku.edu.tw, linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, Kuan-Wei Chiu Subject: [PATCH 1/6] irqchip/goldfish-pic: Use gf_ioread32/gf_iowrite32 for MMIO access Date: Tue, 8 Sep 2026 09:40:11 +0000 Message-ID: <20260908094016.1997918-2-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.979.g7e5102b832-goog In-Reply-To: <20260908094016.1997918-1-visitorckw@gmail.com> References: <20260908094016.1997918-1-visitorckw@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The goldfish PIC driver uses readl() and writel() directly for register accesses. On big endian architectures, goldfish devices require big endian MMIO accessors [1]. Switch to gf_ioread32() and gf_iowrite32() to make MMIO accesses endian safe. Link: https://gitlab.com/qemu-project/qemu/-/blob/stable-11.1/hw/intc/goldf= ish_pic.c#L130 [1] Signed-off-by: Kuan-Wei Chiu --- drivers/irqchip/irq-goldfish-pic.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-goldfish-pic.c b/drivers/irqchip/irq-goldf= ish-pic.c index d458cf898f8e..c3c33f066140 100644 --- a/drivers/irqchip/irq-goldfish-pic.c +++ b/drivers/irqchip/irq-goldfish-pic.c @@ -7,6 +7,7 @@ =20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 +#include #include #include #include @@ -38,7 +39,7 @@ static void goldfish_pic_cascade(struct irq_desc *desc) =20 chained_irq_enter(host_chip, desc); =20 - pending =3D readl(gfpic->base + GFPIC_REG_IRQ_PENDING); + pending =3D gf_ioread32(gfpic->base + GFPIC_REG_IRQ_PENDING); while (pending) { hwirq =3D __fls(pending); generic_handle_domain_irq(gfpic->irq_domain, hwirq); @@ -52,6 +53,16 @@ static const struct irq_domain_ops goldfish_irq_domain_o= ps =3D { .xlate =3D irq_domain_xlate_onecell, }; =20 +static u32 gfpic_read(void __iomem *addr) +{ + return gf_ioread32(addr); +} + +static void gfpic_write(u32 val, void __iomem *addr) +{ + gf_iowrite32(val, addr); +} + static int __init goldfish_pic_of_init(struct device_node *of_node, struct device_node *parent) { @@ -82,7 +93,7 @@ static int __init goldfish_pic_of_init(struct device_node= *of_node, } =20 /* Mask interrupts. */ - writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL); + gf_iowrite32(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL); =20 gc =3D irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base, handle_level_irq); @@ -92,6 +103,9 @@ static int __init goldfish_pic_of_init(struct device_nod= e *of_node, goto out_iounmap; } =20 + gc->reg_readl =3D gfpic_read; + gc->reg_writel =3D gfpic_write; + ct =3D gc->chip_types; ct->regs.enable =3D GFPIC_REG_IRQ_ENABLE; ct->regs.disable =3D GFPIC_REG_IRQ_DISABLE; --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 21:40:23 2026 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 496854B0487 for ; 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[35.229.176.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08cacbb0sm31999240a91.13.2026.09.08.02.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:40:47 -0700 (PDT) From: Kuan-Wei Chiu To: geert@linux-m68k.org, tglx@kernel.org, miodrag.dinic@mips.com Cc: radu@rendec.net, zewenchen@google.com, jamiechen@google.com, edwardwchen@google.com, marscheng@google.com, eleanor15x@gmail.com, jserv@ccns.ncku.edu.tw, linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, Kuan-Wei Chiu Subject: [PATCH 2/6] irqchip/goldfish-pic: Use for_each_set_bit() to iterate pending IRQ Date: Tue, 8 Sep 2026 09:40:12 +0000 Message-ID: <20260908094016.1997918-3-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.979.g7e5102b832-goog In-Reply-To: <20260908094016.1997918-1-visitorckw@gmail.com> References: <20260908094016.1997918-1-visitorckw@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use for_each_set_bit() instead of open-coding the loop with __fls() in goldfish_pic_cascade() to simplify the code. Signed-off-by: Kuan-Wei Chiu --- drivers/irqchip/irq-goldfish-pic.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-goldfish-pic.c b/drivers/irqchip/irq-goldf= ish-pic.c index c3c33f066140..12113ca90872 100644 --- a/drivers/irqchip/irq-goldfish-pic.c +++ b/drivers/irqchip/irq-goldfish-pic.c @@ -7,6 +7,7 @@ =20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 +#include #include #include #include @@ -35,16 +36,14 @@ static void goldfish_pic_cascade(struct irq_desc *desc) { struct goldfish_pic_data *gfpic =3D irq_desc_get_handler_data(desc); struct irq_chip *host_chip =3D irq_desc_get_chip(desc); - u32 pending, hwirq; + unsigned long pending; + u32 hwirq; =20 chained_irq_enter(host_chip, desc); =20 pending =3D gf_ioread32(gfpic->base + GFPIC_REG_IRQ_PENDING); - while (pending) { - hwirq =3D __fls(pending); + for_each_set_bit(hwirq, &pending, GFPIC_NR_IRQS) generic_handle_domain_irq(gfpic->irq_domain, hwirq); - pending &=3D ~(1 << hwirq); - } =20 chained_irq_exit(host_chip, desc); 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[35.229.176.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08cacbb0sm31999240a91.13.2026.09.08.02.40.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:40:52 -0700 (PDT) From: Kuan-Wei Chiu To: geert@linux-m68k.org, tglx@kernel.org, miodrag.dinic@mips.com Cc: radu@rendec.net, zewenchen@google.com, jamiechen@google.com, edwardwchen@google.com, marscheng@google.com, eleanor15x@gmail.com, jserv@ccns.ncku.edu.tw, linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, Kuan-Wei Chiu Subject: [PATCH 3/6] irqchip/goldfish-pic: Allow selecting CONFIG_GOLDFISH_PIC on other architectures Date: Tue, 8 Sep 2026 09:40:13 +0000 Message-ID: <20260908094016.1997918-4-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.979.g7e5102b832-goog In-Reply-To: <20260908094016.1997918-1-visitorckw@gmail.com> References: <20260908094016.1997918-1-visitorckw@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop the MIPS dependency from CONFIG_GOLDFISH_PIC so that other architectures can use this driver. Also update the file header comment to remove the MIPS reference. Signed-off-by: Kuan-Wei Chiu --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-goldfish-pic.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 20b77fbc51ee..a0f0f3a0e8ea 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -513,7 +513,7 @@ config MESON_IRQ_GPIO =20 config GOLDFISH_PIC bool "Goldfish programmable interrupt controller" - depends on MIPS && (GOLDFISH || COMPILE_TEST) + depends on GOLDFISH || COMPILE_TEST select GENERIC_IRQ_CHIP select IRQ_DOMAIN help diff --git a/drivers/irqchip/irq-goldfish-pic.c b/drivers/irqchip/irq-goldf= ish-pic.c index 12113ca90872..8d40df0e3a88 100644 --- a/drivers/irqchip/irq-goldfish-pic.c +++ b/drivers/irqchip/irq-goldfish-pic.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Driver for MIPS Goldfish Programmable Interrupt Controller. + * Driver for Goldfish Programmable Interrupt Controller. * * Author: Miodrag Dinic */ --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 21:40:23 2026 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 162154BC005 for ; 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[35.229.176.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08cacbb0sm31999240a91.13.2026.09.08.02.40.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:40:57 -0700 (PDT) From: Kuan-Wei Chiu To: geert@linux-m68k.org, tglx@kernel.org, miodrag.dinic@mips.com Cc: radu@rendec.net, zewenchen@google.com, jamiechen@google.com, edwardwchen@google.com, marscheng@google.com, eleanor15x@gmail.com, jserv@ccns.ncku.edu.tw, linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, Kuan-Wei Chiu Subject: [PATCH 4/6] irqchip/goldfish-pic: Add goldfish_pic_init() for non DT platforms Date: Tue, 8 Sep 2026 09:40:14 +0000 Message-ID: <20260908094016.1997918-5-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.979.g7e5102b832-goog In-Reply-To: <20260908094016.1997918-1-visitorckw@gmail.com> References: <20260908094016.1997918-1-visitorckw@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver currently only supports device tree initialization and hardcodes the IRQ base to 8, which prevents non DT platforms from using it. Split the core controller setup out of goldfish_pic_of_init() into a new exported helper goldfish_pic_init() that accepts a mapped base address, parent IRQ, IRQ base, and fwnode. Signed-off-by: Kuan-Wei Chiu --- MAINTAINERS | 1 + drivers/irqchip/irq-goldfish-pic.c | 84 ++++++++++++++---------- include/linux/irqchip/irq-goldfish-pic.h | 15 +++++ 3 files changed, 67 insertions(+), 33 deletions(-) create mode 100644 include/linux/irqchip/irq-goldfish-pic.h diff --git a/MAINTAINERS b/MAINTAINERS index 6215fcb07770..f6c37e1dbee7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2004,6 +2004,7 @@ M: Miodrag Dinic S: Supported F: Documentation/devicetree/bindings/interrupt-controller/google,goldfish-= pic.yaml F: drivers/irqchip/irq-goldfish-pic.c +F: include/linux/irqchip/irq-goldfish-pic.h =20 ANDROID GOLDFISH RTC DRIVER M: Jiaxun Yang diff --git a/drivers/irqchip/irq-goldfish-pic.c b/drivers/irqchip/irq-goldf= ish-pic.c index 8d40df0e3a88..a3e9d4672ffd 100644 --- a/drivers/irqchip/irq-goldfish-pic.c +++ b/drivers/irqchip/irq-goldfish-pic.c @@ -13,15 +13,13 @@ #include #include #include +#include #include #include #include =20 #define GFPIC_NR_IRQS 32 =20 -/* 8..39 Cascaded Goldfish PIC interrupts */ -#define GFPIC_IRQ_BASE 8 - #define GFPIC_REG_IRQ_PENDING 0x04 #define GFPIC_REG_IRQ_DISABLE_ALL 0x08 #define GFPIC_REG_IRQ_DISABLE 0x0c @@ -62,44 +60,29 @@ static void gfpic_write(u32 val, void __iomem *addr) gf_iowrite32(val, addr); } =20 -static int __init goldfish_pic_of_init(struct device_node *of_node, - struct device_node *parent) +int __init goldfish_pic_init(void __iomem *base, unsigned int parent_irq, + unsigned int irq_base, struct fwnode_handle *fwnode) { struct goldfish_pic_data *gfpic; struct irq_chip_generic *gc; struct irq_chip_type *ct; - unsigned int parent_irq; - int ret =3D 0; + int ret; =20 gfpic =3D kzalloc_obj(*gfpic); - if (!gfpic) { - ret =3D -ENOMEM; - goto out_err; - } + if (!gfpic) + return -ENOMEM; =20 - parent_irq =3D irq_of_parse_and_map(of_node, 0); - if (!parent_irq) { - pr_err("Failed to map parent IRQ!\n"); - ret =3D -EINVAL; - goto out_free; - } - - gfpic->base =3D of_iomap(of_node, 0); - if (!gfpic->base) { - pr_err("Failed to map base address!\n"); - ret =3D -ENOMEM; - goto out_unmap_irq; - } + gfpic->base =3D base; =20 /* Mask interrupts. */ gf_iowrite32(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL); =20 - gc =3D irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base, + gc =3D irq_alloc_generic_chip("GFPIC", 1, irq_base, gfpic->base, handle_level_irq); if (!gc) { pr_err("Failed to allocate chip structures!\n"); ret =3D -ENOMEM; - goto out_iounmap; + goto out_free; } =20 gc->reg_readl =3D gfpic_read; @@ -114,8 +97,9 @@ static int __init goldfish_pic_of_init(struct device_nod= e *of_node, irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0, IRQ_NOPROBE | IRQ_LEVEL, 0); =20 - gfpic->irq_domain =3D irq_domain_create_legacy(of_fwnode_handle(of_node),= GFPIC_NR_IRQS, - GFPIC_IRQ_BASE, 0, &goldfish_irq_domain_ops, + gfpic->irq_domain =3D irq_domain_create_legacy(fwnode, GFPIC_NR_IRQS, + irq_base, 0, + &goldfish_irq_domain_ops, NULL); if (!gfpic->irq_domain) { pr_err("Failed to add irqdomain!\n"); @@ -132,15 +116,49 @@ static int __init goldfish_pic_of_init(struct device_= node *of_node, out_destroy_generic_chip: irq_destroy_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), IRQ_NOPROBE | IRQ_LEVEL, 0); -out_iounmap: - iounmap(gfpic->base); -out_unmap_irq: - irq_dispose_mapping(parent_irq); out_free: kfree(gfpic); -out_err: pr_err("Failed to initialize! (errno =3D %d)\n", ret); return ret; } =20 +#ifdef CONFIG_OF +/* 8..39 Cascaded Goldfish PIC interrupts */ +#define GFPIC_OF_IRQ_BASE 8 + +static int __init goldfish_pic_of_init(struct device_node *of_node, + struct device_node *parent) +{ + unsigned int parent_irq; + void __iomem *base; + int ret; + + parent_irq =3D irq_of_parse_and_map(of_node, 0); + if (!parent_irq) { + pr_err("Failed to map parent IRQ!\n"); + return -EINVAL; + } + + base =3D of_iomap(of_node, 0); + if (!base) { + pr_err("Failed to map base address!\n"); + ret =3D -ENOMEM; + goto out_unmap_irq; + } + + ret =3D goldfish_pic_init(base, parent_irq, GFPIC_OF_IRQ_BASE, + of_fwnode_handle(of_node)); + if (ret) + goto out_iounmap; + + return 0; + +out_iounmap: + iounmap(base); +out_unmap_irq: + irq_dispose_mapping(parent_irq); + return ret; +} + IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init= ); +#endif diff --git a/include/linux/irqchip/irq-goldfish-pic.h b/include/linux/irqch= ip/irq-goldfish-pic.h new file mode 100644 index 000000000000..f2e8762aec88 --- /dev/null +++ b/include/linux/irqchip/irq-goldfish-pic.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Goldfish Programmable Interrupt Controller support + */ + +#ifndef __LINUX_IRQCHIP_IRQ_GOLDFISH_PIC_H +#define __LINUX_IRQCHIP_IRQ_GOLDFISH_PIC_H + +#include +#include + +int goldfish_pic_init(void __iomem *base, unsigned int parent_irq, + unsigned int irq_base, struct fwnode_handle *fwnode); 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[35.229.176.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08cacbb0sm31999240a91.13.2026.09.08.02.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:41:02 -0700 (PDT) From: Kuan-Wei Chiu To: geert@linux-m68k.org, tglx@kernel.org, miodrag.dinic@mips.com Cc: radu@rendec.net, zewenchen@google.com, jamiechen@google.com, edwardwchen@google.com, marscheng@google.com, eleanor15x@gmail.com, jserv@ccns.ncku.edu.tw, linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, Kuan-Wei Chiu Subject: [PATCH 5/6] m68k/irq: Add empty irq_eoi callback to auto/user IRQ chips Date: Tue, 8 Sep 2026 09:40:15 +0000 Message-ID: <20260908094016.1997918-6-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.979.g7e5102b832-goog In-Reply-To: <20260908094016.1997918-1-visitorckw@gmail.com> References: <20260908094016.1997918-1-visitorckw@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When an irq_chip lacks an irq_eoi callback, chained_irq_enter() falls back to invoking chip->irq_mask(). On auto_irq_chip and user_irq_chip, this leads to a NULL pointer dereference because autovector interrupts are masked via the CPU SR rather than dedicated mask registers. Add a no-op m68k_irq_eoi() callback to auto_irq_chip and user_irq_chip so chained interrupt handlers can safely attach to these chips. Signed-off-by: Kuan-Wei Chiu --- arch/m68k/kernel/ints.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/m68k/kernel/ints.c b/arch/m68k/kernel/ints.c index cf2b13488476..731d04ac95bd 100644 --- a/arch/m68k/kernel/ints.c +++ b/arch/m68k/kernel/ints.c @@ -33,16 +33,22 @@ extern u16 user_irqvec_fixup[]; =20 static int m68k_first_user_vec; =20 +static void m68k_irq_eoi(struct irq_data *data) +{ +} + static struct irq_chip auto_irq_chip =3D { .name =3D "auto", .irq_startup =3D m68k_irq_startup, .irq_shutdown =3D m68k_irq_shutdown, + .irq_eoi =3D m68k_irq_eoi, }; =20 static struct irq_chip user_irq_chip =3D { .name =3D "user", .irq_startup =3D m68k_irq_startup, .irq_shutdown =3D m68k_irq_shutdown, + .irq_eoi =3D m68k_irq_eoi, }; =20 /* --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 21:40:23 2026 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAFEA5237A2 for ; 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[35.229.176.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08cacbb0sm31999240a91.13.2026.09.08.02.41.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:41:07 -0700 (PDT) From: Kuan-Wei Chiu To: geert@linux-m68k.org, tglx@kernel.org, miodrag.dinic@mips.com Cc: radu@rendec.net, zewenchen@google.com, jamiechen@google.com, edwardwchen@google.com, marscheng@google.com, eleanor15x@gmail.com, jserv@ccns.ncku.edu.tw, linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, Kuan-Wei Chiu Subject: [PATCH 6/6] m68k: virt: Switch to generic goldfish-pic driver Date: Tue, 8 Sep 2026 09:40:16 +0000 Message-ID: <20260908094016.1997918-7-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.979.g7e5102b832-goog In-Reply-To: <20260908094016.1997918-1-visitorckw@gmail.com> References: <20260908094016.1997918-1-visitorckw@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The m68k virt platform implements a custom irq_chip and chained handler in arch/m68k/virt/ints.c to handle its 6 goldfish PIC instances. Replace this custom implementation with calls to goldfish_pic_init() to use the generic goldfish-pic driver, and select CONFIG_GOLDFISH_PIC for CONFIG_VIRT. Signed-off-by: Kuan-Wei Chiu --- arch/m68k/Kconfig.machine | 1 + arch/m68k/virt/ints.c | 89 ++++----------------------------------- 2 files changed, 10 insertions(+), 80 deletions(-) diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine index cff990c319cb..7b15012ffb28 100644 --- a/arch/m68k/Kconfig.machine +++ b/arch/m68k/Kconfig.machine @@ -130,6 +130,7 @@ config VIRT depends on MMU select GENERIC_CLOCKEVENTS select GOLDFISH + select GOLDFISH_PIC select GOLDFISH_TIMER select GOLDFISH_TTY select M68040 diff --git a/arch/m68k/virt/ints.c b/arch/m68k/virt/ints.c index 896aa6eb8bcc..54da6b1f5ce7 100644 --- a/arch/m68k/virt/ints.c +++ b/arch/m68k/virt/ints.c @@ -1,25 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 =20 -#include #include -#include -#include -#include -#include -#include #include +#include =20 -#include #include #include #include #include =20 -#define GFPIC_REG_IRQ_PENDING 0x04 -#define GFPIC_REG_IRQ_DISABLE_ALL 0x08 -#define GFPIC_REG_IRQ_DISABLE 0x0c -#define GFPIC_REG_IRQ_ENABLE 0x10 - static struct resource picres[6]; static const char *picname[6] =3D { "goldfish_pic.0", @@ -50,43 +39,6 @@ static const char *picname[6] =3D { * CPU IRQ #7 -> NMI */ =20 -static u32 gfpic_read(int pic, int reg) -{ - void __iomem *base =3D (void __iomem *)(virt_bi_data.pic.mmio + - pic * 0x1000); - - return ioread32be(base + reg); -} - -static void gfpic_write(u32 value, int pic, int reg) -{ - void __iomem *base =3D (void __iomem *)(virt_bi_data.pic.mmio + - pic * 0x1000); - - iowrite32be(value, base + reg); -} - -#define GF_PIC(irq) ((irq - IRQ_USER) / 32) -#define GF_IRQ(irq) ((irq - IRQ_USER) % 32) - -static void virt_irq_enable(struct irq_data *data) -{ - gfpic_write(BIT(GF_IRQ(data->irq)), GF_PIC(data->irq), - GFPIC_REG_IRQ_ENABLE); -} - -static void virt_irq_disable(struct irq_data *data) -{ - gfpic_write(BIT(GF_IRQ(data->irq)), GF_PIC(data->irq), - GFPIC_REG_IRQ_DISABLE); -} - -static unsigned int virt_irq_startup(struct irq_data *data) -{ - virt_irq_enable(data); - return 0; -} - static irqreturn_t virt_nmi_handler(int irq, void *dev_id) { static int in_nmi; @@ -102,40 +54,12 @@ static irqreturn_t virt_nmi_handler(int irq, void *dev= _id) return IRQ_HANDLED; } =20 -static struct irq_chip virt_irq_chip =3D { - .name =3D "virt", - .irq_enable =3D virt_irq_enable, - .irq_disable =3D virt_irq_disable, - .irq_startup =3D virt_irq_startup, - .irq_shutdown =3D virt_irq_disable, -}; - -static void goldfish_pic_irq(struct irq_desc *desc) -{ - u32 irq_pending; - unsigned int irq_num; - unsigned int pic =3D desc->irq_data.irq - 1; - - irq_pending =3D gfpic_read(pic, GFPIC_REG_IRQ_PENDING); - irq_num =3D IRQ_USER + pic * 32; - - do { - if (irq_pending & 1) - generic_handle_irq(irq_num); - ++irq_num; - irq_pending >>=3D 1; - } while (irq_pending); -} - void __init virt_init_IRQ(void) { unsigned int i; - - m68k_setup_irq_controller(&virt_irq_chip, handle_simple_irq, IRQ_USER, - NUM_VIRT_SOURCES - IRQ_USER); + int ret; =20 for (i =3D 0; i < 6; i++) { - picres[i] =3D (struct resource) DEFINE_RES_MEM_NAMED(virt_bi_data.pic.mmio + i * 0x1000, 0x1000, picname[i]); @@ -144,8 +68,13 @@ void __init virt_init_IRQ(void) return; } =20 - irq_set_chained_handler(virt_bi_data.pic.irq + i, - goldfish_pic_irq); + ret =3D goldfish_pic_init((void __iomem *)(virt_bi_data.pic.mmio + i * 0= x1000), + virt_bi_data.pic.irq + i, + IRQ_USER + i * 32, NULL); + if (ret) { + pr_err("Failed to initialize %s\n", picname[i]); + return; + } } =20 if (request_irq(IRQ_AUTO_7, virt_nmi_handler, 0, "NMI", --=20 2.55.0.979.g7e5102b832-goog