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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08c39227sm32109846a91.9.2026.09.08.02.28.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:28:51 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v6 1/6] dt-bindings: display: verisilicon,dc: add support for nuvoton,ma35d1-dcu Date: Tue, 8 Sep 2026 17:28:35 +0800 Message-ID: <20260908092840.225220-2-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908092840.225220-1-a0987203069@gmail.com> References: <20260908092840.225220-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the Nuvoton MA35D1 DCUltraLite (nuvoton,ma35d1-dcu) to the binding. The DCUltraLite uses only four clocks (core, axi, ahb, pix0) and one reset (core), with a single output port. The MA35D1 clock controller gates the core, AXI and AHB clocks with a single bit, but each remains a distinct clock line feeding the IP with its own rate constraints, so all four must still be listed individually in the devicetree; core, axi and ahb happen to share the same clock phandle. Move the clocks/clock-names minItems to 4 and resets/reset-names minItems to 1 at the top level, since that is the lowest count any supported variant needs. Add an allOf/if block that tightens the constraint back up to the fixed 5-clock/3-reset topology required by the existing thead,th1520-dc8200 compatible, and another one that caps the new nuvoton,ma35d1-dcu compatible at the 4-clock/1-reset count it actually wires up. Signed-off-by: Joey Lu Acked-by: Conor Dooley --- .../bindings/display/verisilicon,dc.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml = b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml index 919a900122012..773966677d0f4 100644 --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml @@ -17,6 +17,7 @@ properties: items: - enum: - thead,th1520-dc8200 + - nuvoton,ma35d1-dcu - const: verisilicon,dc # DC IPs have discoverable ID/revision regis= ters =20 reg: @@ -26,6 +27,7 @@ properties: maxItems: 1 =20 clocks: + minItems: 4 items: - description: DC Core clock - description: DMA AXI bus clock @@ -34,6 +36,7 @@ properties: - description: Pixel clock of output 1 =20 clock-names: + minItems: 4 items: - const: core - const: axi @@ -42,12 +45,14 @@ properties: - const: pix1 =20 resets: + minItems: 1 items: - description: DC Core reset - description: DMA AXI bus reset - description: Configuration AHB bus reset =20 reset-names: + minItems: 1 items: - const: core - const: axi @@ -79,6 +84,45 @@ required: - reset-names - ports =20 +allOf: + - if: + properties: + compatible: + contains: + const: thead,th1520-dc8200 + then: + properties: + clocks: + minItems: 5 + + clock-names: + minItems: 5 + + resets: + minItems: 3 + + reset-names: + minItems: 3 + + - if: + properties: + compatible: + contains: + const: nuvoton,ma35d1-dcu + then: + properties: + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + additionalProperties: false =20 examples: --=20 2.43.0 From nobody Fri Sep 25 21:40:24 2026 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA489517BD1 for ; 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08c39227sm32109846a91.9.2026.09.08.02.28.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:28:54 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v6 2/6] drm/verisilicon: add register-level macros for DC8000 Date: Tue, 8 Sep 2026 17:28:36 +0800 Message-ID: <20260908092840.225220-3-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908092840.225220-1-a0987203069@gmail.com> References: <20260908092840.225220-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add register-level constants needed by the forthcoming DC8000 (DCUltraLite) hardware ops: VSDC_DISP_IRQ_VSYNC(n) in vs_crtc_regs.h: bit mask for per-output VSYNC interrupt bits in DISP_IRQ_STA (0x147C) / DISP_IRQ_EN (0x1480), which are the IRQ registers used by DCUltraLite in place of the DC8200 TOP_IRQ_ACK / TOP_IRQ_EN registers. VSDC_FB_CONFIG_ENABLE (bit 0), VSDC_FB_CONFIG_VALID (bit 3) and VSDC_FB_CONFIG_RESET (bit 4) in vs_primary_plane_regs.h: control bits in the FB_CONFIG register used by DCUltraLite for framebuffer enable and per-frame commit handshake. No behaviour change for existing DC8200 platforms. Signed-off-by: Joey Lu Reviewed-by: Icenowy Zheng --- drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 1 + drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h b/drivers/gpu/drm/v= erisilicon/vs_crtc_regs.h index c7930e817635c..d4da22b08cd5c 100644 --- a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h +++ b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h @@ -54,6 +54,7 @@ #define VSDC_DISP_GAMMA_DATA(n) (0x1460 + 0x4 * (n)) =20 #define VSDC_DISP_IRQ_STA 0x147C +#define VSDC_DISP_IRQ_VSYNC(n) BIT(n) =20 #define VSDC_DISP_IRQ_EN 0x1480 =20 diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h b/drivers/= gpu/drm/verisilicon/vs_primary_plane_regs.h index cbb125c46b390..67d4b00f294e2 100644 --- a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h @@ -16,6 +16,9 @@ #define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n)) =20 #define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n)) +#define VSDC_FB_CONFIG_ENABLE BIT(0) +#define VSDC_FB_CONFIG_VALID BIT(3) +#define VSDC_FB_CONFIG_RESET BIT(4) #define VSDC_FB_CONFIG_CLEAR_EN BIT(8) #define VSDC_FB_CONFIG_ROT_MASK GENMASK(13, 11) #define VSDC_FB_CONFIG_ROT(v) ((v) << 11) --=20 2.43.0 From nobody Fri Sep 25 21:40:24 2026 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEED351FCBA for ; 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08c39227sm32109846a91.9.2026.09.08.02.28.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:28:58 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v6 3/6] drm/verisilicon: introduce per-variant hardware ops table Date: Tue, 8 Sep 2026 17:28:37 +0800 Message-ID: <20260908092840.225220-4-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908092840.225220-1-a0987203069@gmail.com> References: <20260908092840.225220-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DC8200 and DCUltraLite share a broadly similar register layout but differ in how the bridge, CRTC, primary plane and IRQ paths are driven. Introduce a vs_dc_funcs vtable so each variant can supply its own implementation without scattering conditionals across multiple files. Add a generation field to struct vs_chip_identity to distinguish variants. Extract the DC8200-specific hardware ops into vs_dc8200.c and add unified IRQ bit definitions so implementations can translate hardware-specific bits to a common set. Update the shared code to dispatch through dc->funcs. No behaviour change for existing DC8200 platforms. Signed-off-by: Joey Lu Reviewed-by: Icenowy Zheng --- drivers/gpu/drm/verisilicon/Makefile | 2 +- drivers/gpu/drm/verisilicon/vs_bridge.c | 20 +-- drivers/gpu/drm/verisilicon/vs_crtc.c | 38 +++++- drivers/gpu/drm/verisilicon/vs_dc.c | 6 +- drivers/gpu/drm/verisilicon/vs_dc.h | 32 +++++ drivers/gpu/drm/verisilicon/vs_dc8200.c | 121 ++++++++++++++++++ drivers/gpu/drm/verisilicon/vs_drm.c | 5 +- drivers/gpu/drm/verisilicon/vs_drm.h | 8 ++ drivers/gpu/drm/verisilicon/vs_hwdb.c | 4 + drivers/gpu/drm/verisilicon/vs_hwdb.h | 6 + .../gpu/drm/verisilicon/vs_primary_plane.c | 32 +---- 11 files changed, 220 insertions(+), 54 deletions(-) create mode 100644 drivers/gpu/drm/verisilicon/vs_dc8200.c diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisil= icon/Makefile index 426f4bcaa834d..9d4cd16452fa1 100644 --- a/drivers/gpu/drm/verisilicon/Makefile +++ b/drivers/gpu/drm/verisilicon/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only =20 -verisilicon-dc-objs :=3D vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o \ +verisilicon-dc-objs :=3D vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o vs_drm.= o vs_hwdb.o \ vs_plane.o vs_primary_plane.o vs_cursor_plane.o =20 obj-$(CONFIG_DRM_VERISILICON_DC) +=3D verisilicon-dc.o diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.c b/drivers/gpu/drm/veri= silicon/vs_bridge.c index dc7c85b07fe32..3fbc8d57f8a1e 100644 --- a/drivers/gpu/drm/verisilicon/vs_bridge.c +++ b/drivers/gpu/drm/verisilicon/vs_bridge.c @@ -162,15 +162,8 @@ static void vs_bridge_enable_common(struct vs_crtc *cr= tc, VSDC_DISP_PANEL_CONFIG_DE_EN | VSDC_DISP_PANEL_CONFIG_DAT_EN | VSDC_DISP_PANEL_CONFIG_CLK_EN); - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), - VSDC_DISP_PANEL_CONFIG_RUNNING); - regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, - VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, - VSDC_DISP_PANEL_START_RUNNING(output)); - - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), - VSDC_DISP_PANEL_CONFIG_EX_COMMIT); + + dc->funcs->panel_enable_ex(dc, output); } =20 static void vs_bridge_atomic_enable_dpi(struct drm_bridge *bridge, @@ -228,14 +221,7 @@ static void vs_bridge_atomic_disable(struct drm_bridge= *bridge, struct vs_dc *dc =3D crtc->dc; unsigned int output =3D crtc->id; =20 - regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, - VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | - VSDC_DISP_PANEL_START_RUNNING(output)); - regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), - VSDC_DISP_PANEL_CONFIG_RUNNING); - - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), - VSDC_DISP_PANEL_CONFIG_EX_COMMIT); + dc->funcs->panel_disable_ex(dc, output); } =20 static const struct drm_bridge_funcs vs_dpi_bridge_funcs =3D { diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisi= licon/vs_crtc.c index c24c1588cbe69..2d4bf6af1f56e 100644 --- a/drivers/gpu/drm/verisilicon/vs_crtc.c +++ b/drivers/gpu/drm/verisilicon/vs_crtc.c @@ -16,10 +16,33 @@ #include "vs_crtc_regs.h" #include "vs_crtc.h" #include "vs_dc.h" -#include "vs_dc_top_regs.h" #include "vs_drm.h" #include "vs_plane.h" =20 +static void vs_crtc_atomic_begin(struct drm_crtc *crtc, + struct drm_atomic_commit *state) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + unsigned int output =3D vcrtc->id; + + if (dc->funcs->crtc_begin) + dc->funcs->crtc_begin(dc, output); +} + +static void vs_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_atomic_commit *state) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + unsigned int output =3D vcrtc->id; + + if (dc->funcs->crtc_flush) + dc->funcs->crtc_flush(dc, output); + + drm_crtc_vblank_atomic_flush(crtc, state); +} + static void vs_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *state) { @@ -30,6 +53,9 @@ static void vs_crtc_atomic_disable(struct drm_crtc *crtc, drm_crtc_vblank_off(crtc); =20 clk_disable_unprepare(dc->pix_clk[output]); + + if (dc->funcs->crtc_disable_ex) + dc->funcs->crtc_disable_ex(dc, output); } =20 static void vs_crtc_atomic_enable(struct drm_crtc *crtc, @@ -42,6 +68,9 @@ static void vs_crtc_atomic_enable(struct drm_crtc *crtc, drm_WARN_ON(&dc->drm_dev->base, clk_prepare_enable(dc->pix_clk[output])); =20 + if (dc->funcs->crtc_enable_ex) + dc->funcs->crtc_enable_ex(dc, output); + drm_crtc_vblank_on(crtc); } =20 @@ -119,7 +148,8 @@ static bool vs_crtc_mode_fixup(struct drm_crtc *crtc, } =20 static const struct drm_crtc_helper_funcs vs_crtc_helper_funcs =3D { - .atomic_flush =3D drm_crtc_vblank_atomic_flush, + .atomic_begin =3D vs_crtc_atomic_begin, + .atomic_flush =3D vs_crtc_atomic_flush, .atomic_enable =3D vs_crtc_atomic_enable, .atomic_disable =3D vs_crtc_atomic_disable, .mode_set_nofb =3D vs_crtc_mode_set_nofb, @@ -132,7 +162,7 @@ static int vs_crtc_enable_vblank(struct drm_crtc *crtc) struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); + dc->funcs->enable_vblank(dc, vcrtc->id); =20 return 0; } @@ -142,7 +172,7 @@ static void vs_crtc_disable_vblank(struct drm_crtc *crt= c) struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id= )); + dc->funcs->disable_vblank(dc, vcrtc->id); } =20 static const struct drm_crtc_funcs vs_crtc_funcs =3D { diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisili= con/vs_dc.c index dad9967bc10b8..9729b693d360e 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -8,9 +8,7 @@ #include #include =20 -#include "vs_crtc.h" #include "vs_dc.h" -#include "vs_dc_top_regs.h" #include "vs_drm.h" #include "vs_hwdb.h" =20 @@ -33,7 +31,7 @@ static irqreturn_t vs_dc_irq_handler(int irq, void *priva= te) struct vs_dc *dc =3D private; u32 irqs; =20 - regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &irqs); + irqs =3D dc->funcs->irq_ack(dc); =20 vs_drm_handle_irq(dc, irqs); =20 @@ -136,6 +134,8 @@ static int vs_dc_probe(struct platform_device *pdev) dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model, dc->identity.revision, dc->identity.customer_id); =20 + dc->funcs =3D &vs_dc8200_funcs; + if (port_count > dc->identity.display_count) { dev_err(dev, "too many downstream ports than HW capability\n"); ret =3D -EINVAL; diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisili= con/vs_dc.h index ed1016f18758e..825f5dd6bf174 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.h +++ b/drivers/gpu/drm/verisilicon/vs_dc.h @@ -14,6 +14,7 @@ #include =20 #include +#include =20 #include "vs_hwdb.h" =20 @@ -22,6 +23,34 @@ =20 struct vs_drm_dev; struct vs_crtc; +struct vs_dc; + +struct vs_dc_funcs { + /* Bridge: atomic_enable, atomic_disable */ + void (*panel_enable_ex)(struct vs_dc *dc, unsigned int output); + void (*panel_disable_ex)(struct vs_dc *dc, unsigned int output); + + /* CRTC: atomic_begin, atomic_flush */ + void (*crtc_begin)(struct vs_dc *dc, unsigned int output); + void (*crtc_flush)(struct vs_dc *dc, unsigned int output); + + /* CRTC: atomic_enable, atomic_disable */ + void (*crtc_enable_ex)(struct vs_dc *dc, unsigned int output); + void (*crtc_disable_ex)(struct vs_dc *dc, unsigned int output); + + /* CRTC: enable_vblank, disable_vblank */ + void (*enable_vblank)(struct vs_dc *dc, unsigned int output); + void (*disable_vblank)(struct vs_dc *dc, unsigned int output); + + /* Primary plane: atomic_enable, atomic_disable, atomic_update */ + void (*primary_plane_enable_ex)(struct vs_dc *dc, unsigned int output); + void (*primary_plane_disable_ex)(struct vs_dc *dc, unsigned int output); + void (*primary_plane_update_ex)(struct vs_dc *dc, unsigned int output, + struct drm_plane_state *state); + + /* IRQ acknowledge */ + u32 (*irq_ack)(struct vs_dc *dc); +}; =20 struct vs_dc { struct regmap *regs; @@ -33,6 +62,9 @@ struct vs_dc { =20 struct vs_drm_dev *drm_dev; struct vs_chip_identity identity; + const struct vs_dc_funcs *funcs; }; =20 +extern const struct vs_dc_funcs vs_dc8200_funcs; + #endif /* _VS_DC_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_dc8200.c b/drivers/gpu/drm/veri= silicon/vs_dc8200.c new file mode 100644 index 0000000000000..77752d0cb28b0 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_dc8200.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#include + +#include + +#include "vs_bridge_regs.h" +#include "vs_dc.h" +#include "vs_dc_top_regs.h" +#include "vs_drm.h" +#include "vs_plane.h" +#include "vs_primary_plane_regs.h" + +static void vs_dc8200_panel_enable_ex(struct vs_dc *dc, unsigned int outpu= t) +{ + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_RUNNING); + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_RUNNING(output)); + + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(output), + VSDC_DISP_PANEL_CONFIG_EX_COMMIT); +} + +static void vs_dc8200_panel_disable_ex(struct vs_dc *dc, unsigned int outp= ut) +{ + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_RUNNING); + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | + VSDC_DISP_PANEL_START_RUNNING(output)); + + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(output), + VSDC_DISP_PANEL_CONFIG_EX_COMMIT); +} + +static void vs_dc8200_enable_vblank(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, + VSDC_TOP_IRQ_VSYNC(output)); +} + +static void vs_dc8200_disable_vblank(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, + VSDC_TOP_IRQ_VSYNC(output)); +} + +static void vs_dc8200_plane_commit(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_COMMIT); +} + +static void vs_dc8200_primary_plane_enable_ex(struct vs_dc *dc, unsigned i= nt output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_FB_EN); + regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, + VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); + + vs_dc8200_plane_commit(dc, output); +} + +static void vs_dc8200_primary_plane_disable_ex(struct vs_dc *dc, unsigned = int output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_FB_EN); + + vs_dc8200_plane_commit(dc, output); +} + +static void vs_dc8200_primary_plane_update_ex(struct vs_dc *dc, unsigned i= nt output, + struct drm_plane_state *state) +{ + regmap_write(dc->regs, VSDC_FB_TOP_LEFT(output), + VSDC_MAKE_PLANE_POS(state->crtc_x, state->crtc_y)); + regmap_write(dc->regs, VSDC_FB_BOTTOM_RIGHT(output), + VSDC_MAKE_PLANE_POS(state->crtc_x + state->crtc_w, + state->crtc_y + state->crtc_h)); + regmap_write(dc->regs, VSDC_FB_BLEND_CONFIG(output), + VSDC_FB_BLEND_CONFIG_BLEND_DISABLE); + + vs_dc8200_plane_commit(dc, output); +} + +static u32 vs_dc8200_irq_ack(struct vs_dc *dc) +{ + u32 hw_irqs, unified =3D 0, known =3D 0; + unsigned int i; + + regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &hw_irqs); + + for (i =3D 0; i < VSDC_MAX_OUTPUTS; i++) { + known |=3D VSDC_TOP_IRQ_VSYNC(i); + if (hw_irqs & VSDC_TOP_IRQ_VSYNC(i)) + unified |=3D VSDC_IRQ_VSYNC(i); + } + + drm_WARN_ONCE(&dc->drm_dev->base, hw_irqs & ~known, + "Unknown hardware IRQ bits: %#x\n", hw_irqs & ~known); + + return unified; +} + +const struct vs_dc_funcs vs_dc8200_funcs =3D { + .panel_enable_ex =3D vs_dc8200_panel_enable_ex, + .panel_disable_ex =3D vs_dc8200_panel_disable_ex, + .enable_vblank =3D vs_dc8200_enable_vblank, + .disable_vblank =3D vs_dc8200_disable_vblank, + .primary_plane_enable_ex =3D vs_dc8200_primary_plane_enable_ex, + .primary_plane_disable_ex =3D vs_dc8200_primary_plane_disable_ex, + .primary_plane_update_ex =3D vs_dc8200_primary_plane_update_ex, + .irq_ack =3D vs_dc8200_irq_ack, +}; diff --git a/drivers/gpu/drm/verisilicon/vs_drm.c b/drivers/gpu/drm/verisil= icon/vs_drm.c index fd259d53f49f1..24e9d0b008f31 100644 --- a/drivers/gpu/drm/verisilicon/vs_drm.c +++ b/drivers/gpu/drm/verisilicon/vs_drm.c @@ -25,7 +25,6 @@ #include "vs_bridge.h" #include "vs_crtc.h" #include "vs_dc.h" -#include "vs_dc_top_regs.h" #include "vs_drm.h" =20 #define DRIVER_NAME "verisilicon" @@ -168,8 +167,8 @@ void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs) unsigned int i; =20 for (i =3D 0; i < dc->identity.display_count; i++) { - if (irqs & VSDC_TOP_IRQ_VSYNC(i)) { - irqs &=3D ~VSDC_TOP_IRQ_VSYNC(i); + if (irqs & VSDC_IRQ_VSYNC(i)) { + irqs &=3D ~VSDC_IRQ_VSYNC(i); if (dc->drm_dev->crtcs[i]) drm_crtc_handle_vblank(&dc->drm_dev->crtcs[i]->base); } diff --git a/drivers/gpu/drm/verisilicon/vs_drm.h b/drivers/gpu/drm/verisil= icon/vs_drm.h index 606338206a427..6a89c20879df7 100644 --- a/drivers/gpu/drm/verisilicon/vs_drm.h +++ b/drivers/gpu/drm/verisilicon/vs_drm.h @@ -6,6 +6,7 @@ #ifndef _VS_DRM_H_ #define _VS_DRM_H_ =20 +#include #include #include =20 @@ -13,6 +14,13 @@ =20 struct vs_dc; =20 +/* + * DC variants use different interrupt registers with diverging bit + * assignments; each irq_ack() implementation must translate its + * hardware-specific bits into these definitions. + */ +#define VSDC_IRQ_VSYNC(n) BIT(n) + struct vs_drm_dev { struct drm_device base; =20 diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisi= licon/vs_hwdb.c index 2a0f7c59afa3a..91524d16f7785 100644 --- a/drivers/gpu/drm/verisilicon/vs_hwdb.c +++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c @@ -94,6 +94,7 @@ static struct vs_chip_identity vs_chip_identities[] =3D { .revision =3D 0x5720, .customer_id =3D ~0U, =20 + .generation =3D VSDC_GEN_DC8200, .display_count =3D 2, .max_cursor_size =3D 64, .formats =3D &vs_formats_no_yuv444, @@ -103,6 +104,7 @@ static struct vs_chip_identity vs_chip_identities[] =3D= { .revision =3D 0x5721, .customer_id =3D 0x30B, =20 + .generation =3D VSDC_GEN_DC8200, .display_count =3D 2, .max_cursor_size =3D 64, .formats =3D &vs_formats_no_yuv444, @@ -112,6 +114,7 @@ static struct vs_chip_identity vs_chip_identities[] =3D= { .revision =3D 0x5720, .customer_id =3D 0x310, =20 + .generation =3D VSDC_GEN_DC8200, .display_count =3D 2, .max_cursor_size =3D 64, .formats =3D &vs_formats_with_yuv444, @@ -121,6 +124,7 @@ static struct vs_chip_identity vs_chip_identities[] =3D= { .revision =3D 0x5720, .customer_id =3D 0x311, =20 + .generation =3D VSDC_GEN_DC8200, .display_count =3D 2, .max_cursor_size =3D 64, .formats =3D &vs_formats_no_yuv444, diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisi= licon/vs_hwdb.h index 2065ecb730437..a15c8b5656044 100644 --- a/drivers/gpu/drm/verisilicon/vs_hwdb.h +++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h @@ -9,6 +9,11 @@ #include #include =20 +enum vs_dc_generation { + VSDC_GEN_DC8000, + VSDC_GEN_DC8200, +}; + struct vs_formats { const u32 *array; unsigned int num; @@ -19,6 +24,7 @@ struct vs_chip_identity { u32 revision; u32 customer_id; =20 + enum vs_dc_generation generation; u32 display_count; /* * The hardware only supports square cursor planes, so this field diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane.c b/drivers/gpu/d= rm/verisilicon/vs_primary_plane.c index 2750016a7f2c3..85ba2068172db 100644 --- a/drivers/gpu/drm/verisilicon/vs_primary_plane.c +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane.c @@ -54,12 +54,6 @@ static int vs_primary_plane_atomic_check(struct drm_plan= e *plane, return 0; } =20 -static void vs_primary_plane_commit(struct vs_dc *dc, unsigned int output) -{ - regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_COMMIT); -} - static void vs_primary_plane_atomic_enable(struct drm_plane *plane, struct drm_atomic_commit *atomic_state) { @@ -70,13 +64,8 @@ static void vs_primary_plane_atomic_enable(struct drm_pl= ane *plane, unsigned int output =3D vcrtc->id; struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_FB_EN); - regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, - VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); - - vs_primary_plane_commit(dc, output); + if (dc->funcs->primary_plane_enable_ex) + dc->funcs->primary_plane_enable_ex(dc, output); } =20 static void vs_primary_plane_atomic_disable(struct drm_plane *plane, @@ -89,10 +78,8 @@ static void vs_primary_plane_atomic_disable(struct drm_p= lane *plane, unsigned int output =3D vcrtc->id; struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_FB_EN); - - vs_primary_plane_commit(dc, output); + if (dc->funcs->primary_plane_disable_ex) + dc->funcs->primary_plane_disable_ex(dc, output); } =20 static void vs_primary_plane_atomic_update(struct drm_plane *plane, @@ -138,18 +125,11 @@ static void vs_primary_plane_atomic_update(struct drm= _plane *plane, regmap_write(dc->regs, VSDC_FB_STRIDE(output), fb->pitches[0]); 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08c39227sm32109846a91.9.2026.09.08.02.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:29:02 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v6 4/6] drm/verisilicon: add DC8000 (DCUltraLite) display controller support Date: Tue, 8 Sep 2026 17:28:38 +0800 Message-ID: <20260908092840.225220-5-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908092840.225220-1-a0987203069@gmail.com> References: <20260908092840.225220-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Verisilicon DC IP family also ships in a DCUltraLite (DC8000 generation) configuration that lacks the DC8200's CONFIG_EX staging registers and PANEL_START sync register, and exposes its VSYNC interrupt through a differently laid out status/enable register pair. Add a vs_dc_funcs implementation for the DC8000 generation in vs_dc8000.c: framebuffer updates are latched directly through FB_CONFIG's enable/reset/valid bits instead of a staging commit, panel output starts as soon as PANEL_CONFIG.RUNNING is set with no separate sync register to arm, and the VSYNC interrupt is acknowledged through DISP_IRQ_STA/DISP_IRQ_EN. Select this vtable in the probe path based on the chip identity's generation field. Signed-off-by: Joey Lu Reviewed-by: Icenowy Zheng --- drivers/gpu/drm/verisilicon/Makefile | 2 +- drivers/gpu/drm/verisilicon/vs_dc.c | 5 +- drivers/gpu/drm/verisilicon/vs_dc.h | 1 + drivers/gpu/drm/verisilicon/vs_dc8000.c | 92 +++++++++++++++++++++++++ 4 files changed, 98 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/verisilicon/vs_dc8000.c diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisil= icon/Makefile index 9d4cd16452fa1..d2fd8e4dff242 100644 --- a/drivers/gpu/drm/verisilicon/Makefile +++ b/drivers/gpu/drm/verisilicon/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only =20 -verisilicon-dc-objs :=3D vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o vs_drm.= o vs_hwdb.o \ +verisilicon-dc-objs :=3D vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o vs_dc80= 00.o vs_drm.o vs_hwdb.o \ vs_plane.o vs_primary_plane.o vs_cursor_plane.o =20 obj-$(CONFIG_DRM_VERISILICON_DC) +=3D verisilicon-dc.o diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisili= con/vs_dc.c index 9729b693d360e..3e9e2c0264f5d 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -134,7 +134,10 @@ static int vs_dc_probe(struct platform_device *pdev) dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model, dc->identity.revision, dc->identity.customer_id); =20 - dc->funcs =3D &vs_dc8200_funcs; + if (dc->identity.generation =3D=3D VSDC_GEN_DC8200) + dc->funcs =3D &vs_dc8200_funcs; + else + dc->funcs =3D &vs_dc8000_funcs; =20 if (port_count > dc->identity.display_count) { dev_err(dev, "too many downstream ports than HW capability\n"); diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisili= con/vs_dc.h index 825f5dd6bf174..ac96ad7011994 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.h +++ b/drivers/gpu/drm/verisilicon/vs_dc.h @@ -66,5 +66,6 @@ struct vs_dc { }; =20 extern const struct vs_dc_funcs vs_dc8200_funcs; +extern const struct vs_dc_funcs vs_dc8000_funcs; =20 #endif /* _VS_DC_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_dc8000.c b/drivers/gpu/drm/veri= silicon/vs_dc8000.c new file mode 100644 index 0000000000000..df7bd5bdd7f2a --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_dc8000.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Joey Lu + */ + +#include + +#include + +#include "vs_crtc_regs.h" +#include "vs_dc.h" +#include "vs_drm.h" +#include "vs_primary_plane_regs.h" + +static void vs_dc8000_panel_enable_ex(struct vs_dc *dc, unsigned int outpu= t) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_RESET); +} + +static void vs_dc8000_panel_disable_ex(struct vs_dc *dc, unsigned int outp= ut) +{ + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_RESET); +} + +static void vs_dc8000_crtc_begin(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_VALID); +} + +static void vs_dc8000_crtc_flush(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_VALID); +} + +static void vs_dc8000_crtc_enable_ex(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_ENABLE); +} + +static void vs_dc8000_crtc_disable_ex(struct vs_dc *dc, unsigned int outpu= t) +{ + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_ENABLE); +} + +static void vs_dc8000_enable_vblank(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_DISP_IRQ_EN, + VSDC_DISP_IRQ_VSYNC(output)); +} + +static void vs_dc8000_disable_vblank(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_DISP_IRQ_EN, + VSDC_DISP_IRQ_VSYNC(output)); +} + +static u32 vs_dc8000_irq_ack(struct vs_dc *dc) +{ + u32 hw_irqs, unified =3D 0, known =3D 0; + unsigned int i; + + regmap_read(dc->regs, VSDC_DISP_IRQ_STA, &hw_irqs); + + for (i =3D 0; i < VSDC_MAX_OUTPUTS; i++) { + known |=3D VSDC_DISP_IRQ_VSYNC(i); + if (hw_irqs & VSDC_DISP_IRQ_VSYNC(i)) + unified |=3D VSDC_IRQ_VSYNC(i); + } + + drm_WARN_ONCE(&dc->drm_dev->base, hw_irqs & ~known, + "Unknown hardware IRQ bits: %#x\n", hw_irqs & ~known); + + return unified; +} + +const struct vs_dc_funcs vs_dc8000_funcs =3D { + .panel_enable_ex =3D vs_dc8000_panel_enable_ex, + .panel_disable_ex =3D vs_dc8000_panel_disable_ex, + .crtc_begin =3D vs_dc8000_crtc_begin, + .crtc_flush =3D vs_dc8000_crtc_flush, + .crtc_enable_ex =3D vs_dc8000_crtc_enable_ex, + .crtc_disable_ex =3D vs_dc8000_crtc_disable_ex, + .enable_vblank =3D vs_dc8000_enable_vblank, + .disable_vblank =3D vs_dc8000_disable_vblank, + .irq_ack =3D vs_dc8000_irq_ack, +}; --=20 2.43.0 From nobody Fri Sep 25 21:40:24 2026 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48866521239 for ; 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08c39227sm32109846a91.9.2026.09.08.02.29.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:29:06 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v6 5/6] drm/verisilicon: add DCUltraLite chip identity to HWDB Date: Tue, 8 Sep 2026 17:28:39 +0800 Message-ID: <20260908092840.225220-6-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908092840.225220-1-a0987203069@gmail.com> References: <20260908092840.225220-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Nuvoton MA35D1 chip contains a DCUltraLite display controller with model number 0x0 (sic, the model name contains no number either), revision 0x5560 and customer ID 0x305. It has a similar register map with DC8000, only one display output and only 32x32 cursor supported. Signed-off-by: Joey Lu Reviewed-by: Icenowy Zheng --- drivers/gpu/drm/verisilicon/vs_hwdb.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisi= licon/vs_hwdb.c index 91524d16f7785..7d630a667a3f0 100644 --- a/drivers/gpu/drm/verisilicon/vs_hwdb.c +++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c @@ -129,6 +129,16 @@ static struct vs_chip_identity vs_chip_identities[] = =3D { .max_cursor_size =3D 64, .formats =3D &vs_formats_no_yuv444, }, + { + .model =3D 0x0, /* DCUltraLite */ + .revision =3D 0x5560, + .customer_id =3D 0x305, + + .generation =3D VSDC_GEN_DC8000, + .display_count =3D 1, + .max_cursor_size =3D 32, + .formats =3D &vs_formats_no_yuv444, + }, }; =20 int vs_fill_chip_identity(struct regmap *regs, --=20 2.43.0 From nobody Fri Sep 25 21:40:24 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B86A5221FE for ; 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08c39227sm32109846a91.9.2026.09.08.02.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:29:09 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v6 6/6] drm/verisilicon: extend Kconfig to support ARCH_MA35 platforms Date: Tue, 8 Sep 2026 17:28:40 +0800 Message-ID: <20260908092840.225220-7-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908092840.225220-1-a0987203069@gmail.com> References: <20260908092840.225220-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ARCH_MA35 to the platform dependencies to allow the driver to be built for Nuvoton MA35D1. Signed-off-by: Joey Lu Reviewed-by: Icenowy Zheng --- drivers/gpu/drm/verisilicon/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisili= con/Kconfig index 7cce86ec8603c..295d246eb4b40 100644 --- a/drivers/gpu/drm/verisilicon/Kconfig +++ b/drivers/gpu/drm/verisilicon/Kconfig @@ -2,7 +2,7 @@ config DRM_VERISILICON_DC tristate "DRM Support for Verisilicon DC-series display controllers" depends on DRM && COMMON_CLK - depends on RISCV || COMPILE_TEST + depends on RISCV || ARCH_MA35 || COMPILE_TEST select DRM_BRIDGE_CONNECTOR select DRM_CLIENT_SELECTION select DRM_DISPLAY_HELPER --=20 2.43.0