From nobody Fri Sep 25 21:40:43 2026 Received: from out28-97.mail.aliyun.com (out28-97.mail.aliyun.com [115.124.28.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D683B49F102; Tue, 8 Sep 2026 08:36:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.97 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788856603; cv=none; b=fDgbbs4MZw4oTHp7KRkwKEoOpt6YO2lE/1KvffGMdz/noSQ0JeYqJoHIVi8yx64hnLqLAtAsNS+5lXk1LzSPyDVAkmg9vOkcbOVNsJGfkFMq1PPY95qw5il9526Oq/Bue2mWgTuPqBEv1BfYcj8LXOa7oVRz9CGTINIpL+U7Qlo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788856603; c=relaxed/simple; bh=fLvibXgApQU7oiU9OujdiMn+/7rALkKQzP+5Qt1UmPc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Y5VbRXqmpN8sdEm91r3MNpOVxxFWeTy9hNgc4BI67zsaLSbtLgRdZp1XE63CiJeVXPuz+Mab11y0Q8Xp3EPErikRtGcodBV5fA3lgIumUpdClEsHinu23TK0t4RcWAJgsaPFss3ubFw6GqCqstqfcYM1mw0KRsJK3gCCU/JEzxo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=motor-comm.com; spf=pass smtp.mailfrom=motor-comm.com; arc=none smtp.client-ip=115.124.28.97 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=motor-comm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=motor-comm.com X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07496805|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.116249-0.000297545-0.883454;FP=13943110808289023700|0|0|0|0|-1|-1|-1;HT=maildocker-contentspam033037028158;MF=kyle.switch@motor-comm.com;NM=1;PH=DS;RN=16;RT=16;SR=0;TI=SMTPD_---.j8Z17tY_1788856588; Received: from motor-comm.com(mailfrom:kyle.switch@motor-comm.com fp:SMTPD_---.j8Z17tY_1788856588 cluster:ay29) by smtp.aliyun-inc.com; Tue, 08 Sep 2026 16:36:29 +0800 From: Kyle Switch To: andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mmyangfl@gmail.com, horms@kernel.org, linux@armlinux.org.uk, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ming.xu@motor-comm.com, xiaolin.xu@motor-comm.com, jianmin.wang@motor-comm.com, wei.zhang@gl-inet.com, sijia.huang@gl-inet.com Subject: [PATCH net-next v6 1/6] net: dsa: motorcomm: initialize dsa_switch based on chipid Date: Tue, 8 Sep 2026 16:36:09 +0800 Message-Id: <20260908083614.2210505-2-kyle.switch@motor-comm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260908083614.2210505-1-kyle.switch@motor-comm.com> References: <20260908083614.2210505-1-kyle.switch@motor-comm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce yt92xx_series structure to hold private data for different switch families, replacing hardcoded logic in probe(). This makes the driver more extensible for future switch support. Signed-off-by: Kyle Switch --- drivers/net/dsa/motorcomm/chip.c | 81 +++++++++++++++++++++++++++----- drivers/net/dsa/motorcomm/chip.h | 20 ++++++++ 2 files changed, 90 insertions(+), 11 deletions(-) diff --git a/drivers/net/dsa/motorcomm/chip.c b/drivers/net/dsa/motorcomm/c= hip.c index d663af010f43..ffed823f26a8 100644 --- a/drivers/net/dsa/motorcomm/chip.c +++ b/drivers/net/dsa/motorcomm/chip.c @@ -4679,6 +4679,68 @@ static const struct dsa_switch_ops yt921x_dsa_switch= _ops =3D { .setup =3D yt921x_dsa_setup, }; =20 +static const struct yt92xx_series yt92xx_series_table[] =3D { + [YT92XX_MODE_YT921X] =3D { + .mode =3D YT92XX_MODE_YT921X, + .name =3D "YT921x", + .max_ports =3D YT921X_PORT_NUM, + .num_lag_ids =3D YT921X_LAG_NUM, + .ageing_time_min =3D 1 * 5000, + .ageing_time_max =3D U16_MAX * 5000, + .dscp_prio_mapping_is_global =3D true, + .assisted_learning_on_cpu_port =3D true, + .switch_ops =3D &yt921x_dsa_switch_ops, + .mac_ops =3D &yt921x_phylink_mac_ops + }, +}; + +static const struct yt92xx_series *yt92xx_series_lookup(u32 major) +{ + enum yt92xx_mode mode =3D YT92XX_MODE_MAX; + int i; + + if (major =3D=3D YT9215_MAJOR || major =3D=3D YT9218_MAJOR) + mode =3D YT92XX_MODE_YT921X; + + for (i =3D 0; i < ARRAY_SIZE(yt92xx_series_table); ++i) + if (yt92xx_series_table[i].mode =3D=3D mode) + return &yt92xx_series_table[i]; + + return NULL; +} + +static int yt92xx_register_switch(struct dsa_switch *ds) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + const struct yt92xx_series *series; + u32 chipid; + u32 major; + int res; + + res =3D yt921x_reg_read(priv, YT921X_CHIP_ID, &chipid); + if (res) + return res; + + major =3D FIELD_GET(YT921X_CHIP_ID_MAJOR, chipid); + series =3D yt92xx_series_lookup(major); + if (!series) + return -ENODEV; + priv->series =3D series; + + ds->assisted_learning_on_cpu_port =3D + priv->series->assisted_learning_on_cpu_port; + ds->dscp_prio_mapping_is_global =3D + priv->series->dscp_prio_mapping_is_global; + ds->ageing_time_min =3D priv->series->ageing_time_min; + ds->ageing_time_max =3D priv->series->ageing_time_max; + ds->num_lag_ids =3D priv->series->num_lag_ids; + ds->num_ports =3D priv->series->max_ports; + ds->ops =3D priv->series->switch_ops; + ds->phylink_mac_ops =3D priv->series->mac_ops; + + return 0; +} + static void yt921x_mdio_shutdown(struct mdio_device *mdiodev) { struct yt921x_priv *priv =3D mdiodev_get_drvdata(mdiodev); @@ -4727,6 +4789,7 @@ static int yt921x_mdio_probe(struct mdio_device *mdio= dev) struct yt921x_reg_mdio *mdio; struct yt921x_priv *priv; struct dsa_switch *ds; + int res; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -4754,15 +4817,9 @@ static int yt921x_mdio_probe(struct mdio_device *mdi= odev) =20 ds =3D &priv->ds; ds->dev =3D dev; - ds->assisted_learning_on_cpu_port =3D true; - ds->dscp_prio_mapping_is_global =3D true; - ds->priv =3D priv; - ds->ops =3D &yt921x_dsa_switch_ops; - ds->ageing_time_min =3D 1 * 5000; - ds->ageing_time_max =3D U16_MAX * 5000; - ds->phylink_mac_ops =3D &yt921x_phylink_mac_ops; - ds->num_lag_ids =3D YT921X_LAG_NUM; - ds->num_ports =3D YT921X_PORT_NUM; + res =3D yt92xx_register_switch(ds); + if (res) + return res; =20 mdiodev_set_drvdata(mdiodev, priv); =20 @@ -4770,8 +4827,10 @@ static int yt921x_mdio_probe(struct mdio_device *mdi= odev) } =20 static const struct of_device_id yt921x_of_match[] =3D { - { .compatible =3D "motorcomm,yt9215" }, - {} + { + .compatible =3D "motorcomm,yt9215", + }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, yt921x_of_match); =20 diff --git a/drivers/net/dsa/motorcomm/chip.h b/drivers/net/dsa/motorcomm/c= hip.h index 83cd454955dd..c446aea449ed 100644 --- a/drivers/net/dsa/motorcomm/chip.h +++ b/drivers/net/dsa/motorcomm/chip.h @@ -960,9 +960,29 @@ struct yt921x_reg_ops { int (*write)(void *context, u32 reg, u32 val); }; =20 +enum yt92xx_mode { + YT92XX_MODE_YT921X, + YT92XX_MODE_YT922X, + YT92XX_MODE_MAX, +}; + +struct yt92xx_series { + enum yt92xx_mode mode; + const char *name; + unsigned int max_ports; + unsigned int num_lag_ids; + unsigned int ageing_time_min; + unsigned int ageing_time_max; + u32 dscp_prio_mapping_is_global; + u32 assisted_learning_on_cpu_port; + const struct dsa_switch_ops *switch_ops; + const struct phylink_mac_ops *mac_ops; +}; + struct yt921x_priv { struct dsa_switch ds; =20 + const struct yt92xx_series *series; const struct yt921x_info *info; unsigned int meter_slot_ns; unsigned int port_shape_slot_ns; --=20 2.25.1 From nobody Fri Sep 25 21:40:43 2026 Received: from out28-197.mail.aliyun.com (out28-197.mail.aliyun.com [115.124.28.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A028C49CF3E; Tue, 8 Sep 2026 08:36:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788856603; cv=none; b=m8vkP7yhNHrZXve2cwfwhqenMRQoDXTU4zz2rmbz/J/wAFZI96Xnmaes6iNeCPYDYTlLCHI6npZLPk8+3Tn+MQS7FK6Om9GvvQMgpWGZ+JlJ7SIk3HRjhsVHuDE+rDSqRlrok9giaGY2UMDDiMISQbzNxpH6hYxG0Ldq5VPv7Hk= ARC-Message-Signature: i=1; a=rsa-sha256; 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Received: from motor-comm.com(mailfrom:kyle.switch@motor-comm.com fp:SMTPD_---.j8Z17ul_1788856589 cluster:ay29) by smtp.aliyun-inc.com; Tue, 08 Sep 2026 16:36:29 +0800 From: Kyle Switch To: andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mmyangfl@gmail.com, horms@kernel.org, linux@armlinux.org.uk, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ming.xu@motor-comm.com, xiaolin.xu@motor-comm.com, jianmin.wang@motor-comm.com, wei.zhang@gl-inet.com, sijia.huang@gl-inet.com Subject: [PATCH net-next v6 2/6] net: dsa: motorcomm: use max_ports in series for port bounds checking Date: Tue, 8 Sep 2026 16:36:10 +0800 Message-Id: <20260908083614.2210505-3-kyle.switch@motor-comm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260908083614.2210505-1-kyle.switch@motor-comm.com> References: <20260908083614.2210505-1-kyle.switch@motor-comm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the hardcoded YT921X_PORT_NUM macro with the per-series max_ports field in port validation. This removes family-specific constants from the common code path and simplifies adding new switch families with different port counts. No functional change for existing YT921X devices. Signed-off-by: Kyle Switch --- drivers/net/dsa/motorcomm/chip.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/motorcomm/chip.c b/drivers/net/dsa/motorcomm/c= hip.c index ffed823f26a8..191a7aa3733e 100644 --- a/drivers/net/dsa/motorcomm/chip.c +++ b/drivers/net/dsa/motorcomm/chip.c @@ -357,7 +357,7 @@ static int yt921x_mbus_int_read(struct mii_bus *mbus, i= nt port, int reg) u16 val; int res; =20 - if (port >=3D YT921X_PORT_NUM) + if (port >=3D priv->series->max_ports) return U16_MAX; =20 mutex_lock(&priv->reg_lock); @@ -375,7 +375,7 @@ yt921x_mbus_int_write(struct mii_bus *mbus, int port, i= nt reg, u16 data) struct yt921x_priv *priv =3D mbus->priv; int res; =20 - if (port >=3D YT921X_PORT_NUM) + if (port >=3D priv->series->max_ports) return -ENODEV; =20 mutex_lock(&priv->reg_lock); @@ -390,6 +390,7 @@ yt921x_mbus_int_init(struct yt921x_priv *priv, struct d= evice_node *mnp) { struct device *dev =3D to_device(priv); struct mii_bus *mbus; + u32 max_ports; int res; =20 mbus =3D devm_mdiobus_alloc(dev); @@ -402,7 +403,8 @@ yt921x_mbus_int_init(struct yt921x_priv *priv, struct d= evice_node *mnp) mbus->read =3D yt921x_mbus_int_read; mbus->write =3D yt921x_mbus_int_write; mbus->parent =3D dev; - mbus->phy_mask =3D (u32)~GENMASK(YT921X_PORT_NUM - 1, 0); + max_ports =3D priv->series->max_ports; + mbus->phy_mask =3D (u32)~GENMASK(max_ports - 1, 0); =20 res =3D devm_of_mdiobus_register(dev, mbus, mnp); if (res) --=20 2.25.1 From nobody Fri Sep 25 21:40:43 2026 Received: from out28-75.mail.aliyun.com (out28-75.mail.aliyun.com [115.124.28.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A49E47B432; Tue, 8 Sep 2026 08:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.75 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788856597; cv=none; b=PbMSMjsR2seUX9eX2CiGRW7LnwYLl6WNabArdnsBku5QJ/gpbRLYolCm7FVAWK0dAGkH9H1va5o2kSdR2hrs5NYXTXPtZy4Un0zEbmHJhtD50R1vfgdkk9N0zkYmmQ/NN5DFFgSRF/vn+T8so05a+qmz22OM5NHiSiKB3Z+LJIk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788856597; c=relaxed/simple; bh=YjxRUskLY0z6TMN8uIAPdwZc0chDsWJhincUyimo9GM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TYLselZQAEXNyRYdArbRyraHnY/DOsCq/J8df7fotrums6QZw47rhUTA7WZYSiQHvAdok13frVF9s6bGJrRJFyGNlqGxIID71gHYvAAgC4eeFCk50IAEn/jw+H6BQ8GXF2TPwHgm/iglZi+PYFiM8J0s/V8GLwKbPxaNuDKsJHY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=motor-comm.com; spf=pass smtp.mailfrom=motor-comm.com; arc=none smtp.client-ip=115.124.28.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=motor-comm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=motor-comm.com X-Alimail-AntiSpam: AC=CONTINUE;BC=0.1035972|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.0197986-0.000307085-0.979894;FP=11994835652634511012|0|0|0|0|-1|-1|-1;HT=maildocker-contentspam033037028158;MF=kyle.switch@motor-comm.com;NM=1;PH=DS;RN=16;RT=16;SR=0;TI=SMTPD_---.j8Z17vm_1788856590; Received: from motor-comm.com(mailfrom:kyle.switch@motor-comm.com fp:SMTPD_---.j8Z17vm_1788856590 cluster:ay29) by smtp.aliyun-inc.com; Tue, 08 Sep 2026 16:36:30 +0800 From: Kyle Switch To: andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mmyangfl@gmail.com, horms@kernel.org, linux@armlinux.org.uk, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ming.xu@motor-comm.com, xiaolin.xu@motor-comm.com, jianmin.wang@motor-comm.com, wei.zhang@gl-inet.com, sijia.huang@gl-inet.com Subject: [PATCH net-next v6 3/6] net: dsa: motorcomm: move mib start from probe() to dsa_setup() Date: Tue, 8 Sep 2026 16:36:11 +0800 Message-Id: <20260908083614.2210505-4-kyle.switch@motor-comm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260908083614.2210505-1-kyle.switch@motor-comm.com> References: <20260908083614.2210505-1-kyle.switch@motor-comm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move MIB polling start from probe() to dsa_setup().so that it can be enabled based on the actual switch family support. Signed-off-by: Kyle Switch --- drivers/net/dsa/motorcomm/chip.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/motorcomm/chip.c b/drivers/net/dsa/motorcomm/c= hip.c index 191a7aa3733e..3a70ff00c126 100644 --- a/drivers/net/dsa/motorcomm/chip.c +++ b/drivers/net/dsa/motorcomm/chip.c @@ -4553,6 +4553,14 @@ static int yt921x_dsa_setup(struct dsa_switch *ds) struct device_node *child; int res; =20 + /* mib polling init */ + for (size_t i =3D 0; i < ARRAY_SIZE(priv->ports); i++) { + struct yt921x_port *pp =3D &priv->ports[i]; + + pp->index =3D i; + INIT_DELAYED_WORK(&pp->mib_read, yt921x_poll_mib); + } + mutex_lock(&priv->reg_lock); res =3D yt921x_chip_reset(priv); mutex_unlock(&priv->reg_lock); @@ -4810,13 +4818,6 @@ static int yt921x_mdio_probe(struct mdio_device *mdi= odev) priv->reg_ops =3D &yt921x_reg_ops_mdio; priv->reg_ctx =3D mdio; =20 - for (size_t i =3D 0; i < ARRAY_SIZE(priv->ports); i++) { - struct yt921x_port *pp =3D &priv->ports[i]; - - pp->index =3D i; - INIT_DELAYED_WORK(&pp->mib_read, yt921x_poll_mib); - } - ds =3D &priv->ds; ds->dev =3D dev; res =3D yt92xx_register_switch(ds); --=20 2.25.1 From nobody Fri Sep 25 21:40:43 2026 Received: from out28-172.mail.aliyun.com (out28-172.mail.aliyun.com [115.124.28.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AD1947D450; Tue, 8 Sep 2026 08:36:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788856598; cv=none; b=ZWFzbm65y/jglIUztMxmwHNqFoTd89gSPBV4c7E7xccbf0FqfwdaEuSEJ/ylEx+5KVK8gdtiSeoyB80r0ugn+rMcF2d7Mf1iQST/6+nJ8BosSkUg7d39gXLi0njuQD6LUx72AU05NXVYvwc3sEa5791a2DwKTYZYBxK98c8FJ5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788856598; c=relaxed/simple; bh=6V6IazCTTLRXtDDeC869PPBPA0ym/IWF4PhYzjwPfVY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YFpWApBzjr+pESmVqWSaP4FJ1c4fipS4V4nsUww9ONEPxh5l3+aXwXzUkEjUC5ocGF6p9GHc/DiUgm8LVsh6iuHAhQzxLJJoxknjmICM+Y1e0wWbPpHEBi5qQ81NO4n8FMQiqJjQhuntNUBiL+pZG3vSSnmOmJCX2kEs6uF1u8g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=motor-comm.com; spf=pass smtp.mailfrom=motor-comm.com; arc=none smtp.client-ip=115.124.28.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=motor-comm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=motor-comm.com X-Alimail-AntiSpam: AC=CONTINUE;BC=0.1226109|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.220266-0.00123502-0.778499;FP=11778661651840679552|0|0|0|0|-1|-1|-1;HT=maildocker-contentspam033037071049;MF=kyle.switch@motor-comm.com;NM=1;PH=DS;RN=16;RT=16;SR=0;TI=SMTPD_---.j8Z17x1_1788856591; Received: from motor-comm.com(mailfrom:kyle.switch@motor-comm.com fp:SMTPD_---.j8Z17x1_1788856591 cluster:ay29) by smtp.aliyun-inc.com; Tue, 08 Sep 2026 16:36:31 +0800 From: Kyle Switch To: andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mmyangfl@gmail.com, horms@kernel.org, linux@armlinux.org.uk, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ming.xu@motor-comm.com, xiaolin.xu@motor-comm.com, jianmin.wang@motor-comm.com, wei.zhang@gl-inet.com, sijia.huang@gl-inet.com Subject: [PATCH net-next v6 4/6] net: dsa: motorcomm: move mib stop from remove() to teardown() Date: Tue, 8 Sep 2026 16:36:12 +0800 Message-Id: <20260908083614.2210505-5-kyle.switch@motor-comm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260908083614.2210505-1-kyle.switch@motor-comm.com> References: <20260908083614.2210505-1-kyle.switch@motor-comm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This change ensures symmetry with the MIB start operation, which is already invoked in the setup(). Additionally, it consolidates per-switch operation into the appropriate DSA ops, improving code organization and maintainability. Signed-off-by: Kyle Switch --- drivers/net/dsa/motorcomm/chip.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/motorcomm/chip.c b/drivers/net/dsa/motorcomm/c= hip.c index 3a70ff00c126..f960edabde2b 100644 --- a/drivers/net/dsa/motorcomm/chip.c +++ b/drivers/net/dsa/motorcomm/chip.c @@ -4233,6 +4233,11 @@ static void yt921x_dsa_teardown(struct dsa_switch *d= s) #if IS_ENABLED(CONFIG_NET_DSA_YT921X_LEDS) yt921x_leds_remove(priv); #endif + for (size_t i =3D ARRAY_SIZE(priv->ports); i-- > 0; ) { + struct yt921x_port *pp =3D &priv->ports[i]; + + disable_delayed_work_sync(&pp->mib_read); + } } =20 static int yt921x_chip_detect(struct yt921x_priv *priv) @@ -4768,12 +4773,6 @@ static void yt921x_mdio_remove(struct mdio_device *m= diodev) if (!priv) return; =20 - for (size_t i =3D ARRAY_SIZE(priv->ports); i-- > 0; ) { - struct yt921x_port *pp =3D &priv->ports[i]; - - disable_delayed_work_sync(&pp->mib_read); - } - dsa_unregister_switch(&priv->ds); =20 for (unsigned int i =3D 0; i < ARRAY_SIZE(priv->acl_blks); i++) { --=20 2.25.1 From nobody Fri Sep 25 21:40:43 2026 Received: from out28-51.mail.aliyun.com (out28-51.mail.aliyun.com [115.124.28.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F4D637F318; Tue, 8 Sep 2026 08:36:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788856608; cv=none; b=otBZwafjKCNq8FFm2Aii77AXWamu7DSHx4bVypn38VZchF/4epS+cP/Q9eYA8+tLyyaf8IrWBuwQ6K9zKMdR7sQ3aHAbWqcFM0zZk+4eMwn08axSxkuonSr1IlP0OpWPXjdG4Vrd5zSLZxba9oMR2ut/b6ibbUhiERQbX6/O1l4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788856608; c=relaxed/simple; bh=cWcR3NF6dmpZ5N01x5Daet1Ub7pZTU2NTOVNzaxZaqQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sZKQ64DQJFSuG9/4bJw9DCXriCnvOgkq10R3TW1eB8lGQwZmIRufviCh+1D8DTSBpR2ybtdKBwxwb7YoPK6A1xU4NLfVNs0teKDdyDTQcH3EKym5006C24gBSU500vKYkR4qsnKsf3+54rFpaeXmcVAbQ76p0RRAtM4hfxM4PUM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=motor-comm.com; spf=pass smtp.mailfrom=motor-comm.com; arc=none smtp.client-ip=115.124.28.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=motor-comm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=motor-comm.com X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07437124|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.0202984-0.000282288-0.979419;FP=10833301415773638288|0|0|0|0|-1|-1|-1;HT=maildocker-contentspam033045213054;MF=kyle.switch@motor-comm.com;NM=1;PH=DS;RN=16;RT=16;SR=0;TI=SMTPD_---.j8Z17yB_1788856591; Received: from motor-comm.com(mailfrom:kyle.switch@motor-comm.com fp:SMTPD_---.j8Z17yB_1788856591 cluster:ay29) by smtp.aliyun-inc.com; Tue, 08 Sep 2026 16:36:32 +0800 From: Kyle Switch To: andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mmyangfl@gmail.com, horms@kernel.org, linux@armlinux.org.uk, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ming.xu@motor-comm.com, xiaolin.xu@motor-comm.com, jianmin.wang@motor-comm.com, wei.zhang@gl-inet.com, sijia.huang@gl-inet.com Subject: [PATCH net-next v6 5/6] net: dsa: tag_yt922x: add support for Motorcomm YT922x tags Date: Tue, 8 Sep 2026 16:36:13 +0800 Message-Id: <20260908083614.2210505-6-kyle.switch@motor-comm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260908083614.2210505-1-kyle.switch@motor-comm.com> References: <20260908083614.2210505-1-kyle.switch@motor-comm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Motorcomm YT922x tags with 8bytes. which includes ethertype field (default to 0x9988). Signed-off-by: Kyle Switch --- include/net/dsa.h | 2 + net/dsa/Kconfig | 6 +++ net/dsa/Makefile | 1 + net/dsa/tag_yt922x.c | 111 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 120 insertions(+) create mode 100644 net/dsa/tag_yt922x.c diff --git a/include/net/dsa.h b/include/net/dsa.h index 7507d632e7c6..0807a595aaad 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -61,6 +61,7 @@ struct tc_action; #define DSA_TAG_PROTO_NETC_VALUE 33 #define DSA_TAG_PROTO_KSZ8463_VALUE 34 #define DSA_TAG_PROTO_MT7628_VALUE 35 +#define DSA_TAG_PROTO_YT922X_VALUE 36 =20 enum dsa_tag_protocol { DSA_TAG_PROTO_NONE =3D DSA_TAG_PROTO_NONE_VALUE, @@ -99,6 +100,7 @@ enum dsa_tag_protocol { DSA_TAG_PROTO_NETC =3D DSA_TAG_PROTO_NETC_VALUE, DSA_TAG_PROTO_KSZ8463 =3D DSA_TAG_PROTO_KSZ8463_VALUE, DSA_TAG_PROTO_MT7628 =3D DSA_TAG_PROTO_MT7628_VALUE, + DSA_TAG_PROTO_YT922X =3D DSA_TAG_PROTO_YT922X_VALUE, }; =20 struct dsa_switch; diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig index 23b4b74004ed..0b9f8a632cf2 100644 --- a/net/dsa/Kconfig +++ b/net/dsa/Kconfig @@ -227,4 +227,10 @@ config NET_DSA_TAG_YT921X Say Y or M if you want to enable support for tagging frames for Motorcomm YT921x switches. =20 +config NET_DSA_TAG_YT922X + tristate "Tag driver for Motorcomm YT922x switches" + help + Say Y or M if you want to enable support for tagging frames for + Motorcomm YT922x switches. + endif diff --git a/net/dsa/Makefile b/net/dsa/Makefile index d15bcf5c68f0..0c53f4184bdb 100644 --- a/net/dsa/Makefile +++ b/net/dsa/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_NET_DSA_TAG_TRAILER) +=3D tag_trailer.o obj-$(CONFIG_NET_DSA_TAG_VSC73XX_8021Q) +=3D tag_vsc73xx_8021q.o obj-$(CONFIG_NET_DSA_TAG_XRS700X) +=3D tag_xrs700x.o obj-$(CONFIG_NET_DSA_TAG_YT921X) +=3D tag_yt921x.o +obj-$(CONFIG_NET_DSA_TAG_YT922X) +=3D tag_yt922x.o =20 # for tracing framework to find trace.h CFLAGS_trace.o :=3D -I$(src) diff --git a/net/dsa/tag_yt922x.c b/net/dsa/tag_yt922x.c new file mode 100644 index 000000000000..1ee9d1773598 --- /dev/null +++ b/net/dsa/tag_yt922x.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Motorcomm YT922x Switch Extended CPU Port Tagging + * + * Copyright (c) 2026 Kyle switch + * + */ + +#include + +#include "tag.h" + +#define YT922X_TAG_LEN 8 + +/* + * To define the from cpu tag format 8 bytes: + */ +#define YT922X_TAG_NAME "yt922x" +#define YT922X_TAG_PORTMASK_0 BIT(15) +#define YT922X_TAG_PORTMASK_M GENMASK(8, 0) +#define YT922X_TAG_PORTS(x) FIELD_PREP(YT922X_TAG_PORTMASK_M, (x)) +#define YT922X_TAG_FORCE_DST BIT(9) +#define YT922X_TAG_PRIO_M GENMASK(12, 10) +#define YT922X_TAG_PRIO_EN BIT(13) +#define YT922X_TAG_PRIO(x) (FIELD_PREP(YT922X_TAG_PRIO_M, (x)) | YT922X_= TAG_PRIO_EN) +#define YT922X_TAG_RX_PORT_M GENMASK(5, 2) +#define YT922X_TAG_RX_PRIO_M GENMASK(15, 13) + +static struct sk_buff * +yt922x_tag_xmit(struct sk_buff *skb, struct net_device *netdev) +{ + unsigned long ports; + __be16 *tag; + u16 ctrl; + + skb_push(skb, YT922X_TAG_LEN); + dsa_alloc_etype_header(skb, YT922X_TAG_LEN); + tag =3D dsa_etype_header_pos_tx(skb); + + tag[0] =3D htons(ETH_P_YT921X); + ports =3D dsa_xmit_port_mask(skb, netdev); + /*To fill in the case where the port index is not 0 */ + ctrl =3D YT922X_TAG_PRIO(skb->priority) | YT922X_TAG_FORCE_DST | + YT922X_TAG_PORTS(ports >> 1); + tag[1] =3D htons(ctrl); + if (ports & BIT(0)) { + /* To fill in the case where the port index is 0 */ + ctrl =3D YT922X_TAG_PORTMASK_0; + tag[2] =3D htons(ctrl); + } else { + tag[2] =3D 0; + } + tag[3] =3D 0; + + return skb; +} + +static struct sk_buff * +yt922x_tag_rcv(struct sk_buff *skb, struct net_device *netdev) +{ + unsigned int port; + __be16 *tag; + u16 rx; + + if (unlikely(!pskb_may_pull(skb, YT922X_TAG_LEN))) { + kfree_skb(skb); + return NULL; + } + + tag =3D dsa_etype_header_pos_rx(skb); + + if (unlikely(tag[0] !=3D htons(ETH_P_YT921X))) { + dev_warn_ratelimited(&netdev->dev, + "Unexpected EtherType 0x%04x\n", + ntohs(tag[0])); + kfree_skb(skb); + return NULL; + } + + /* Locate which port this is coming from */ + rx =3D ntohs(tag[2]); + port =3D FIELD_GET(YT922X_TAG_RX_PORT_M, rx); + skb->dev =3D dsa_conduit_find_user(netdev, 0, port); + if (unlikely(!skb->dev)) { + dev_warn_ratelimited(&netdev->dev, + "Couldn't decode source port %u\n", port); + kfree_skb(skb); + return NULL; + } + + /* Remove tag and update checksum */ + skb_pull_rcsum(skb, YT922X_TAG_LEN); + dsa_strip_etype_header(skb, YT922X_TAG_LEN); + + return skb; +} + +static const struct dsa_device_ops yt922x_netdev_ops =3D { + .name =3D YT922X_TAG_NAME, + .proto =3D DSA_TAG_PROTO_YT922X, + .xmit =3D yt922x_tag_xmit, + .rcv =3D yt922x_tag_rcv, + .needed_headroom =3D YT922X_TAG_LEN, +}; + +MODULE_DESCRIPTION("DSA tag driver for Motorcomm YT922x switches"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_YT922X, YT922X_TAG_NAME); + +module_dsa_tag_driver(yt922x_netdev_ops); + --=20 2.25.1 From nobody Fri Sep 25 21:40:43 2026 Received: from out28-193.mail.aliyun.com (out28-193.mail.aliyun.com [115.124.28.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB6D538655E; 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dmarc=pass (p=none dis=none) header.from=motor-comm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=motor-comm.com X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436259|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.0110083-5.85252e-05-0.988933;FP=15184871686268471958|0|0|0|0|-1|-1|-1;HT=maildocker-contentspam033037032089;MF=kyle.switch@motor-comm.com;NM=1;PH=DS;RN=16;RT=16;SR=0;TI=SMTPD_---.j8Z17zg_1788856592; Received: from motor-comm.com(mailfrom:kyle.switch@motor-comm.com fp:SMTPD_---.j8Z17zg_1788856592 cluster:ay29) by smtp.aliyun-inc.com; Tue, 08 Sep 2026 16:36:33 +0800 From: Kyle Switch To: andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mmyangfl@gmail.com, horms@kernel.org, linux@armlinux.org.uk, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ming.xu@motor-comm.com, xiaolin.xu@motor-comm.com, jianmin.wang@motor-comm.com, wei.zhang@gl-inet.com, sijia.huang@gl-inet.com Subject: [PATCH net-next v6 6/6] net: dsa: motorcomm: Add support for Motorcomm YT922x Date: Tue, 8 Sep 2026 16:36:14 +0800 Message-Id: <20260908083614.2210505-7-kyle.switch@motor-comm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260908083614.2210505-1-kyle.switch@motor-comm.com> References: <20260908083614.2210505-1-kyle.switch@motor-comm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Motorcomm YT922X, which is series of ethernet switches developed by Motorcomm Electronic Technology, includes YT9224 and YT9228. This patch adds basic support for a working DSA switch. Signed-off-by: Kyle Switch --- drivers/net/dsa/motorcomm/Kconfig | 1 + drivers/net/dsa/motorcomm/chip.c | 853 +++++++++++++++++++++++++++++- drivers/net/dsa/motorcomm/chip.h | 103 ++++ 3 files changed, 955 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/motorcomm/Kconfig b/drivers/net/dsa/motorcomm/= Kconfig index 79cdd79a1fd2..f690de4c7a7c 100644 --- a/drivers/net/dsa/motorcomm/Kconfig +++ b/drivers/net/dsa/motorcomm/Kconfig @@ -2,6 +2,7 @@ config NET_DSA_YT921X tristate "Motorcomm YT9215 ethernet switch chip support" select NET_DSA_TAG_YT921X + select NET_DSA_TAG_YT922X select NET_IEEE8021Q_HELPERS if DCB help This enables support for the Motorcomm YT9215 ethernet switch diff --git a/drivers/net/dsa/motorcomm/chip.c b/drivers/net/dsa/motorcomm/c= hip.c index f960edabde2b..4a052b1886b5 100644 --- a/drivers/net/dsa/motorcomm/chip.c +++ b/drivers/net/dsa/motorcomm/chip.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Driver for Motorcomm YT921x Switch + * Driver for Motorcomm YT921x and YT922x Switch * * Should work on YT9213/YT9214/YT9215/YT9218, but only tested on YT9215+S= GMII, * be sure to do your own checks before porting to another chip. @@ -112,6 +112,7 @@ struct yt921x_info { #define YT921X_PORT_MASK_INT0_n(n) GENMASK((n) - 1, 0) #define YT921X_PORT_MASK_EXT0 BIT(8) #define YT921X_PORT_MASK_EXT1 BIT(9) +#define YT922X_PORT_MASK_INTm_n(m, n) GENMASK((n), (m)) =20 static const struct yt921x_info yt921x_infos[] =3D { { @@ -149,9 +150,17 @@ static const struct yt921x_info yt921x_infos[] =3D { YT921X_PORT_MASK_INT0_n(8), YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, }, + { + "YT9224", YT9224_MAJOR, 0, 0, + YT922X_PORT_MASK_INTm_n(4, 7) | YT921X_PORT_MASK_INTn(0) | YT921X_PORT_M= ASK_INTn(8), + 0x0, + }, {} }; =20 +/* Define top ext addr */ +#define YT922X_COMMON_EXT_PHYADDR 9 + #define YT921X_VID_UNWARE 4095 =20 /* The interval should be small enough to avoid overflow of 32bit MIBs. @@ -4694,6 +4703,826 @@ static const struct dsa_switch_ops yt921x_dsa_switc= h_ops =3D { .setup =3D yt921x_dsa_setup, }; =20 +static int yt922x_port_down(struct yt921x_priv *priv, int port) +{ + u32 mask; + int res; + + /* mac force down */ + mask =3D YT922X_PORT_LINK | YT922X_PORT_RX_MAC_EN | + YT922X_PORT_TX_MAC_EN | YT922X_PORT_LINK_AN; + res =3D yt921x_reg_clear_bits(priv, YT922X_PORTn_CTRL(port), mask); + if (res) + return res; + /* Need force op to make soft configuration effective */ + mask =3D YT922X_PORT_FORCE_OP; + res =3D yt921x_reg_set_bits(priv, YT922X_PORTn_CTRL(port), mask); + if (res) + return res; + + /* disable en_phy */ + res =3D yt921x_reg_clear_bits(priv, YT922X_EN_PHY_VALUE, BIT(port)); + if (res) + return res; + res =3D yt921x_reg_set_bits(priv, YT922X_EN_PHY_OVERWRITE, BIT(port)); + if (res) + return res; + + return 0; +} + +static void +yt922x_phylink_mac_link_down(struct phylink_config *config, unsigned int m= ode, + phy_interface_t interface) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct yt921x_priv *priv =3D to_yt921x_priv(dp->ds); + int port =3D dp->index; + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt922x_port_down(priv, port); + mutex_unlock(&priv->reg_lock); + + if (res) + dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "bring down", + port, res); +} + +static int +yt922x_port_up(struct yt921x_priv *priv, int port, unsigned int mode, + phy_interface_t interface, int speed, int duplex, + bool tx_pause, bool rx_pause) +{ + u32 mask; + u32 ctrl; + int res; + + switch (speed) { + case SPEED_10: + ctrl =3D YT921X_PORT_SPEED_10; + break; + case SPEED_100: + ctrl =3D YT921X_PORT_SPEED_100; + break; + case SPEED_1000: + ctrl =3D YT921X_PORT_SPEED_1000; + break; + case SPEED_2500: + ctrl =3D YT921X_PORT_SPEED_2500; + break; + case SPEED_5000: + ctrl =3D YT921X_PORT_SPEED_5000; + break; + case SPEED_10000: + ctrl =3D YT921X_PORT_SPEED_10000; + break; + default: + return -EINVAL; + } + if (duplex =3D=3D DUPLEX_FULL) + ctrl |=3D YT922X_PORT_DUPLEX_FULL; + if (tx_pause) + ctrl |=3D YT922X_PORT_TX_PAUSE; + if (rx_pause) + ctrl |=3D YT922X_PORT_RX_PAUSE; + ctrl |=3D YT922X_PORT_RX_MAC_EN | YT922X_PORT_TX_MAC_EN | + YT922X_PORT_CFG_TX_EN | YT922X_PORT_LINK | + YT922X_PORT_CFG_RX_EN; + ctrl &=3D ~(YT922X_PORT_FC_AN | YT922X_PORT_LINK_AN); + res =3D yt921x_reg_write(priv, YT922X_PORTn_CTRL(port), ctrl); + if (res) + return res; + + /* force op */ + mask =3D YT922X_PORT_FORCE_OP; + res =3D yt921x_reg_set_bits(priv, YT922X_PORTn_CTRL(port), mask); + if (res) + return res; + + /* enable en_phy */ + res =3D yt921x_reg_set_bits(priv, YT922X_EN_PHY_VALUE, BIT(port)); + if (res) + return res; + res =3D yt921x_reg_set_bits(priv, YT922X_EN_PHY_OVERWRITE, BIT(port)); + if (res) + return res; + + return 0; +} + +static void +yt922x_phylink_mac_link_up(struct phylink_config *config, + struct phy_device *phydev, unsigned int mode, + phy_interface_t interface, int speed, int duplex, + bool tx_pause, bool rx_pause) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct yt921x_priv *priv =3D to_yt921x_priv(dp->ds); + int port =3D dp->index; + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt922x_port_up(priv, port, mode, interface, speed, duplex, + tx_pause, rx_pause); + mutex_unlock(&priv->reg_lock); + + if (res) + dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "bring up", + port, res); +} + +static int +yt921x_intif_ext_write(struct yt921x_priv *priv, int port, int reg, u16 va= l) +{ + int res; + + if (port >=3D priv->series->max_ports) + return -ENODEV; + + res =3D yt921x_intif_write(priv, port, YT92XX_PAGE_SELECT, reg); + if (res) + return res; + + res =3D yt921x_intif_write(priv, port, YT92XX_PAGE, val); + if (res) + return res; + + return 0; +} + +static int +yt921x_intif_ext_read(struct yt921x_priv *priv, int port, int reg, u16 *va= lp) +{ + int res; + + if (port >=3D priv->series->max_ports) + return -ENODEV; + + res =3D yt921x_intif_write(priv, port, YT92XX_PAGE_SELECT, reg); + if (res) + return res; + + res =3D yt921x_intif_read(priv, port, YT92XX_PAGE, valp); + if (res) + return res; + + return 0; +} + +static int yt922x_sds_phyaddr_get(int port, + enum yt922x_phy_reg_type reg_type, + enum yt922x_phy_reg_space reg_space) +{ + int res =3D port; + + /* + * sds phyaddr mapping depend on reg_type and reg_space + */ + if (!yt922x_port_is_internal_sds(port)) + return -EOPNOTSUPP; + if (reg_type =3D=3D YT922X_PHY_REG_TYPE_COMMON_EXT) { + res =3D YT922X_COMMON_EXT_PHYADDR; + return res; + } + + return res; +} + +/** + * Initialize serdes configuration based on interface mode. + */ +static int yt922x_sds_init(struct yt921x_priv *priv, int port, + phy_interface_t interface) +{ + int addr; + u16 data; + int res; + + addr =3D yt922x_sds_phyaddr_get + (port, YT922X_PHY_REG_TYPE_SDS_COMMON_EXT, + YT922X_PHY_REG_SPACE_SGMII); + if (addr < 0) + return -EINVAL; + /* write protect */ + res =3D yt921x_intif_ext_write(priv, addr, 0x4be, 0xd); + if (res) + return res; + /* CDR */ + if (interface =3D=3D PHY_INTERFACE_MODE_100BASEX) { + res =3D yt921x_intif_ext_write(priv, addr, 0x406, 0x0); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x416, 0x3458); + if (res) + return res; + } else { + res =3D yt921x_intif_ext_write(priv, addr, 0x406, 0x800); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x416, 0x4558); + if (res) + return res; + } + /* PLL */ + if (interface =3D=3D PHY_INTERFACE_MODE_USXGMII) { + res =3D yt921x_intif_ext_write(priv, addr, 0x43a, 0x1006); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x43f, 0x3029); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x42a, 0xf070); + if (res) + return res; + } else { + res =3D yt921x_intif_ext_write(priv, addr, 0x43d, 0x207d); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x43c, 0x207d); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x43f, 0x3032); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x43a, 0x6); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x42a, 0xf070); + if (res) + return res; + } + /* VCO */ + res =3D yt921x_intif_ext_write(priv, addr, 0x439, 0xC0); + if (res) + return res; + /* Vdac */ + res =3D yt921x_intif_ext_write(priv, addr, 0x492, 0x7f7f); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x491, 0x7f); + if (res) + return res; + /* Eye */ + res =3D yt921x_intif_ext_write(priv, addr, 0x454, 0xf14); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x497, 0xa44); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x4cd, 0x0); + if (res) + return res; + + res =3D yt921x_intif_ext_write(priv, addr, 0x4af, 0x45e3); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x48a, 0xfff); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x408, 0x7c00); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x4d6, 0x7f); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x44f, 0xff08); + if (res) + return res; + /* FFE */ + res =3D yt921x_intif_ext_write(priv, addr, 0x48e, 0x7d00); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0xd, 0x60f); + if (res) + return res; + /* CTLE */ + res =3D yt921x_intif_ext_write(priv, addr, 0x4b0, 0x804); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x4b1, 0x7774); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x4af, 0x45e7); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x3, 0x5603); + if (res) + return res; + + msleep(20); + res =3D yt921x_intif_ext_write(priv, addr, 0x492, 0x7fff); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x492, 0x7f7f); + if (res) + return res; + /* CTLE */ + res =3D yt921x_intif_ext_write(priv, addr, 0x2000, 0x40); + if (res) + return res; + res =3D yt921x_intif_ext_write(priv, addr, 0x2000, 0x0); + if (res) + return res; + + if (interface =3D=3D PHY_INTERFACE_MODE_SGMII) { + res =3D yt921x_intif_ext_write(priv, addr, 0x1042, 0x48c); + if (res) + return res; + } + /* soft reset */ + addr =3D yt922x_sds_phyaddr_get(port, YT922X_PHY_REG_TYPE_MII, + YT922X_PHY_REG_SPACE_SGMII); + if (addr < 0) + return res; + res =3D yt921x_intif_read(priv, addr, 0x0, &data); + if (res) + return res; + data &=3D ~(1 << 15); + res =3D yt921x_intif_write(priv, addr, 0x0, data); + if (res) + return res; + addr =3D yt922x_sds_phyaddr_get(port, YT922X_PHY_REG_TYPE_MII, + YT922X_PHY_REG_SPACE_USXGMII); + if (addr < 0) + return res; + res =3D yt921x_intif_read(priv, addr, 0x0, &data); + if (res) + return res; + data |=3D 1 << 15; + res =3D yt921x_intif_write(priv, addr, 0x0, data); + if (res) + return res; + + return 0; +} + +static void +yt922x_phylink_mac_config(struct phylink_config *config, unsigned int mode, + const struct phylink_link_state *state) +{ +} + +static struct phylink_pcs * +yt922x_phylink_mac_select_pcs(struct phylink_config *config, + phy_interface_t interface) +{ + struct dsa_port *dp =3D dsa_phylink_to_port(config); + struct yt921x_priv *priv =3D dp->ds->priv; + struct phylink_pcs *pcs =3D NULL; + int port =3D dp->index; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_100BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_USXGMII: + switch (port) { + case 0: + pcs =3D &priv->pcs_port_0.pcs; + break; + + case 8: + pcs =3D &priv->pcs_port_8.pcs; + break; + } + break; + + default: + break; + } + + return pcs; +} + +static const struct phylink_mac_ops yt922x_phylink_mac_ops =3D { + .mac_select_pcs =3D yt922x_phylink_mac_select_pcs, + .mac_link_down =3D yt922x_phylink_mac_link_down, + .mac_link_up =3D yt922x_phylink_mac_link_up, + .mac_config =3D yt922x_phylink_mac_config, +}; + +static struct yt922x_pcs *pcs_to_yt922x_pcs(struct phylink_pcs *pcs) +{ + return container_of(pcs, struct yt922x_pcs, pcs); +} + +static void yt922x_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg= _mode, + struct phylink_link_state *state) +{ + struct yt921x_priv *priv =3D pcs_to_yt922x_pcs(pcs)->priv; + int port =3D pcs_to_yt922x_pcs(pcs)->port; + u32 reg; + int res; + + res =3D yt921x_reg_read(priv, YT922X_PORTn_STATUS(port), ®); + if (res < 0) { + state->link =3D false; + return; + } + + state->link =3D !!(reg & YT922X_PORT_LINK_STATE); + state->an_complete =3D state->link; + state->duplex =3D (reg & YT922X_PORT_LINK_DUPLEX) ? DUPLEX_FULL : + DUPLEX_HALF; + + switch (reg & YT922X_PORT_SPEED_M) { + case YT922X_PORT_SPEED_10: + state->speed =3D SPEED_10; + break; + case YT922X_PORT_SPEED_100: + state->speed =3D SPEED_100; + break; + case YT922X_PORT_SPEED_1000: + state->speed =3D SPEED_1000; + break; + case YT922X_PORT_SPEED_10000: + state->speed =3D SPEED_10000; + break; + case YT922X_PORT_SPEED_2500: + state->speed =3D SPEED_2500; + break; + case YT922X_PORT_SPEED_5000: + state->speed =3D SPEED_5000; + break; + default: + state->speed =3D SPEED_UNKNOWN; + break; + } +} + +static void yt922x_pcs_an_restart(struct phylink_pcs *pcs) +{ +} + +static int yt922x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mod= e, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + struct yt921x_priv *priv =3D pcs_to_yt922x_pcs(pcs)->priv; + int res, port; + u16 data; + u16 ctrl; + int addr; + + port =3D pcs_to_yt922x_pcs(pcs)->port; + if (port !=3D 0 && port !=3D 8) + return -EINVAL; + + /* SERDES init and interface configuration */ + res =3D yt922x_sds_init(priv, port, interface); + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + ctrl =3D YT92XX_SERDES_MODE_SGMII; + break; + case PHY_INTERFACE_MODE_100BASEX: + ctrl =3D YT92XX_SERDES_MODE_100BASEX; + break; + case PHY_INTERFACE_MODE_1000BASEX: + ctrl =3D YT92XX_SERDES_MODE_1000BASEX; + break; + case PHY_INTERFACE_MODE_2500BASEX: + ctrl =3D YT92XX_SERDES_MODE_2500BASEX; + break; + case PHY_INTERFACE_MODE_USXGMII: + ctrl =3D YT92XX_SERDES_MODE_USXGMII; + break; + default: + return -EINVAL; + } + addr =3D yt922x_sds_phyaddr_get + (port, YT922X_PHY_REG_TYPE_SDS_COMMON_EXT, + YT922X_PHY_REG_SPACE_SGMII); + if (addr < 0) + return -EINVAL; + + res =3D yt921x_intif_ext_read(priv, addr, YT922X_PORT_SDSn, &data); + if (res) + return res; + data &=3D ~YT922X_SERDES_MODE_M; + data |=3D ctrl; + res =3D yt921x_intif_ext_write(priv, addr, YT922X_PORT_SDSn, data); + + return res; +} + +static const struct phylink_pcs_ops yt922x_pcs_ops =3D { + .pcs_get_state =3D yt922x_pcs_get_state, + .pcs_config =3D yt922x_pcs_config, + .pcs_an_restart =3D yt922x_pcs_an_restart, +}; + +static enum dsa_tag_protocol +yt922x_dsa_get_tag_protocol(struct dsa_switch *ds, int port, + enum dsa_tag_protocol m) +{ + return DSA_TAG_PROTO_YT922X; +} + +static void +yt922x_dsa_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + const struct yt921x_info *info =3D priv->info; + + config->mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000; + + if (info->internal_mask & BIT(port)) { + if (port >=3D 4 && port <=3D 7) { + /* port 4 to port 7, internal utp */ + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + config->mac_capabilities |=3D MAC_2500FD; + } else { + __set_bit(PHY_INTERFACE_MODE_SGMII, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_100BASEX, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_1000BASEX, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, + config->supported_interfaces); + config->mac_capabilities |=3D MAC_2500FD; + __set_bit(PHY_INTERFACE_MODE_USXGMII, + config->supported_interfaces); + config->mac_capabilities |=3D MAC_2500FD; + config->mac_capabilities |=3D MAC_5000FD; + config->mac_capabilities |=3D MAC_10000FD; + } + } else { + /* external port will added later */ + } +} + +static int yt922x_port_setup(struct yt921x_priv *priv, int port) +{ + struct dsa_switch *ds =3D &priv->ds; + u32 mask; + u32 ctrl; + int res; + + /* enable user port isolation and disable fdb learning */ + ctrl =3D ~priv->cpu_ports_mask; + res =3D yt921x_reg_write(priv, YT922X_PORTn_ISOLATION(port), ctrl); + if (res) + return res; + + mask =3D YT922X_PORT_LEARN_DIS; + res =3D yt921x_reg_set_bits(priv, YT922X_PORTn_LEARN(port), mask); + if (res) + return res; + + if (dsa_is_cpu_port(ds, port)) { + ctrl =3D ~(u32)0; + res =3D yt921x_reg_write(priv, YT922X_PORTn_ISOLATION(port), + ctrl); + if (res) + return res; + } + + return 0; +} + +static int yt922x_dsa_port_setup(struct dsa_switch *ds, int port) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt922x_port_setup(priv, port); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static int yt922x_chip_detect(struct yt921x_priv *priv) +{ + struct device *dev =3D to_device(priv); + const struct yt921x_info *info; + u32 chipid; + u32 major; + int res; + + res =3D yt921x_reg_read(priv, YT921X_CHIP_ID, &chipid); + if (res) + return res; + major =3D FIELD_GET(YT921X_CHIP_ID_MAJOR, chipid); + for (info =3D yt921x_infos; info->name; info++) + if (info->major =3D=3D major) + break; + if (!info->name) { + dev_err(dev, "Unexpected chipid 0x%x\n", chipid); + return -ENODEV; + } + priv->info =3D info; + + return 0; +} + +static int yt922x_chip_reset(struct yt921x_priv *priv) +{ + struct device *dev =3D to_device(priv); + u16 eth_p_tag; + u32 val; + int res; + + res =3D yt922x_chip_detect(priv); + if (res) + return res; + + /* Reset */ + res =3D yt921x_reg_write(priv, YT921X_RST, YT921X_RST_HW); + if (res) + return res; + + fsleep(YT921X_RST_DELAY_US); + + val =3D 0; + res =3D yt921x_reg_wait(priv, YT921X_RST, ~0, &val); + if (res) + return res; + + /* TPID check */ + res =3D yt921x_reg_read(priv, YT921X_CPU_TAG_TPID, &val); + if (res) + return res; + eth_p_tag =3D FIELD_GET(YT921X_CPU_TAG_TPID_TPID_M, val); + if (eth_p_tag !=3D ETH_P_YT921X) { + dev_err(dev, "Tag type 0x%x !=3D 0x%x\n", eth_p_tag, + ETH_P_YT921X); + return -EINVAL; + } + + return 0; +} + +static int yt922x_chip_setup_dsa(struct yt921x_priv *priv) +{ + unsigned long cpu_ports_mask; + u32 ctrl; + int port; + int res; + + ctrl =3D GENMASK(9, 0); + res =3D yt921x_reg_write(priv, YT922X_FILTER_UNK_UCAST, ctrl); + if (res) + return res; + + ctrl =3D 0; + for (int i =3D 0; i < priv->series->max_ports; i++) + ctrl |=3D YT922X_ACT_UNK_ACTn_TRAP(i); + cpu_ports_mask =3D priv->cpu_ports_mask; + for_each_set_bit(port, &cpu_ports_mask, priv->series->max_ports) { + ctrl &=3D ~YT922X_ACT_UNK_ACTn_M(port); + ctrl |=3D YT922X_ACT_UNK_ACTn_DROP(port); + } + res =3D yt921x_reg_write(priv, YT922X_ACT_UNK_UCAST, ctrl); + if (res) + return res; + res =3D yt921x_reg_write(priv, YT922X_ACT_UNK_MCAST, ctrl); + if (res) + return res; + + return 0; +} + +static int yt922x_chip_setup(struct yt921x_priv *priv) +{ + u32 ctrl; + int res; + + ctrl =3D YT922X_FUNC_MIB | YT922X_FUNC_ACL; + res =3D yt921x_reg_set_bits(priv, YT921X_FUNC, ctrl); + if (res) + return res; + + res =3D yt922x_chip_setup_dsa(priv); + if (res) + return res; + + return 0; +} + +static int yt922x_cpu_tag_mode_set_8b(struct yt921x_priv *priv) +{ + u32 val; + u32 val1; + int res; + + /* cpu tag mode set to 8b*/ + res =3D yt921x_reg_read(priv, YT922X_CPU_TAG_RX_CTRL, &val); + if (res) + return res; + res =3D yt921x_reg_read(priv, YT922X_CPU_TAG_TX_CTRL, &val1); + if (res) + return res; + val &=3D ~YT922X_CPU_TAG_RX_MODE; + val1 &=3D ~YT922X_CPU_TAG_TX_MODE; + val1 &=3D ~YT922X_CPU_TAG_TX_TYPE; + res =3D yt921x_reg_write(priv, YT922X_CPU_TAG_RX_CTRL, val); + if (res) + return res; + res =3D yt921x_reg_write(priv, YT922X_CPU_TAG_TX_CTRL, val1); + if (res) + return res; + + return 0; +} + +static int yt922x_cpu_port_set(struct yt921x_priv *priv) +{ + struct dsa_switch *ds =3D &priv->ds; + u32 ctrl; + int res; + + /* cpu tag mode */ + res =3D yt922x_cpu_tag_mode_set_8b(priv); + if (res) + return res; + + /* Enable DSA */ + priv->cpu_ports_mask =3D dsa_cpu_ports(ds); + ctrl =3D YT921X_EXT_CPU_PORT_TAG_EN | YT921X_EXT_CPU_PORT_PORT_EN | + YT921X_EXT_CPU_PORT_PORT(__ffs(priv->cpu_ports_mask)); + res =3D yt921x_reg_write(priv, YT921X_EXT_CPU_PORT, ctrl); + if (res) + return res; + + /* Setup software switch */ + ctrl =3D YT922X_CPU_COPY_TO_EXT_CPU; + res =3D yt921x_reg_write(priv, YT922X_CPU_COPY, ctrl); + if (res) + return res; + + return res; +} + +static void yt922x_setup_pcs(struct yt921x_priv *priv, struct yt922x_pcs *= pcs, + int port) +{ + pcs->pcs.ops =3D &yt922x_pcs_ops; + + pcs->priv =3D priv; + pcs->port =3D port; +} + +static int yt922x_dsa_setup(struct dsa_switch *ds) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + struct device *dev =3D to_device(priv); + struct device_node *np =3D dev->of_node; + struct device_node *child; + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt922x_chip_reset(priv); + mutex_unlock(&priv->reg_lock); + if (res) + return res; + + /* Register the internal mdio bus. */ + child =3D of_get_child_by_name(np, "mdio"); + if (child) { + res =3D yt921x_mbus_int_init(priv, child); + of_node_put(child); + if (res) + return res; + } + + /* cpu port set */ + mutex_lock(&priv->reg_lock); + res =3D yt922x_cpu_port_set(priv); + mutex_unlock(&priv->reg_lock); + if (res) + return res; + + mutex_lock(&priv->reg_lock); + res =3D yt922x_chip_setup(priv); + mutex_unlock(&priv->reg_lock); + if (res) + return res; + + /* switch sds pcs setup */ + yt922x_setup_pcs(priv, &priv->pcs_port_0, 0); + yt922x_setup_pcs(priv, &priv->pcs_port_8, 8); + + return 0; +} + +static const struct dsa_switch_ops yt922x_dsa_switch_ops =3D { + /* port */ + .get_tag_protocol =3D yt922x_dsa_get_tag_protocol, + .phylink_get_caps =3D yt922x_dsa_phylink_get_caps, + .port_setup =3D yt922x_dsa_port_setup, + /* chip */ + .setup =3D yt922x_dsa_setup, +}; + static const struct yt92xx_series yt92xx_series_table[] =3D { [YT92XX_MODE_YT921X] =3D { .mode =3D YT92XX_MODE_YT921X, @@ -4707,6 +5536,18 @@ static const struct yt92xx_series yt92xx_series_tabl= e[] =3D { .switch_ops =3D &yt921x_dsa_switch_ops, .mac_ops =3D &yt921x_phylink_mac_ops }, + [YT92XX_MODE_YT922X] =3D { + .mode =3D YT92XX_MODE_YT922X, + .name =3D "YT922x", + .max_ports =3D YT922X_PORT_NUM, + .num_lag_ids =3D YT922X_LAG_NUM, + .ageing_time_min =3D 1 * 6000, + .ageing_time_max =3D U16_MAX * 6000, + .dscp_prio_mapping_is_global =3D true, + .assisted_learning_on_cpu_port =3D true, + .switch_ops =3D &yt922x_dsa_switch_ops, + .mac_ops =3D &yt922x_phylink_mac_ops, + }, }; =20 static const struct yt92xx_series *yt92xx_series_lookup(u32 major) @@ -4716,6 +5557,10 @@ static const struct yt92xx_series *yt92xx_series_loo= kup(u32 major) =20 if (major =3D=3D YT9215_MAJOR || major =3D=3D YT9218_MAJOR) mode =3D YT92XX_MODE_YT921X; + else if (major =3D=3D YT9224_MAJOR) + mode =3D YT92XX_MODE_YT922X; + else + mode =3D YT92XX_MODE_MAX; =20 for (i =3D 0; i < ARRAY_SIZE(yt92xx_series_table); ++i) if (yt92xx_series_table[i].mode =3D=3D mode) @@ -4832,6 +5677,9 @@ static const struct of_device_id yt921x_of_match[] = =3D { { .compatible =3D "motorcomm,yt9215", }, + { + .compatible =3D "motorcomm,yt9224", + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, yt921x_of_match); @@ -4849,5 +5697,6 @@ static struct mdio_driver yt921x_mdio_driver =3D { mdio_module_driver(yt921x_mdio_driver); =20 MODULE_AUTHOR("David Yang "); -MODULE_DESCRIPTION("Driver for Motorcomm YT921x Switch"); +MODULE_AUTHOR("Kyle Switch "); +MODULE_DESCRIPTION("Driver for Motorcomm YT921x and YT922x Switch"); MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/motorcomm/chip.h b/drivers/net/dsa/motorcomm/c= hip.h index c446aea449ed..3b7ea3cbf522 100644 --- a/drivers/net/dsa/motorcomm/chip.h +++ b/drivers/net/dsa/motorcomm/chip.h @@ -111,6 +111,7 @@ #define YT921X_PORT_SPEED_1000 YT921X_PORT_SPEED(2) #define YT921X_PORT_SPEED_10000 YT921X_PORT_SPEED(3) #define YT921X_PORT_SPEED_2500 YT921X_PORT_SPEED(4) +#define YT921X_PORT_SPEED_5000 YT921X_PORT_SPEED(5) #define YT921X_PON_STRAP_FUNC 0x80320 #define YT921X_PON_STRAP_VAL 0x80324 #define YT921X_PON_STRAP_CAP 0x80328 @@ -837,6 +838,7 @@ enum yt921x_fdb_entry_status { =20 #define YT9215_MAJOR 0x9002 #define YT9218_MAJOR 0x9001 +#define YT9224_MAJOR 0x9004 =20 /* required for a hard reset */ #define YT921X_RST_DELAY_US 10000 @@ -861,6 +863,99 @@ enum yt921x_fdb_entry_status { #define yt921x_port_is_internal(port) ((port) < 8) #define yt921x_port_is_external(port) ((port) =3D=3D 8 || (port) =3D=3D 9) =20 +/* yt922x register lists */ +#define YT92XX_PAGE_SELECT 0x1e +#define YT92XX_PAGE 0x1f +#define YT922X_PORTn_STATUS(port) (0x80200 + 4 * (port)) +#define YT922X_PORT_LINK_STATE BIT(8) +#define YT922X_PORT_LINK_DUPLEX BIT(7) +#define YT922X_PORT_RX_FC_EN BIT(6) +#define YT922X_PORT_TX_FC_EN BIT(5) +#define YT922X_PORT_SPEED_10 0 +#define YT922X_PORT_SPEED_100 1 +#define YT922X_PORT_SPEED_1000 2 +#define YT922X_PORT_SPEED_10000 3 +#define YT922X_PORT_SPEED_2500 4 +#define YT922X_PORT_SPEED_5000 5 +#define YT922X_EN_PHY_OVERWRITE (0x80040) +#define YT922X_EN_PHY_VALUE (0x8003c) +/* CTRL: force op to make soft configuration effective */ +#define YT922X_PORTn_CTRL(port) (0x80080 + 4 * (port)) +#define YT922X_PORT_FORCE_OP BIT(14) +#define YT922X_PORT_CFG_TX_EN BIT(13) +#define YT922X_PORT_CFG_RX_EN BIT(12) +#define YT922X_PORT_FC_AN BIT(11) +#define YT922X_PORT_LINK_AN BIT(10) /* CTRL: auto negotiation */ +#define YT922X_PORT_LINK BIT(9) /* CTRL: link status */ +#define YT922X_PORT_HALF_PAUSE BIT(8) /* Half-duplex back pressure mod= e */ +#define YT922X_PORT_DUPLEX_FULL BIT(7) +#define YT922X_PORT_RX_PAUSE BIT(6) +#define YT922X_PORT_TX_PAUSE BIT(5) +#define YT922X_PORT_RX_MAC_EN BIT(4) +#define YT922X_PORT_TX_MAC_EN BIT(3) +#define YT922X_PORT_SPEED_M GENMASK(2, 0) +#define YT922X_PORT_SDSn 0x400 +#define YT922X_SERDES_MODE_M GENMASK(6, 4) +#define YT922X_SERDES_MODE(x) FIELD_PREP(YT922X_SERDES_MODE_M, (x)) +#define YT92XX_SERDES_MODE_SGMII YT922X_SERDES_MODE(0) +#define YT92XX_SERDES_MODE_REVSGMII YT921X_SERDES_MODE(1) +#define YT92XX_SERDES_MODE_1000BASEX YT921X_SERDES_MODE(2) +#define YT92XX_SERDES_MODE_100BASEX YT921X_SERDES_MODE(3) +#define YT92XX_SERDES_MODE_2500BASEX YT921X_SERDES_MODE(4) +#define YT92XX_SERDES_MODE_USXGMII YT922X_SERDES_MODE(6) +#define YT922X_PORT_NUM 9 + +/* LAG */ +#define YT922X_LAG_NUM 4 +/* ISO */ +#define YT922X_PORTn_ISOLATION(port) (0x4 * (port) + 0x180d80) +/* FDB */ +#define YT922X_PORTn_LEARN(port) (0x180300 + 4 * (port)) +#define YT922X_PORT_LEARN_DIS BIT(18) +/* GLOBAL CTRL */ +#define YT922X_FUNC_ACL BIT(5) +#define YT922X_FUNC_MIB BIT(4) +/* CTRL PKT */ +#define YT922X_FILTER_UNK_UCAST 0x180ec8 +#define YT922X_ACT_UNK_UCAST 0x180ed8 +#define YT922X_ACT_UNK_MCAST 0x180ee0 +#define YT922X_ACT_UNK_MCAST_BYPASS_DROP_PIM BIT(22) +#define YT922X_ACT_UNK_MCAST_BYPASS_DROP_MLD BIT(21) +#define YT922X_ACT_UNK_MCAST_BYPASS_DROP_IGMP BIT(20) +#define YT922X_ACT_UNK_ACTn_M(port) GENMASK(2 * (port) + 1, 2 * (port)) +#define YT922X_ACT_UNK_ACTn(port, x) ((x) << (2 * (port))) +#define YT922X_ACT_UNK_ACTn_FORWARD(port) YT922X_ACT_UNK_ACTn(port, 0) /= * flood */ +#define YT922X_ACT_UNK_ACTn_DROP(port) YT922X_ACT_UNK_ACTn(port, 1) /* = discard */ +#define YT922X_ACT_UNK_ACTn_TRAP(port) YT922X_ACT_UNK_ACTn(port, 3) /* = steer to CPU */ + +/* CPU PORT */ +#define YT922X_CPU_COPY 0x181100 +#define YT922X_CPU_COPY_TO_INT_CPU BIT(1) +#define YT922X_CPU_COPY_TO_EXT_CPU BIT(0) +#define YT922X_CPU_TAG_RX_CTRL 0x80504 +#define YT922X_CPU_TAG_RX_MODE BIT(0) +#define YT922X_CPU_TAG_TX_CTRL 0x100710 +#define YT922X_CPU_TAG_TX_TYPE BIT(0) +#define YT922X_CPU_TAG_TX_MODE BIT(1) +#define YT922X_CPU_TAG_TX_CTAG_OP BIT(2) +#define YT922X_CPU_TAG_TX_STAG_OP BIT(3) + +#define yt922x_port_is_internal_sds(port) ((port) =3D=3D 0 || (port) =3D= =3D 8) + +enum yt922x_phy_reg_type { + YT922X_PHY_REG_TYPE_COMMON_EXT, + YT922X_PHY_REG_TYPE_SDS_COMMON_EXT, + YT922X_PHY_REG_TYPE_MII, + YT922X_PHY_REG_TYPE_EXT, + YT922X_PHY_REG_TYPE_MAX +}; + +enum yt922x_phy_reg_space { + YT922X_PHY_REG_SPACE_SGMII, + YT922X_PHY_REG_SPACE_USXGMII, + YT922X_PHY_REG_SPACE_MAX +}; + struct yt921x_mib { u64 rx_broadcast; u64 rx_pause; @@ -979,6 +1074,12 @@ struct yt92xx_series { const struct phylink_mac_ops *mac_ops; }; =20 +struct yt922x_pcs { + struct phylink_pcs pcs; + struct yt921x_priv *priv; + int port; +}; + struct yt921x_priv { struct dsa_switch ds; =20 @@ -1007,6 +1108,8 @@ struct yt921x_priv { =20 u8 acl_masks[YT921X_ACL_BLK_NUM]; struct yt921x_acl_blk *acl_blks[YT921X_ACL_BLK_NUM]; + struct yt922x_pcs pcs_port_0; + struct yt922x_pcs pcs_port_8; }; =20 #endif --=20 2.25.1