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charset="utf-8" Add bindings for the pin controller in the QCS615 Low Power Audio SubSystem (LPASS) Low Power Island (LPI). The LPASS LPI TLMM is a dedicated pin controller for audio pins on QCS615 which supports 32 GPIOs (gpio0-gpio31) with functions including i2s1, dmic1, dmic2 and spkr_i2s_mclk_a. Signed-off-by: Karthik S --- .../qcom,qcs615-lpass-lpi-pinctrl.yaml | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,qcs615-l= pass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-lpass-lp= i-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-lpas= s-lpi-pinctrl.yaml new file mode 100644 index 000000000000..dc1525d7bf55 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-lpass-lpi-pinct= rl.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcs615-lpass-lpi-pinctrl.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS615 SoC LPASS LPI TLMM + +maintainers: + - Karthik S + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSyst= em + (LPASS) Low Power Island (LPI) of Qualcomm QCS615 SoC. + +properties: + compatible: + const: qcom,qcs615-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + + clock-names: + items: + - const: core + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qcs615-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qcs615-lpass-state" + additionalProperties: false + +$defs: + qcom-qcs615-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-9]|3[0-1])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, gpio, i2s1_c= lk, + i2s1_data, i2s1_ws, spkr_i2s_mclk_a ] + description: + Specify the alternative function to be configured for the specif= ied + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + lpi_tlmm: pinctrl@62b40000 { + compatible =3D "qcom,qcs615-lpass-lpi-pinctrl"; + reg =3D <0x62b40000 0x20000>, + <0x62b00000 0x10000>; + clocks =3D <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPL= E_NO>; + clock-names =3D "core"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpi_tlmm 0 0 32>; + + i2s1-active-state { + clk-pins { + pins =3D "gpio8"; + function =3D "i2s1_clk"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins =3D "gpio9"; + function =3D "i2s1_ws"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + data-pins { + pins =3D "gpio10", "gpio11"; + function =3D "i2s1_data"; + drive-strength =3D <8>; + bias-disable; + }; + }; + }; --=20 2.34.1 From nobody Fri Sep 25 21:40:58 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABC5B3A544F; Tue, 8 Sep 2026 07:59:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on QCS615. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Signed-off-by: Karthik S --- arch/arm64/configs/defconfig | 1 + drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + .../pinctrl/qcom/pinctrl-qcs615-lpass-lpi.c | 185 ++++++++++++++++++ 4 files changed, 197 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-qcs615-lpass-lpi.c diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6ec8d3a69c98..80423678fe25 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -700,6 +700,7 @@ CONFIG_PINCTRL_IMX_SCMI=3Dy CONFIG_PINCTRL_IMX91=3Dy CONFIG_PINCTRL_QCOM_SPMI_PMIC=3Dy CONFIG_PINCTRL_LPASS_LPI=3Dm +CONFIG_PINCTRL_QCS615_LPASS_LPI=3Dm CONFIG_PINCTRL_MILOS_LPASS_LPI=3Dm CONFIG_PINCTRL_SC7280_LPASS_LPI=3Dm CONFIG_PINCTRL_SM6115_LPASS_LPI=3Dm diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 18db350222b9..9cef5fccae3f 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -62,6 +62,16 @@ config PINCTRL_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SoCs. =20 +config PINCTRL_QCS615_LPASS_LPI + tristate "Qualcomm Technologies Inc QCS615 LPASS LPI pin controller= driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc QCS615 + platform. + config PINCTRL_MILOS_LPASS_LPI tristate "Qualcomm Milos LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 43ecd246afe8..de2c9bdfbad2 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PINCTRL_MSM8998) +=3D pinctrl-msm8998.o obj-$(CONFIG_PINCTRL_QCM2290) +=3D pinctrl-qcm2290.o obj-$(CONFIG_PINCTRL_QCS404) +=3D pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCS615) +=3D pinctrl-qcs615.o +obj-$(CONFIG_PINCTRL_QCS615_LPASS_LPI) +=3D pinctrl-qcs615-lpass-lpi.o obj-$(CONFIG_PINCTRL_QCS8300) +=3D pinctrl-qcs8300.o obj-$(CONFIG_PINCTRL_QDF2XXX) +=3D pinctrl-qdf2xxx.o obj-$(CONFIG_PINCTRL_MDM9607) +=3D pinctrl-mdm9607.o diff --git a/drivers/pinctrl/qcom/pinctrl-qcs615-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-qcs615-lpass-lpi.c new file mode 100644 index 000000000000..78c8e7670c38 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qcs615-lpass-lpi.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * ALSA SoC platform-machine driver for QTi LPASS + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s1_data, + LPI_MUX_spkr_i2s_mclk_a, + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio8_pins[] =3D { 8 }; +static int gpio9_pins[] =3D { 9 }; +static int gpio10_pins[] =3D { 10 }; +static int gpio11_pins[] =3D { 11 }; +static int gpio19_pins[] =3D { 19 }; +static int gpio26_pins[] =3D { 26 }; +static int gpio27_pins[] =3D { 27 }; +static int gpio28_pins[] =3D { 28 }; +static int gpio29_pins[] =3D { 29 }; +static int gpio0_pins[] =3D { 0 }; +static int gpio1_pins[] =3D { 1 }; +static int gpio2_pins[] =3D { 2 }; +static int gpio3_pins[] =3D { 3 }; +static int gpio4_pins[] =3D { 4 }; +static int gpio5_pins[] =3D { 5 }; +static int gpio6_pins[] =3D { 6 }; +static int gpio7_pins[] =3D { 7 }; +static int gpio12_pins[] =3D { 12 }; +static int gpio13_pins[] =3D { 13 }; +static int gpio14_pins[] =3D { 14 }; +static int gpio15_pins[] =3D { 15 }; +static int gpio16_pins[] =3D { 16 }; +static int gpio17_pins[] =3D { 17 }; +static int gpio18_pins[] =3D { 18 }; +static int gpio20_pins[] =3D { 20 }; +static int gpio21_pins[] =3D { 21 }; +static int gpio22_pins[] =3D { 22 }; +static int gpio23_pins[] =3D { 23 }; +static int gpio24_pins[] =3D { 24 }; +static int gpio25_pins[] =3D { 25 }; +static int gpio30_pins[] =3D { 30 }; +static int gpio31_pins[] =3D { 31 }; + +static const struct pinctrl_pin_desc qcs615_lpi_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), +}; + +static const char * const i2s1_clk_groups[] =3D { "gpio8" }; +static const char * const i2s1_ws_groups[] =3D { "gpio9" }; +static const char * const i2s1_data_groups[] =3D { "gpio10", "gpio11" }; +static const char * const spkr_i2s_mclk_a_groups[] =3D { "gpio19" }; +static const char * const dmic1_clk_groups[] =3D { "gpio26" }; +static const char * const dmic1_data_groups[] =3D { "gpio27" }; +static const char * const dmic2_clk_groups[] =3D { "gpio28" }; +static const char * const dmic2_data_groups[] =3D { "gpio29" }; + +static const struct lpi_pingroup qcs615_groups[] =3D { + LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, _, _, i2s1_clk, _), + LPI_PINGROUP(9, LPI_NO_SLEW, _, _, i2s1_ws, _), + LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, i2s1_data), + LPI_PINGROUP(11, LPI_NO_SLEW, _, i2s1_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, spkr_i2s_mclk_a, _, _, _), + LPI_PINGROUP(20, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(21, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(23, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(24, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(25, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(26, LPI_NO_SLEW, dmic1_clk, _, _, _), + LPI_PINGROUP(27, LPI_NO_SLEW, dmic1_data, _, _, _), + LPI_PINGROUP(28, LPI_NO_SLEW, dmic2_clk, _, _, _), + LPI_PINGROUP(29, LPI_NO_SLEW, dmic2_data, _, _, _), + LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _), +}; + +static const struct lpi_function qcs615_functions[] =3D { + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(spkr_i2s_mclk_a), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), +}; + +static const struct lpi_pinctrl_variant_data qcs615_lpi_data =3D { + .pins =3D qcs615_lpi_pins, + .npins =3D ARRAY_SIZE(qcs615_lpi_pins), + .groups =3D qcs615_groups, + .ngroups =3D ARRAY_SIZE(qcs615_groups), + .functions =3D qcs615_functions, + .nfunctions =3D ARRAY_SIZE(qcs615_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,qcs615-lpass-lpi-pinctrl", + .data =3D &qcs615_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static struct platform_driver lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-qcs615-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI QCS615 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1