From nobody Fri Sep 25 22:18:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA594351C2E; Tue, 8 Sep 2026 04:19:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788841183; cv=none; b=R81TtI65B+toQoDeIlpZOav8Libq3yjm9uW7tRusNkbYMU7d+roe1gmKGgtiUD93CfTYUKSQfVuBP+J+ZV2+h9Uk+Ggj72/zDj1tYLJ3AVwK/k7u1q49NpPdo70jEKBMk9Aww3rE4OlAlLR2Xxy4JwCKc3Zt3Kw9VjQM/i9lXms= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788841183; c=relaxed/simple; bh=4EGpw+4NS2YtAY7YoxGWZBkJsbNtVsJZcX5YGO4nDa0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s2zVEYpFkpyhCenqX8qAuOQsNnSLuh8e/cpE8BkHxyv2miL/6rDJiywIJvh5e8pgy6l3LbYoPa0OLlApoka3OE8pFUqv+N0A3QWJ+yelQ++4loNzZsGYgNkUM5DakkdASaa7mSVP+dqcFyiqlcEd+ZAEd2EArwlY2Gkk8u/v8qw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zbr4OiRc; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zbr4OiRc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1CE341F00A3E; Tue, 8 Sep 2026 04:19:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788841181; bh=vKmo73A1z07iImrTwKZJE9KTVXf5sPh6dnxOhpUAZiQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Zbr4OiRclB4X6We7yyJ1uPWtwt+Yk9YMV6t0rd3uHCElqrnQnHJQLxwOZWDj/+T9L cb88V5y5Ch+LqGtX6jHfioaAkWSwjqSVMSuo06XcwzeSIwLHH5JBH/MC84Vp2MTzpK FAEadJ6KbL9u+f9MN/qSkbR366fymsS80OkjaNt5MLhNH6Kpaq2FnIFM5sMULh2hSv R7JR+EYTHXwKpfEN9HRDN0BsQXKQ4GmNx2fbMFDGSFElKC0greGK4J3JMbBI5M86Zl lGJVIWjpkvf5DX5kEwKnOgz5bd27tqoKMLZJcjlRkuttm2CSuVyYVhTUK6MZxmFEnM hE5Sx5R2AG6Mg== From: "Mario Limonciello (AMD)" To: K Prateek Nayak Cc: Perry Yuan , linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-pm@vger.kernel.org (open list:CPU FREQUENCY SCALING FRAMEWORK), Vishal Badole , Richard Gong , "Mario Limonciello (AMD)" Subject: [PATCH v2 1/3] cpufreq/amd-pstate: Add per SoC and per core type EPP tuning values Date: Mon, 7 Sep 2026 23:19:33 -0500 Message-ID: <20260908041935.402116-2-superm1@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260908041935.402116-1-superm1@kernel.org> References: <20260908041935.402116-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On newer SoCs the behavior of the platform has changed, and using the same EPP values for everything will yield worse results than expected. Add a x86_cpu_id match table that allows setting policies on a per-SoC/per-core type basis. If a SoC is missing, fallback to legacy values that are used. Changes also: - Change epp_values array and amd_pstate_cpu_epp_values() from unsigned int= to u8 - Add static_assert to ensure epp_values has rows for all CPU types - Fix show_energy_performance_preference() loop to exclude uninitialized EPP_INDEX_CUSTOM and EPP_INDEX_DYNAMIC slots - Add debug print statements - Remove amd_pstate_get_epp_from_platform_profile and inline the logic - Fix cleanup path in amd_pstate_set_dynamic_epp - Change show_energy_performance_preference to use for loop with preference= tracking - Add debug prints in amd_pstate_init_epp_values Behavioral change: show_energy_performance_preference() now returns a numer= ic EPP value via sysfs when the cached EPP does not match any named preference, instead of returning -EINVAL as before. This provides visibility into custom EPP values set by hardware or BIOS. No new platforms are added in this commit. Signed-off-by: Mario Limonciello (AMD) --- drivers/cpufreq/amd-pstate.c | 197 ++++++++++++++++++++++++++++------- 1 file changed, 160 insertions(+), 37 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9325c657d2d49..960db977cc8ca 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -55,10 +55,10 @@ #define AMD_PSTATE_TRANSITION_DELAY 1000 #define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600 =20 -#define AMD_CPPC_EPP_PERFORMANCE 0x00 -#define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80 -#define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF -#define AMD_CPPC_EPP_POWERSAVE 0xFF +#define AMD_CPPC_EPP_LEGACY_PERFORMANCE 0x00 +#define AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMANCE 0x80 +#define AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE 0xBF +#define AMD_CPPC_EPP_LEGACY_POWERSAVE 0xFF =20 static const char * const amd_pstate_mode_string[] =3D { [AMD_PSTATE_UNDEFINED] =3D "undefined", @@ -129,14 +129,102 @@ static const char * const energy_perf_strings[] =3D { }; static_assert(ARRAY_SIZE(energy_perf_strings) =3D=3D EPP_INDEX_MAX); =20 -static unsigned int epp_values[] =3D { - [EPP_INDEX_DEFAULT] =3D 0, - [EPP_INDEX_PERFORMANCE] =3D AMD_CPPC_EPP_PERFORMANCE, - [EPP_INDEX_BALANCE_PERFORMANCE] =3D AMD_CPPC_EPP_BALANCE_PERFORMANCE, - [EPP_INDEX_BALANCE_POWERSAVE] =3D AMD_CPPC_EPP_BALANCE_POWERSAVE, - [EPP_INDEX_POWERSAVE] =3D AMD_CPPC_EPP_POWERSAVE, +/* + * The numeric EPP value programmed for each named preference. First dimen= sion + * is CPU type (TOPO_CPU_TYPE_ANY for non-hybrid, TOPO_CPU_TYPE_PERFORMANC= E/ + * EFFICIENCY/LOW_POWER for hybrid). The initializer holds the legacy valu= es + * used as the fallback on any platform not listed in amd_pstate_epp_soc_i= ds[]; + * amd_pstate_init_epp_values() overwrites slots at boot when the running = SoC + * has a per-SoC (and potentially per-CPU-type) override. + */ +static u8 epp_values[][EPP_INDEX_MAX] =3D { + [TOPO_CPU_TYPE_ANY] =3D { + [EPP_INDEX_DEFAULT] =3D 0, + [EPP_INDEX_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_PERFORMANCE, + [EPP_INDEX_BALANCE_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMA= NCE, + [EPP_INDEX_BALANCE_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, + [EPP_INDEX_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_POWERSAVE, + }, + [TOPO_CPU_TYPE_PERFORMANCE] =3D { + [EPP_INDEX_DEFAULT] =3D 0, + [EPP_INDEX_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_PERFORMANCE, + [EPP_INDEX_BALANCE_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMA= NCE, + [EPP_INDEX_BALANCE_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, + [EPP_INDEX_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_POWERSAVE, + }, + [TOPO_CPU_TYPE_EFFICIENCY] =3D { + [EPP_INDEX_DEFAULT] =3D 0, + [EPP_INDEX_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_PERFORMANCE, + [EPP_INDEX_BALANCE_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMA= NCE, + [EPP_INDEX_BALANCE_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, + [EPP_INDEX_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_POWERSAVE, + }, + [TOPO_CPU_TYPE_LOW_POWER] =3D { + [EPP_INDEX_DEFAULT] =3D 0, + [EPP_INDEX_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_PERFORMANCE, + [EPP_INDEX_BALANCE_PERFORMANCE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMA= NCE, + [EPP_INDEX_BALANCE_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, + [EPP_INDEX_POWERSAVE] =3D AMD_CPPC_EPP_LEGACY_POWERSAVE, + }, +}; +static_assert(ARRAY_SIZE(epp_values) =3D=3D TOPO_CPU_TYPE_LOW_POWER + 1, + "epp_values must have entries for all CPU types up to TOPO_CPU_TYPE= _LOW_POWER"); + +/* + * Get the EPP value row for a given CPU, accounting for hybrid CPU types. + * Non-hybrid systems use TOPO_CPU_TYPE_ANY; hybrid systems use the CPU's + * actual type (PERFORMANCE/EFFICIENCY/LOW_POWER). + */ +static inline u8 *amd_pstate_cpu_epp_values(int cpu) +{ + enum x86_topology_cpu_type type =3D cpu_data(cpu).topo.cpu_type; + + if (type =3D=3D TOPO_CPU_TYPE_PERFORMANCE || + type =3D=3D TOPO_CPU_TYPE_EFFICIENCY || + type =3D=3D TOPO_CPU_TYPE_LOW_POWER) + return epp_values[type]; + + return epp_values[TOPO_CPU_TYPE_ANY]; +} + +/** + * struct amd_pstate_epp_values - EPP values for the four named preferences + * @performance: value for the "performance" preference + * @balance_performance: value for the "balance_performance" preference + * @balance_power: value for the "balance_power" preference + * @power: value for the "power" preference + */ +struct amd_pstate_epp_values { + u8 performance; + u8 balance_performance; + u8 balance_power; + u8 power; +}; + +/** + * struct amd_pstate_epp_soc - per-CPU-type EPP overrides for hybrid syste= ms + * @performance_core: values for TOPO_CPU_TYPE_PERFORMANCE cores + * @efficiency_core: values for TOPO_CPU_TYPE_EFFICIENCY cores + * @low_power_core: values for TOPO_CPU_TYPE_LOW_POWER cores + * + * Referenced from amd_pstate_epp_soc_ids[] to give a hybrid platform its = own + * numeric EPP values for the four named preferences, with distinct values= per + * CPU type. Non-hybrid systems are not listed in the table and always use= the + * legacy defaults. + */ +struct amd_pstate_epp_soc { + struct amd_pstate_epp_values performance_core; + struct amd_pstate_epp_values efficiency_core; + struct amd_pstate_epp_values low_power_core; +}; + +/* + * Per-CPU-type EPP overrides for hybrid systems. Only hybrid SoCs should = be + * listed here; non-hybrid systems always use the legacy defaults. + */ +static const struct x86_cpu_id amd_pstate_epp_soc_ids[] __initconst =3D { + {} }; -static_assert(ARRAY_SIZE(epp_values) =3D=3D EPP_INDEX_MAX - 2); =20 typedef int (*cppc_mode_transition_fn)(int); =20 @@ -1204,13 +1292,16 @@ static int amd_pstate_power_supply_notifier(struct = notifier_block *nb, static int amd_pstate_get_epp_from_platform_profile(struct cpufreq_policy = *policy, enum platform_profile_option profile) { + struct amd_cpudata *cpudata =3D policy->driver_data; + u8 *values =3D amd_pstate_cpu_epp_values(cpudata->cpu); + switch (profile) { case PLATFORM_PROFILE_PERFORMANCE: - return AMD_CPPC_EPP_PERFORMANCE; + return values[EPP_INDEX_PERFORMANCE]; case PLATFORM_PROFILE_BALANCED: return amd_pstate_get_balanced_epp(policy); case PLATFORM_PROFILE_LOW_POWER: - return AMD_CPPC_EPP_POWERSAVE; + return values[EPP_INDEX_POWERSAVE]; default: break; } @@ -1420,6 +1511,7 @@ ssize_t store_energy_performance_preference(struct cp= ufreq_policy *policy, const char *buf, size_t count) { struct amd_cpudata *cpudata =3D policy->driver_data; + u8 *values =3D amd_pstate_cpu_epp_values(policy->cpu); ssize_t ret; bool raw_epp =3D false; u8 epp; @@ -1454,12 +1546,13 @@ ssize_t store_energy_performance_preference(struct = cpufreq_policy *policy, } =20 if (ret) - epp =3D epp_values[ret]; + epp =3D values[ret]; else epp =3D cpudata->epp_default_dc; } =20 - if (epp > 0 && cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) { + if (epp > 0 && epp !=3D values[EPP_INDEX_PERFORMANCE] && + cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) { pr_debug("EPP cannot be set under performance policy\n"); return -EBUSY; } @@ -1484,34 +1577,31 @@ EXPORT_SYMBOL_FOR_PSTATE_UT(store_energy_performanc= e_preference); ssize_t show_energy_performance_preference(struct cpufreq_policy *policy, = char *buf) { struct amd_cpudata *cpudata =3D policy->driver_data; - u8 preference, epp; + u8 *values =3D amd_pstate_cpu_epp_values(policy->cpu); + u8 epp; + int i; =20 epp =3D FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cpudata->cppc_req_cached); =20 if (!cpudata->dynamic_epp && cpudata->raw_epp) return sysfs_emit(buf, "%u\n", epp); =20 - switch (epp) { - case AMD_CPPC_EPP_PERFORMANCE: - preference =3D EPP_INDEX_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_PERFORMANCE: - preference =3D EPP_INDEX_BALANCE_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_POWERSAVE: - preference =3D EPP_INDEX_BALANCE_POWERSAVE; - break; - case AMD_CPPC_EPP_POWERSAVE: - preference =3D EPP_INDEX_POWERSAVE; - break; - default: - return -EINVAL; - } + /* + * Map the cached EPP value back to a named preference. Skip the + * "default" slot (index 0) so an EPP of 0 reports as "performance". + * Stop at POWERSAVE; CUSTOM and DYNAMIC are not initialized in epp_value= s. + */ + for (i =3D EPP_INDEX_PERFORMANCE; i <=3D EPP_INDEX_POWERSAVE; i++) { + const char *name =3D energy_perf_strings[i]; =20 - if (cpudata->dynamic_epp) - return sysfs_emit(buf, "dynamic(profile:%s)\n", energy_perf_strings[pref= erence]); + if (epp =3D=3D values[i]) { + if (cpudata->dynamic_epp) + return sysfs_emit(buf, "dynamic(profile:%s)\n", name); + return sysfs_emit(buf, "%s\n", name); + } + } =20 - return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); + return sysfs_emit(buf, "%u\n", epp); } EXPORT_SYMBOL_FOR_PSTATE_UT(show_energy_performance_preference); =20 @@ -1953,9 +2043,11 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_po= licy *policy) cpudata->epp_default_ac =3D cpudata->epp_default_dc =3D default_epp; cpudata->current_profile =3D PLATFORM_PROFILE_PERFORMANCE; } else { + u8 *values =3D amd_pstate_cpu_epp_values(policy->cpu); + policy->policy =3D CPUFREQ_POLICY_POWERSAVE; - cpudata->epp_default_ac =3D AMD_CPPC_EPP_PERFORMANCE; - cpudata->epp_default_dc =3D AMD_CPPC_EPP_BALANCE_PERFORMANCE; + cpudata->epp_default_ac =3D values[EPP_INDEX_PERFORMANCE]; + cpudata->epp_default_dc =3D values[EPP_INDEX_BALANCE_PERFORMANCE]; cpudata->current_profile =3D PLATFORM_PROFILE_BALANCED; } =20 @@ -2254,6 +2346,34 @@ static bool amd_cppc_supported(void) return true; } =20 +/* + * Resolve the numeric EPP values for hybrid systems. Only hybrid SoCs are= listed + * in amd_pstate_epp_soc_ids[]; non-hybrid systems always use the legacy d= efaults. + */ +static inline void __init amd_pstate_set_epp_values(enum x86_topology_cpu_= type type, + const struct amd_pstate_epp_values *core) +{ + epp_values[type][EPP_INDEX_PERFORMANCE] =3D core->performance; + epp_values[type][EPP_INDEX_BALANCE_PERFORMANCE] =3D core->balance_perform= ance; + epp_values[type][EPP_INDEX_BALANCE_POWERSAVE] =3D core->balance_power; + epp_values[type][EPP_INDEX_POWERSAVE] =3D core->power; +} + +static void __init amd_pstate_init_epp_values(void) +{ + const struct x86_cpu_id *id =3D x86_match_cpu(amd_pstate_epp_soc_ids); + const struct amd_pstate_epp_soc *soc; + + if (!id || !id->driver_data) + return; + + soc =3D (const struct amd_pstate_epp_soc *)id->driver_data; + + amd_pstate_set_epp_values(TOPO_CPU_TYPE_PERFORMANCE, &soc->performance_co= re); + amd_pstate_set_epp_values(TOPO_CPU_TYPE_EFFICIENCY, &soc->efficiency_core= ); + amd_pstate_set_epp_values(TOPO_CPU_TYPE_LOW_POWER, &soc->low_power_core); +} + static int __init amd_pstate_init(void) { struct device *dev_root; @@ -2281,6 +2401,9 @@ static int __init amd_pstate_init(void) /* check if this machine need CPPC quirks */ dmi_check_system(amd_pstate_quirks_table); =20 + /* resolve per-SoC EPP values for the named preferences */ + amd_pstate_init_epp_values(); + /* * determine the driver mode from the command line or kernel config. * If no command line input is provided, cppc_state will be AMD_PSTATE_UND= EFINED. --=20 2.43.0 From nobody Fri Sep 25 22:18:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E80E2369D71; Tue, 8 Sep 2026 04:19:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788841184; cv=none; b=UstLaZpEniY3QmQtJt2cTsuUPegbEw4j6q04axZzHF4PgxQ3Ruw/px4GKDnVFl+qhRL0Td53xFDTVbsCCCTOHhjskRS+yl9Y1nLZIPyzi39EXH9E//41oZ351NY4c93vauSn0BnkcpVRJtTAwkcsTpVSZJRr893jD8Q6jIwpDwk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788841184; c=relaxed/simple; bh=IodXG4lHNRDM03mdwVFGayfNkzbEz7fNLzad88A3XGg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=glRFUEMG8Krro8MEaJ5ASmY00Inwo8Nqdggag++FriEBqbXJoaTpGRLZnxyQuLjVQzlhocRAYBthxBEENhtJvvCoAcNcRx8Dlde8aQBXi7ofLE9pxQ/DPhIwhaLP+aOdKBA03q9u/qk9Zg9okM/2iZB7VVFw+FbFRMJeyRQ6J7w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cLMbzuh3; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cLMbzuh3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 074271F00A3D; Tue, 8 Sep 2026 04:19:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788841182; bh=CdwxAckwRlfy05peFTwVSSHY/yansdRIEpEZXK5h+5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=cLMbzuh3ax2tGFl8t+DoX/UAY1uUc892wLn9uGauOkDeMtxuMXmouAOWQZoM02pNU LPXUiTZBnsWoyLadYMCawe4QV2l2VHsClXrIhtm7C/rsSpwGMQOeBw8gHiExMrJGMN Jphw61AQZSsQtKBYAkcVFLYTaUjtgbeAvkMffZKuzDu24mUARosgtMBvLl2Gus/+zd VeMMrzeIfocRn94qne0sBTNHoFTkpaBhaVKUfLIUThXWAWjvZOD6wZKv26/5kJ/mS2 l0TxpCq2eel/uKpigtZY5MulXbmbcxfM+L2E49idvQlsbdC6BhnchebQ5vLeYBqMYv zQtF8VAKYHXYg== From: "Mario Limonciello (AMD)" To: K Prateek Nayak Cc: Perry Yuan , linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-pm@vger.kernel.org (open list:CPU FREQUENCY SCALING FRAMEWORK), Vishal Badole , Richard Gong , "Mario Limonciello (AMD)" Subject: [PATCH v2 2/3] cpufreq/amd-pstate: Add EPP tunings for Zen6 client platforms Date: Mon, 7 Sep 2026 23:19:34 -0500 Message-ID: <20260908041935.402116-3-superm1@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260908041935.402116-1-superm1@kernel.org> References: <20260908041935.402116-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Zen6 client platforms perform better with individual tunings for different core types. Add initial EPP tuning values for those platforms. Signed-off-by: Mario Limonciello (AMD) --- drivers/cpufreq/amd-pstate.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 960db977cc8ca..543ec143efc94 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -222,7 +222,33 @@ struct amd_pstate_epp_soc { * Per-CPU-type EPP overrides for hybrid systems. Only hybrid SoCs should = be * listed here; non-hybrid systems always use the legacy defaults. */ +static const struct amd_pstate_epp_soc epp_soc_zen6_client __initconst =3D= { + .performance_core =3D { + .performance =3D 25, + .balance_performance =3D 51, + .balance_power =3D 64, + .power =3D 64, + }, + .efficiency_core =3D { + .performance =3D 25, + .balance_performance =3D 51, + .balance_power =3D 64, + .power =3D 115, + }, + .low_power_core =3D { + .performance =3D 25, + .balance_performance =3D 51, + .balance_power =3D 64, + .power =3D 115, + }, +}; + static const struct x86_cpu_id amd_pstate_epp_soc_ids[] __initconst =3D { + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x80, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x81, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x84, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x85, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0xe0, &epp_soc_zen6_client), {} }; =20 --=20 2.43.0 From nobody Fri Sep 25 22:18:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEE5C370AF3; Tue, 8 Sep 2026 04:19:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788841185; cv=none; b=MkH6a421pktS/ilM7csOZnfMcPuXLEbdyWyfhr6IWzGPBVasbIF9MmhXHmZSwUCVaGjIhMn/l8r9XbwYMoGwkvF51LYyO1G5gulICnuNDTjFds5k1Og8v8L+c26WhKznCzn4dN7StuedlmrX3tEDmKFV1Dqp0SAefJLkUni8NkI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788841185; c=relaxed/simple; bh=lpZzYy/VdGBhiRlw842ZMFFoGDx1XZvt95G9BzAIUK4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N7ojI41JhsEvygZ5FaU9C702pU8MbGk6prWTKripaM8jEvglBNxirlbp+DYAkb5hnsgmsRf8TEhZEUqyIBx+p4Zc2359ap6T9N3hph2bNCggJSE+DHHrUgGtn4FrZb4lWEnrzwoyGBrJgeZYoftzUW00O93N5rl9RlPOs/ML3hU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PDFzNtNm; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PDFzNtNm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E44731F00A3F; Tue, 8 Sep 2026 04:19:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788841183; bh=ltwDh5bKYcNkq1n5dZV/QwH3SJk32AnsNrJAoqNE1us=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=PDFzNtNmgPDRoa6yUo71gDD5jScfx7bF3JOKXf/irSVlcEq3BZHHeI0WPifA9Dg2k HG5qOo+UVTysLX/w1LrGny4UjvP0OOFDYgNTxB2+DHDl2q9eyc/YbLS3djsMl8LL3M 4KW/38AP7KMn+IKmHGTzwd+l8tlKjDYXl4SzKEmP320M0+qLF/3BZANC+2+oirKGLY +8o8p94vg/Ywz3i5GHFCOCoTrMD1BE+EX6d9O7iaOj9w2YF3Pguc0ytyIu5RfUx/FR 13unPSPoUGXbPE0VeTxFrani3khW0Qd9EI48v1X5j8NLeNYLu/9hvdUlQBx88w6bPh Mlm1UE5f9EBOA== From: "Mario Limonciello (AMD)" To: K Prateek Nayak Cc: Perry Yuan , linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-pm@vger.kernel.org (open list:CPU FREQUENCY SCALING FRAMEWORK), Vishal Badole , Richard Gong , "Mario Limonciello (AMD)" , Christian Ludloff Subject: [PATCH v2 3/3] cpufreq/amd-pstate: Show a warning if missing EPP tunings Date: Mon, 7 Sep 2026 23:19:35 -0500 Message-ID: <20260908041935.402116-4-superm1@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260908041935.402116-1-superm1@kernel.org> References: <20260908041935.402116-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" EPP tunings are going to be more important going forward. Show a warning if on a heterogenous platform without them. Suggested-by: Christian Ludloff Signed-off-by: Mario Limonciello (AMD) --- drivers/cpufreq/amd-pstate.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 543ec143efc94..7c1f8ca7b7f72 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -2390,8 +2390,12 @@ static void __init amd_pstate_init_epp_values(void) const struct x86_cpu_id *id =3D x86_match_cpu(amd_pstate_epp_soc_ids); const struct amd_pstate_epp_soc *soc; =20 - if (!id || !id->driver_data) + if (!id || !id->driver_data) { + if (cpu_feature_enabled(X86_FEATURE_ZEN6) && + cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) + pr_warn_once("No EPP tunings found for platform\n"); return; + } =20 soc =3D (const struct amd_pstate_epp_soc *)id->driver_data; =20 --=20 2.43.0