From nobody Fri Sep 25 20:48:39 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B33A556BB6; Tue, 8 Sep 2026 14:51:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879121; cv=none; b=RL8HfCNExwdygxtfhmUEiJwmP8ENqvBfek04fpPsw74GJqfKzxZ63ILAo/OEl17ADoDrmGg4Z3NU8ib0uzAWZ85QjtEhwB0pqlM2rNJtQX7PubDosqWzB1x08Z9hMm6FRlgKP9or1858W6EvzQB2d0FPc2p07R4HUItlKQJSpUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879121; c=relaxed/simple; bh=Fg34IEunqJ87tallgVaqmL3g1l7Lk3fv7w8kAzfIgiQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W2Rf53MmWQx9wKVsssbgTfWcRRaU0HZ86PouqBEG1eSODSToJdIuqBFRWPgX793G4LOV69cvVHFOUkjs6rZWQBcX1YT3A6QAy4SAGWrdjnoqcqIeCa5PtAP1Jw92ItkPG//cHDf6fWC8JlGxvt1/ovr74KRl15fZwfUd3UzqELg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=TbNDZZCk; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="TbNDZZCk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788879101; bh=Fg34IEunqJ87tallgVaqmL3g1l7Lk3fv7w8kAzfIgiQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TbNDZZCkh3+30wTwoHAFATA8ACNPU5c21RyKLa28Dmqn83mRr7ahXKFBIkHIzoV9Y XX+GJtDg28T26H66tGuYlK4VWBSYKHIfzPIitwGlFVlkfjwDR4VAq9KSQ5EhYGV4fz AP1GgYxwLMUBUkDMLIP8AMAWft6KPATxQHNzPSiDJAqz/ro+L3XZoBZFtSlVrHAvfQ CkvONTw4W+fvwE0ii/iHhMXGIcUX1gNIPU8AyG/YMye0Liige0huoQT0ooLrLQNTGK NBS6OBqAhI0PpukKElgCZCCfdaE8Qo1Tvzn8m8WnP3MQNFNsxE+1lk4YZc61m4JV0p 2o3fSxnOQbCUg== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id D83D817E0CA6; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 8E17C480029; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) From: Sebastian Reichel Date: Tue, 08 Sep 2026 16:51:19 +0200 Subject: [PATCH v6 01/10] PCI: dw-rockchip: Fix LTSSM set functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-rockchip-pcie-system-suspend-v6-1-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1781; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=Fg34IEunqJ87tallgVaqmL3g1l7Lk3fv7w8kAzfIgiQ=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqgIPwEwohiJhIRtREX/UPidd6YqPL8FjV5B /2sETgGRQv07IkCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqoCD8AAoJENju1/PI O/qadEkQAJq+v1y4/jvh+oo3YY3fY5I+eWTBo+SLQvRumeyeqQEPeRMCgyu/I8i42rprrdh3ciZ zNFR3QwfFJfxrqdhS65Mz2/u+xF+JzFUJjSiKsAmUvQ65yy2npvrnXbwkA3fPdFyRSS+OwsL5F8 NSG75CrMRJAvXprI3B8jNwSDgxAR31LpauxDUMwru9tQhwpKAOQlyz3/rCoIgKcaJY1OOlqY5Ej Pfkw/vVeZLZgl9iJzPusU+xRO0zD11RX2N/XAv2qfKz9aOtC3UbRDdn1PwroMRIKE4mJaSTamWK LPblA2NVdE3WA65rxFPZ+WgkOamc5KWgyz0HT5Njz4WpwmkUuKQw1ii4a7J7jMlbYE4c8Nl08Gd qE/epbdwETAb5o0O7+8+e5HPe6EVIsDiC7MCTyZ9h9GtxnSVSKxieTIEByI8TlDcTm+9H8g79qb cCo7iGYj0vt/VAJBaxP1CG67ZrQoQGS230mG27YKLWNG7QD7A5DyrPnPDS9/GoKkI7uqFvn9qrt utZqRGGoPTncdQF0lltIqyGe57JlzDZng4ZWcRCEB+T6YW8n0wKEUrrWq8gliMsgNVilTHOBwMU UMTV+FVW/qQmKrZxEiX6xj6SL8cz0cWrRGp6OUFxAMrbhwUvSUbEdforXcOnEa5Ub0ZxDEmg0JL JpYJr+o/gVyhmUzW+P3owcg== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Before the Rockchip PCIe driver has been switched over to the FIELD_PREP_WM16 macro, PCIE_CLIENT_ENABLE_LTSSM and PCIE_CLIENT_DISABLE_LTSSM were setting bits with a mask of 0xc =3D 0b1100, which means BIT 2 and BIT 3. After the conversion it only sets bit 2, with bit 3 being handled by a separate define named PCIE_CLIENT_LD_RQ_RST_GRT. Apparently the conversion missed to make use of this new macros resulting in the third bit not being set. Fixes: 30e919570581 ("PCI: dw-rockchip: Switch to FIELD_PREP_WM16 macro") Signed-off-by: Sebastian Reichel Reviewed-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index af26a07c0c9e..dc85564e5001 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -321,14 +321,16 @@ static void rockchip_pcie_ltssm_trace(struct rockchip= _pcie *rockchip, =20 static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, - PCIE_CLIENT_GENERAL_CON); + u32 val =3D PCIE_CLIENT_ENABLE_LTSSM | PCIE_CLIENT_LD_RQ_RST_GRT; + + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_GENERAL_CON); } =20 static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip) { - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM, - PCIE_CLIENT_GENERAL_CON); + u32 val =3D PCIE_CLIENT_DISABLE_LTSSM | PCIE_CLIENT_LD_RQ_RST_GRT; + + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_GENERAL_CON); } =20 static bool rockchip_pcie_link_up(struct dw_pcie *pci) --=20 2.53.0 From nobody Fri Sep 25 20:48:39 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51636556BAF; Tue, 8 Sep 2026 14:51:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879117; cv=none; b=Yh9sYyWwuP7kRLGZQm8NryLZ/x6sAEaSPe2etesBoIWEvgLnBpCkG0Uw1jw4q4iQq+tgpBcasrxCMOWx7vRETwc6nTJ6s3xoVxRaEWRW+pxIp5M5Nrj3sTZQFE9UqGUdkP5PvUSqTLDsNpnME5cEMUEnTbTswJttE88fp9T3Vmc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879117; c=relaxed/simple; bh=kZcRY1c6StE/iaMpmxijtqbRZWber+zT7CoQUOt7B+w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oHyvPtCk6a8+jFDM76POymOOYqj5xz24q8jawf04F+21huPhGAgcxlq5Zx6ZFyWDijOHCQQ5Jw6jLiN3lWx4VypuYsKWqItWAdNUhIaR6xKbbncVW60ydwL80OZ5PBdbaMJtbU+Owsu9YVcX2vJgUobLXvLlFxXw7+XVtMCAKV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=lWtInLD7; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="lWtInLD7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788879101; bh=kZcRY1c6StE/iaMpmxijtqbRZWber+zT7CoQUOt7B+w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lWtInLD7Mx+sw6LyHTAZmsnTe4uKElQZXMls+6J0T9WruF6eaGus3+dnYXWc6eZBw YnYb0b4CRdV29kNGnK3pbY0sm3ieN/8NSIqGb+NbHyztVV6x83uBp9t2F2T9aGX7fT +/5J/fqdTByNNWCAjWomgApGf3QbW0gd5ZT9IjTeXRAj0VyVwNpQ0MkNFOQ8o0beO7 Fv7HCXLScWgv9CcxfbGGYpwPkYa6e5xY/V30KDRKixKIbHk5fTuLS41lfHcGL9a3Wg 1SkrLaLDe/OA+Gok5MeDlND7c5LL6OEJ/tUMwWMp+scLnh2+hW0LLDqeBQtz+xkWce TGNeGUv3cSL7g== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id D973817E0D02; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 8EDE748002F; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) From: Sebastian Reichel Date: Tue, 08 Sep 2026 16:51:20 +0200 Subject: [PATCH v6 02/10] PCI: dw-rockchip: Restore vpcie3v3 regulator handle Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-rockchip-pcie-system-suspend-v6-2-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2369; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=kZcRY1c6StE/iaMpmxijtqbRZWber+zT7CoQUOt7B+w=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqgIPwdJHE0SdIZNod/yxUcsi9mnZYZi5vOp gV2BaUaH13o94kCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqoCD8AAoJENju1/PI O/qaUAoP/1jsU5fM8qWI7cJi8JJOag6aW+owxxRh1q9w3/2XzYTNsKsvXjczx9+1XqiiIs8HU9q aBIkUH+DpIDIUA9ZCyYqwGCDleUbeGVvD5G7whCWrur9sdDsu6j3dSiNqYyOux4Epzj50+xJHcM cfIXLCd++9+CQcBUqwBLj3qlPLxBxvOSHWwpO2QqBsw4r8/FWp84ab2Um4IRV60V2LsOW+ZLpRF ktqnFIH8rT2UxFbp+lyC2nmWizs67+5DM8lGBR8J1cweR5lMBWPNpn5zUWnZbKh3rJij+HnufTO EeTpQovIOJ2g6tL8UesKKbTb6Qj3RCvELjmAm01EPxvdExekuWgG8vYsbFLq5exEZvHk2ao/bcH MaRxV1UgeLWCpt0BEnwWHpuXHYoVIidT8qtqZoBz2sxWzymHIWsei3aePTD/bMy3YdRFfakA8Gv ga/12s+HXKn/QzC7PXD4xcv99GFp8oGzdP94mpjJ74cl6rBBxkbnEl8w4qFQLiyS7zKEKsb3aPk Nx6Ik80z3UpGB/jHWD0L5d+gXitvs2eiA+fz+w8DmEMJFIZoLGGMX9BCpZl0pNOCTRCZJt9TuMW 3zGcDEsnc9iwTn86j3EfvNe6b4xYYa0X89H/qRFHhWsKj8AWb4S9g51q1o0XI7+oOD/TZtRR6+d 0MS6gmMRfM/fZzfUjoNEtgg== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A This reverts commit c930b10f17c0 ("PCI: dw-rockchip: Simplify regulator setup with devm_regulator_get_enable_optional()"), which nicely cleaned up the code. The vpcie3v3 regulator handle is needed to disable the regulator during system suspend (to be added in its own patch). Signed-off-by: Sebastian Reichel Reviewed-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index dc85564e5001..f67ad3c31c35 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -112,6 +112,7 @@ struct rockchip_pcie { unsigned int clk_cnt; struct reset_control *rst; struct gpio_desc *rst_gpio; + struct regulator *vpcie3v3; struct irq_domain *irq_domain; const struct rockchip_pcie_of_data *data; bool supports_clkreq; @@ -844,15 +845,22 @@ static int rockchip_pcie_probe(struct platform_device= *pdev) return ret; =20 /* DON'T MOVE ME: must be enable before PHY init */ - ret =3D devm_regulator_get_enable_optional(dev, "vpcie3v3"); - if (ret < 0 && ret !=3D -ENODEV) - return dev_err_probe(dev, ret, - "failed to enable vpcie3v3 regulator\n"); + rockchip->vpcie3v3 =3D devm_regulator_get_optional(dev, "vpcie3v3"); + if (IS_ERR(rockchip->vpcie3v3)) { + if (PTR_ERR(rockchip->vpcie3v3) !=3D -ENODEV) + return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3), + "failed to get vpcie3v3 regulator\n"); + rockchip->vpcie3v3 =3D NULL; + } else { + ret =3D regulator_enable(rockchip->vpcie3v3); + if (ret) + return dev_err_probe(dev, ret, + "failed to enable vpcie3v3 regulator\n"); + } =20 ret =3D rockchip_pcie_phy_init(rockchip); if (ret) - return dev_err_probe(dev, ret, - "failed to initialize the phy\n"); + goto disable_regulator; =20 ret =3D reset_control_deassert(rockchip->rst); if (ret) @@ -885,6 +893,9 @@ static int rockchip_pcie_probe(struct platform_device *= pdev) clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); deinit_phy: rockchip_pcie_phy_deinit(rockchip); +disable_regulator: + if (rockchip->vpcie3v3) + regulator_disable(rockchip->vpcie3v3); =20 return ret; } --=20 2.53.0 From nobody Fri Sep 25 20:48:39 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 514A05540BD; Tue, 8 Sep 2026 14:51:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879131; cv=none; b=VgUw1z3J3kN1t9VTLV85MDdKAeeVNH3lpq7I7igiV0w+X88Eu177Zruq/gBHX0Zm9pCTaAOADeMRxIwbnS4+AHOgtFh4bL2gal65nBOv+B4Nm40EyF96AWfVwfKX/5a1EDOUeBWphnnuUn9K77rzPVQbWa5fuXJvPsjpYVX0lzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879131; c=relaxed/simple; bh=xW4LeQKGVm10NdrT7G+AboGl+alKfkI0kXweV+6EAlQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OhVK3NZbFHBLOeHe//R3npWPtx6j7fk4tuZB5dnE9XT6FY1zWHT/WfQy4ZHJVjh8mfmJRARTlWK5JnFOnbYhlJzUlNnYRVseeYc7wPy/n8Mu77/k4Vnu378skm5tTMaZ7SO+Ry6/PvgLXCmb5ZeM7GEBe0Fm3OT5wMw/L7IZzxs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=XITebiz8; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="XITebiz8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788879101; bh=xW4LeQKGVm10NdrT7G+AboGl+alKfkI0kXweV+6EAlQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=XITebiz8sCBUSB51TxPDsp0eAqYjh8o0CYhi99c5KRkA1gZ+A54Ne95vvVdqVM7o+ MJOcfCB3XiWBmC/x56pe1VcNIH4tG49URWKgGUIwdORBefwEkVBi1hWeWuuntXI7ga pZ4YMW3mmqsCaLarwrT0HSqyxB06HAsQ4deq9OB+B6tSH3UHf/+msIheY1AU62l0X8 stYlaXpQ18UVc/vV9hkle6U1w3EwM27oVG+WYUtAik6lLws1/gfawkiASGq8VjnQvO RA8deXfKmHK0U85Hex0HqMH2/bOBWs65hVSlE4RYivLTrJYmhTgz4xH4R9gjV2hfjp hG6FXk02M2Elg== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id D6EA817E0B0B; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 9098A480030; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) From: Sebastian Reichel Date: Tue, 08 Sep 2026 16:51:21 +0200 Subject: [PATCH v6 03/10] PCI: dw-rockchip: Move devm_phy_get out of phy_init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-rockchip-pcie-system-suspend-v6-3-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1528; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=xW4LeQKGVm10NdrT7G+AboGl+alKfkI0kXweV+6EAlQ=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqgIPzP5vtX1eOUuG/C0eZZ0K7IKtb+8xCK9 BCYcww5LZCknYkCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqoCD8AAoJENju1/PI O/qaByYQAIctAdoBWshDPlv0tQeySFix3D56ihdtVGD+K8r25coThtHVEUmXTrlgvkafyA0D3U3 3l9srdpmUfFX6cqhRt6PcO1Vo3ChZ4l7eEGdRLWkGbV5/+8ZmodUgF2djTIwK5Ey9JdA8XuLg1H OfGV9WX40kpGh79mOgrrdlFCAzD2advUyuCnOyH29Z4AoEGVAKs1gMiTKWSiHQhs3jbekiCdFsT g0x+iOpucKPQftMYpg/xYF3zS3F8P8srioK/mx/fGn2EEofBRZLQxERqhrLupd9+2E/eCpSLY0l qskFZswIzVa6/a+IccD7YACoBOGauvfCCdSYP/hsz4QY7A2yfoCl0wDmmMhgBC3/18Mn2hpsyWf dMye2K3J3jZ/bk5hiE9mTwtDEakh3iH9jVzwahrIzD8frGgVx7F4jrcranAg8NhsUwa5i9btwg6 jbOwmOq2ZnemLUeWOA3ZXagnGEOmygRCmA7ChP/ZDzGvDuSvJalb+LiULiLQlMYlgmZjo71Dukr JFrRIoyKBfeOy3tc9DyGa4/Y1S05nJO+MBl/I11EIWet0nGRnQA23wKbL76BLISHVCI39tIcp/p PfHhKLs2eBwAt8SLo/k1JmMdVX0QFTJjxvkOEpwXar5zKsGl1EKNjziZwR7csHcd/t7lpDP9QXO KCFB4N/PQXyBK0rY7Nl8pDg== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A By moving devm_phy_get() to the probe routine, rockchip_pcie_phy_init() can be used to re-initialize the PCIe PHY, which is for example needed after a system suspend/resume cycle. Signed-off-by: Sebastian Reichel Reviewed-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index f67ad3c31c35..7472ec78b473 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -612,14 +612,8 @@ static int rockchip_pcie_resource_get(struct platform_= device *pdev, =20 static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip) { - struct device *dev =3D rockchip->pci.dev; int ret; =20 - rockchip->phy =3D devm_phy_get(dev, "pcie-phy"); - if (IS_ERR(rockchip->phy)) - return dev_err_probe(dev, PTR_ERR(rockchip->phy), - "missing PHY\n"); - ret =3D phy_init(rockchip->phy); if (ret < 0) return ret; @@ -858,6 +852,13 @@ static int rockchip_pcie_probe(struct platform_device = *pdev) "failed to enable vpcie3v3 regulator\n"); } =20 + rockchip->phy =3D devm_phy_get(dev, "pcie-phy"); + if (IS_ERR(rockchip->phy)) { + ret =3D PTR_ERR(rockchip->phy); + dev_err_probe(dev, ret, "missing PHY\n"); + goto disable_regulator; + } + ret =3D rockchip_pcie_phy_init(rockchip); if (ret) goto disable_regulator; --=20 2.53.0 From nobody Fri Sep 25 20:48:39 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE552556BA9; Tue, 8 Sep 2026 14:51:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879118; cv=none; b=Uv4Nyx5/NVTyIs/I1ymtjs5HkUVxGL9FntoKHPzVbA/1FMQxw81m7UUNCYnMaZlGQd8qLlCm8nl99Qqfu87hBBGDspMvkf8sAqayvJbWfadJBt1NWy+lHc/RW3q0q2ayl4Mk+Xsd7qoAwaTCAuK5/DMJYWhS1Ch/3XCiLhxdIsw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879118; c=relaxed/simple; bh=/o+l1qIsF9Zr/xYqxxnlQCMTg653lSAB0Qv1ngIO08g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RXCtxoXriz2SesZrI/nVkZfiXLvpgMQha2AhDi/nUgrZIJ3H7TzTuw3TDtw4RfMt+TCNoIOw5w0EpX7lNuteme85NYA5UW4IO46W9bLbB1RDroEkIbQlUVBEo3haZcoBNqON3NqQMv3VQ+msEqdB4duMRe5n1Lk5Dpn+BanV4GQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=P2GCIKL1; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="P2GCIKL1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788879101; bh=/o+l1qIsF9Zr/xYqxxnlQCMTg653lSAB0Qv1ngIO08g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=P2GCIKL15/xCxvt7wOi42I7oiKGRF+hd++o5QvHbYSf1GChB6liobxvA2WNbaF7mq 2IHZ2CQQ4TeCOZGIVLhkYeqUc0xsVMmD9ft95zB0dxnZTiqlFHq/5R1QvflwtqsBus sNAQ3GTDQSRxGLWYCe3HorG6hzRSw11B7xdIr9Ozx+BrAbv7ItUxwtE26+bAy9tSmc kd7mNCkLJzyNaPhc4kdhWpfuqbG8lduBvzUWkrl9bZfMDw7a535MNSgDKu03FAdV9b bqClAkFEkMXiac9nz4z/NGJCqtUX1DUbtP6005gZROeUYGtPpGsNSNHPt2kURg2ss9 sL1XwydXArVig== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id DAA1717E0D0F; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 925E4480031; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) From: Sebastian Reichel Date: Tue, 08 Sep 2026 16:51:22 +0200 Subject: [PATCH v6 04/10] PCI: dw-rockchip: Add helper function for enhanced LTSSM control mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-rockchip-pcie-system-suspend-v6-4-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2254; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=/o+l1qIsF9Zr/xYqxxnlQCMTg653lSAB0Qv1ngIO08g=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqgIPzG8lmf1Uh1szusvt5lHxBgi9WY2KwuF JSLZyp8YwB67IkCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqoCD8AAoJENju1/PI O/qaiugP/irEE4CMxtrHvE+jLBRNAODaQtvniKHUCsg1Dui4RZeRWOrMkatpx0yQfd3m/lqzzLq VB/GiIvW2SjsEIws9Il5gVm7DrshhDi1zwNPtEaSeuN3i21wEF6nhWLrL1iMiMZGO4vWt6/zwJX Y4QWYZFnQK47VhAY7bXo0bt1HxWruTkMxFqQOgsh/lyYopXQmWr1oVeLzT+gMCJkMxB8rQrnNxz Ow/EuJpdK5TOVeG92Hj75E0bZQQ3WXGdSCXZBbExap5RLSAg9YAHdOWDoAzx0WrBpkMmyLYFdOq slS7sroO83knebfIwbQLKZEMhHKYQWhKwheooFKj2w6Nj8Ex0OKZ+0ZBNPvKEXqe5K5wRkf8rCE v/sG2REwrATwK4oE4V67p/mOpTDFd6sdfDOh30CagXS99K+RUK5PxiS1FLrfK4EIhm6kfs7ESW6 WB9WHuvUWNPwW9b6elpwZPWZIdPDsd0zpDVfXAcNoMojcrQL3BK17Xv+/ixMk7FbYFYdv8SVgCV nrmoUyVLXv0WgZDQB8Ko9gDq9CR/Gv0gkfj+OtW1pocTaE7FkJaLLyR4NJwPiPtbCnbAGPYOiAc 2oRTAEDGOK7LL+JCqjDnWTFFEurtLNiZTKz+F02QslDP2ws2UVBa3OWq7MMne3rH0EoKC5vzIrJ 3y5hzlaLECTR4PyU5KN8tqg== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Remove code duplication and improve readability by introducing a new function to setup the enhanced LTSSM mode. Signed-off-by: Sebastian Reichel Reviewed-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 7472ec78b473..6f84b07406d4 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -696,6 +696,18 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int= irq, void *arg) return IRQ_HANDLED; } =20 +static void rockchip_pcie_enable_enhanced_ltssm_control_mode(struct rockch= ip_pcie *rockchip, + u32 flags) +{ + u32 val; + + /* Enable the enhanced control mode of signal app_ltssm_enable */ + val =3D FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1); + if (flags) + val |=3D FIELD_PREP_WM16(flags, 1); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); +} + static int rockchip_pcie_configure_rc(struct platform_device *pdev, struct rockchip_pcie *rockchip) { @@ -719,9 +731,7 @@ static int rockchip_pcie_configure_rc(struct platform_d= evice *pdev, return ret; } =20 - /* LTSSM enable control mode */ - val =3D FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, 0); =20 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_RC), @@ -765,13 +775,7 @@ static int rockchip_pcie_configure_ep(struct platform_= device *pdev, return ret; } =20 - /* - * LTSSM enable control mode, and automatically delay link training on - * hot reset/link-down reset. - */ - val =3D FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1) | - FIELD_PREP_WM16(PCIE_LTSSM_APP_DLY2_EN, 1); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, PCIE_LTSSM_APP= _DLY2_EN); =20 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_EP), --=20 2.53.0 From nobody Fri Sep 25 20:48:39 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C792949C4C5; Tue, 8 Sep 2026 14:52:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879132; cv=none; b=VN12iywkwnatmipzAHk12Kzy/Gw1Eg0N8jIChUTlhyWeuPMKZGIO0SFcKrqeVMOL4LGM1YCvBelQmFkyGOlxz7y9LpxEAKEyFofM0dB5vCJ/ze2H1UtnlGq/Ty0JXmQE42fLDDJcCOqqH+twy6L+PJ2ma+nPAWJzhvQEeA8VM5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879132; c=relaxed/simple; bh=Z+Lzstt3geCgNqqc4sfbPOYtUjgypQ6xYnIT7nuZdGQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SLLNP2DiuwQg4GOzH1z33v7vKHgGRg8tDfNtEBDHfw668x3OCIeuNjMZxd0+lrp3qUulEWSoxbFwBEn7xUjO8jIzPdx/RssVAkW8ahZK/hN8TOqctVEdGHp+NT6BS5/W7IjCV2l0XH1U5nV1QaI6/pAsdqqfHuSfOFyn5aSDodA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=F+EPk/5B; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="F+EPk/5B" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788879101; bh=Z+Lzstt3geCgNqqc4sfbPOYtUjgypQ6xYnIT7nuZdGQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=F+EPk/5B2xyBMlHRVcf0uFe7s1um5d9n/42+dNT7XL7dkONh+jCNHIiXUgwjza0U2 YA8YAEipXhaNpbQQuCbecAN6BwE80DHQ75PtNmNy1zFoeVlUDz3JtfXSnI+jRnKy54 /qoKRtQ6hRdY1RD2j5qNRGWNpAeEuqKcVrc5QwDLLWDwrul9e7pPzMB6DRyXwxwr8f x/ggPVC1/urtHe+DZ1bVPFkxWPBdcq4Z+LrWRQI6RK0FAQTPuwZHUXf46GQDNttbIW pbOO5u7rPoJCBJzmRf2VHybHPD2MVICT/JwbJfzFajvd3SHmBl0B/FPFsWDtUOxVfI 5qq5942DtJZlg== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 32F7617E0D43; Tue, 08 Sep 2026 16:51:41 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 94010480035; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) From: Sebastian Reichel Date: Tue, 08 Sep 2026 16:51:23 +0200 Subject: [PATCH v6 05/10] PCI: dw-rockchip: Add helper function for controller mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-rockchip-pcie-system-suspend-v6-5-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1964; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=Z+Lzstt3geCgNqqc4sfbPOYtUjgypQ6xYnIT7nuZdGQ=; b=owJ4nAFsApP9kA0DAAoB2O7X88g7+poByyZiAGqgIPwgM3qXGwQtQCIgGMAprVKfcJl1XSgth pPm2ueEaZ34hIkCMgQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqoCD8AAoJENju1/PI O/qaDRYP9infvMVbVZC87GDb1FHBu40+qE6n9tyX2bNz/Vc1hd4eT+k6Lyah9Lc9rrRRcPOQLLP QZNDLTMXd4nesDB/ABjn1RVObkRca4RDC5UiLM3B+FdexIcm7zBbK7qxlWqqJ6CNZ7GRLP4ibGO wi65WzgfH0fjVOQNRgTNzrHOQ97NUNj6wCK9oywSGcbEdbGAF8gpiX1YwCA2az4C4dWFwA9orTn /1z5lwgmY6UTCpBW6PninQmgUMV7V3kwKPFCP5Q2tI5nxzbgs8PTBEyxgDdf1xyVHlyHDufGflD 7fa1/9xQc8QsJfDa2DzJ3vHRyC2CGnrUltTfkgasOr/q27yunslJkZq5M1wzDvEyXuoasIRNHrl VZslbeOyYbXuj2zvzcL34BuREz9Q6nf3+9xJGQENClBwc2HIUs0smAnf/Fvh5ylqRrkrle3vkOA aHfoOfv8evhvnZzAyJvoFu0l3HgMx/C53UqsXrKAMyrlY79zXm6e6zCIExruFTWCSiBueAZSCdb 810hrlr2wu9NaUphFvIML7AwJPYXOaJ1XGh+qppICAT/DZN5jFcvQy7lTTnw6hvaeFVPNbj93Wn Lp8rpWJufLmqOn2q0DyBLiMNe/pIMI1976gnSfQx8xGyuxlBk+0weE707IEBZpDakWcmjU38BpO 9UNLFf8LSCYTYsJdCWDjz X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Remove code duplication and improve readability by introducing a new function to setup the controller mode. Signed-off-by: Sebastian Reichel Reviewed-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 6f84b07406d4..211776bbcb99 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -708,6 +708,11 @@ static void rockchip_pcie_enable_enhanced_ltssm_contro= l_mode(struct rockchip_pci rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); } =20 +static void rockchip_pcie_set_controller_mode(struct rockchip_pcie *rockch= ip, u32 mode) +{ + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(mode), PCIE_CLIEN= T_GENERAL_CON); +} + static int rockchip_pcie_configure_rc(struct platform_device *pdev, struct rockchip_pcie *rockchip) { @@ -732,10 +737,7 @@ static int rockchip_pcie_configure_rc(struct platform_= device *pdev, } =20 rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, 0); - - rockchip_pcie_writel_apb(rockchip, - PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_RC), - PCIE_CLIENT_GENERAL_CON); + rockchip_pcie_set_controller_mode(rockchip, PCIE_CLIENT_MODE_RC); =20 pp =3D &rockchip->pci.pp; pp->ops =3D &rockchip_pcie_host_ops; @@ -776,10 +778,7 @@ static int rockchip_pcie_configure_ep(struct platform_= device *pdev, } =20 rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, PCIE_LTSSM_APP= _DLY2_EN); - - rockchip_pcie_writel_apb(rockchip, - PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_EP), - PCIE_CLIENT_GENERAL_CON); + rockchip_pcie_set_controller_mode(rockchip, PCIE_CLIENT_MODE_EP); =20 rockchip->pci.ep.ops =3D &rockchip_pcie_ep_ops; rockchip->pci.ep.page_size =3D SZ_64K; --=20 2.53.0 From nobody Fri Sep 25 20:48:39 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7EB9554083; Tue, 8 Sep 2026 14:52:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879134; cv=none; b=pTmi9KrHkE56D8PjOMIGLDZtkity89y0IZSh95D1zbY5Gr63nrm2d5ZNQaVxNkIcZQ74biIxEDwp78ge/45A3eHYBS00QZJFQuOrGcU7IevbIqJ3JiKU2XbQe7fjJ1JbJYuomWkOR7RTokksZYfQGuXE7YfOWG9OFjo7ECjdZbE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879134; c=relaxed/simple; bh=pQ075WLFf2brXAVxwHCIqRV7MiZ2UQ9bz57J6cuXjls=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fo3MhqUyd0zPsDK7poM6ZQuYmrpFxesdZ3pi+Ih+jENAWcIX6v+K1372FmqUJGCz/bMWsZAStsJTcwaM+g/cTxWwOBWLqVSzv2VY8hy/MRUXx2ghPt2AinczPPDBDGoGl7X1ze7KqPn8tAn/xJyS6p9me4okz1t4qQmQ0/V2/B8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Tlr2ZA8x; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Tlr2ZA8x" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788879101; bh=pQ075WLFf2brXAVxwHCIqRV7MiZ2UQ9bz57J6cuXjls=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Tlr2ZA8xG8wupPbHFg9adiM37IzUpaw5DIVzYbhDijv9DA17+mrqZFRk65xYfRwiR 8a0CRf1mx3QWt1+636B/HbF0n9eXQUQBE4jNvB3EBL3AVrOvTz+uCxM2mWjcdefVvL u0zGkbOPIlU6dRNLpONP4FMOD0QHhxq4RmOYobKVV1Nz4Tv4it8soBwKhwd0t6Y10m 8Ty+TkI+AIkKsfsdLD37uucyxpSiN7hwLYfWpTZ9OzXEKtF64l3Ltzp6dFk1LW+Nms 5yLvLBOtESuEsTRQFdrkamDPibFzYFDvceuUYurdPAkcarG9jhxI4YIkdEQESEH+nq 33sfrsABq5cLA== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 35DD017E0D7F; Tue, 08 Sep 2026 16:51:41 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 95DE1480038; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) From: Sebastian Reichel Date: Tue, 08 Sep 2026 16:51:24 +0200 Subject: [PATCH v6 06/10] PCI: dw-rockchip: Add helper function for DDL indicator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-rockchip-pcie-system-suspend-v6-6-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1947; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=pQ075WLFf2brXAVxwHCIqRV7MiZ2UQ9bz57J6cuXjls=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqgIPxanYSFeNaTKI80U9Qk5pMvLkD/tATIm bJl2oJDZLST14kCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqoCD8AAoJENju1/PI O/qaIeQP/2bqoeDyDW7+kPK44HOhBltY6S7QNU3cZa+i6Q8PIxcsQXUjVfb8OoBsWSKB8YvIrqJ x2GzmmRTwNlvzcdaq3wZ6a9za/lmATJoLnM4gv+yC5Wfnq6+qcu2kDMrtLx/D3+Wih7WGF5cTyS jOAg4gzcf3HYU03/cpcp/xJsmdW+h3DPCrkp7Imf+6aOC6R1j+0PU3zC8IoJi0CdNC7SsIxncuZ seMM/55ddl9jWkM7TYyZGqjwYiKxP2QnAfLPhSXjAUHChHgGcOfZlSH4M/Odd81zwpTEiXNLhyt GsxLUxsgrV/SUSSqruNMuDhGdbOP6OTY2LIVHn4YSY24I7HKWZCFNofs5t9X7E6T8ntbMQkjfWx KO6sMZUfzbGdqKvlutq2Yv6Z78iTRLGvNZKdC9F0AVsRtadNIfOiV1N2WMqYHHXpYM96/icyLtj Shj0rNBUBWF9K+1SSFvGvzhcBEuFPghLKLE9VzxbZrURkfizsPdyLR9kqQDEbpZertOyAev1M85 9maIGOXdasRs/KO18Lr2C6uP3q8fJSO3NRqjOFoMihM2+BTq6gKOnBejTEUx4dooDlTrghWq9GB FH2ZrblBWvvtF5HMubmv0DEvRxDAfs9ROGVY2RxT8FvVgt4xH20w9M6tA1vy70BRjhIKxPnkpxN TQYkvtHyh9gunyGptVQo3mw== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Remove code duplication and improve readability by introducing a new function to setup the DLL indicator. Signed-off-by: Sebastian Reichel Reviewed-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 211776bbcb99..1e48099e36e4 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -713,6 +713,16 @@ static void rockchip_pcie_set_controller_mode(struct r= ockchip_pcie *rockchip, u3 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(mode), PCIE_CLIEN= T_GENERAL_CON); } =20 +static void rockchip_pcie_unmask_dll_indicator(struct rockchip_pcie *rockc= hip) +{ + u32 val; + + /* unmask DLL up/down indicator and hot reset/link-down reset */ + val =3D FIELD_PREP_WM16(PCIE_RDLH_LINK_UP_CHGED, 0) | + FIELD_PREP_WM16(PCIE_LINK_REQ_RST_NOT_INT, 0); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC); +} + static int rockchip_pcie_configure_rc(struct platform_device *pdev, struct rockchip_pcie *rockchip) { @@ -760,7 +770,6 @@ static int rockchip_pcie_configure_ep(struct platform_d= evice *pdev, { struct device *dev =3D &pdev->dev; int irq, ret; - u32 val; =20 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP)) return -ENODEV; @@ -800,10 +809,7 @@ static int rockchip_pcie_configure_ep(struct platform_= device *pdev, =20 pci_epc_init_notify(rockchip->pci.ep.epc); =20 - /* unmask DLL up/down indicator and hot reset/link-down reset */ - val =3D FIELD_PREP_WM16(PCIE_RDLH_LINK_UP_CHGED, 0) | - FIELD_PREP_WM16(PCIE_LINK_REQ_RST_NOT_INT, 0); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC); + rockchip_pcie_unmask_dll_indicator(rockchip); =20 return ret; } --=20 2.53.0 From nobody Fri Sep 25 20:48:39 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6FAD5519A4; Tue, 8 Sep 2026 14:52:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879130; cv=none; b=ndtSfQH17oQmfIJNkyA1k6oCGnUkJP45DttfeozrjU42nRVtL9DxiKtpJU8NfO26uVFMjAOhNGdAOpGp7J2QVY5jNDXf1H7r/BGj+CGqfW+iD1Hl6uON9YcWFsYmVJpaMlXumdM3DXAAWVRajpHZvDyX1hNP6QKe6kj8lOoINl0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879130; c=relaxed/simple; bh=L4M7hLiRxDRX1JjACPykw3mztl3t/GK4QMLCwWFrxIo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uMGReHmp2SEm0IzBirOYecUd0/+vYI5ANyT0rYDGBRFOORDM/m41DErJTagP2NUntkDXpvOSIdJaTC5LUHdNJ8rv4oQFq/7V9FOJaM7K5q5kMlaw1zwJSrww9/wHpQciN7a60kY/T4oum/7yr1TtTmZGA5nEeMkDlCQg10cw0Jo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=kW0ee1qC; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="kW0ee1qC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788879101; bh=L4M7hLiRxDRX1JjACPykw3mztl3t/GK4QMLCwWFrxIo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kW0ee1qC0mWQjAr1zWej6iBHaL/pedHxs0MoPFbMbpp7UHet1M/me8w/7ikqnvwio OfFPrVq+Eb7Bce+wUGuP6RlreC5vX7HV/Hxazj4uin98eiYsZelg+EAGSdSMGG19kv MCEBdfZmGusea7/XGt7YQKccST+LYlBcWfbPOmJG1fuGvih8yf10Bll8Wd4hxEuHWG 8P6AfXMxKDZ5LD5xymYcGdszsoMH0CU7gNdH+S1L5LVVWJjQ75CmAFxK5gacYkJoTz wL+gOEHyuDaS+42xwy77K5QK2UoOCz/3BsE7N1pi1nmbTp2Nhh3Lo4yr8F5ZD1SeIr PN9XAbud11iyw== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3C67E17E0D81; Tue, 08 Sep 2026 16:51:41 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 979CA48003A; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) From: Sebastian Reichel Date: Tue, 08 Sep 2026 16:51:25 +0200 Subject: [PATCH v6 07/10] PCI: dw-rockchip: Add pme_turn_off support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-rockchip-pcie-system-suspend-v6-7-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3022; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=L4M7hLiRxDRX1JjACPykw3mztl3t/GK4QMLCwWFrxIo=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqgIPwONPLCUoy4DvvoogqBm9II90BbJz5ht eejLik2EOCWKYkCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqoCD8AAoJENju1/PI O/qaGZQP+gOurxzOFdXPQH/FppuFVPfAZBUWPfQAUq/RHhR7nlu/RavTNBh/+wmJnox+7OcVRm4 IpCPBVCl6o0sXgL5myrdgqw8EyUIwyvcX9PSAQ0tBM+F2bdW9FOB4tDwtwI+kt/4w7j97QZdWlB O6Nf6na/zPD4q4V93PqLTQC07pczGYcXRo08398LQU8kTFETitEm/X3KTLl2mZSbAMsZAjKTyvA ZaTVaL/KBXEWLlsbC9UzhCPquLIjvhO/epJCiUc3LPNOJN1g6PFBz5llnyEIn+g+u9+j1hiLjXx JSV92CfOxYxiODNfSY3ZqTiPBgTwVj6BV/jlwkEXzJ+Spxi1yFnLcXi8RNfvNzYhuOaqxbsZwLI FiB9366KJiii4d4KNdP25wgnWhRt7ZRJAVME3Tt1RMzXSq462vWVb8c/yM4rhTITMc3abgYfjfi I6834iZKidFeqelUf3Z/LeYEbnzNWtM4FcJyxC8ShTvSyso+VgJir8+SHfdk5QJvhSocyNzt0RX AiewwJfk7FyPrGdkr13fNqRcfldOTP9TddhpnZ9aUrpCvqWVNqaOzwvH+zNtz4Ekfld7t2XtZLP LLRUrKEl91b2pqck+Xdh8R0W8SCTb68aGa4CwgjyqrHQQ6Qjf34PZ2kF2jGwuUpN9r7ZYKFjqlE WZCE/bMJ/ugNr3eB9PV4zcg== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Prepare Rockchip PCIe controller for system suspend support by adding the PME turn off operation. Signed-off-by: Sebastian Reichel Reviewed-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 44 +++++++++++++++++++++++= ++++ 1 file changed, 44 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 1e48099e36e4..17530507e41b 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -45,6 +45,7 @@ #define PCIE_CLIENT_LD_RQ_RST_GRT FIELD_PREP_WM16(BIT(3), 1) #define PCIE_CLIENT_ENABLE_LTSSM FIELD_PREP_WM16(BIT(2), 1) #define PCIE_CLIENT_DISABLE_LTSSM FIELD_PREP_WM16(BIT(2), 0) +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 =20 /* Interrupt Status Register Related to Legacy Interrupt */ #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 @@ -64,6 +65,11 @@ =20 /* Interrupt Mask Register Related to Miscellaneous Operation */ #define PCIE_CLIENT_INTR_MASK_MISC 0x24 +#define PCIE_CLIENT_POWER 0x2c +#define PCIE_CLIENT_MSG_GEN 0x34 +#define PME_READY_ENTER_L23 BIT(3) +#define PME_TURN_OFF FIELD_PREP_WM16(BIT(4), 1) +#define PME_TO_ACK FIELD_PREP_WM16(BIT(9), 1) =20 /* Power Management Control Register */ #define PCIE_CLIENT_POWER_CON 0x2c @@ -452,8 +458,46 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *= pp) return 0; } =20 +static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); + struct device *dev =3D rockchip->pci.dev; + u32 status; + int ret; + + /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */ + rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN); + ret =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN, + status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10, + PCIE_PME_TO_L2_TIMEOUT_US); + if (ret) { + dev_warn(dev, "Failed to send PME_Turn_Off\n"); + return; + } + + /* 2. Wait for PME_TO_Ack, bit 9 will be set once received */ + ret =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_INTR_STATUS_M= SG_RX, + status, status & BIT(9), PCIE_PME_TO_L2_TIMEOUT_US / 10, + PCIE_PME_TO_L2_TIMEOUT_US); + if (ret) { + dev_warn(dev, "Failed to receive PME_TO_Ack\n"); + return; + } + + /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */ + rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATUS_MS= G_RX); + ret =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER, + status, status & PME_READY_ENTER_L23, + PCIE_PME_TO_L2_TIMEOUT_US / 10, + PCIE_PME_TO_L2_TIMEOUT_US); + if (ret) + dev_err(dev, "Failed to get ready to enter L23 message\n"); +} + static const struct dw_pcie_host_ops rockchip_pcie_host_ops =3D { .init =3D rockchip_pcie_host_init, + .pme_turn_off =3D rockchip_pcie_pme_turn_off, }; =20 /* --=20 2.53.0 From nobody Fri Sep 25 20:48:39 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3A9754A7C9; Tue, 8 Sep 2026 14:52:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879137; cv=none; b=IAoWkZiDeaEAA11yQ4iHpd1dAfS9AeXmoTzvBUuRILLKH6ByrrRO0gOXsVcCi5S0M9o6N4mts+pIYAr/mLjxXBN1iWYiNOHbeIt+YSxdSRiZPT18e8+mG2+2LDYkMMIkBxJH2dfDLVvl8v98gxknE4PK516VwSeDUx3G9XxG6w4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879137; c=relaxed/simple; bh=ZfxhLkyDar7QOwr+Kdk2fm5x7d8U5zVs/P2O97TfAjw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SFLWoK/bgE4DfO3Desq/Q6KyUdxhtzprbSzxw+Cj92tjRbEi2PzVaOe7n9MAqYkeeuhaLu1qy76kz12c7+NQyS8IagX4OmMsOcu3bO+FbvOuruXOjtC/Tfdb4BdAVa6VIXma46I0WWNl4o+8+XVQ0k7VT+VFcOMRNN8Jrc08XkE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=I8lYyIa0; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="I8lYyIa0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788879101; bh=ZfxhLkyDar7QOwr+Kdk2fm5x7d8U5zVs/P2O97TfAjw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=I8lYyIa0jegdk6hb0a5KgEp36jQFVuep5w5QMNSwxJSwbbvei3voypD/SjpgVV+PQ FekQYpH+Nb2V0PUaYtfiKJL5uUbr5ZxEFI2yPogmJQ/+ybmyhZgttpRBF65Mtq+JDl 1IQIYwO5yvqjeuudSOFROf93L6sQGo70nSSUHUl+frTsZ20741C2lln9Whfuf5Dv5r dSaVkLevPHWJQFlV8oeEN9x0TDsdmnkq1G8W4icmNBRq2gsiSYXiCU3imNjn9lDffd 8C6liZz8vnix6mm5Nuj4R7qt47IuuYOPyDe+LFK8f6QFYpmqPcqXB3VM97m4MxtUyf xekszrCj8uPfA== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3D84D17E0EB0; Tue, 08 Sep 2026 16:51:41 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 9949E48003D; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) From: Sebastian Reichel Date: Tue, 08 Sep 2026 16:51:26 +0200 Subject: [PATCH v6 08/10] PCI: dw-rockchip: Set broken L1SS resume flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-rockchip-pcie-system-suspend-v6-8-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1793; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=ZfxhLkyDar7QOwr+Kdk2fm5x7d8U5zVs/P2O97TfAjw=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqgIPxJGUR4srONtxKLTKD8iRMLzHqyacXSU urMkN+gYiF/WIkCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqoCD8AAoJENju1/PI O/qa4bQP/RAVyzs6Q5cmYt9KdhW4mRITRHknDz3whcxrHmHfBVHR8lxrZjeVOY8kKCeKoKdCBlP Q8+d+B9u8hBwrsaUfYbUzR64z3LvmYtzFkaGCWXEjS2RSIK3xHtkaOP2dsZLzgzkU7ETC7etRmN KdV6I/rtKWN3wCLRWHs8HZvn9FoXv6as4FKnqBKiMIhNjWJY5fBKKrFoPrSxJMlUIkwYU6/skbJ lnFBE5aJt7IO0YXXfI7yJox46FidoKltTKj8rxURAeDkVORKcxzVMTOpLiBIytq5SykfP44Ax2o 61se21x8mhC0PQ2owE3FcF44GUDxyLqK//1Bgv9VNiNJ00Agz2TNWH/RtQwsP+VflY/ypb+kJ1L nki861JQYSP0sTvTmIu5yc8DvI7xJXGfOxmkaKC16+Gq1LHQhMnH95OgrHXOa++KTKxLgn7ySuV nXSPPqLkKEgX7lbuiacIfQkaAvEEsgDL5OmRzipsB9XmGUsIMp0gaa25zqdgRMa/NQQviC3V5G+ v1nreo7Tt+na2cI3goYJGb9uGCKiqnOhlSxjYW0llTJeqegXj7J3yzLPo9BV2DYA8IW6bjALz4E cDhgCbUUD42jX0GaYCRvdcICEEpmiL/OYtc8mo34hXWdYI/AchN+++U1xKsOve9grVeUVS9XmyR /teDWU0A0DDvas9bAQSArTQ== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Setup the broken_l1ss_resume flag, so that pci_suspend_retains_context() returns false on the Rockchip platform allowing PCIe peripheral device drivers to act upon. Signed-off-by: Sebastian Reichel Reviewed-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 17530507e41b..47d9cab909bc 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -458,6 +458,21 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *= pp) return 0; } =20 +static void rockchip_pcie_host_post_init(struct dw_pcie_rp *pp) +{ + /* + * During system suspend, the Rockchip RC driver effectively powers off + * the controller. If the link is in L1SS and the endpoint asserts + * CLKREQ# to exit L1SS, the time required to wake the system and + * restore the PHY/REFCLK may exceed the L1SS exit timing + * (L10_REFCLK_ON + T_COMMONMODE), resulting in Link Down (LDn) and a + * reset of the endpoint. Set this flag to indicate this limitation to + * client drivers so that they can avoid relying on device state being + * preserved during system suspend. + */ + pp->bridge->broken_l1ss_resume =3D true; +} + static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -497,6 +512,7 @@ static void rockchip_pcie_pme_turn_off(struct dw_pcie_r= p *pp) =20 static const struct dw_pcie_host_ops rockchip_pcie_host_ops =3D { .init =3D rockchip_pcie_host_init, + .post_init =3D rockchip_pcie_host_post_init, .pme_turn_off =3D rockchip_pcie_pme_turn_off, }; =20 --=20 2.53.0 From nobody Fri Sep 25 20:48:39 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C813D55408F; Tue, 8 Sep 2026 14:52:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879129; cv=none; b=RInXnZIxuxel1ZXHEliCaXAKayNFFLPcPyMQr56kCseZZ6sRrZ88iHgHvfe5Y14f/xhC4gh5H9M6bMS0K8ED9JvO8+0iMnN200aost8l2KkN7XX/n8kyIrqF8XABmNReaPLdlDvMULJHNoqNbTIap8EKz/GcFtAHOtxNjOjJd+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879129; c=relaxed/simple; bh=hZ3jR5I88dlqu7N8y9bM7MOwuCfID3HH/p/t8qYgLU4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Gjl8AyF7Yt35yWnMxmJaQ40Avmgtmso7/o7U5O73s3ejxlVk23IXI/81yYFErQo4x55TepG63Zo+IfZqLgQOHtt0kCbltiPccyaT1FraoMDyz3o1vmrp9HCBJP7lOC8ngQISBJrtMIzYKE4wonC94N+E1Gkh3UOd5xQpBM34J5s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=COunSn9f; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="COunSn9f" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788879101; bh=hZ3jR5I88dlqu7N8y9bM7MOwuCfID3HH/p/t8qYgLU4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=COunSn9fYuWjZyAvncm1dACaKDp5N5NfEMlz0PzD5u5Db0iHM4fv2M6/Wsgg3dDPD QHAyn3Ve0GaDZ/qGQLV3cKXeNGWJ7gTyhZSKdC2xXUbcQMtWeH3KnEjMUcknZkEEm8 r4hYF8ay8Luvr8MPFfCbuL9NpzuMKyt2iszGXHckgzFCQYNO27sHr9wG8JS9u91bvV rBkclSee4P9nNS/ayf7i/2AJb9Qso8AmqQn9hho+D2zDC2cEFssnleyUVsEvaKecZz Lw7fczOlZVP0ZlwnN+2yWQ/8r82qxPXavIiZbM7QqJ8dNHiWNqZgKreZFo7/tpApQ6 cUGRKfjlMJW0w== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 464E617E0FAA; Tue, 08 Sep 2026 16:51:41 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 9B1B6480047; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) From: Sebastian Reichel Date: Tue, 08 Sep 2026 16:51:27 +0200 Subject: [PATCH v6 09/10] PCI: dw-rockchip: Add system PM support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-rockchip-pcie-system-suspend-v6-9-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4775; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=hZ3jR5I88dlqu7N8y9bM7MOwuCfID3HH/p/t8qYgLU4=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqgIPzrY9okFDFC/XHI6kbGOodCmMLlVc9ZD kwcO93H8rHbdokCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqoCD8AAoJENju1/PI O/qa7kUP/R+bktuSwgozZ6MMNHsqOW9CmySZghLnw/8aghGzt4j5grq1NPITrkmRUL7c/o4jkpA 6WzHmdp1cnr6bBx9k7+KUgklP9RAkAdfR9hjr912JdXayVl0xUmAd5q33HUBBSJBEbQkETOhvU8 44njXZ5I8xVUHkmDWyL+KPSkehYRXF/Dg60qnF+mPcnfVleJmbirpppjLYAvzd5f1HqS3qDbS+r 3UJ4v2qo13u0A7tMQVBhZeciyHoe/FgIB3est859jmAd2elNx/t/3avWW2ShgiD+NcopWC/sEv+ FxIoDYh9DSnGyEji6PoQV3borYp0N64FjBa2Cb45S3A9zFyO/2FJjKtUTr/hhdL1/D8ZETS5fpT v1aMv1Oy9ZPfyVH6scitkjmZmNSKM2GWAUI7jsK6yn5FTmff+9CebntIki+P+GBWeHaVViIDXd0 5qz9NgFtaOATGnoufTpKU9+e8JcpI2fbQg0MItxXMYrI7SfvjklXbabOWkQWb1vPc2gwZd08hjk PC5XjONQjoMps9rTQWfoUg0V6DHVuDvb9mFv3pdl3l0S4NsPm07m9FZqP4D1jYZWOKgiBSM5juX HpFe3mMkPQdRswLAvIxSXNWsOACVOPj2QNCDp3jRG3LYQwQVHiL+jkkIYziy8qmnIvJ8cF0f2aS pz4C4vBsjDT3U1I4Nys425g== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Add system PM support for Rockchip PCIe Designware Controllers. I've tested this on the Rockchip RK3576 EVB1, the Radxa ROCK 4D and the ArmSom Sige5 boards. While I haven't experienced any issues, most of my tests have been done without any devices attached (i.e. default board without any extras), so there _might_ still be some problems. As system suspend does not work at all right now, I think it makes sense to get at least the basic configurations working as soon as possible as it will allow us to catch regressions by enabling system suspend in CI systems like KernelCI. Co-developed-by: Shawn Lin Signed-off-by: Shawn Lin Signed-off-by: Sebastian Reichel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 100 ++++++++++++++++++++++= ++++ 1 file changed, 100 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 47d9cab909bc..e675918ba184 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -120,6 +120,7 @@ struct rockchip_pcie { struct gpio_desc *rst_gpio; struct regulator *vpcie3v3; struct irq_domain *irq_domain; + u32 intx; const struct rockchip_pcie_of_data *data; bool supports_clkreq; struct delayed_work trace_work; @@ -1042,6 +1043,99 @@ static int rockchip_pcie_rc_reset_root_port(struct p= ci_host_bridge *bridge, return ret; } =20 +static int rockchip_pcie_suspend(struct device *dev) +{ + struct rockchip_pcie *rockchip =3D dev_get_drvdata(dev); + struct dw_pcie *pci =3D &rockchip->pci; + int ret; + + if (rockchip->data->mode =3D=3D DW_PCIE_EP_TYPE) { + dev_err(dev, "suspend is not supported in EP mode\n"); + return -EOPNOTSUPP; + } + + rockchip->intx =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_MAS= K_LEGACY); + + ret =3D dw_pcie_suspend_noirq(pci); + if (ret) + return ret; + + gpiod_set_value_cansleep(rockchip->rst_gpio, 0); + rockchip_pcie_phy_deinit(rockchip); + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); + reset_control_assert(rockchip->rst); + if (rockchip->vpcie3v3) + regulator_disable(rockchip->vpcie3v3); + + return 0; +} + +static int rockchip_pcie_resume(struct device *dev) +{ + struct rockchip_pcie *rockchip =3D dev_get_drvdata(dev); + struct dw_pcie *pci =3D &rockchip->pci; + int ret; + + if (rockchip->data->mode =3D=3D DW_PCIE_EP_TYPE) { + dev_err(dev, "resume is not supported in EP mode\n"); + return -EOPNOTSUPP; + } + + ret =3D clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks); + if (ret) { + dev_err(dev, "clock init failed: %d\n", ret); + return ret; + } + + if (rockchip->vpcie3v3) { + ret =3D regulator_enable(rockchip->vpcie3v3); + if (ret) + goto err_disable_clk; + } + + ret =3D rockchip_pcie_phy_init(rockchip); + if (ret) { + dev_err(dev, "phy init failed: %d\n", ret); + goto err_disable_regulator; + } + + reset_control_deassert(rockchip->rst); + + rockchip_pcie_writel_apb(rockchip, FIELD_PREP_WM16(0xffff, rockchip->intx= ), + PCIE_CLIENT_INTR_MASK_LEGACY); + + rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, 0); + rockchip_pcie_set_controller_mode(rockchip, PCIE_CLIENT_MODE_RC); + rockchip_pcie_unmask_dll_indicator(rockchip); + + gpiod_set_value_cansleep(rockchip->rst_gpio, 1); + + ret =3D dw_pcie_resume_noirq(pci); + if (ret) { + dev_err(dev, "failed to resume: %d\n", ret); + /* + * During resume, dw_pcie_wait_for_link() is called and when + * there is no device connected at all it returns -EIO with + * the message "Device found, but not active". Ignore it for + * now. + */ + if (ret !=3D -EIO) + goto err_deinit_phy; + } + + return 0; + +err_deinit_phy: + gpiod_set_value_cansleep(rockchip->rst_gpio, 0); + rockchip_pcie_phy_deinit(rockchip); +err_disable_regulator: + if (rockchip->vpcie3v3) + regulator_disable(rockchip->vpcie3v3); +err_disable_clk: + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); + return ret; +} + static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = =3D { .mode =3D DW_PCIE_RC_TYPE, }; @@ -1072,11 +1166,17 @@ static const struct of_device_id rockchip_pcie_of_m= atch[] =3D { {}, }; =20 +static const struct dev_pm_ops rockchip_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend, + rockchip_pcie_resume) +}; + static struct platform_driver rockchip_pcie_driver =3D { .driver =3D { .name =3D "rockchip-dw-pcie", .of_match_table =3D rockchip_pcie_of_match, .suppress_bind_attrs =3D true, + .pm =3D &rockchip_pcie_pm_ops, }, .probe =3D rockchip_pcie_probe, }; --=20 2.53.0 From nobody Fri Sep 25 20:48:39 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D6E5530DEC; Tue, 8 Sep 2026 14:52:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879140; cv=none; b=R3mwN2gymvj/0YTunyjUzVC60bWR9+dkT7DJTp83LwRcHfxktoyKXQsxN7/Ka9xACJDXyJsYm9wjTUzcJYJm8KJFYpeDcJAKVfx8Hc/e92Bz7s+7jb8u5av6kr1D+mhnme5qJFwrox9eYtKRpq5+//jhUkk+CXCq2cf5afZkHFc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788879140; c=relaxed/simple; bh=T2E33x//zZv34p7VqHG8S4S8Gcb0wfJ11dQV0Vms09o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mqLEMVMQWKgR8BElL0I/T5bxp/V8kqylIpSkDjuXw7rXkUqN0UfnSCCyJE2ci06YxTpKprIJyAKcIpa0csFOCryXnpv1Yc2Yk/at9PvJxeUKEIYv9Jn9qJxy6dFvJzK79AeEjfW1w/bA8j3AsyrWwfppfpazL5EPwYAUYZmDIss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=gx4zacVm; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="gx4zacVm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788879101; bh=T2E33x//zZv34p7VqHG8S4S8Gcb0wfJ11dQV0Vms09o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gx4zacVme7Cb/WJWMF51IiBYVhNXoQuO/Xg/biEFIQ7ZxnpOk+pDC8fkq54ejfm4P 1O36Gxw31Hk18mEtWBVUfHHKrEe7dQiW38KdKJi3WzjBIGA8F0AABqIuP6RP05tHHV 0Xrbui6o7JQenjtc8LeGM8MBWzckBp3HdZBrhNkPZOI9wScUHzv/iF4SrNHfBf4BQ3 Z7qIsDWx7S1CPUnXL3kcSyYXbRxfPikx3WTkqwKlbYq1H1YCKH67Pvdh8aPXnbLTcp PxQYrukrhkz3gfyJQ4hT1Pb4mUfapCTSunF8xZ6x0zXH+2ghJqNmp6RdzNHrUVgftM vM0Rj6pE/ydZw== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4A8C817E0FE2; Tue, 08 Sep 2026 16:51:41 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 9CC47480048; Tue, 08 Sep 2026 16:51:40 +0200 (CEST) From: Sebastian Reichel Date: Tue, 08 Sep 2026 16:51:28 +0200 Subject: [PATCH v6 10/10] PCI: dw-rockchip: Clear debug buffer before entering L2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-rockchip-pcie-system-suspend-v6-10-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1731; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=T2E33x//zZv34p7VqHG8S4S8Gcb0wfJ11dQV0Vms09o=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqgIPxM5BtG5TqRDBVCuGbS8z6iuqCgAxY17 ahfCBQp2DV9c4kCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqoCD8AAoJENju1/PI O/qaty8QAJ8td11B3+qPI+KtA21Q0cYszi6xEntVmNV9V2BWUiJt03mDyIPet2ld7lAwolemgzq TVRfdWvL+N2KcWgZMYSR9dltxPr/dKma7J5cKLmzgVhJ7Y3VktbMMkjKcwdgOYF24vlLkIBnniA WsAQBy3/m2to0+B/Ls+vRKcqYfeqyAkVoeJ6xgHb5wGhomZxgYsbYwgEswXMYsNwMdmEi1BCrz2 NYWu/g9F7XNSnLTBhml3knIvqvJBHzbyQElF9CSa7cx8Llolln6oDIGxxGTUAFmBh+T88izWQN5 8w2+CxxbXkgeaSkQKjJRsqr6trosRMWDUwh+93+AqvAtYjQ96Ag0b4/NIkvmX9lSlyr1kiZ5fNF bYnKgReb6bV4QLSSGzlriXluJAe8iA/9+CLob0Pu8BYvmAcmFREPsuK0OyjuGHAAXzHP/xWpsoa 4OXHcmML5E/jUery+AuXb6cBAyLX6kC6mveQ7NGkLJB+JFlV3ACzQRlZZG4np/vXM2U12E6j/wY LqOp3uInUWUoJ/zw9CEWip9bW9qEi+90c5nJ/N9ATtNJJlkgy6Vkb2qarOxYwwG5PuvrgIQdTqH yk1d3MUu+ChPPOdZjW3o7O2jsitRGjNXW6YrzMemUAmXjE+MCrvg/X26K5SCs2YKqa83A/N+rSv PIdn1Jmtwcez+fHGZzWAePA== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Clear the debug buffer before entering the L2 state to ease debugging link training issues on resume. Cc: Shawn Lin Signed-off-by: Sebastian Reichel Reviewed-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index e675918ba184..a508f4fffd2a 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -77,6 +77,9 @@ #define PCIE_CLKREQ_NOT_READY FIELD_PREP_WM16(BIT(0), 0) #define PCIE_CLKREQ_PULL_DOWN FIELD_PREP_WM16(GENMASK(13, 12), 1) =20 +/* General Debug Register */ +#define PCIE_CLIENT_GENERAL_DEBUG 0x104 + /* RASDES TBA information */ #define PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN 0x154 #define PCIE_CLIENT_CDM_RASDES_TBA_L1_1 BIT(4) @@ -1043,6 +1046,11 @@ static int rockchip_pcie_rc_reset_root_port(struct p= ci_host_bridge *bridge, return ret; } =20 +static inline void rockchip_pcie_link_status_clear(struct rockchip_pcie *r= ockchip) +{ + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_GENERAL_DEBUG, 0x0); +} + static int rockchip_pcie_suspend(struct device *dev) { struct rockchip_pcie *rockchip =3D dev_get_drvdata(dev); @@ -1056,6 +1064,11 @@ static int rockchip_pcie_suspend(struct device *dev) =20 rockchip->intx =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_MAS= K_LEGACY); =20 + /* All sub-devices are in D3hot by PCIe stack */ + dw_pcie_dbi_ro_wr_dis(pci); + + rockchip_pcie_link_status_clear(rockchip); + ret =3D dw_pcie_suspend_noirq(pci); if (ret) return ret; --=20 2.53.0