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Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala Acked-by: Manivannan Sadhasivam Fixes: 5b289913959b ("phy: qualcomm: qmp-combo: Update QMP PHY with Glymur = settings") Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index c39ced168d03..4d31637f1dce 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -51,6 +51,7 @@ #include "phy-qcom-qmp-dp-phy-v5.h" #include "phy-qcom-qmp-dp-phy-v6.h" #include "phy-qcom-qmp-dp-phy-v8.h" +#include "phy-qcom-qmp-qserdes-dp-com-v8.h" #include "phy-qcom-qmp-dp-phy-v10.h" =20 #include "phy-qcom-qmp-usb43-pcs-v8.h" @@ -318,8 +319,8 @@ static const unsigned int qmp_v8_n3_usb43dpphy_regs_lay= out[QPHY_LAYOUT_SIZE] =3D { [QPHY_DP_AON_TOGGLE_ENABLE] =3D QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE, =20 [QPHY_COM_RESETSM_CNTRL] =3D QSERDES_V8_COM_RESETSM_CNTRL, - [QPHY_COM_C_READY_STATUS] =3D QSERDES_V8_COM_C_READY_STATUS, - [QPHY_COM_CMN_STATUS] =3D QSERDES_V8_COM_CMN_STATUS, + [QPHY_COM_C_READY_STATUS] =3D DP_QSERDES_V8_COM_C_READY_STATUS, + [QPHY_COM_CMN_STATUS] =3D DP_QSERDES_V8_COM_CMN_STATUS, [QPHY_COM_BIAS_EN_CLKBUFLR_EN] =3D QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, =20 [QPHY_DP_PHY_STATUS] =3D QSERDES_V8_DP_PHY_STATUS, --=20 2.34.1 From nobody Fri Sep 25 20:48:39 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27FC7538D8B for ; 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Tue, 08 Sep 2026 07:01:24 -0700 (PDT) Received: from hu-naala-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339af25062sm57506667eec.16.2026.09.08.07.01.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 07:01:23 -0700 (PDT) From: Nabige Aala Date: Tue, 08 Sep 2026 19:30:55 +0530 Subject: [PATCH v4 2/9] phy: qualcomm: qmp-combo: Update DP PHY common init tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-glymur-phy-v3-v4-2-ff22e5150538@oss.qualcomm.com> References: <20260908-glymur-phy-v3-v4-0-ff22e5150538@oss.qualcomm.com> In-Reply-To: <20260908-glymur-phy-v3-v4-0-ff22e5150538@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Ritesh Kumar , Mahadevan P , Nabige Aala , Manivannan Sadhasivam , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.16-dev-d5d98 X-Developer-Signature: v=1; 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Fixes: d10736db98d25 ("phy: qualcomm: qmp-combo: Add DP offsets and setting= s for Glymur platforms") Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala Acked-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 4d31637f1dce..b2ffc20e8f6a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1494,10 +1494,10 @@ static const struct qmp_phy_init_tbl qmp_v6_n4_dp_s= erdes_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), @@ -1512,12 +1512,13 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_RESETSM_CNTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_EN, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x56), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x16), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD1, 0x24), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_1, 0x40), @@ -1553,26 +1554,26 @@ static const struct qmp_phy_init_tbl qmp_v6_n4_dp_t= x_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl qmp_v8_n3p_dp_tx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x1a), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VMODE_CTRL1, 0x40), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT1, 0x07), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT2, 0x18), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCS_INTERFACE_SELECT1, 0x50), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_1, 0x0d), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x87), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRAN_DRVR_EMP_EN, 0x5f), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_EMP_POST1_LVL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 0x2b), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_EMP_POST1_LVL, 0x2b), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_PRE1_EMPH, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_PRE1_EMPH, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_DRV_LVL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_DRV_LVL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_HIGHZ_DRVR_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_HIGHZ_DRVR_EN, 0x3f), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_2, 0x50), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_3, 0x51), - QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x0c), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET, 0x10), --=20 2.34.1 From nobody Fri Sep 25 20:48:39 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB36A544898 for ; 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Tue, 08 Sep 2026 07:01:28 -0700 (PDT) Received: from hu-naala-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339af25062sm57506667eec.16.2026.09.08.07.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 07:01:28 -0700 (PDT) From: Nabige Aala Date: Tue, 08 Sep 2026 19:30:56 +0530 Subject: [PATCH v4 3/9] phy: qualcomm: qmp-combo: Update link rate specific DP PHY tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-glymur-phy-v3-v4-3-ff22e5150538@oss.qualcomm.com> References: <20260908-glymur-phy-v3-v4-0-ff22e5150538@oss.qualcomm.com> In-Reply-To: <20260908-glymur-phy-v3-v4-0-ff22e5150538@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Ritesh Kumar , Mahadevan P , Nabige Aala , Manivannan Sadhasivam , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.16-dev-d5d98 X-Developer-Signature: v=1; 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Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala Acked-by: Manivannan Sadhasivam Fixes: d10736db98d2 ("phy: qualcomm: qmp-combo: Add DP offsets and settings= for Glymur platforms") Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 43 +++++++++++++++++----------= ---- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index b2ffc20e8f6a..16ccabd945f7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1746,11 +1746,12 @@ static const struct qmp_phy_init_tbl qmp_v6_n4_dp_s= erdes_tbl_hbr3[] =3D { =20 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x7a), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x8d), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x27), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x83), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x37), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x54), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x06), @@ -1758,16 +1759,17 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serd= es_tbl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x05), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa4), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa7), }; =20 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x21), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xf6), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x08), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x07), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x46), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), @@ -1784,7 +1786,8 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes= _tbl_hbr2[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xf6), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x20), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x10), @@ -1794,9 +1797,9 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes= _tbl_hbr2[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x05), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xae), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x17), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_RESETSM_CNTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x03), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), @@ -1804,8 +1807,8 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes= _tbl_hbr2[] =3D { =20 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr3[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x63), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x25), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x5b), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), @@ -1813,7 +1816,7 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serdes= _tbl_hbr3[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), =20 - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x18), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x15), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x4f), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), @@ -1832,19 +1835,19 @@ static const struct qmp_phy_init_tbl qmp_v8_dp_serd= es_tbl_hbr3[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x16), 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Define named constants QSERDES_DP_PHY_AUX_CFG2_V456/V8 and QSERDES_DP_PHY_CFG1_V456/V8 for better readability and maintainability. Populate the new fields in all existing DP PHY cfg structures: - V456-based platforms (sar2130p, sc8180x, sc8280xp, x1e80100, sm8250, sm8350, sm8475, sm8550, sm8650, sm8750) use V456 constants - Glymur (V8) uses V8 constants and sets dp_mode_ignore_reverse =3D true Update qmp_combo_configure_dp_mode() to honor dp_mode_ignore_reverse, so Glymur can bypass TypeC orientation-based lane reversal. Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 44 +++++++++++++++++++++++++++= +++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 16ccabd945f7..53fc1d1e8494 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -2478,6 +2478,14 @@ static const struct qmp_combo_lane_mapping dp_data_l= anes[] =3D { =20 struct qmp_combo; =20 +/* DP PHY AUX_CFG2 register values for different hardware versions */ +#define QSERDES_DP_PHY_AUX_CFG2_V456 0xa4 +#define QSERDES_DP_PHY_AUX_CFG2_V8 0x06 + +/* DP PHY CFG_1 register values for different hardware versions */ +#define QSERDES_DP_PHY_CFG1_V456 0x0f +#define QSERDES_DP_PHY_CFG1_V8 0x2f + struct qmp_combo_offsets { u16 com; u16 txa; @@ -2541,6 +2549,15 @@ struct qmp_phy_cfg { int (*calibrate_dp_phy)(struct qmp_combo *qmp); void (*dp_aux_init)(struct qmp_combo *qmp); =20 + /* DP PHY AUX_CFG2 register value (hardware-specific) */ + unsigned int dp_aux_cfg2; + + /* DP PHY CFG_1 register value (hardware-specific) */ + unsigned int dp_phy_cfg1; + + /* Set if DP mode configuration should ignore TypeC orientation */ + bool dp_mode_ignore_reverse; + /* resets to be requested */ const char * const *reset_list; int num_resets; @@ -2780,6 +2797,8 @@ static const struct qmp_phy_cfg sar2130p_usb3dpphy_cf= g =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V456, =20 .regs =3D qmp_v6_usb3phy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, @@ -2916,6 +2935,8 @@ static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg= =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V456, =20 .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -2962,6 +2983,8 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_c= fg =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V456, =20 .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -3007,6 +3030,8 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cf= g =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V456, =20 .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -3116,6 +3141,8 @@ static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V456, =20 .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -3164,6 +3191,8 @@ static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V456, =20 .reset_list =3D msm8996_usb3phy_reset_l, .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), @@ -3211,6 +3240,8 @@ static const struct qmp_phy_cfg sm8475_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V456, =20 .regs =3D qmp_v6_usb3phy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, @@ -3256,6 +3287,8 @@ static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V456, =20 .regs =3D qmp_v6_usb3phy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, @@ -3301,6 +3334,8 @@ static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V456, =20 .regs =3D qmp_v6_usb3phy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, @@ -3346,6 +3381,8 @@ static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V456, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V456, =20 .regs =3D qmp_v8_usb3phy_regs_layout, .reset_list =3D msm8996_usb3phy_reset_l, @@ -3391,6 +3428,9 @@ static const struct qmp_phy_cfg glymur_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v8_configure_dp_clocks, .configure_dp_phy =3D qmp_v8_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V8, + .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V8, + .dp_mode_ignore_reverse =3D true, =20 .regs =3D qmp_v8_n3_usb43dpphy_regs_layout, .reset_list =3D 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X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_02,2026-09-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 priorityscore=1501 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609080151 From: Ritesh Kumar Add PCS-level drive level tables for the Glymur (V8) DP PHY: - qmp_dp_v8_ln_drv_lvl_hbr3_hbr2: LN0/LN1_DRV_LVL settings for HBR3/HBR2 - qmp_dp_v8_ln_drv_lvl_hbr_rbr: LN0/LN1_DRV_LVL settings for HBR/RBR - qmp_dp_v8_pre_emphasis_hbr_rbr: updated TX_EMP_POST1_LVL values for HBR/RBR Add ln_drv_lvl_hbr_rbr and ln_drv_lvl_hbr3_hbr2 pointer fields to qmp_phy_cfg to allow per-platform PCS drive level table selection. Wire the new tables into glymur_usb3dpphy_cfg, replacing the previously used qmp_dp_v6_pre_emphasis_hbr_rbr with the corrected v8 table. Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 33 +++++++++++++++++++++++++++= +++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 53fc1d1e8494..0ec382aebe2b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -2456,6 +2456,30 @@ static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4]= =3D { { 0x22, 0xff, 0xff, 0xff } }; =20 +/* HBR3 & HBR2: DP2_LN0/LN1_DRV_LVL swing settings (PCS level) */ +static const u8 qmp_dp_v8_ln_drv_lvl_hbr3_hbr2[4][4] =3D { + { 0x02, 0x12, 0x16, 0x1a }, + { 0x09, 0x19, 0x1f, 0xff }, + { 0x10, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +/* HBR & RBR: DP2_LN0/LN1_DRV_LVL swing settings (PCS level) */ +static const u8 qmp_dp_v8_ln_drv_lvl_hbr_rbr[4][4] =3D { + { 0x07, 0x0f, 0x16, 0x1f }, + { 0x11, 0x1e, 0x1f, 0xff }, + { 0x16, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +/* HBR & RBR: TX_EMP_POST1_LVL emphasis settings */ +static const u8 qmp_dp_v8_pre_emphasis_hbr_rbr[4][4] =3D { + { 0x20, 0x2d, 0x34, 0x3b }, + { 0x20, 0x2e, 0x35, 0xff }, + { 0x20, 0x2e, 0xff, 0xff }, + { 0x22, 0xff, 0xff, 0xff } +}; + struct qmp_combo_lane_mapping { unsigned int lanes_count; enum typec_orientation orientation; @@ -2542,6 +2566,10 @@ struct qmp_phy_cfg { const u8 (*pre_emphasis_hbr_rbr)[4][4]; const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; =20 + /* PCS-level drive level tables (v8 / Glymur) */ + const u8 (*ln_drv_lvl_hbr_rbr)[4][4]; + const u8 (*ln_drv_lvl_hbr3_hbr2)[4][4]; + /* DP PHY callbacks */ int (*configure_dp_clocks)(struct qmp_combo *qmp); int (*configure_dp_phy)(struct qmp_combo *qmp); @@ -3420,10 +3448,13 @@ static const struct qmp_phy_cfg glymur_usb3dpphy_cf= g =3D { .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v8_dp_serdes_tbl_hbr3), =20 .swing_hbr_rbr =3D &qmp_dp_v6_voltage_swing_hbr_rbr, - .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, + .pre_emphasis_hbr_rbr =3D &qmp_dp_v8_pre_emphasis_hbr_rbr, .swing_hbr3_hbr2 =3D &qmp_dp_v5_voltage_swing_hbr3_hbr2, .pre_emphasis_hbr3_hbr2 =3D &qmp_dp_v5_pre_emphasis_hbr3_hbr2, =20 + .ln_drv_lvl_hbr_rbr =3D &qmp_dp_v8_ln_drv_lvl_hbr_rbr, + .ln_drv_lvl_hbr3_hbr2 =3D &qmp_dp_v8_ln_drv_lvl_hbr3_hbr2, + .dp_aux_init =3D qmp_v8_dp_aux_init, .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v8_configure_dp_clocks, --=20 2.34.1 From nobody Fri Sep 25 20:48:39 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FA1854CF4E for ; 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Tue, 08 Sep 2026 07:01:40 -0700 (PDT) Received: from hu-naala-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339af25062sm57506667eec.16.2026.09.08.07.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 07:01:39 -0700 (PDT) From: Nabige Aala Date: Tue, 08 Sep 2026 19:30:59 +0530 Subject: [PATCH v4 6/9] phy: qualcomm: qmp-combo: Extract common DP PHY init sequence Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-glymur-phy-v3-v4-6-ff22e5150538@oss.qualcomm.com> References: <20260908-glymur-phy-v3-v4-0-ff22e5150538@oss.qualcomm.com> In-Reply-To: <20260908-glymur-phy-v3-v4-0-ff22e5150538@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Ritesh Kumar , Mahadevan P , Nabige Aala X-Mailer: b4 0.16-dev-d5d98 X-Developer-Signature: v=1; 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The common sequence covers: - Validation that dp_aux_cfg2 is configured for the platform - Writing dp_phy_cfg1 and dp_aux_cfg2 hardware-specific register values - Calling configure_dp_mode() for TypeC lane orientation - Programming AUX_CFG1, TX lane control registers - Invoking configure_dp_clocks() callback - PHY_CFG reset/enable sequence - Polling COM_C_READY_STATUS and COM_CMN_STATUS for PLL lock Refactor qmp_v456_configure_dp_phy() to call the common function, removing the duplicated initialization code. Update qmp_v8_configure_dp_phy() to call qmp_combo_configure_dp_phy_common() directly instead of going through qmp_v456_configure_dp_phy(). Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala Reviewed-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 99 ++++++++++++++++++---------= ---- 1 file changed, 59 insertions(+), 40 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 0ec382aebe2b..79006469f3d4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -3459,6 +3459,7 @@ static const struct qmp_phy_cfg glymur_usb3dpphy_cfg = =3D { .configure_dp_tx =3D qmp_v4_configure_dp_tx, .configure_dp_clocks =3D qmp_v8_configure_dp_clocks, .configure_dp_phy =3D qmp_v8_configure_dp_phy, + .dp_aux_cfg2 =3D QSERDES_DP_PHY_AUX_CFG2_V8, .dp_phy_cfg1 =3D QSERDES_DP_PHY_CFG1_V8, .dp_mode_ignore_reverse =3D true, @@ -3766,6 +3767,62 @@ static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); } =20 +static int qmp_combo_configure_dp_phy_common(struct qmp_combo *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + u32 status; + int ret; + + if (!cfg->dp_aux_cfg2) { + dev_err(qmp->dev, "DP AUX CFG2 value not configured\n"); + return -EINVAL; + } + + writel(cfg->dp_phy_cfg1, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); + + qmp_combo_configure_dp_mode(qmp); + + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); + writel(cfg->dp_aux_cfg2, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); + + writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); + + ret =3D qmp->cfg->configure_dp_clocks(qmp); + if (ret) + return ret; + + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + + writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); + + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS= ], + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + return 0; +} + static void qmp_v8_dp_aux_init(struct qmp_combo *qmp) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -3866,48 +3923,10 @@ static int qmp_v456_configure_dp_phy(struct qmp_com= bo *qmp) u32 status; int ret; =20 - writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); - - qmp_combo_configure_dp_mode(qmp); - - writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); - writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); - - writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); - writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); - - ret =3D qmp->cfg->configure_dp_clocks(qmp); + ret =3D qmp_combo_configure_dp_phy_common(qmp); if (ret) return ret; =20 - writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); - writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); - writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); - writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); - - writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); - - if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS= ], - status, - ((status & BIT(0)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], - status, - ((status & BIT(0)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - - if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], - status, - ((status & BIT(1)) > 0), - 500, - 10000)) - return -ETIMEDOUT; - writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); =20 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], @@ -3999,7 +4018,7 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo *= qmp) u32 status; int ret; =20 - ret =3D qmp_v456_configure_dp_phy(qmp); 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Add per-link-rate auxless setup/silence cycle and LFPS period values instead of using fixed constants: RBR (1.62 Gbps): setup=3D0x03, silence=3D0x06, lfps_period=3D0x00 HBR (2.70 Gbps): setup=3D0x04, silence=3D0x08, lfps_period=3D0x11 HBR2 (5.40 Gbps): setup=3D0x09, silence=3D0x11, lfps_period=3D0x33 HBR3 (8.10 Gbps): setup=3D0x0f, silence=3D0x1a, lfps_period=3D0x55 Add per-lane drive level lookup from the ln_drv_lvl tables based on the maximum voltage swing and pre-emphasis levels across all active lanes, replacing the hardcoded 0x1f value. Remove the duplicate LFPS_PERIOD write that was present after the AUXLESS_CFG1 programming. Fixes: d10736db98d25 ("phy: qualcomm: qmp-combo: Add DP offsets and setting= s for Glymur platforms") Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 45 ++++++++++++++++++++++-----= ---- 1 file changed, 32 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 79006469f3d4..a07ad858b0d3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -3868,48 +3868,67 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo= *qmp) static int qmp_v8_configure_dp_clocks(struct qmp_combo *qmp) { const struct phy_configure_opts_dp *dp_opts =3D &qmp->dp_opts; - u32 phy_vco_div; - unsigned long pixel_freq; const struct qmp_phy_cfg *cfg =3D qmp->cfg; + unsigned long pixel_freq; + u32 auxless_setup, auxless_silence, lfps_period; + unsigned int v_level =3D 0, p_level =3D 0; + u8 ln_drv_lvl; + int i; + + for (i =3D 0; i < dp_opts->lanes; i++) { + v_level =3D max(v_level, dp_opts->voltage[i]); + p_level =3D max(p_level, dp_opts->pre[i]); + } + + if (dp_opts->link_rate <=3D 2700) + ln_drv_lvl =3D (*cfg->ln_drv_lvl_hbr_rbr)[v_level][p_level]; + else + ln_drv_lvl =3D (*cfg->ln_drv_lvl_hbr3_hbr2)[v_level][p_level]; =20 switch (dp_opts->link_rate) { case 1620: - phy_vco_div =3D 0x4; pixel_freq =3D 1620000000UL / 2; + auxless_setup =3D 0x03; + auxless_silence =3D 0x06; + lfps_period =3D 0x00; break; case 2700: - phy_vco_div =3D 0x2; pixel_freq =3D 2700000000UL / 2; + auxless_setup =3D 0x04; + auxless_silence =3D 0x08; + lfps_period =3D 0x11; break; case 5400: - phy_vco_div =3D 0x4; pixel_freq =3D 5400000000UL / 4; + auxless_setup =3D 0x09; + auxless_silence =3D 0x11; + lfps_period =3D 0x33; break; case 8100: - phy_vco_div =3D 0x3; pixel_freq =3D 8100000000UL / 6; + auxless_setup =3D 0x0f; + auxless_silence =3D 0x1a; + lfps_period =3D 0x55; break; default: /* Other link rates aren't supported */ return -EINVAL; } - writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); =20 /* disable core reset tsync */ writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); =20 - writel(0x04, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC); - writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC); + writel(auxless_setup, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CY= C); + writel(auxless_silence, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENC= E_CYC); writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_CYC); - writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); + writel(lfps_period, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); =20 writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX2_TX3_LANE_CTL); writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX0_TX1_LANE_CTL); writel(0x01, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_CFG1); - writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); - writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN0_DRV_LVL); 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=20 - writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_= PWRDN | - DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + writel(0x3f, qmp->dp_serdes + QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1); + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); =20 /* Turn on BIAS current for PHY/PLL */ - writel(0x1c, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); + writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); =20 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); @@ -3859,8 +3862,8 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo *= qmp) writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); =20 - writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); - writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); + writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); + writel(0x2b, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); =20 qmp_combo_configure_dp_swing(qmp); } @@ -4049,20 +4052,31 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo= *qmp) } else if (dp_opts->lanes =3D=3D 2) { bias0_en =3D reverse ? 0x3f : 0x15; bias1_en =3D reverse ? 0x15 : 0x3f; - drvr0_en =3D 0x10; - drvr1_en =3D 0x10; + drvr0_en =3D reverse ? 0x30 : 0x10; + drvr1_en =3D reverse ? 0x10 : 0x30; } else { bias0_en =3D 0x3f; bias1_en =3D 0x3f; - drvr0_en =3D 0x34; - drvr1_en =3D 0x34; + drvr0_en =3D 0x30; + drvr1_en =3D 0x30; } =20 + writel(0x87, qmp->dp_tx + QSERDES_V8_LALB_CLKBUF_ENABLE); + writel(0x87, qmp->dp_tx2 + QSERDES_V8_LALB_CLKBUF_ENABLE); writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); =20 + writel(0x03, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + writel(0x23, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + writel(0x22, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + + writel(0x0a, qmp->dp_tx + QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL); + writel(0x0a, qmp->dp_tx2 + QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL); + + writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); + writel(0x08, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); udelay(100); writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); @@ -4070,16 +4084,25 @@ static int qmp_v8_configure_dp_phy(struct qmp_combo= *qmp) =20 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], status, - ((status & BIT(1)) > 0), + ((status & BIT(0)) > 0), 500, 10000)) return -ETIMEDOUT; =20 - writel(0x00, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); - writel(0x00, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); =20 - writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 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a=ed25519-sha256; t=1788876071; l=1577; i=nabige.aala@oss.qualcomm.com; s=20260520; h=from:subject:message-id; bh=+W/VJmY/w0HJ6vMFhBO//YD0odQ6tMzQHwNFCFAKC3w=; b=Qg5AE0TCNknurbJSvtaEURuTubSChdXOV0gEsrmJNfxzxW8mB+xtNlJApI8ubBM90QoeZ8dfr EZaWbAZaeWlALGKz4wIfLGGU35VJfwnqcyq/ZHf7Hjr2oQXjaM1pSUV X-Developer-Key: i=nabige.aala@oss.qualcomm.com; a=ed25519; pk=PYHJom8sPos1IGkrbCCsWiE7XTBQrQZd9jzAo051tgw= X-Authority-Analysis: v=2.4 cv=Qu9uG1yd c=1 sm=1 tr=0 ts=6aa01551 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=X8Wa9jmQWlBxTcu95m0A:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: _JMiDjTOOuES7VxCqfhU3YMqmuXWiRdx X-Proofpoint-GUID: _JMiDjTOOuES7VxCqfhU3YMqmuXWiRdx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA4MDE1MSBTYWx0ZWRfX2ObMfKWFIKHF cShh7GNSadcMUw7TrMPCt7FG/Pig2SVXqGVfu5RhUiiF4YGP7yMbNig+1p4iqSBXmxU2I4zBWVG pYQbigu6fvULBpEuVpdZko+UxLeMOC1Cx/TNRaw0NFeu/RL5GwLgxSn1Aam5iteOgWle8xKBr1G bjRx8jypwWmjxRqO6QqlTK4cjLIPlMVnMPa5LCtoI2+HpR32A48vPiTeQ0bZQKZqLVc/KXrVgxU fUoTSTbnldTwreOGoOqtgIRvfKGFBXeejhON++2dYqy91ylSDJ/kYd9xmIFX5maedmqQLNSQ7lF cFA1DJbyTElIYD7hrpet0udI8o6UxSEijDK7CD5aH8wMf2lOKp0eVUywiuXy6/KvaeS7/LZZ4zu JTMNtXzzkfvh1C7zzK2uwxtE896yUhd64SIcZ+TzItfKI+hQOeDlwhbVFQFbkino2USZfTlBKjW qRZ/nfakvZ/1SiESh7w== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA4MDE1MSBTYWx0ZWRfX6bTTyA2mgPiL bllgr4LPysXNwKR5xZs4nJTD4tgNOx4GRFEqGnhMRwa3BZZSolTCubcSDizTY8LqfnoDM/Au3we QPHGGmsKNfltEAUFm2o5z5lbEgKsBQI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_02,2026-09-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609080151 The configure_dp_phy() callback can return an error (e.g. -ETIMEDOUT on PLL lock failure), but qmp_combo_dp_power_on() was ignoring the return value and always returning 0. Capture the return value, skip setting dp_powered_on on failure, and propagate the error to the caller. Signed-off-by: Ritesh Kumar Signed-off-by: Mahadevan P Signed-off-by: Nabige Aala --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index bb1c5df52d09..d77fe94b312c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -4316,6 +4316,7 @@ static int qmp_combo_dp_power_on(struct phy *phy) const struct qmp_phy_cfg *cfg =3D qmp->cfg; void __iomem *tx =3D qmp->dp_tx; void __iomem *tx2 =3D qmp->dp_tx2; + int ret =3D 0; =20 mutex_lock(&qmp->phy_mutex); =20 @@ -4328,13 +4329,17 @@ static int qmp_combo_dp_power_on(struct phy *phy) cfg->configure_dp_tx(qmp); =20 /* Configure link rate, swing, etc. */ - cfg->configure_dp_phy(qmp); + ret =3D cfg->configure_dp_phy(qmp); + if (ret) { + dev_err(qmp->dev, "DP PHY configuration failed: %d\n", ret); + goto out_unlock; + } =20 qmp->dp_powered_on =3D true; =20 +out_unlock: mutex_unlock(&qmp->phy_mutex); - - return 0; + return ret; } =20 static int qmp_combo_dp_power_off(struct phy *phy) --=20 2.34.1