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Signed-off-by: Petar Stepanovic Acked-by: Conor Dooley --- .../devicetree/bindings/pwm/axiado,ax3000-pwm.yaml | 53 ++++++++++++++++++= ++++ MAINTAINERS | 8 ++++ 2 files changed, 61 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/axiado,ax3000-pwm.yaml b= /Documentation/devicetree/bindings/pwm/axiado,ax3000-pwm.yaml new file mode 100644 index 000000000000..3b73b233da86 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/axiado,ax3000-pwm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/axiado,ax3000-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axiado AX3000 PWM controller + +maintainers: + - Petar Stepanovic + - Akhila Kavi + - Prasad Bolisetty + +description: + The Axiado PWM controller found on the AX3000 and AX3005 SoCs. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - const: axiado,ax3000-pwm + - items: + - const: axiado,ax3005-pwm + - const: axiado,ax3000-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + pwm@80801c00 { + compatible =3D "axiado,ax3000-pwm"; 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Tue, 8 Sep 2026 01:28:43 -0700 (PDT) From: Petar Stepanovic Date: Tue, 08 Sep 2026 01:28:35 -0700 Subject: [PATCH v4 2/2] pwm: add Axiado AX3000 PWM driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260908-axiado-ax3000-pwm-v4-2-19a03671cd5b@axiado.com> References: <20260908-axiado-ax3000-pwm-v4-0-19a03671cd5b@axiado.com> In-Reply-To: <20260908-axiado-ax3000-pwm-v4-0-19a03671cd5b@axiado.com> To: Akhila Kavi , Prasad Bolisetty , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Harshit Shah Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, Petar Stepanovic X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788856122; l=12164; i=pstepanovic@axiado.com; s=20250916; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FapakIDHUK1tW7Y7sWSd1fnESDHPBq0g9iRDD4+fmyit17WSWqVsGisk9Djw93LeXh+V/AND1eKvgGpFDfieQ4PA4p0RG1t2mUx09yRt5L6PbFDJLY5SxrS6xLADx+oL5jd/CzrjRPtEs4FJ6bcVg8KhvrMyrk+0Io9ZBzx67ZwIePErn9G69R2CW5HWu1qb00WYhuPz74Ns1kqnkTobF/ZP1SbkAp31h/f18vYjRVte2ldsefpfByaBuwkHZg07fyc3A9DQM7deGSYngQT+BlUC45MsQvPtSbsJ2snkM3xxZcLhFzyWdgPHwEYUdZN7jS6ZQtDyHTQbNet3BxD2lF6d6pQeAkeg2FeJ1Ezsd/gpikv7YkFPamf60kPBt49fdFTANL2fPmpQbdELGSyhxv3ZM1BrF3Ec8GXeCpp5cYkQIC3Fn/S1Uy0zx4pQrF+s X-OriginatorOrg: axiado.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2026 08:28:43.5741 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d27900b7-0c79-4664-4aa6-08df0d8331bd X-MS-Exchange-CrossTenant-Id: ff2db17c-4338-408e-9036-2dee8e3e17d7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=ff2db17c-4338-408e-9036-2dee8e3e17d7;Ip=[64.62.143.114];Helo=[smtp.corp.axiado.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR18MB5884 The Axiado AX3000 and AX3005 SoCs include a single-channel PWM controller. Add a driver supporting period, duty-cycle, and enable-state configuration through the Linux PWM framework. Disabling the hardware controller drives its output high. Implement a logically disabled PWM using the controller's constant-low encoding instead. The same encoding is used for an enabled PWM with a 0% duty cycle, so cache the logical state and requested period for readback. AX3005 uses the same programming model as AX3000 and is supported through the axiado,ax3000-pwm fallback compatible. Signed-off-by: Petar Stepanovic --- MAINTAINERS | 1 + drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-axiado.c | 332 +++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 345 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9999480376cc..14eea3bc4d4d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4319,6 +4319,7 @@ M: Prasad Bolisetty L: linux-pwm@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/pwm/axiado,ax3000-pwm.yaml +F: drivers/pwm/pwm-axiado.c =20 AXIS ARTPEC ARM64 SoC SUPPORT M: Jesper Nilsson diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 6f3147518376..76f6c04b0e23 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -129,6 +129,17 @@ config PWM_ATMEL_TCB To compile this driver as a module, choose M here: the module will be called pwm-atmel-tcb. =20 +config PWM_AXIADO + tristate "Axiado PWM support" + depends on ARCH_AXIADO || COMPILE_TEST + depends on HAS_IOMEM + help + PWM framework driver for the PWM controller found on Axiado + AX3000 and AX3005 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-axiado. + config PWM_AXI_PWMGEN tristate "Analog Devices AXI PWM generator" depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_= SOCFPGA || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0dc0d2b69025..4466a29e780a 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PWM_ARGON_FAN_HAT) +=3D pwm-argon-fan-hat.o obj-$(CONFIG_PWM_ATMEL) +=3D pwm-atmel.o obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) +=3D pwm-atmel-hlcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) +=3D pwm-atmel-tcb.o +obj-$(CONFIG_PWM_AXIADO) +=3D pwm-axiado.o obj-$(CONFIG_PWM_AXI_PWMGEN) +=3D pwm-axi-pwmgen.o obj-$(CONFIG_PWM_BCM2835) +=3D pwm-bcm2835.o obj-$(CONFIG_PWM_BCM_IPROC) +=3D pwm-bcm-iproc.o diff --git a/drivers/pwm/pwm-axiado.c b/drivers/pwm/pwm-axiado.c new file mode 100644 index 000000000000..e1d408809694 --- /dev/null +++ b/drivers/pwm/pwm-axiado.c @@ -0,0 +1,332 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021-2026 Axiado Corporation. + */ + +/* + * - Supports normal polarity. Configuration changes take effect immediate= ly + * without waiting for the current period to complete. + * - The hardware output remains high when the controller is disabled. + * Therefore, a logically disabled PWM is implemented using the hardware + * constant-low representation. + * - Supported period range: 2 through 0xfffffffe PWM input clock cycles; + * 0xffffffff is reserved by the hardware for a constant-low output. + * Longer periods are clamped to the maximum. + * - 0% duty cycle: Programmed as a constant-low period because the + * hardware interprets a zero high time as a constant-high output. + * Consequently, the requested period cannot be read back while the + * duty cycle is 0%. + * - 100% duty cycle: Fully supported and produces a constant-high output. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register offsets */ +#define AXIADO_PWM_CTRL_REG 0x0000 +#define AXIADO_PWM_PERIOD_REG 0x0004 +#define AXIADO_PWM_HIGH_REG 0x0008 + +/* Period and duty cycle limits */ +#define AXIADO_PWM_PERIOD_MIN 2 +#define AXIADO_PWM_PERIOD_MAX 0xfffffffe +#define AXIADO_PWM_PERIOD_CONST_LOW 0xffffffff +#define AXIADO_PWM_DUTY_MIN 1 + +/* Control register bits */ +#define AXIADO_PWM_CTRL_ENABLE BIT(0) + +struct axiado_pwm_chip { + void __iomem *base; + unsigned long rate; + u32 cached_period; + bool logically_disabled; +}; + +struct axiado_pwm_waveform { + u32 period; + u32 duty; + bool enabled; +}; + +static int +axiado_pwm_round_waveform_tohw(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_waveform *wf, + void *_wfhw) +{ + struct axiado_pwm_chip *axpwm =3D pwmchip_get_drvdata(chip); + struct axiado_pwm_waveform *wfhw =3D _wfhw; + u64 period; + u64 duty; + int ret =3D 0; + + /* Encode a disabled request as a zeroed hardware waveform. */ + if (!wf->period_length_ns) { + *wfhw =3D (struct axiado_pwm_waveform) {}; + + return 0; + } + + /* Only an edge-aligned waveform starting at offset zero is supported. */ + if (wf->duty_offset_ns) + return -EINVAL; + + if (wf->duty_length_ns > wf->period_length_ns) + return -EINVAL; + + period =3D mul_u64_u64_div_u64(wf->period_length_ns, axpwm->rate, + NSEC_PER_SEC); + + if (period < AXIADO_PWM_PERIOD_MIN) { + period =3D AXIADO_PWM_PERIOD_MIN; + ret =3D 1; + } else if (period > AXIADO_PWM_PERIOD_MAX) { + period =3D AXIADO_PWM_PERIOD_MAX; + } + + /* + * Keep the rounded period for a 0% duty cycle. .write_waveform() + * translates it to the hardware constant-low representation. + */ + if (!wf->duty_length_ns) { + *wfhw =3D (struct axiado_pwm_waveform) { + .period =3D period, + .duty =3D 0, + .enabled =3D true, + }; + + return ret; + } + + duty =3D mul_u64_u64_div_u64(wf->duty_length_ns, axpwm->rate, + NSEC_PER_SEC); + + /* + * Preserve an exact 100% duty request when the hardware period has + * been clamped. + */ + if (wf->duty_length_ns =3D=3D wf->period_length_ns) + duty =3D period; + + /* + * Period clamping can leave the converted duty greater than the + * final hardware period. In that case, clamp it to 100% duty. + */ + if (duty > period) + duty =3D period; + + *wfhw =3D (struct axiado_pwm_waveform) { + .period =3D period, + .duty =3D duty, + .enabled =3D true, + }; + + return ret; +} + +static int +axiado_pwm_round_waveform_fromhw(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw, + struct pwm_waveform *wf) +{ + struct axiado_pwm_chip *axpwm =3D pwmchip_get_drvdata(chip); + const struct axiado_pwm_waveform *wfhw =3D _wfhw; + + if (!wfhw->enabled) { + *wf =3D (struct pwm_waveform) { + .period_length_ns =3D 0, + .duty_length_ns =3D 0, + .duty_offset_ns =3D 0, + }; + + return 0; + } + + *wf =3D (struct pwm_waveform) { + .period_length_ns =3D + mul_u64_u64_div_u64_roundup(wfhw->period, NSEC_PER_SEC, + axpwm->rate), + .duty_length_ns =3D + mul_u64_u64_div_u64_roundup(wfhw->duty, NSEC_PER_SEC, + axpwm->rate), + .duty_offset_ns =3D 0, + }; + + return 0; +} + +static int axiado_pwm_read_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + void *_wfhw) +{ + struct axiado_pwm_chip *axpwm =3D pwmchip_get_drvdata(chip); + struct axiado_pwm_waveform *wfhw =3D _wfhw; + u32 period; + u32 duty; + u32 ctrl; + + /* + * A logically disabled request is implemented as a constant-low + * hardware waveform because disabling the controller drives the + * output high. + */ + if (axpwm->logically_disabled) { + *wfhw =3D (struct axiado_pwm_waveform) {}; + return 0; + } + + ctrl =3D readl(axpwm->base + AXIADO_PWM_CTRL_REG); + period =3D readl(axpwm->base + AXIADO_PWM_PERIOD_REG); + duty =3D readl(axpwm->base + AXIADO_PWM_HIGH_REG); + + /* The constant-low encoding doesn't hold the period, so restore it. */ + if (period =3D=3D AXIADO_PWM_PERIOD_CONST_LOW) { + period =3D axpwm->cached_period; + duty =3D 0; + } else if (duty > period) { + duty =3D period; + } + + *wfhw =3D (struct axiado_pwm_waveform) { + .period =3D period, + .duty =3D duty, + .enabled =3D !!(ctrl & AXIADO_PWM_CTRL_ENABLE), + }; + + return 0; +} + +static int axiado_pwm_write_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw) +{ + struct axiado_pwm_chip *axpwm =3D pwmchip_get_drvdata(chip); + const struct axiado_pwm_waveform *wfhw =3D _wfhw; + u32 period =3D wfhw->period; + u32 duty =3D wfhw->duty; + + if (!wfhw->enabled) { + /* + * Disabling the controller drives its output high. Implement + * the logically disabled state using the constant-low hardware + * representation instead. + */ + writel(AXIADO_PWM_PERIOD_CONST_LOW, + axpwm->base + AXIADO_PWM_PERIOD_REG); + writel(AXIADO_PWM_DUTY_MIN, + axpwm->base + AXIADO_PWM_HIGH_REG); + writel(AXIADO_PWM_CTRL_ENABLE, + axpwm->base + AXIADO_PWM_CTRL_REG); + axpwm->logically_disabled =3D true; + + return 0; + } + + /* + * A zero high time produces a constant high output, so use the + * constant-low period encoding for a 0% duty cycle. Keep the high time + * non-zero because a zero value takes precedence over that encoding. + * Cache the requested period for .read_waveform(). + */ + if (!duty) { + axpwm->cached_period =3D period; + period =3D AXIADO_PWM_PERIOD_CONST_LOW; + duty =3D AXIADO_PWM_DUTY_MIN; + } + + /* + * The hardware has no shadow registers. These writes may alter the + * active waveform before the current period has completed. + */ + writel(period, axpwm->base + AXIADO_PWM_PERIOD_REG); + writel(duty, axpwm->base + AXIADO_PWM_HIGH_REG); + writel(AXIADO_PWM_CTRL_ENABLE, axpwm->base + AXIADO_PWM_CTRL_REG); + axpwm->logically_disabled =3D false; + + return 0; +} + +static const struct pwm_ops axiado_pwm_ops =3D { + .sizeof_wfhw =3D sizeof(struct axiado_pwm_waveform), + .round_waveform_tohw =3D axiado_pwm_round_waveform_tohw, + .round_waveform_fromhw =3D axiado_pwm_round_waveform_fromhw, + .read_waveform =3D axiado_pwm_read_waveform, + .write_waveform =3D axiado_pwm_write_waveform, +}; + +static int axiado_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct axiado_pwm_chip *axpwm; + struct pwm_chip *chip; + struct clk *clk; + int ret; + + chip =3D devm_pwmchip_alloc(dev, 1, sizeof(*axpwm)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + + axpwm =3D pwmchip_get_drvdata(chip); + + axpwm->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(axpwm->base)) + return dev_err_probe(dev, PTR_ERR(axpwm->base), + "Failed to map registers\n"); + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get/enable clock\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, clk); + if (ret) + return dev_err_probe(dev, ret, + "Failed to lock clock rate\n"); + + axpwm->rate =3D clk_get_rate(clk); + if (!axpwm->rate) + return dev_err_probe(dev, -EINVAL, + "Failed to get clock rate\n"); + + /* + * Provide a valid fallback period if the bootloader left the + * constant-low encoding programmed. + */ + axpwm->cached_period =3D AXIADO_PWM_PERIOD_MIN; + + chip->ops =3D &axiado_pwm_ops; + chip->atomic =3D true; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret) + return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); + + return 0; +} + +static const struct of_device_id axiado_pwm_match[] =3D { + { .compatible =3D "axiado,ax3000-pwm" }, + { } +}; +MODULE_DEVICE_TABLE(of, axiado_pwm_match); + +static struct platform_driver axiado_pwm_driver =3D { + .driver =3D { + .name =3D "axiado-pwm", + .of_match_table =3D axiado_pwm_match, + }, + .probe =3D axiado_pwm_probe, +}; +module_platform_driver(axiado_pwm_driver); + +MODULE_AUTHOR("Axiado Corporation"); +MODULE_DESCRIPTION("Axiado PWM driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1