From nobody Fri Sep 25 23:08:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D9505111A9 for ; Mon, 7 Sep 2026 16:40:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799239; cv=none; b=OIs9BXiDO8H0NDLQGfC25wci/xVmmvSTxneCwotJplUs+r4kGqhhje2sGloAAUcqABhEA8HO00Ue0sDpYm8QEtYniDPXKJMBk4MsOUu5GIddI5aIIbRie/od6j9MhUpoBZF6mocjqy+8JFBpQDy+53wabduTP+QuLd8jV+O2viI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799239; c=relaxed/simple; bh=/VXTzC70t4yVtBJrIF0JdWDh1gG30uuP/DaOv76dDnI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Yb8q0HDwcIDILeDqyn4oIIQSYC0qdhjVtYIx88Dy6itJf0Kdb0G70nXaysjJb0TLPNcxIXQLThOYseBriPVu7tI6w7F+UMmYxliMvEgxcZD+bnjEEV0lf3LRBXTTF2Yqr7sgvkmckqJ8cfhTbBitQUvgALm0ED2U+CgHrclFI/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WEAuga3D; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WEAuga3D" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B82701F00A3D; Mon, 7 Sep 2026 16:40:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799238; bh=FqgwtArQEQvqOYaVK+gx/Kqx6LAzmgUYoWNYaDKBbKE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=WEAuga3D54bnE4s0DofA7MVFKNKHnqgNmAre3Hhj0U6WmlwtuxQPCrQu+AKNUPQJo tr8Lxgx/y1EH6GKMDXEpYn739KWLPguFaMoTmniBwthEdL3qQkLe3BpdlLlatkkOHO jQNNzZKR52nktGtQS2W6YR2dOr3Ml+i1cHA7wCK3MJnRRyQNdPa7MHODZhNWtVIlkH UbxhpAPyvsRVidn0YSO9S2rvZWnVbYK8VjmkDiDeUhVLd2Q2SECL2xOHfB+72vH8yU Wz9ys7Z7cbzILEqGiUruDo2+tuLhqnpunJwAsYf7U61fsMfNAOPdtIozNcVuutqo6b N7PP+WS45LgTQ== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 01/19] cpu/hotplug: Clean up cmpxchg() logic in cpuhp_can_boot_ap() Date: Mon, 7 Sep 2026 17:40:04 +0100 Message-ID: <20260907164024.17164-2-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" cpuhp_can_boot_ap() uses atomic_try_cmpxchg() to transition the sync state of the incoming CPU to SYNC_STATE_KICKED. However, this is unnecessary if the state is SYNC_STATE_DEAD, since there will not be any concurrent state modifications, and also if the state is already set to SYNC_STATE_KICKED. Restrict the use of cmpxchg() to the case where the existing state is SYNC_STATE_ALIVE. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- kernel/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/kernel/cpu.c b/kernel/cpu.c index b3c8553d7bd6..198c929c452a 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -408,22 +408,22 @@ static bool cpuhp_can_boot_ap(unsigned int cpu) switch (sync) { case SYNC_STATE_DEAD: /* CPU is properly dead */ + atomic_set(st, SYNC_STATE_KICKED); break; case SYNC_STATE_KICKED: /* CPU did not come up in previous attempt */ break; case SYNC_STATE_ALIVE: /* CPU is stuck cpuhp_ap_sync_alive(). */ + if (!atomic_try_cmpxchg_relaxed(st, &sync, SYNC_STATE_KICKED)) + goto again; break; default: /* CPU failed to report online or dead and is in limbo state. */ return false; } =20 - /* Prepare for booting */ - if (!atomic_try_cmpxchg(st, &sync, SYNC_STATE_KICKED)) - goto again; - + /* Continue with booting */ return true; } =20 --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B849513542 for ; Mon, 7 Sep 2026 16:40:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799242; cv=none; b=LD2TORwErN36hcXdoE/e70D5CPvs96qDe3aCiV6yIN6VCBowHIp4uMkr1A0CpK/RzvwoVv3tAL2Q/Ot79CJpqxJPmFHXzvPOq4yu4DpHnCP9J03nt02s5mNWGSXpwSijUshHsi4CFeGM98zQ/OGD+LZ1XaY5kFEku/uyyCI7VCY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799242; c=relaxed/simple; bh=7fLL46OhSlXLJfTuycNHlvAzCjbTsvU0wCv5wzKp0Ag=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qGPx92P221jI2gWIasfgTOhwbMt6KuQ8yC2IlS/+MoU/zfiR9cHse+bqLxjLeYmYoG98WpwtHue1CGycp+5ju7gdmbkiUZc+GuQYIQAsmpKlbvt81xYuRk8wjz/r9KTBVpaL4e2k8GzYzJjd3x4yz9vRzN4gFKdLbD1OsCyzw+k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fEbnloOv; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fEbnloOv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 986811F00A3A; Mon, 7 Sep 2026 16:40:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799240; bh=G0TnF0EdtSAjs6s5ohnJS7vNK/6l+Z91b6PJOF9Vof0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=fEbnloOv9GjrTNDcDEMqFW38QNNqnZpKB9puUB8QoNObvdlHLcsM81ng0rRPCK1dm utIwFWmbXy/TAaw85mSe61P3d4AlUptqlHawOUo1yba9WbrXaLUDZksEmbqfrST+8n C9w9YCRmxbNVGQ+MOa+x/UnM+losT0dErQofYVEQIR2CMyQVyxwHI5oTGgIVhHHmPW 4pZ3JdZFXC3HvfO8VspXHSva0AjQCfD+j3GgG7+YN8FON4LDgTKn9gYO9GB3jAZH93 AnDVoOIKRrpM+4IlgzNfPFg3wq3gqFM2z0kYR3yy2EIFuJu3yskk42nEoJs5WtzmRF lVZl8OsZD7cUw== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 02/19] cpu/hotplug: Avoid trying to bring up CPUs that are already online Date: Mon, 7 Sep 2026 17:40:05 +0100 Message-ID: <20260907164024.17164-3-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There's little point trying to bring up a CPU that is already online. Although _cpu_up() handles this case by doing nothing (because the target state has already been reached), it's wasted effort when we can easily elide the call to cpu_up() in the first place. Check that the target CPU isn't already online before invoking cpu_up() from cpuhp_bringup_mask(). Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- kernel/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/cpu.c b/kernel/cpu.c index 198c929c452a..97a9bfe4edad 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -1769,7 +1769,8 @@ static void __init cpuhp_bringup_mask(const struct cp= umask *mask, unsigned int n for_each_cpu(cpu, mask) { struct cpuhp_cpu_state *st =3D per_cpu_ptr(&cpuhp_state, cpu); =20 - if (cpu_up(cpu, target) && can_rollback_cpu(st)) { + if (!cpu_online(cpu) && cpu_up(cpu, target) && + can_rollback_cpu(st)) { /* * If this failed then cpu_up() might have only * rolled back to CPUHP_BP_KICK_AP for the final --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21F2451D520 for ; Mon, 7 Sep 2026 16:40:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799245; cv=none; b=qF6J1MWOjH/FJ1IkyCbkk8/KVgpuGSlz4cHm1MlEWmRonn+w/DMEgvYC8au7Ba1s1JYyah4ZoNCSK5SsnQejjJBMm6VzLSq60RZxcaJMSh9WkdhG56ubrR7f9WZlC/7dbyuD+1wo2SHbsKmyB254mcqJqg7sJaRxtO9AKxA4rP0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799245; c=relaxed/simple; bh=F/eIKVxoRM7+eCCK+fTCtxM0onowSoTzMu5Ye07uNJA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ROK6rZkwP2nHtr3Tj8ilr1H/dw22HGOsOSgeruJA2WHYY+mwqH+Vq02jUHkRCVFvZIr90ulpToTsqZMGAF5OyMhm1EFM4DJU40VtWCrW4n839CGmfxplcLu4RXItjtMxMoE7tz49d1lZS0fK/r4mDBVFgATJekA3mS0pAxvHNdk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GqQiwLF6; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GqQiwLF6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A86F1F00A3D; Mon, 7 Sep 2026 16:40:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799243; bh=PaWEgmueo8IVck4dwZ9rseBcFsOQjJHuo9EpQo9RZ2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=GqQiwLF6RV4PV/kPo9LX/Uy9wh7QegNKRRoE7fAt79YnY2JfLZFFZy60iRpZOp5WB tdjgrwZcdhoE1wd/pTZSJfNdGTo8O5ppaUQI4ffmQFR4/9ummYcWOwiO4PJ6CBotNx sHVV8Kg5d3WlkKtpMfEcyWchmhitnmtbqd/ff8eG02835Scub+c5eC+InTP87TQY75 unamOUxBVHNQI1zhqs1SffAPEJF/g1zbbRegcGwI72bhowr2OPT9SgceLYEdAUYk9q vtGYxNdK6m5Fk8UumgaEWP2N9XxlKr2NLJmo4G+Ov2xx7JSi3QK25FPrFpgERLqK3a KEBuXf0R5I3dQ== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 03/19] cpu/hotplug: Avoid busy-polling on archs where cpu_relax() is a no-op Date: Mon, 7 Sep 2026 17:40:06 +0100 Message-ID: <20260907164024.17164-4-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On some architectures (such as arm64), cpu_relax() is effectively a NOP and so isn't particularly efficient when used in a tight polling loop such as the CPU state synchronisation in cpuhp_wait_for_sync_state(). Once an incoming CPU has reached the SYNC_STATE_ALIVE state, we know that it is executing within the kernel and so we can use the more efficient polling mechanism provided by the atomic_cond_read* API. Extend the generic implementation of arch_cpuhp_sync_state_poll() to take the state details as additional parameters and polling using atomic_cond_read_relaxed() instead of cpu_relax() once we have reached the alive state. No change on x86. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/x86/kernel/smpboot.c | 2 +- include/linux/cpuhotplug.h | 2 +- kernel/cpu.c | 13 +++++++++---- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index ba01a9e919b7..362f85cbdbaf 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1138,7 +1138,7 @@ void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) pr_info("CPU %u is now offline\n", cpu); } =20 -void arch_cpuhp_sync_state_poll(void) +void arch_cpuhp_sync_state_poll(atomic_t *st, int old) { if (smp_ops.poll_sync_state) smp_ops.poll_sync_state(); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index feb32949aeea..bbcee650155f 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -509,7 +509,7 @@ static inline void cpuhp_online_idle(enum cpuhp_state s= tate) { } struct task_struct; =20 void cpuhp_ap_sync_alive(void); -void arch_cpuhp_sync_state_poll(void); +void arch_cpuhp_sync_state_poll(atomic_t *st, int old); void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu); int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle); bool arch_cpuhp_init_parallel_bringup(void); diff --git a/kernel/cpu.c b/kernel/cpu.c index 97a9bfe4edad..d9fe204f02cb 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -303,7 +303,13 @@ static inline void cpuhp_ap_update_sync_state(enum cpu= hp_sync_state state) (void)atomic_xchg(st, state); } =20 -void __weak arch_cpuhp_sync_state_poll(void) { cpu_relax(); } +void __weak arch_cpuhp_sync_state_poll(atomic_t *st, int old) +{ + if (old < SYNC_STATE_ALIVE) + cpu_relax(); + else + atomic_cond_read_relaxed(st, VAL !=3D old); +} =20 static bool cpuhp_wait_for_sync_state(unsigned int cpu, enum cpuhp_sync_st= ate state, enum cpuhp_sync_state next_state) @@ -328,7 +334,7 @@ static bool cpuhp_wait_for_sync_state(unsigned int cpu,= enum cpuhp_sync_state st return false; } else if (now - start < NSEC_PER_MSEC) { /* Poll for one millisecond */ - arch_cpuhp_sync_state_poll(); + arch_cpuhp_sync_state_poll(st, sync); } else { usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); } @@ -395,8 +401,7 @@ void cpuhp_ap_sync_alive(void) cpuhp_ap_update_sync_state(SYNC_STATE_ALIVE); =20 /* Wait for the control CPU to release it. */ - while (atomic_read(st) !=3D SYNC_STATE_SHOULD_ONLINE) - cpu_relax(); + atomic_cond_read_acquire(st, VAL =3D=3D SYNC_STATE_SHOULD_ONLINE); } =20 static bool cpuhp_can_boot_ap(unsigned int cpu) --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 180B53F1048 for ; Mon, 7 Sep 2026 16:40:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799249; cv=none; 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a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799246; bh=1trb6sOqqOL4Nzv46ncJB/f9wXUiCIM1M1i+sR/0Dd4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KxGmw1rDW6DoBlnXfG7919mo46pF1j91hFaT2fajfjZ52NazOaNnNUHbofkElmOn3 fqTGBVt7K1L64uB7APqwaZfNer/ZAGm/BDvMd4X7uxjbOW6uFWFSdymFMTTs8K0n5o /WmUzZh16xOL7ZXO8w/aTlJY3prb0maYtHOUVe49XFZYdd9czRDctiymPdRgEviguG a4hD5vyyuaq+TCgRJBhNdEiNrrn0EY8Igb5u3NvYowm5WUotI4hHmG1ORegpovXil5 WRfz1d5bd4SgcR0mnVSRyU7Md+uUa08z8Zi2Siol4TVgoV0Y20PeZXQygQDo0gC4ae GLzyKFRLDK1qA== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 04/19] cpu/hotplug: Propagate bring-up status to arch_cpuhp_cleanup_kick_cpu() Date: Mon, 7 Sep 2026 17:40:07 +0100 Message-ID: <20260907164024.17164-5-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for enabling the generic CPU hotplug machinery on arm64, which has architecture-specific handling of early bringup failures, extend arch_cpuhp_cleanup_kick_cpu() to take an additional argument indicating whether or not the target AP reached the alive state. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/x86/kernel/smpboot.c | 4 ++-- include/linux/cpuhotplug.h | 2 +- kernel/cpu.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 362f85cbdbaf..ce4e8fba5fed 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1074,7 +1074,7 @@ static int do_boot_cpu(u32 apicid, unsigned int cpu, = struct task_struct *idle) =20 /* If the wakeup mechanism failed, cleanup the warm reset vector */ if (ret) - arch_cpuhp_cleanup_kick_cpu(cpu); + arch_cpuhp_cleanup_kick_cpu(cpu, false); return ret; } =20 @@ -1122,7 +1122,7 @@ int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct= task_struct *tidle) return smp_ops.kick_ap_alive(cpu, tidle); } =20 -void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) +void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu, bool is_alive) { /* Cleanup possible dangling ends... */ if (smp_ops.kick_ap_alive =3D=3D native_kick_ap && x86_platform.legacy.wa= rm_reset) diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index bbcee650155f..83ef0c4d8bbe 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -510,7 +510,7 @@ struct task_struct; =20 void cpuhp_ap_sync_alive(void); void arch_cpuhp_sync_state_poll(atomic_t *st, int old); -void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu); +void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu, bool is_alive); int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle); bool arch_cpuhp_init_parallel_bringup(void); =20 diff --git a/kernel/cpu.c b/kernel/cpu.c index d9fe204f02cb..595258e2b6cc 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -432,7 +432,7 @@ static bool cpuhp_can_boot_ap(unsigned int cpu) return true; } =20 -void __weak arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) { } +void __weak arch_cpuhp_cleanup_kick_cpu(unsigned int cpu, bool is_alive) {= } =20 /* * Early CPU bringup synchronization point. Cannot use cpuhp_state::done_up @@ -451,7 +451,7 @@ static int cpuhp_bp_sync_alive(unsigned int cpu) } =20 /* Let the architecture cleanup the kick alive mechanics. */ - arch_cpuhp_cleanup_kick_cpu(cpu); + arch_cpuhp_cleanup_kick_cpu(cpu, !ret); return ret; } #else /* CONFIG_HOTPLUG_CORE_SYNC_FULL */ --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFA8E3537E5 for ; Mon, 7 Sep 2026 16:40:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799251; cv=none; b=RJgP8PKpEFPvMwf01SUcdzIVQF0c4LeUxBXLIl70bviwzsQKrb3M7UM/QRlkuStvGcR1dUouUGKZ12jnSWHMhPiTvVtWoSO1wKL4AZPdX6+0jY4rV5lp9iSYf/Yuc9ylFLw6tVPdiZRYLfCzxPtWDrTKDE9MMzojyTf2UVeGNTo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799251; c=relaxed/simple; bh=ipUAJJcrukKW2d4Wbw2f+Yj6q9MH9fMPDKvTGoFmEs8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Dz4eqmxc94OHBFLrOVj5+KFof8+Mv7MHkS/hOXjktP7BcpagnERy57P/Gj/295rOnsodrM0n5P/oMjLRU1VXbM455vUhm272zqSKRb3aeycrC2v2qDXwxPqxZQjKmYUEi6UGMPuCgy+oN8Pd8taGP/Gsi6j9fY9MXMkvpZCXAzE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jmKzXbtp; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jmKzXbtp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 346321F00A3D; Mon, 7 Sep 2026 16:40:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799249; bh=0a/iC5zjIZl1+yxWZkKQgEAnwYE6tHACp2aQjXaciqo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=jmKzXbtp/XFzVXuQ0ObYir5nG2l4DtxVWqG4ztdZKe/OuMmrnbn+pMu0hbGlXCir2 aJKxp3dmesHH8d+bW1Lew1SSOTBNWUMiBzUV7YgbWb4XaheDHyNvMGZzm1qXvDMHME 7kyh1pNiujEpMmMlRNY3JdMf1dY1QXypQJNeSwlhnYgiOWQ53kCmiPTq7w7oTQtSQ+ brMx+dBmZAbfUOauVcMlVYJtCh+ZSDQrrlf6LFRSGNzMqsSuXj14zgM344yb5EIamd xjv37Y2RsgnlGufseee9IXP27P5Is4MQVTrjtNeADYW7ueUNDZ6CDUZZov8Xf8Hcx3 O7Q+808rBEchg== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 05/19] arm64: smp: Tidy up smp_prepare_cpus() Date: Mon, 7 Sep 2026 17:40:08 +0100 Message-ID: <20260907164024.17164-6-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" smp_prepare_cpus() is always run on the boot CPU (i.e. CPU 0) but goes to great lengths to support running on a CPU where smp_processor_id() is non-zero. Clean up the code a little by hardcoding zero for the boot CPU ID. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm64/kernel/smp.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index a61dc3016a11..ff045080ca1b 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -779,16 +779,14 @@ void __init smp_init_cpus(void) void __init smp_prepare_cpus(unsigned int max_cpus) { const struct cpu_operations *ops; - int err; unsigned int cpu; - unsigned int this_cpu; + int err; =20 init_cpu_topology(); =20 - this_cpu =3D smp_processor_id(); - store_cpu_topology(this_cpu); - numa_store_cpu_info(this_cpu); - numa_add_cpu(this_cpu); + store_cpu_topology(0); + numa_store_cpu_info(0); + numa_add_cpu(0); =20 /* * If UP is mandated by "nosmp" (which implies "maxcpus=3D0"), don't set @@ -803,8 +801,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) * secondaries from the bootloader. */ for_each_possible_cpu(cpu) { - - if (cpu =3D=3D smp_processor_id()) + if (cpu =3D=3D 0) continue; =20 ops =3D get_cpu_ops(cpu); --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B27E451FCA4 for ; Mon, 7 Sep 2026 16:40:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799254; cv=none; b=japAlHwkIPauWtFmHNk2M3JNu9cgym/MqMuh1siaSabb6HkrJ2KHqN/a/FEoQ5BhSA4jNsPNOojRjFCrZrNVlEcx1jTthVXwmFWw4cs9ffp4F0Oq87GASo12lfPNmraH5i45N+lHVbX/K6ZucWCx2YVCyUJLc5VAvLFiZ1pbC30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799254; c=relaxed/simple; bh=LrvXE1raeDbjqxcZRef3F3YWyzEGkfHLlBd1keSAddQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iRefuYHPD2hm9cBlJHnOuzIxcFN3u9gz2ScZZT0rzKR1f/W6jn+YEgUeNktfOGG8beIjTffPDGFUkFr7QkWCuYsW6EPde9sbwXVUsFHzF+uGDK6JZGDj5tsGDxbHr6Sg3Hjy7W8rwwqz/sUzhT9X07jBU/ZxWfHm/uHaOI4u9bQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ATZKoBJ6; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ATZKoBJ6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1478A1F00A3A; Mon, 7 Sep 2026 16:40:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799252; bh=At9LJdU5cgvv7ZJbfKjHKjwlaWl9OU0fIElfasVAlIk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ATZKoBJ6yED1rP5d6J8G3v3sB24Zd+iIkkfd6VIIjXAdkxKL7Iq/Kd6QuqbjOVd5q GBOSIAxxaCK4TCVnMtbvH6at6Wfggfqeokn41oSz9y33aNmrLICEIoVjzFzBzvDRDP AHzpESl2SwUm8TNCuF9XnX/52yNMClhxtdOKnfxTKWXniB706SKnpcOkbqTP2qp+IK Mr6QzXePojRAOTAZDA0DPFmQIi7m/FBDcFOEYMX49H12JBLNzcxzkF9gkC++MZqOKM TiEQSQLVISk/w7oIsbEIU5uGwZBDhFDxSWfIXHFmX/eZZr6xK1yQCBntrBECnkK9Gf GkfCVIfYYf4xQ== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 06/19] arm64: smp: Tidy up cpuinfo init and cpufeature updates Date: Mon, 7 Sep 2026 17:40:09 +0100 Message-ID: <20260907164024.17164-7-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Populating the 'cpuinfo_arm64' structure during CPU bringup and subsequently checking/updating cpufeature structures is slightly convoluted and differs unnecessarily between the boot CPU and secondary CPUs. Rework the code so that cpuinfo_store_cpu() is used to populate the 'cpuinfo_arm64' structure for each CPU, with secondary CPUs then calling update_cpu_features() to update the global view of the available features. This allows us to internalise the 'boot_cpu_data' in cpufeature.c and paves the way for parallelising the ID register probing during bring-up of secondary CPUs. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm64/include/asm/cpu.h | 7 +++---- arch/arm64/kernel/cpufeature.c | 21 +++++++++++++++++---- arch/arm64/kernel/cpuinfo.c | 11 ----------- arch/arm64/kernel/smp.c | 3 ++- 4 files changed, 22 insertions(+), 20 deletions(-) diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index 3c008821219c..733178520c45 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -73,11 +73,10 @@ struct cpuinfo_arm64 { DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data); =20 void cpuinfo_store_cpu(void); -void __init cpuinfo_store_boot_cpu(void); =20 -void __init init_cpu_features(struct cpuinfo_arm64 *info); -void update_cpu_features(int cpu, struct cpuinfo_arm64 *info, - struct cpuinfo_arm64 *boot); +void __init init_cpu_features(void); +void update_cpu_features(int cpu); + bool gmid_el1_accessible(const struct cpuinfo_arm64 *info); =20 #endif /* __ASM_CPU_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 32102c3912fa..33279a264145 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -117,6 +117,7 @@ EXPORT_SYMBOL(system_cpucaps); static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[AR= M64_NCAPS]; =20 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); +static struct cpuinfo_arm64 boot_cpu_data; =20 /* * arm64_use_ng_mappings must be placed in the .data section, otherwise it @@ -1205,11 +1206,19 @@ bool gmid_el1_accessible(const struct cpuinfo_arm64= *info) return mte >=3D ID_AA64PFR1_EL1_MTE_MTE2; } =20 -void __init init_cpu_features(struct cpuinfo_arm64 *info) +void __init init_cpu_features(void) { + struct cpuinfo_arm64 *info =3D &per_cpu(cpu_data, 0); + /* Before we start using the tables, make sure it is sorted */ sort_ftr_regs(); =20 + /* + * We keep a copy of the boot CPU registers so that physical hotplug + * of CPU 0 can still be properly checked. + */ + boot_cpu_data =3D *info; + init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); @@ -1404,12 +1413,14 @@ static int update_32bit_cpu_features(int cpu, struc= t cpuinfo_32bit *info, * non-boot CPU. Also performs SANITY checks to make sure that there * aren't any insane variations from that of the boot CPU. */ -void update_cpu_features(int cpu, - struct cpuinfo_arm64 *info, - struct cpuinfo_arm64 *boot) +void update_cpu_features(int cpu) { + struct cpuinfo_arm64 *boot, *info; int taint =3D 0; =20 + boot =3D &boot_cpu_data; + info =3D per_cpu_ptr(&cpu_data, cpu); + /* * The kernel can handle differing I-cache policies, but otherwise * caches should look identical. Userspace JITs will make use of @@ -3978,6 +3989,8 @@ static void __init setup_boot_cpu_capabilities(void) =20 void __init setup_boot_cpu_features(void) { + init_cpu_features(); + /* * Initialize the indirect array of CPU capabilities pointers before we * handle the boot CPU. diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 45c63f3d75c5..b423301a13cc 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -31,7 +31,6 @@ * values depending on configuration at or after reset. */ DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); -static struct cpuinfo_arm64 boot_cpu_data; =20 static inline const char *icache_policy_str(int l1ip) { @@ -531,14 +530,4 @@ void cpuinfo_store_cpu(void) { struct cpuinfo_arm64 *info =3D this_cpu_ptr(&cpu_data); __cpuinfo_store_cpu(info); - update_cpu_features(smp_processor_id(), info, &boot_cpu_data); -} - -void __init cpuinfo_store_boot_cpu(void) -{ - struct cpuinfo_arm64 *info =3D &per_cpu(cpu_data, 0); - __cpuinfo_store_cpu(info); - - boot_cpu_data =3D *info; - init_cpu_features(&boot_cpu_data); } diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index ff045080ca1b..f4cabf9e19e6 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -235,6 +235,7 @@ asmlinkage notrace void secondary_start_kernel(void) * Log the CPU info before it is marked online and might get read. */ cpuinfo_store_cpu(); + update_cpu_features(cpu); store_cpu_topology(cpu); =20 /* @@ -455,7 +456,7 @@ void __init smp_prepare_boot_cpu(void) */ set_my_cpu_offset(per_cpu_offset(smp_processor_id())); =20 - cpuinfo_store_boot_cpu(); + cpuinfo_store_cpu(); setup_boot_cpu_features(); =20 /* Conditionally switch to GIC PMR for interrupt masking */ --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA20751FCAD for ; Mon, 7 Sep 2026 16:40:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799257; cv=none; b=emJqgcuq2trO3e0KpROas97VdEAoeEZTAx88ckW8BQsdK0ekteWebIW73puamcN8/nk0inaB+jqwEIyq1veb0hWzRlREcp6IHBXKdmop7w88NZff5rpr7EqEV1Dp+TALlDnQHYSylksW4PwRpq8d3n9jo24RaqbfgeOWZXFlQis= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799257; c=relaxed/simple; bh=unB9HLg/A52hjV9RXAp9bO5R7C9p4LOr3SHaG1NcH4U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nMWUGD/ke0DqhgWR46l2OuVKLYNGcxED+BAb9EAcXtDHb2NGx0A+UkQ+W3J7r6nYYAlEr2KRlmlFstmVHdfP9FV1vju1fYrCzTT128FSZwGmx1B2IiR4UJQbkLW09KKZar1BHTQdXgT0otBgAK8HuQT2Ac/FJcwU2JycIf/mbkc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CxoXJiCk; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CxoXJiCk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E69981F00A3D; Mon, 7 Sep 2026 16:40:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799255; bh=puRxUS2/XAPl8zTD4NIPKVxwBIteg8DAERZVvuIbp4I=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=CxoXJiCk9jy52gzQo1fE0/EPtcgByPb2aekDRwGXIUBCStgxq0xf039Huc/1cqpZ/ YdXujKVw/hqR8aIgKejJbvd7qFGnEL++OUIe/88ADEB2AOMdHiMhZKxXzkOTqXd5Tz D6gsZ8VrZ0wht8v2ko5b4tDabq6dTf9py7C9V3OGkKNjyYE38NyXYf0utw3mwJNLnT hH9yGQcAJaBZRjFmGuoAB+8SIUnDp32kyY0QvSMXRewnGqdNdvfqm66J6F+DhSIvIp JlZnBaeK5TUm6kXgbrtk2w31qKGRCfBMUaOhX8Iean3Ry5jL53uXo6LLqS2ihoDgmD W7ErQ0s2ac3vQ== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 07/19] arm64: smp: Defer update of secondary CPU capabilities Date: Mon, 7 Sep 2026 17:40:10 +0100 Message-ID: <20260907164024.17164-8-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" check_local_cpu_capabilities() runs relatively early during the boot of each secondary CPU and, despite its name, calls update_cpu_capabilities() to manipulate the global 'system_cpucaps' based on the features detected by the incoming CPU. In preparation for parallel bringup of secondary CPUs, move the call to update_cpu_capabilities() into update_cpu_features(), allowing check_local_cpu_capabilities() to run concurrently in future, as it now only performs local verification of the incoming CPU. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm64/kernel/cpufeature.c | 311 +++++++++++++++++---------------- 1 file changed, 157 insertions(+), 154 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 33279a264145..fadc36cdff99 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1408,156 +1408,6 @@ static int update_32bit_cpu_features(int cpu, struc= t cpuinfo_32bit *info, return taint; } =20 -/* - * Update system wide CPU feature registers with the values from a - * non-boot CPU. Also performs SANITY checks to make sure that there - * aren't any insane variations from that of the boot CPU. - */ -void update_cpu_features(int cpu) -{ - struct cpuinfo_arm64 *boot, *info; - int taint =3D 0; - - boot =3D &boot_cpu_data; - info =3D per_cpu_ptr(&cpu_data, cpu); - - /* - * The kernel can handle differing I-cache policies, but otherwise - * caches should look identical. Userspace JITs will make use of - * *minLine. - */ - taint |=3D check_update_ftr_reg(SYS_CTR_EL0, cpu, - info->reg_ctr, boot->reg_ctr); - - /* - * Userspace may perform DC ZVA instructions. Mismatched block sizes - * could result in too much or too little memory being zeroed if a - * process is preempted and migrated between CPUs. - */ - taint |=3D check_update_ftr_reg(SYS_DCZID_EL0, cpu, - info->reg_dczid, boot->reg_dczid); - - /* If different, timekeeping will be broken (especially with KVM) */ - taint |=3D check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, - info->reg_cntfrq, boot->reg_cntfrq); - - /* - * The kernel uses self-hosted debug features and expects CPUs to - * support identical debug features. We presently need CTX_CMPs, WRPs, - * and BRPs to be identical. - * ID_AA64DFR1 is currently RES0. - */ - taint |=3D check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, - info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); - taint |=3D check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, - info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); - /* - * Even in big.LITTLE, processors should be identical instruction-set - * wise. - */ - taint |=3D check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, - info->reg_id_aa64isar0, boot->reg_id_aa64isar0); - taint |=3D check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, - info->reg_id_aa64isar1, boot->reg_id_aa64isar1); - taint |=3D check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, - info->reg_id_aa64isar2, boot->reg_id_aa64isar2); - taint |=3D check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, - info->reg_id_aa64isar3, boot->reg_id_aa64isar3); - - /* - * Differing PARange support is fine as long as all peripherals and - * memory are mapped within the minimum PARange of all CPUs. - * Linux should not care about secure memory. - */ - taint |=3D check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, - info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); - taint |=3D check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, - info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); - taint |=3D check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, - info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); - taint |=3D check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, - info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); - taint |=3D check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, - info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); - - taint |=3D check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, - info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); - taint |=3D check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, - info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); - taint |=3D check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, - info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); - - taint |=3D check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, - info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); - - taint |=3D check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, - info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); - - taint |=3D check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, - info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); - - /* Probe vector lengths */ - if (IS_ENABLED(CONFIG_ARM64_SVE) && - id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { - if (!system_capabilities_finalized()) { - unsigned long cpacr =3D cpacr_save_enable_kernel_sve(); - - vec_update_vq_map(ARM64_VEC_SVE); - - cpacr_restore(cpacr); - } - } - - if (IS_ENABLED(CONFIG_ARM64_SME) && - id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { - unsigned long cpacr =3D cpacr_save_enable_kernel_sme(); - - /* Probe vector lengths */ - if (!system_capabilities_finalized()) - vec_update_vq_map(ARM64_VEC_SME); - - cpacr_restore(cpacr); - } - - if (detect_ftr_has_mpam()) { - info->reg_mpamidr =3D read_cpuid(MPAMIDR_EL1); - taint |=3D check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, - info->reg_mpamidr, boot->reg_mpamidr); - } - - /* - * The kernel uses the LDGM/STGM instructions and the number of tags - * they read/write depends on the GMID_EL1.BS field. Check that the - * value is the same on all CPUs. - */ - if (gmid_el1_accessible(info)) - taint |=3D check_update_ftr_reg(SYS_GMID_EL1, cpu, - info->reg_gmid, boot->reg_gmid); - - /* - * If we don't have AArch32 at all then skip the checks entirely - * as the register values may be UNKNOWN and we're not going to be - * using them for anything. - * - * This relies on a sanitised view of the AArch64 ID registers - * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. - */ - if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { - lazy_init_32bit_cpu_features(info, boot); - taint |=3D update_32bit_cpu_features(cpu, &info->aarch32, - &boot->aarch32); - } - - /* - * Mismatched CPU features are a recipe for disaster. Don't even - * pretend to support them. - */ - if (taint) { - pr_warn_once("Unsupported CPU feature variation detected.\n"); - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); - } -} - u64 read_sanitised_ftr_reg(u32 id) { struct arm64_ftr_reg *regp =3D get_arm64_ftr_reg(id); @@ -3902,16 +3752,169 @@ void check_local_cpu_capabilities(void) */ check_early_cpu_features(); =20 + /* + * Verify that this CPU has all the system advertised + * capabilities. + */ + if (system_capabilities_finalized()) + verify_local_cpu_capabilities(); +} + +/* + * Update system wide CPU feature registers with the values from a + * non-boot CPU. Also performs SANITY checks to make sure that there + * aren't any insane variations from that of the boot CPU. + */ +void update_cpu_features(int cpu) +{ + struct cpuinfo_arm64 *boot, *info; + int taint =3D 0; + /* * If we haven't finalised the system capabilities, this CPU gets * a chance to update the errata work arounds and local features. - * Otherwise, this CPU should verify that it has all the system - * advertised capabilities. */ if (!system_capabilities_finalized()) update_cpu_capabilities(SCOPE_LOCAL_CPU); - else - verify_local_cpu_capabilities(); + + boot =3D &boot_cpu_data; + info =3D per_cpu_ptr(&cpu_data, cpu); + + /* + * The kernel can handle differing I-cache policies, but otherwise + * caches should look identical. Userspace JITs will make use of + * *minLine. + */ + taint |=3D check_update_ftr_reg(SYS_CTR_EL0, cpu, + info->reg_ctr, boot->reg_ctr); + + /* + * Userspace may perform DC ZVA instructions. Mismatched block sizes + * could result in too much or too little memory being zeroed if a + * process is preempted and migrated between CPUs. + */ + taint |=3D check_update_ftr_reg(SYS_DCZID_EL0, cpu, + info->reg_dczid, boot->reg_dczid); + + /* If different, timekeeping will be broken (especially with KVM) */ + taint |=3D check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, + info->reg_cntfrq, boot->reg_cntfrq); + + /* + * The kernel uses self-hosted debug features and expects CPUs to + * support identical debug features. We presently need CTX_CMPs, WRPs, + * and BRPs to be identical. + * ID_AA64DFR1 is currently RES0. + */ + taint |=3D check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, + info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); + taint |=3D check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, + info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); + /* + * Even in big.LITTLE, processors should be identical instruction-set + * wise. + */ + taint |=3D check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, + info->reg_id_aa64isar0, boot->reg_id_aa64isar0); + taint |=3D check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, + info->reg_id_aa64isar1, boot->reg_id_aa64isar1); + taint |=3D check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, + info->reg_id_aa64isar2, boot->reg_id_aa64isar2); + taint |=3D check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, + info->reg_id_aa64isar3, boot->reg_id_aa64isar3); + + /* + * Differing PARange support is fine as long as all peripherals and + * memory are mapped within the minimum PARange of all CPUs. + * Linux should not care about secure memory. + */ + taint |=3D check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, + info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); + taint |=3D check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, + info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); + taint |=3D check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, + info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); + taint |=3D check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, + info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); + taint |=3D check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, + info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); + + taint |=3D check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, + info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); + taint |=3D check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, + info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); + taint |=3D check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, + info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); + + taint |=3D check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, + info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); + + taint |=3D check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, + info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); + + taint |=3D check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, + info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); + + /* Probe vector lengths */ + if (IS_ENABLED(CONFIG_ARM64_SVE) && + id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { + if (!system_capabilities_finalized()) { + unsigned long cpacr =3D cpacr_save_enable_kernel_sve(); + + vec_update_vq_map(ARM64_VEC_SVE); + + cpacr_restore(cpacr); + } + } + + if (IS_ENABLED(CONFIG_ARM64_SME) && + id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { + unsigned long cpacr =3D cpacr_save_enable_kernel_sme(); + + /* Probe vector lengths */ + if (!system_capabilities_finalized()) + vec_update_vq_map(ARM64_VEC_SME); + + cpacr_restore(cpacr); + } + + if (detect_ftr_has_mpam()) { + info->reg_mpamidr =3D read_cpuid(MPAMIDR_EL1); + taint |=3D check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, + info->reg_mpamidr, boot->reg_mpamidr); + } + + /* + * The kernel uses the LDGM/STGM instructions and the number of tags + * they read/write depends on the GMID_EL1.BS field. Check that the + * value is the same on all CPUs. + */ + if (gmid_el1_accessible(info)) + taint |=3D check_update_ftr_reg(SYS_GMID_EL1, cpu, + info->reg_gmid, boot->reg_gmid); + + /* + * If we don't have AArch32 at all then skip the checks entirely + * as the register values may be UNKNOWN and we're not going to be + * using them for anything. + * + * This relies on a sanitised view of the AArch64 ID registers + * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. + */ + if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { + lazy_init_32bit_cpu_features(info, boot); + taint |=3D update_32bit_cpu_features(cpu, &info->aarch32, + &boot->aarch32); + } + + /* + * Mismatched CPU features are a recipe for disaster. Don't even + * pretend to support them. + */ + if (taint) { + pr_warn_once("Unsupported CPU feature variation detected.\n"); + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + } } =20 bool this_cpu_has_cap(unsigned int n) --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A395E519914 for ; Mon, 7 Sep 2026 16:40:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799259; cv=none; b=sjhvdeVAMfDZs1SX8lgaoXyNpXO8N844HS/ADMjMcCVlvgSE/o8ngNCEOEhg3RZxT284VhgD7yw891YXUiLJov0G5gkP7yVMnfD5EZvPJSJsYCjjPMnkFRp/BVV02iYdY/kEO5ZOm0ky072qE+uk10cFlNzFCRQU6jSnHsIXNAI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799259; c=relaxed/simple; bh=Cbo7edR0u4Ntl50z+0N6x5hHPp6wTLUe5ca/xMW2TRI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ijxVvLpEpYpKJSceOIxD7Kzlw/NhLYD0X5LsVYNX64Oye2gcj7tbY3nDRtTV/WlrrqOaMBYOW5T0YzZ7rry4FsDn/xeredgB9nZfFcYbWBqQaQXV00ICb4I+FA5j/KNDllSHYhMC2wqciCR10G383ebMLHVCy8KkWjbQhnyOSYk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BhUr78NX; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BhUr78NX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E66F31F00A3A; Mon, 7 Sep 2026 16:40:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799258; bh=sUkfRfE9yNyBzalxMx3/89AuUQW9k7kD7LJuIN09w18=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=BhUr78NXijbJVLVkM69gB/h8NgBlzzcHr8oX4s2y3NPVMtU3IAVjR5zEPMg2NNDCg 2yDO+i3ySKuMyaNqrgNny+n7QrhcmIFNXN641mG2UkkLLZg75XjHHvVVQ03+9MpvZF 33Hl4vWCHOGExdmjdhl0l/FtPRGEwfd8XCHEBUYshKk+WwfhpoUgFX8savPgljwh38 PjvMvAGvblRyQg8huBMuQ78dK0uVDAXHpAFIFdMxUoNpzEcNjp92E+pjXRKA3+tqvZ O10M0mhQum9kPN/+iCPjSmtCfm4lOhGfCTqj/nAw/RAM0FTqSoBeHzgjyvwpR1Reol ItzJNfDrIeqtw== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 08/19] arm64: smp: Don't bother printing the I-cache policy for each CPU Date: Mon, 7 Sep 2026 17:40:11 +0100 Message-ID: <20260907164024.17164-9-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The I-cache policy isn't particularly interesting but printing it early can result in unnecessary serialisation of onlining CPUs. Remove the pointless print. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm64/kernel/cpuinfo.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index b423301a13cc..6dbea3a8bb23 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -31,19 +31,6 @@ * values depending on configuration at or after reset. */ DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); - -static inline const char *icache_policy_str(int l1ip) -{ - switch (l1ip) { - case CTR_EL0_L1Ip_VIPT: - return "VIPT"; - case CTR_EL0_L1Ip_PIPT: - return "PIPT"; - default: - return "RESERVED/UNKNOWN"; - } -} - unsigned long __icache_flags; =20 static const char *const hwcap_str[] =3D { @@ -424,7 +411,6 @@ device_initcall(cpuinfo_regs_init); =20 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) { - unsigned int cpu =3D smp_processor_id(); u32 l1ip =3D CTR_L1IP(info->reg_ctr); =20 switch (l1ip) { @@ -436,8 +422,6 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo= _arm64 *info) set_bit(ICACHEF_ALIASING, &__icache_flags); break; } - - pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu); } =20 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34F4251FCDA for ; Mon, 7 Sep 2026 16:41:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799262; cv=none; b=EUfNwx3GjvZFRZOLXhzRMKkOSORmpl8YoD+afLKk3Y7OTsXtzWmBQIfSuRtPmJpuhYnQVIEOEBSTLHU0vVn4Q9hcqmrq7yrwDis/agyHKck7pvoBtomV/gIqr7wwmckb1dDm14aIOD5OewZ2Zgl6baz+yn1a0i4q0tm7fQZVFQg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799262; c=relaxed/simple; bh=JITq0QqiTospfA3Bb6L55OzvagCVW6EwDv1LU6sYck8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uIW2vr/ISiI+MoVx1UWdJ1b+PJAeyG7sowildbmwYtnViYkejdvN8mREjutlx7x2NKkoVJhKqHPqMdAeehkrINEh7PGRsnf0Q4JhmsXAB5irwo8KexeiN5oYjUDmsbK3t6fPmaHbofyYORDd9ADMyPCsjMYUT1FF+iVOc+N8yQw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mHJZGIiO; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mHJZGIiO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C26031F00A3D; Mon, 7 Sep 2026 16:40:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799261; bh=LJEGgvgnN1hym5yIpfDS0W2oDSWIdSPnh+cxxfZttlQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=mHJZGIiO+b4ld5TXPrhQUYQg1gt+4WRfvj7fDMWLG6LBnRMyU+izkaFl/m/yW1kuR H253JRi5LDDFu++KHhvMqmblxkZ/SjnpQCLFvuLHHDLavXF9/XwiyHZIcMumGWD2Ck OOZdrPq/8OLdXF1PnfUAYZKoISCSg8krsb2P0sgqhtU766Icv8tXH+swRwPYZxr0Zr Q1TGAXkcmCWH6KEAkLIPL67waOSbKCnLA5vnudzF3RJtHcpWMAK9S/AzJhe+8RfBdP roYUzxNulv+rNbZ6+JcPxSAuTwdSCQ5d0kiKbnpwzRu1FPIS9IWmWSMdVUlfpxkBba eaD9GO7sfkusA== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 09/19] arm64: smp: Defer RCU registration during secondary CPU bringup Date: Mon, 7 Sep 2026 17:40:12 +0100 Message-ID: <20260907164024.17164-10-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Calling rcutree_report_cpu_starting() early during boot can lead to livelocks with the generic CPU hotplug mechanism if the boot CPU blocks on an RCU grace period while the CPU being onlined is spinning in cpuhp_ap_sync_alive(). In preparation for enabling the generic CPU hotplug code on arm64, split up the trace_hardirqs_off() call during secondary CPU bringup so that we update lockdep early but defer the tracing updates until after notify_cpu_starting() has registered the new CPU with RCU, allowing us to drop the explicit call to rcutree_report_cpu_starting() entirely. Signed-off-by: Will Deacon --- arch/arm64/kernel/smp.c | 5 ++--- include/linux/rcutree.h | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index f4cabf9e19e6..ff68640d0c0b 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -217,8 +217,7 @@ asmlinkage notrace void secondary_start_kernel(void) if (system_uses_irq_prio_masking()) init_gic_priority_masking(); =20 - rcutree_report_cpu_starting(cpu); - trace_hardirqs_off(); + lockdep_hardirqs_off(CALLER_ADDR0); =20 /* * If the system has established the capabilities, make sure @@ -242,6 +241,7 @@ asmlinkage notrace void secondary_start_kernel(void) * Enable GIC and timers. */ notify_cpu_starting(cpu); + trace_hardirqs_off_finish(); =20 ipi_setup(cpu); =20 @@ -411,7 +411,6 @@ void __noreturn cpu_die_early(void) =20 /* Mark this CPU absent */ set_cpu_present(cpu, 0); - rcutree_report_cpu_dead(); =20 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { update_cpu_boot_status(CPU_KILL_ME); diff --git a/include/linux/rcutree.h b/include/linux/rcutree.h index 16a04202888b..e6ad4f2a475c 100644 --- a/include/linux/rcutree.h +++ b/include/linux/rcutree.h @@ -116,7 +116,7 @@ int rcutree_offline_cpu(unsigned int cpu); =20 void rcutree_migrate_callbacks(int cpu); =20 -/* Called from hotplug and also arm64 early secondary boot failure */ +/* Called from hotplug */ void rcutree_report_cpu_dead(void); =20 #endif /* __LINUX_RCUTREE_H */ --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19391521217 for ; Mon, 7 Sep 2026 16:41:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799265; cv=none; b=rFsxbndz0B66i/TfciRVM2XYpNgzS+wezpdhajy+rrQZjUWBtXs59x6shVSK3lYnNV77TcPwOyv0CMf5qH6irEGi+tUK20tUVDuyBo6IgYd7HzPhmIbzw1pC4eZ29DykMWCPdxI82abMBXNbhMtx41C8CkljTN5ET8oow+w5W3g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799265; c=relaxed/simple; bh=ktl1ZCJhODHxHsQUeJgSo+99QiZHMC2VNxAPOmKVwxQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FQsw4TBCSgpUd0jAy13XbRSjsR4Gsx7mPApu3fJL3xOl2b00eUomk3btD5Rafi8/H12VWSadAlIuxAN0zMH5T+D1dP6ZpXpKItKc0SC1QX2oWkColf2T727x98thhdueqmXCMpHbJyEWP5XTGB1wKEq3Avqe3LPIpwSmlaXVJxQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BIM21oyM; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BIM21oyM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9FE271F00A3A; Mon, 7 Sep 2026 16:41:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799264; bh=yyPYTrxPqUtbU5EZK4JfbBiGHej8C5k7CQFXZsSwctE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=BIM21oyMH2nqDROiqNNT5p3hi0dt+/D7eVoRyGqywawmePz9bjBhhkkq7SvrXrW7K auNkNIG2ZwcrIm8piTh2fH1zINZeRPh3tUKPzj+1byfod28aUmUhU9615HsrrPr5fD 6DmfzlmzdbSUjfE5OvsllyfjL+quIO0Evzpfe/0IAwpkoWIXsiVva9bux0skemtS+R HeN+/f1f8X0cIwDZKbGdlWrPO4gHKutOANOb0+NGJ+83daLleHPpj2kWHmL2tvEBVS HJuScroQaWhJCXsAz+8AhYtMg8TH4Kgws3giK6gvNgrdSsrnK2k+EA6jdZA6SDDbF9 h829IUqAkl03Q== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 10/19] arm64: smp: Use generic HOTPLUG_CORE_SYNC_FULL machinery for CPU onlining Date: Mon, 7 Sep 2026 17:40:13 +0100 Message-ID: <20260907164024.17164-11-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Select HOTPLUG_CORE_SYNC_FULL on arm64 to replace the 'cpu_running' completion with the generic code for synchronising with secondary CPUs during boot. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm64/Kconfig | 2 +- arch/arm64/include/asm/smp.h | 1 - arch/arm64/kernel/smp.c | 39 +++++++++++++++++------------------- 3 files changed, 19 insertions(+), 23 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b5a51b0ef944..89d1f0f2269c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -230,7 +230,7 @@ config ARM64 select HAVE_SYSCALL_TRACEPOINTS select HAVE_KPROBES select HAVE_KRETPROBES - select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU + select HOTPLUG_CORE_SYNC_FULL select HOTPLUG_SMT if HOTPLUG_CPU select IRQ_DOMAIN select IRQ_FORCED_THREADING diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 10ea4f543069..fe343c30d620 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -12,7 +12,6 @@ #define CPU_BOOT_STATUS_MASK ((UL(1) << CPU_STUCK_REASON_SHIFT) - 1) =20 #define CPU_MMU_OFF (-1) -#define CPU_BOOT_SUCCESS (0) /* The cpu invoked ops->cpu_die, synchronise it with cpu_kill */ #define CPU_KILL_ME (1) /* The cpu couldn't die gracefully and is looping in the kernel */ diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index ff68640d0c0b..00362ed6e1ab 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -108,12 +108,9 @@ static int boot_secondary(unsigned int cpu, struct tas= k_struct *idle) return -EOPNOTSUPP; } =20 -static DECLARE_COMPLETION(cpu_running); - int __cpu_up(unsigned int cpu, struct task_struct *idle) { int ret; - long status; =20 /* * We need to tell the secondary core where to find its stack and the @@ -124,27 +121,24 @@ int __cpu_up(unsigned int cpu, struct task_struct *id= le) =20 /* Now bring the CPU into our world */ ret =3D boot_secondary(cpu, idle); - if (ret) { - if (ret !=3D -EPERM) - pr_err("CPU%u: failed to boot: %d\n", cpu, ret); - return ret; - } + if (ret && ret !=3D -EPERM) + pr_err("CPU%u: failed to boot: %d\n", cpu, ret); + return ret; +} =20 - /* - * CPU was successfully started, wait for it to come online or - * time out. - */ - wait_for_completion_timeout(&cpu_running, - msecs_to_jiffies(5000)); - if (cpu_online(cpu)) - return 0; +void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu, bool is_alive) +{ + long status; + + if (is_alive) + return; =20 - pr_crit("CPU%u: failed to come online\n", cpu); secondary_data.task =3D NULL; status =3D READ_ONCE(secondary_data.status); if (status =3D=3D CPU_MMU_OFF) status =3D READ_ONCE(__early_cpu_boot_status); =20 + /* A CPU has failed to boot. Try to figure out what happened. */ switch (status & CPU_BOOT_STATUS_MASK) { default: pr_err("CPU%u: failed in unknown state : 0x%lx\n", @@ -171,8 +165,6 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) case CPU_PANIC_KERNEL: panic("CPU%u detected unsupported configuration\n", cpu); } - - return -EIO; } =20 static void init_gic_priority_masking(void) @@ -234,6 +226,13 @@ asmlinkage notrace void secondary_start_kernel(void) * Log the CPU info before it is marked online and might get read. */ cpuinfo_store_cpu(); + + /* + * Synchronise with the core bringing us online so that it knows + * we made it into the kernel. We're still not 'online'. + */ + cpuhp_ap_sync_alive(); + update_cpu_features(cpu); store_cpu_topology(cpu); =20 @@ -255,9 +254,7 @@ asmlinkage notrace void secondary_start_kernel(void) pr_info("CPU%u: Booted secondary processor 0x%010lx [0x%08x]\n", cpu, (unsigned long)mpidr, read_cpuid_id()); - update_cpu_boot_status(CPU_BOOT_SUCCESS); set_cpu_online(cpu, true); - complete(&cpu_running); =20 /* * Secondary CPUs enter the kernel with all DAIF exceptions masked. --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE0AB52121F for ; Mon, 7 Sep 2026 16:41:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799268; cv=none; b=Mp+ycXDnyZTMf1FuH3SKGCMZSYC3GwlxyQ4nzjx39Mc9X/drS4fn2dRLQafT+FBe0eXrTpxFwAcmW3vBsoG+qL0TGbjR2r8yde0wvY3XwL6EWvitE2jTrvELYYzBT4/WM0RpKXgbJDZpC3szPRvokUocoIC7v7Ikwd4Aud9tUFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799268; c=relaxed/simple; bh=zq1NTUJXe6gRBk7GXPljzwtMW/+LkxPVf5mJuuWkV+E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RcVUL6TqiGpnxakCKD2SXA3WY0EubZ/PePKcI9lBv8QBf3yoFZIvekQcd1fzaxxauV6jtFI8Z4MbNWB2bj1PEfgZcRG/JsXN0sq+NW9MO9L2NUjYSEaQ/GfJTQxMfpdtWdW/z+c0KhkCIFHyAH1uFC6JPR5/zKOkK0ppyJ6BYNE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Cl6u/ywB; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cl6u/ywB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8351E1F00A3F; Mon, 7 Sep 2026 16:41:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799266; bh=IrTLbOTuuMQ4L6f9zvoUGhlf4wkNs5/PIEKC6sIRKzw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Cl6u/ywB2DKdlUfB00LGseaWWQeZTgxCSacs6+G9B2GLgrcRdNqVSfBdgAGDki+cP pRVU96/X2jGIRvB24yRvH7MGvvgLZTne8ceL3es+phtgtgaFn4ylSIgtvJ2mNdN8hM IpZwPAENDmZ5ZkL2k3en4xblqBTjDtOU8SSO4RdVIgAKHGHwVmMau1gVQXLzLxrMIb ev8n+hrFdyud9E7/79AoKY0LUtAVy3lfM1Dgn7Ir3QVGm8QAFgkn4/9yRxKWA7SKm0 l7qslGovC2LRdlg9leogMDNSvgxU5cZfHzjBDKzb+Vd4FZCAaSlLLd96RVyvlPodd9 idk9CX2H4Jujg== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 11/19] arm64: smp: Use generic HOTPLUG_SPLIT_STARTUP machinery for CPU onlining Date: Mon, 7 Sep 2026 17:40:14 +0100 Message-ID: <20260907164024.17164-12-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for enabling parallel bringup of secondary CPUs on arm64, take the baby step of moving from HOTPLUG_CORE_SYNC_FULL to HOTPLUG_SPLIT_STARTUP. Rework the cpu_die_early() path to use a private cpumask, otherwise clearing the incoming CPU from the present mask in the 'kick' stage will prevent the hotplug stage machine from progressing and arch_cpuhp_cleanup_kick_cpu() will not be called. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm64/Kconfig | 2 +- arch/arm64/include/asm/smp.h | 1 + arch/arm64/kernel/smp.c | 9 +++++---- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 89d1f0f2269c..fd8cf792b7fd 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -230,7 +230,7 @@ config ARM64 select HAVE_SYSCALL_TRACEPOINTS select HAVE_KPROBES select HAVE_KRETPROBES - select HOTPLUG_CORE_SYNC_FULL + select HOTPLUG_SPLIT_STARTUP select HOTPLUG_SMT if HOTPLUG_CPU select IRQ_DOMAIN select IRQ_FORCED_THREADING diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index fe343c30d620..7b986a6a765b 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -89,6 +89,7 @@ asmlinkage void secondary_start_kernel(void); struct secondary_data { struct task_struct *task; long status; + cpumask_t cpu_died_early_mask; }; =20 extern struct secondary_data secondary_data; diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 00362ed6e1ab..c5e9d5d5e003 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -62,7 +62,7 @@ * so we need some other way of telling a new secondary core * where to place its SVC stack */ -struct secondary_data secondary_data; +struct secondary_data secondary_data =3D {}; /* Number of CPUs which aren't online, but looping in kernel text. */ static int cpus_stuck_in_kernel; =20 @@ -108,7 +108,7 @@ static int boot_secondary(unsigned int cpu, struct task= _struct *idle) return -EOPNOTSUPP; } =20 -int __cpu_up(unsigned int cpu, struct task_struct *idle) +int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *idle) { int ret; =20 @@ -146,6 +146,8 @@ void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu, bool= is_alive) cpus_stuck_in_kernel++; break; case CPU_KILL_ME: + if (cpumask_test_cpu(cpu, &secondary_data.cpu_died_early_mask)) + set_cpu_present(cpu, false); if (!op_cpu_kill(cpu)) { pr_crit("CPU%u: died during early boot\n", cpu); break; @@ -406,8 +408,7 @@ void __noreturn cpu_die_early(void) =20 pr_crit("CPU%d: will not boot\n", cpu); =20 - /* Mark this CPU absent */ - set_cpu_present(cpu, 0); + cpumask_set_cpu(cpu, &secondary_data.cpu_died_early_mask); =20 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { update_cpu_boot_status(CPU_KILL_ME); --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6924B5221D6 for ; Mon, 7 Sep 2026 16:41:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799272; cv=none; b=tz5YYiAsPJOp9hrOCHZnLfrigaRPmk27larLezPqFYhRPPQoK8hImO+5/hGgV79RB9dR5wOh/868a0mLCklxjlvsapbBRwh64Dys4v3a2SHj+d8T8NKookU7u8pPv5p/2/VHUR1hH6/QYlo3IJ1lBbSLnJsDYkJq3GMhhhSbRVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799272; c=relaxed/simple; bh=N9lnQLkeplkCv1wPilKKijOZP/z6UyXjFuVLPGZlpPg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vn7ANKfNXcxcUg/ZTbfSPBiR+QR9uxR9FZUCZLH8koEkhLo1ll+AQZbZf1cSQlM3T92ZFRRvmfhg6hoaX78qXDcQoa84B/jg/L5n8FgqoIJGunxhpO2I7nzz29ZyBz38gF7AKDvY2WLgyfzo+m1BGPdv8a/ccrbqU/AUtRxjIxA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iOkITSgh; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iOkITSgh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 62F081F00ADB; Mon, 7 Sep 2026 16:41:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799269; bh=vOcosIoOZUylABIr2H2Dhy/0SsM1lRvXoK46nuhzuCs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=iOkITSghGleQZW/uuzPixqRARqkNrb+Gcku9ztKJFGvgPMGdTwTM3VGf67kBXUwvB VHLuMowJNNEC4rw38yEj4iZ0j9yjq7WKSIdAWHl+qUDp1Xo6tl9gKsbSQRSftocDjJ P8QDk2bNG5gWsnRdjAEx9t1NAloDA/AkmHktxDRK1xj7izXzRJciUpKFEt6nU3TBd7 /Q+5ToQHPwvWPLWx6AVZqg2A0J8sPyuworDM0u6tPs0vnlpkwZwPCho7v6sssFfdwT hIJKMyyALF308ik//Ps1QVHGBwStx2Aci6hBKk/JuvE6Cnd7wNGk1SQH5+IqneMK7i HyKZuJpY3Vl8Q== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 12/19] arm64: cpu_ops: Make 'cpu_operations' pointer global instead of per-cpu Date: Mon, 7 Sep 2026 17:40:15 +0100 Message-ID: <20260907164024.17164-13-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" 'cpu_ops' is an NR_CPUS-length array of 'cpu_operations' pointers, which theoretically allows for different CPUs to have different bringup and hotplug backends. In reality, this complexity exists only to deal with the case where CPU0 is not hotpluggable, so replace the array with a single, global pointer and record separately whether or not they apply to the boot CPU. Update the logic in init_cpu_ops() to enforce that only a single set of 'cpu_ops' is required. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm64/kernel/cpu_ops.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c index e133011f64b5..eacfb88a0c0c 100644 --- a/arch/arm64/kernel/cpu_ops.c +++ b/arch/arm64/kernel/cpu_ops.c @@ -20,7 +20,8 @@ extern const struct cpu_operations acpi_parking_protocol_= ops; #endif extern const struct cpu_operations cpu_psci_ops; =20 -static const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init; +static const struct cpu_operations *cpu_ops __ro_after_init; +static bool boot_cpu_has_enable_method __ro_after_init; =20 static const struct cpu_operations *const dt_supported_cpu_ops[] __initcon= st =3D { &smp_spin_table_ops, @@ -40,6 +41,9 @@ static const struct cpu_operations * __init cpu_get_ops(c= onst char *name) { const struct cpu_operations *const *ops; =20 + if (!name) + return NULL; + ops =3D acpi_disabled ? dt_supported_cpu_ops : acpi_supported_cpu_ops; =20 while (*ops) { @@ -49,6 +53,7 @@ static const struct cpu_operations * __init cpu_get_ops(c= onst char *name) ops++; } =20 + pr_warn("Unsupported enable-method: %s\n", name); return NULL; } =20 @@ -94,25 +99,31 @@ static const char *__init cpu_read_enable_method(int cp= u) return enable_method; } /* - * Read a cpu's enable method and record it in cpu_ops. + * Read a cpu's enable method and update/check cpu_ops. */ int __init init_cpu_ops(int cpu) { const char *enable_method =3D cpu_read_enable_method(cpu); + const struct cpu_operations *ops =3D cpu_get_ops(enable_method); =20 - if (!enable_method) + if (!ops) return -ENODEV; =20 - cpu_ops[cpu] =3D cpu_get_ops(enable_method); - if (!cpu_ops[cpu]) { - pr_warn("Unsupported enable-method: %s\n", enable_method); - return -EOPNOTSUPP; - } + if (!cpu_ops) + cpu_ops =3D ops; + else if (cpu_ops !=3D ops) + return -EBUSY; + + if (cpu =3D=3D 0) + boot_cpu_has_enable_method =3D true; =20 return 0; } =20 const struct cpu_operations *get_cpu_ops(int cpu) { - return cpu_ops[cpu]; + if (cpu || boot_cpu_has_enable_method) + return cpu_ops; + + return NULL; } --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5C8E5221C0 for ; Mon, 7 Sep 2026 16:41:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799274; cv=none; b=s5b9SKFJ6hhGKT/C7IjjhYmADgNip0lPqMfWf2u1Nffs+PJbM0KITFusmVtcHMFNKJR4eTDFJQeCbB4NPNvQLcBT0Fkb/XuI4M6Ra7tk519D07brZYVp8TkACy3PJiCEdyBon3EawVQsqdVOU18mOqSiU4GPrN9ZvyQoFwdXNhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799274; c=relaxed/simple; bh=OAJiIKD1N1j/cScevb9eqWToHp4DxASBEb1Rg4Xgxp8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m8WkI3ZTA+5XjSn7jwuP+bFLc+Z3FEVudgHce0xPdAekDqP6N7jhogp8VTqtHhm2RV8MXF3COQzfmIGaEqW14e6XMfeQVgmmeT9tre4Fe/wZZ7KBRIS0OLcMzaw/VyClcIgIXW5LgwaXf0w+KWoCIhbFMJje7kGJC2zFA+ZJr+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NbyzKcmF; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NbyzKcmF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3E38D1F00A3F; Mon, 7 Sep 2026 16:41:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799272; bh=n0w3iQzXGo6gJeBOFFPeG8YoxiowoM54dI9r5vI+0Yg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=NbyzKcmF10RlZINRWL1FRhKqgh0mCjzT7LwUmCoNK4NmCQ3qS70T3ajRbvs37twft LRXpUjYNlMjJPGz9VJEpayDvGqC1V8sfXNb3iuynWiRXAlaHwAk04RWL5O1UbYGvRl BLs4eBgJ2Nf7IZwR/LPB/pkfW9lqjaR9km9B1+LIoqipZ64uS6SW6q8PZ1MzdK+uWd BXMsFu5ChjDJ5bV/n0ZcB2bKKsKLDn1pI9STv6y/swnCu1qhw9nJCzK42dZ8g8AsCi 8znmuefFOlk2NYetnziamWmReI6Kf6BxgSS4Hu/h2YrazFQ0HJlFcOJ/lVU7ORUXtB 4DvX5M/utLrSA== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 13/19] arm64: cpu_ops: Introduce get_secondary_cpu_ops() Date: Mon, 7 Sep 2026 17:40:16 +0100 Message-ID: <20260907164024.17164-14-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce get_secondary_cpu_ops() to retrieve a pointer to the 'cpu_operations' structure for the non-boot CPUs and use it instead of get_cpu_ops() where we are dealing with secondary CPUs. This is a pre-requisite for enabling parallel CPU bring-up. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm64/include/asm/cpu_ops.h | 1 + arch/arm64/kernel/cpu_ops.c | 5 +++++ arch/arm64/kernel/smp.c | 19 +++++++------------ 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_= ops.h index a444c8915e88..cd298a8710d8 100644 --- a/arch/arm64/include/asm/cpu_ops.h +++ b/arch/arm64/include/asm/cpu_ops.h @@ -48,6 +48,7 @@ struct cpu_operations { =20 int __init init_cpu_ops(int cpu); extern const struct cpu_operations *get_cpu_ops(int cpu); +extern const struct cpu_operations *get_secondary_cpu_ops(void); =20 static inline void __init init_bootcpu_ops(void) { diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c index eacfb88a0c0c..7d183ca31dc8 100644 --- a/arch/arm64/kernel/cpu_ops.c +++ b/arch/arm64/kernel/cpu_ops.c @@ -127,3 +127,8 @@ const struct cpu_operations *get_cpu_ops(int cpu) =20 return NULL; } + +const struct cpu_operations *get_secondary_cpu_ops(void) +{ + return cpu_ops; +} diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index c5e9d5d5e003..2e98a92eb764 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -100,7 +100,7 @@ static inline int op_cpu_kill(unsigned int cpu) */ static int boot_secondary(unsigned int cpu, struct task_struct *idle) { - const struct cpu_operations *ops =3D get_cpu_ops(cpu); + const struct cpu_operations *ops =3D get_secondary_cpu_ops(); =20 if (ops->cpu_boot) return ops->cpu_boot(cpu); @@ -220,7 +220,7 @@ asmlinkage notrace void secondary_start_kernel(void) */ check_local_cpu_capabilities(); =20 - ops =3D get_cpu_ops(cpu); + ops =3D get_secondary_cpu_ops(); if (ops->cpu_postboot) ops->cpu_postboot(); =20 @@ -327,7 +327,7 @@ int __cpu_disable(void) =20 static int op_cpu_kill(unsigned int cpu) { - const struct cpu_operations *ops =3D get_cpu_ops(cpu); + const struct cpu_operations *ops =3D get_secondary_cpu_ops(); =20 /* * If we have no means of synchronising with the dying CPU, then assume @@ -368,7 +368,7 @@ void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) void __noreturn cpu_die(void) { unsigned int cpu =3D smp_processor_id(); - const struct cpu_operations *ops =3D get_cpu_ops(cpu); + const struct cpu_operations *ops =3D get_secondary_cpu_ops(); =20 idle_task_exit(); =20 @@ -492,7 +492,7 @@ static int __init smp_cpu_setup(int cpu) if (init_cpu_ops(cpu)) return -ENODEV; =20 - ops =3D get_cpu_ops(cpu); + ops =3D get_secondary_cpu_ops(); if (ops->cpu_init(cpu)) return -ENODEV; =20 @@ -776,7 +776,7 @@ void __init smp_init_cpus(void) =20 void __init smp_prepare_cpus(unsigned int max_cpus) { - const struct cpu_operations *ops; + const struct cpu_operations *ops =3D get_secondary_cpu_ops(); unsigned int cpu; int err; =20 @@ -802,10 +802,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) if (cpu =3D=3D 0) continue; =20 - ops =3D get_cpu_ops(cpu); - if (!ops) - continue; - err =3D ops->cpu_prepare(cpu); if (err) continue; @@ -1341,8 +1337,7 @@ bool smp_crash_stop_failed(void) static bool have_cpu_die(void) { #ifdef CONFIG_HOTPLUG_CPU - int any_cpu =3D raw_smp_processor_id(); - const struct cpu_operations *ops =3D get_cpu_ops(any_cpu); + const struct cpu_operations *ops =3D get_secondary_cpu_ops(); =20 if (ops && ops->cpu_die) return true; --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8ABC15221E9 for ; Mon, 7 Sep 2026 16:41:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799277; cv=none; b=DAnMO9/Qq7wz4x/zrw71yjDZNcScX0Nllh+f0MR7nOkjLLJX9DtKGcbY68mutSS0yguz49HcVo6Sy8sYrIZA0uG9Fpyr9zO4QnscngEJ2ixzexSB4Stp02Y/qq5KruUFQVpsiVN2mlE1rNL9DT1Lv1g9oN9Jc3z2ddiQ8WladA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799277; c=relaxed/simple; bh=FXk4Y6n0MApbau7HM+JsM6nsUK9vl07kcs2O3VY89uw=; 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charset="utf-8" Secure monitor calls to EL3 aren't necessarily cheap, so cache the PSCI version number in memory to avoid asking firmware the same question over and over again. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- drivers/firmware/psci/psci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/psci/psci.c b/drivers/firmware/psci/psci.c index e73bae6cb23a..8bb3f7c37678 100644 --- a/drivers/firmware/psci/psci.c +++ b/drivers/firmware/psci/psci.c @@ -155,7 +155,12 @@ static u32 psci_0_1_get_version(void) =20 static u32 psci_0_2_get_version(void) { - return invoke_psci_fn(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0); + static u32 version; + + if (unlikely(!version)) + version =3D invoke_psci_fn(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0); + + return version; } =20 int psci_set_osi_mode(bool enable) --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5E685221DA for ; Mon, 7 Sep 2026 16:41:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799280; cv=none; b=mSDbxeyhMq2mvVqRfPCwrv6i/sIjnHkiSo0YjBdqGc9iZNoWsur8d4k6oaUputoub5VAb+PXQ9uaiA87m54W2wST37v2ITvN6buiLaGXLXkaFsSM3tJXCaLE/P+BfHAUoBAj3xfcki+L8Ee1T3MBZwOuHTEMztg1OXBfz9Gd+w4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799280; c=relaxed/simple; bh=bgPTGnCWVvoxUpLPi2BHrsmzBJzjQX+F6enuRclaGIk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kykta1t7B1y6sgFXNmLCbwrgA9eSv3+BOr80bDdWyAa2zRyZ5O0/1CUwV3CTXoIqxgpx7ePjdj5yaRVTclD588T9T/nauy0VfiDwdaXXXnTWlXvmkd+WzpWmqI2YiuBbxAYUIcS+uJrtn3ioY1WjKrn8JKNXjJZ3QkLDUV1dlqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FohXLra+; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FohXLra+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F06C01F00A3D; Mon, 7 Sep 2026 16:41:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799278; bh=lKt/YMXkeUnOCkc123JiDnkKWT5tbgOcytIjHv2aWXo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=FohXLra+DVZLcaftbKCZPtZXj75Il8RfpJfE/b4/L1kSMIjeDZJQfv0iCN4tN0J14 rW3Ztyp1IwbHYYjnzv+lY2w+6KDDrGhMIJIKPD11I3oC/pIiGOI/HC7FABjgEUZfhE IoSYozs4+sknPsukoWn71BE06yGgakEWc2Vh7n/p4LKEbCl3nYysRw/8iWYOEoAwUD GUigPhlmj+pInbXIs4heHnDWM1Mz8d3PqqkW4rP4FV9gFl+e1cA0pHSw2G0IBtkvpJ kbuuqVvAtowqFkqb2QBFxVEQa+DyYUcBcD5v1MVCfkEfmvdRb8GLl4puqsHAHt98NE TOxUTZIqyqYDw== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 15/19] firmware/psci: Extend ->cpu_on() callback to take an additional argument Date: Mon, 7 Sep 2026 17:40:18 +0100 Message-ID: <20260907164024.17164-16-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for hooking up the 'context ID' parameter introduced by PSCI v0.2 to the CPU_ON call, extend the ->cpu_on() callback to take an additional argument and modify all callers to pass 0 for now. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm/kernel/psci_smp.c | 4 ++-- arch/arm64/kernel/psci.c | 2 +- drivers/firmware/psci/psci.c | 20 ++++++++++++++------ include/linux/psci.h | 3 ++- 4 files changed, 19 insertions(+), 10 deletions(-) diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c index 3bb0c4dcfc5c..bf05dbf433b1 100644 --- a/arch/arm/kernel/psci_smp.c +++ b/arch/arm/kernel/psci_smp.c @@ -49,10 +49,10 @@ static int psci_boot_secondary(unsigned int cpu, struct= task_struct *idle) return psci_ops.cpu_on(cpu_logical_map(cpu), ((phys_addr_t)(&secondary_startup) - XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) - + CONFIG_XIP_PHYS_ADDR)); + + CONFIG_XIP_PHYS_ADDR), 0); #else return psci_ops.cpu_on(cpu_logical_map(cpu), - virt_to_idmap(&secondary_startup)); + virt_to_idmap(&secondary_startup), 0); #endif return -ENODEV; } diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c index fabd732d0a2d..6b25a12ed143 100644 --- a/arch/arm64/kernel/psci.c +++ b/arch/arm64/kernel/psci.c @@ -39,7 +39,7 @@ static int __init cpu_psci_cpu_prepare(unsigned int cpu) static int cpu_psci_cpu_boot(unsigned int cpu) { phys_addr_t pa_secondary_entry =3D __pa_symbol(secondary_entry); - int err =3D psci_ops.cpu_on(cpu_logical_map(cpu), pa_secondary_entry); + int err =3D psci_ops.cpu_on(cpu_logical_map(cpu), pa_secondary_entry, 0); if (err && err !=3D -EPERM) pr_err("failed to boot CPU%d (%d)\n", cpu, err); =20 diff --git a/drivers/firmware/psci/psci.c b/drivers/firmware/psci/psci.c index 8bb3f7c37678..95034485cb4d 100644 --- a/drivers/firmware/psci/psci.c +++ b/drivers/firmware/psci/psci.c @@ -219,22 +219,30 @@ static int psci_0_2_cpu_off(u32 state) return __psci_cpu_off(PSCI_0_2_FN_CPU_OFF, state); } =20 -static int __psci_cpu_on(u32 fn, unsigned long cpuid, unsigned long entry_= point) +static int __psci_cpu_on(u32 fn, unsigned long cpuid, unsigned long entry_= point, + unsigned long context) { int err; =20 - err =3D invoke_psci_fn(fn, cpuid, entry_point, 0); + err =3D invoke_psci_fn(fn, cpuid, entry_point, context); return psci_to_linux_errno(err); } =20 -static int psci_0_1_cpu_on(unsigned long cpuid, unsigned long entry_point) +static int psci_0_1_cpu_on(unsigned long cpuid, unsigned long entry_point, + unsigned long mbz) { - return __psci_cpu_on(psci_0_1_function_ids.cpu_on, cpuid, entry_point); + if (mbz) + return -EINVAL; + + return __psci_cpu_on(psci_0_1_function_ids.cpu_on, cpuid, entry_point, + 0); } =20 -static int psci_0_2_cpu_on(unsigned long cpuid, unsigned long entry_point) +static int psci_0_2_cpu_on(unsigned long cpuid, unsigned long entry_point, + unsigned long context) { - return __psci_cpu_on(PSCI_FN_NATIVE(0_2, CPU_ON), cpuid, entry_point); + return __psci_cpu_on(PSCI_FN_NATIVE(0_2, CPU_ON), cpuid, entry_point, + context); } =20 static int __psci_migrate(u32 fn, unsigned long cpuid) diff --git a/include/linux/psci.h b/include/linux/psci.h index 4ca0060a3fc4..0f43868a0bee 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -25,7 +25,8 @@ struct psci_operations { u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); int (*cpu_off)(u32 state); - int (*cpu_on)(unsigned long cpuid, unsigned long entry_point); + int (*cpu_on)(unsigned long cpuid, unsigned long entry_point, + unsigned long context); int (*migrate)(unsigned long cpuid); int (*affinity_info)(unsigned long target_affinity, unsigned long lowest_affinity_level); --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37A165237A2 for ; Mon, 7 Sep 2026 16:41:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799282; cv=none; b=m40jFG+qRNhx7lFDmSdfSwrmBqXVNPYlQVQVKgNdze6hlaud+4ESvQMzu/howDaPSxfCA3h6IctlvbgzHHPwYyTtLcY+3pqmWoNNwybUWJM9yoUTeQIz2xBcSsd/ay570wzdJnEypQFr667xxEgjdIjDJx3s1IBOV79wGgcYoG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799282; c=relaxed/simple; bh=bg2LtBOiInFvsUQT6RFJe0ZifqG9J3M2uZ08FcfT3C8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" Some backend implementations of 'struct cpu_ops', notably PSCI v0.2+, allow an optional argument to be passed in register X0 to the target CPU during boot. Expose this functionality by extending the ->cpu_boot() CPU operation to take an additional argument which is ignored unless the new optional ->cpu_boot_has_arg() callback is present and returns 'true'. For now, we continue to pass zero. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm64/include/asm/cpu_ops.h | 6 +++++- arch/arm64/kernel/acpi_parking_protocol.c | 3 ++- arch/arm64/kernel/psci.c | 11 +++++++++-- arch/arm64/kernel/smp.c | 2 +- arch/arm64/kernel/smp_spin_table.c | 2 +- 5 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_= ops.h index cd298a8710d8..e7662a1879d9 100644 --- a/arch/arm64/include/asm/cpu_ops.h +++ b/arch/arm64/include/asm/cpu_ops.h @@ -21,6 +21,9 @@ * mechanism for doing so, tests whether it is possible to boot * the given CPU. * @cpu_boot: Boots a cpu into the kernel. + * @cpu_boot_has_arg: Optionally determines whether @cpu_boot passes its + * (non-zero) second argument to the booting CPU in + * register x0. * @cpu_postboot: Optionally, perform any post-boot cleanup or necessary * synchronisation. Called from the cpu being booted. * @cpu_can_disable: Determines whether a CPU can be disabled based on @@ -36,7 +39,8 @@ struct cpu_operations { const char *name; int (*cpu_init)(unsigned int); int (*cpu_prepare)(unsigned int); - int (*cpu_boot)(unsigned int); + int (*cpu_boot)(unsigned int, unsigned long); + bool (*cpu_boot_has_arg)(void); void (*cpu_postboot)(void); #ifdef CONFIG_HOTPLUG_CPU bool (*cpu_can_disable)(unsigned int cpu); diff --git a/arch/arm64/kernel/acpi_parking_protocol.c b/arch/arm64/kernel/= acpi_parking_protocol.c index e1be29e608b7..24ebde1241bf 100644 --- a/arch/arm64/kernel/acpi_parking_protocol.c +++ b/arch/arm64/kernel/acpi_parking_protocol.c @@ -56,7 +56,8 @@ static int acpi_parking_protocol_cpu_prepare(unsigned int= cpu) return 0; } =20 -static int acpi_parking_protocol_cpu_boot(unsigned int cpu) +static int acpi_parking_protocol_cpu_boot(unsigned int cpu, + unsigned long ignored) { struct cpu_mailbox_entry *cpu_entry =3D &cpu_mailbox_entries[cpu]; struct parking_protocol_mailbox __iomem *mailbox; diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c index 6b25a12ed143..3ba4fa14b9e3 100644 --- a/arch/arm64/kernel/psci.c +++ b/arch/arm64/kernel/psci.c @@ -36,16 +36,22 @@ static int __init cpu_psci_cpu_prepare(unsigned int cpu) return 0; } =20 -static int cpu_psci_cpu_boot(unsigned int cpu) +static int cpu_psci_cpu_boot(unsigned int cpu, unsigned long context) { phys_addr_t pa_secondary_entry =3D __pa_symbol(secondary_entry); - int err =3D psci_ops.cpu_on(cpu_logical_map(cpu), pa_secondary_entry, 0); + int err =3D psci_ops.cpu_on(cpu_logical_map(cpu), pa_secondary_entry, + context); if (err && err !=3D -EPERM) pr_err("failed to boot CPU%d (%d)\n", cpu, err); =20 return err; } =20 +static bool cpu_psci_cpu_boot_has_context(void) +{ + return psci_ops.get_version() >=3D PSCI_VERSION(0, 2); +} + #ifdef CONFIG_HOTPLUG_CPU static bool cpu_psci_cpu_can_disable(unsigned int cpu) { @@ -114,6 +120,7 @@ const struct cpu_operations cpu_psci_ops =3D { .cpu_init =3D cpu_psci_cpu_init, .cpu_prepare =3D cpu_psci_cpu_prepare, .cpu_boot =3D cpu_psci_cpu_boot, + .cpu_boot_has_arg =3D cpu_psci_cpu_boot_has_context, #ifdef CONFIG_HOTPLUG_CPU .cpu_can_disable =3D cpu_psci_cpu_can_disable, .cpu_disable =3D cpu_psci_cpu_disable, diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 2e98a92eb764..b57f8f752f78 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -103,7 +103,7 @@ static int boot_secondary(unsigned int cpu, struct task= _struct *idle) const struct cpu_operations *ops =3D get_secondary_cpu_ops(); =20 if (ops->cpu_boot) - return ops->cpu_boot(cpu); + return ops->cpu_boot(cpu, 0); =20 return -EOPNOTSUPP; } diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spi= n_table.c index 49029eace3ad..a5e6f444c25f 100644 --- a/arch/arm64/kernel/smp_spin_table.c +++ b/arch/arm64/kernel/smp_spin_table.c @@ -104,7 +104,7 @@ static int smp_spin_table_cpu_prepare(unsigned int cpu) return 0; } =20 -static int smp_spin_table_cpu_boot(unsigned int cpu) +static int smp_spin_table_cpu_boot(unsigned int cpu, unsigned long ignored) { /* * Update the pen release flag. --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 131FB5221DA for ; Mon, 7 Sep 2026 16:41:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" In preparation for parallel bringup of secondary CPUs, the global 'secondary_data' structure used for initial paramater passing must be localised. Pass the idle 'task_struct' pointer for secondary CPUs directly to ->cpu_boot() if the backend supports it. Signed-off-by: Will Deacon Reviewed-by: Jinjie Ruan --- arch/arm64/include/asm/smp.h | 1 + arch/arm64/kernel/head.S | 12 +++++++++++- arch/arm64/kernel/psci.c | 4 ++-- arch/arm64/kernel/smp.c | 25 +++++++++++-------------- 4 files changed, 25 insertions(+), 17 deletions(-) diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 7b986a6a765b..7f2cd84b7785 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -95,6 +95,7 @@ struct secondary_data { extern struct secondary_data secondary_data; extern long __early_cpu_boot_status; extern void secondary_entry(void); +extern void secondary_entry_with_arg(void); =20 extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 87a822e5c4ca..17868b497d7c 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -335,6 +335,7 @@ SYM_FUNC_END(init_kernel_el) * cores are held until we're ready for them to initialise. */ SYM_FUNC_START(secondary_holding_pen) + mov x19, xzr mov x0, xzr bl init_kernel_el // w0=3Dcpu_boot_mode mrs x2, mpidr_el1 @@ -353,10 +354,16 @@ SYM_FUNC_END(secondary_holding_pen) * be used where CPUs are brought online dynamically by the kernel. */ SYM_FUNC_START(secondary_entry) + mov x0, xzr + b secondary_entry_with_arg +SYM_FUNC_END(secondary_entry) + +SYM_FUNC_START(secondary_entry_with_arg) + mov x19, x0 mov x0, xzr bl init_kernel_el // w0=3Dcpu_boot_mode b secondary_startup -SYM_FUNC_END(secondary_entry) +SYM_FUNC_END(secondary_entry_with_arg) =20 SYM_FUNC_START_LOCAL(secondary_startup) /* @@ -391,10 +398,13 @@ SYM_FUNC_START_LOCAL(__secondary_switched) msr vbar_el1, x5 isb =20 + mov x2, x19 + cbnz x2, 1f adr_l x0, secondary_data ldr x2, [x0, #CPU_BOOT_TASK] cbz x2, __secondary_too_slow =20 +1: init_cpu_task x2, x1, x3 =20 #ifdef CONFIG_ARM64_PTR_AUTH diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c index 3ba4fa14b9e3..c13e635e8a11 100644 --- a/arch/arm64/kernel/psci.c +++ b/arch/arm64/kernel/psci.c @@ -38,8 +38,8 @@ static int __init cpu_psci_cpu_prepare(unsigned int cpu) =20 static int cpu_psci_cpu_boot(unsigned int cpu, unsigned long context) { - phys_addr_t pa_secondary_entry =3D __pa_symbol(secondary_entry); - int err =3D psci_ops.cpu_on(cpu_logical_map(cpu), pa_secondary_entry, + void *entry_va =3D context ? secondary_entry_with_arg : secondary_entry; + int err =3D psci_ops.cpu_on(cpu_logical_map(cpu), __pa_symbol(entry_va), context); if (err && err !=3D -EPERM) pr_err("failed to boot CPU%d (%d)\n", cpu, err); diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index b57f8f752f78..95d5328c3f5a 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -93,34 +93,31 @@ static inline int op_cpu_kill(unsigned int cpu) } #endif =20 - /* * Boot a secondary CPU, and assign it the specified idle task. * This also gives us the initial stack to use for this CPU. */ -static int boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - const struct cpu_operations *ops =3D get_secondary_cpu_ops(); - - if (ops->cpu_boot) - return ops->cpu_boot(cpu, 0); - - return -EOPNOTSUPP; -} - int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *idle) { - int ret; + const struct cpu_operations *ops =3D get_secondary_cpu_ops(); + int ret =3D -EOPNOTSUPP; + void *arg =3D NULL; =20 /* * We need to tell the secondary core where to find its stack and the * page tables. */ - secondary_data.task =3D idle; + if (ops->cpu_boot_has_arg && ops->cpu_boot_has_arg()) + arg =3D idle; + else + secondary_data.task =3D idle; + update_cpu_boot_status(CPU_MMU_OFF); =20 /* Now bring the CPU into our world */ - ret =3D boot_secondary(cpu, idle); + if (ops->cpu_boot) + ret =3D ops->cpu_boot(cpu, (unsigned long)arg); + if (ret && ret !=3D -EPERM) pr_err("CPU%u: failed to boot: %d\n", cpu, ret); return ret; --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E152B524AED for ; Mon, 7 Sep 2026 16:41:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799288; cv=none; b=FtCtE2ADhwlvDyQo6AK4m1YFrjmcCe3G45pXYXhVLMax4QLBRfuWrRy8q+Au+LjucC1jkKuAhxGsxpOYihz0PuJEUrTCDcf/O01F6ijIDze7XCvi/rtAxE4xCRgoy55chw+GJxO5xmdqVjpTNQDTuuG1Q/abbG/PJjOGiQUlrwc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799288; c=relaxed/simple; bh=Hbfz4D+KE8aJfVBAhc2XsoSSEZJ6mfkNmWmxvv4ytPo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gMqAsq3h8L0gHABekJ8eHhnLzGXlBJL5zh7vNqFxur77rBSONcp2p8mrHalvPT3P8BeLL8nnGMA7EYwqLvjopD1vGUtiYwkRKOg8z2PlYbcjEdbz8QPgjRPx/KlJESBxLnqk7+adMsGj9MoqabP+l3ImPXLE2Yy8Zm0ErdhiX6I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IpuGX1WI; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IpuGX1WI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7B3E71F00A3D; Mon, 7 Sep 2026 16:41:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799286; bh=TS0d+Qcb5U7cCVHfErBywRPREk4NWc1936JWNuG9+Kw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=IpuGX1WImTGcOp6VG3QT4xD/Suwr3ntAXeUskBtmTO+PpDhkAaadE8qJiXTbiUZb0 B5+3I17hPKRTOB5jxlYF28DRVRfbjAVVhyefFEg0/dfEo9ljuj5iNtUnrrUqtfh01J gXxmw/MwSNkgqL5FA7TePJP57V9kDRS4+zMKBwW1HXuvjbAS/jEMI4pLrORMf9Nlfk 2dZ47ElPWL3gjFHor6Y/bQJWJ1f7ILld0Sdv2/niR8zVq+rjqQk4ozYqnwqhkhyy7W bYj1tO5rmc6XVR0hnaUKdNxqMCOLjjW1eir3Gu3HBUxvrjWqXT9PL+wIfL8Sbl6Fc4 wp7D/llYIZJXQ== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 18/19] arm64: smp: Use generic HOTPLUG_PARALLEL machinery for CPU onlining Date: Mon, 7 Sep 2026 17:40:21 +0100 Message-ID: <20260907164024.17164-19-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make the move from HOTPLUG_SPLIT_STARTUP to HOTPLUG_PARALLEL and enable parallel CPU bringup on systems with PSCI v0.2 or later. The fiddly part of all this is the error handling if a CPU fails to come up, as we can no longer rely on a single global 'status' flag to capture the details. Instead, the secondary_data::status field is replaced with a zero-initialised byte array, with each byte representing an error reason, so the total set of failures can be accurately captured by the primary CPU. Signed-off-by: Will Deacon --- arch/arm64/Kconfig | 2 +- arch/arm64/include/asm/smp.h | 35 +++++++------ arch/arm64/include/asm/topology.h | 2 + arch/arm64/kernel/head.S | 15 +++--- arch/arm64/kernel/smp.c | 81 ++++++++++++++++--------------- arch/arm64/mm/mmu.c | 2 +- 6 files changed, 72 insertions(+), 65 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fd8cf792b7fd..8d963cec7189 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -230,7 +230,7 @@ config ARM64 select HAVE_SYSCALL_TRACEPOINTS select HAVE_KPROBES select HAVE_KRETPROBES - select HOTPLUG_SPLIT_STARTUP + select HOTPLUG_PARALLEL select HOTPLUG_SMT if HOTPLUG_CPU select IRQ_DOMAIN select IRQ_FORCED_THREADING diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 7f2cd84b7785..3decb42164aa 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -7,20 +7,15 @@ =20 #include =20 -/* Values for secondary_data.status */ -#define CPU_STUCK_REASON_SHIFT (8) -#define CPU_BOOT_STATUS_MASK ((UL(1) << CPU_STUCK_REASON_SHIFT) - 1) +/* Offsets for early CPU boot reasons */ +#define EARLY_CPU_STUCK_REASON_52_BIT_VA (0) +#define EARLY_CPU_STUCK_REASON_NO_GRAN (1) +#define EARLY_CPU_STUCK_REASON_MAX (2) =20 -#define CPU_MMU_OFF (-1) -/* The cpu invoked ops->cpu_die, synchronise it with cpu_kill */ -#define CPU_KILL_ME (1) -/* The cpu couldn't die gracefully and is looping in the kernel */ -#define CPU_STUCK_IN_KERNEL (2) +/* Offsets for late (i.e. MMU-enabled) CPU boot reasons */ /* Fatal system error detected by secondary CPU, crash the system */ -#define CPU_PANIC_KERNEL (3) - -#define CPU_STUCK_REASON_52_BIT_VA (UL(1) << CPU_STUCK_REASON_SHIFT) -#define CPU_STUCK_REASON_NO_GRAN (UL(2) << CPU_STUCK_REASON_SHIFT) +#define CPU_PANIC_KERNEL (0) +#define CPU_STATUS_FLAGS_MAX (1) =20 #ifndef __ASSEMBLER__ =20 @@ -81,6 +76,14 @@ static inline void set_smp_ipi_range(int ipi_base, int n) */ asmlinkage void secondary_start_kernel(void); =20 +union secondary_status { + u64 val; + union { + u8 flags[CPU_STATUS_FLAGS_MAX]; + u8 early_flags[EARLY_CPU_STUCK_REASON_MAX]; + }; +}; + /* * Initial data for bringing up a secondary CPU. * @status - Result passed back from the secondary CPU to @@ -88,7 +91,7 @@ asmlinkage void secondary_start_kernel(void); */ struct secondary_data { struct task_struct *task; - long status; + union secondary_status status; cpumask_t cpu_died_early_mask; }; =20 @@ -123,9 +126,11 @@ static inline void __noreturn cpu_park_loop(void) } } =20 -static inline void update_cpu_boot_status(int val) +static inline void update_cpu_boot_status(const unsigned int val) { - WRITE_ONCE(secondary_data.status, val); + BUILD_BUG_ON(val >=3D CPU_STATUS_FLAGS_MAX); + + WRITE_ONCE(secondary_data.status.flags[val], 1); /* Ensure the visibility of the status update */ dsb(ishst); } diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/top= ology.h index b9eaf4ad7085..f1ff9e40b7cd 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -41,4 +41,6 @@ void update_freq_counters_refs(void); =20 #include =20 +#define cpu_primary_thread_mask cpu_none_mask + #endif /* _ASM_ARM_TOPOLOGY_H */ diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 17868b497d7c..bec4bc1b12db 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -393,7 +393,6 @@ SYM_FUNC_START_LOCAL(__secondary_switched) mov x0, x20 bl finalise_el2 =20 - str_l xzr, __early_cpu_boot_status, x3 adr_l x5, vectors msr vbar_el1, x5 isb @@ -439,15 +438,15 @@ SYM_FUNC_END(set_cpu_boot_mode_flag) * with MMU turned off. * * update_early_cpu_boot_status tmp, status - * - Corrupts tmp1, tmp2 - * - Writes 'status' to __early_cpu_boot_status and makes sure + * - Corrupts tmp1 + * - Writes 1 to the 'status' field of __early_cpu_boot_status and makes = sure * it is committed to memory. */ =20 .macro update_early_cpu_boot_status status, tmp1, tmp2 - mov \tmp2, #\status adr_l \tmp1, __early_cpu_boot_status - str \tmp2, [\tmp1] + mov \tmp2, #1 + strb w\tmp2, [\tmp1, #\status] dmb sy dc ivac, \tmp1 // Invalidate potentially stale cache line .endm @@ -495,8 +494,7 @@ SYM_FUNC_START(__cpu_secondary_check52bitva) b.ge 2f #endif =20 - update_early_cpu_boot_status \ - CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1 + update_early_cpu_boot_status EARLY_CPU_STUCK_REASON_52_BIT_VA, x0, x1 1: wfe wfi b 1b @@ -507,8 +505,7 @@ SYM_FUNC_END(__cpu_secondary_check52bitva) =20 SYM_FUNC_START_LOCAL(__no_granule_support) /* Indicate that this CPU can't boot and is stuck in the kernel */ - update_early_cpu_boot_status \ - CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2 + update_early_cpu_boot_status EARLY_CPU_STUCK_REASON_NO_GRAN, x1, x2 1: wfe wfi diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 95d5328c3f5a..d5da44949671 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -64,7 +64,7 @@ */ struct secondary_data secondary_data =3D {}; /* Number of CPUs which aren't online, but looping in kernel text. */ -static int cpus_stuck_in_kernel; +static bool cpus_stuck_in_kernel; =20 static int ipi_irq_base __ro_after_init; static int nr_ipi __ro_after_init =3D NR_IPI; @@ -93,6 +93,18 @@ static inline int op_cpu_kill(unsigned int cpu) } #endif =20 +static bool smp_parallel_bringup; + +bool arch_cpuhp_init_parallel_bringup(void) +{ + const struct cpu_operations *ops =3D get_secondary_cpu_ops(); + + smp_parallel_bringup =3D ops && + ops->cpu_boot_has_arg && + ops->cpu_boot_has_arg(); + return smp_parallel_bringup; +} + /* * Boot a secondary CPU, and assign it the specified idle task. * This also gives us the initial stack to use for this CPU. @@ -107,13 +119,11 @@ int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct= task_struct *idle) * We need to tell the secondary core where to find its stack and the * page tables. */ - if (ops->cpu_boot_has_arg && ops->cpu_boot_has_arg()) + if (smp_parallel_bringup) arg =3D idle; else secondary_data.task =3D idle; =20 - update_cpu_boot_status(CPU_MMU_OFF); - /* Now bring the CPU into our world */ if (ops->cpu_boot) ret =3D ops->cpu_boot(cpu, (unsigned long)arg); @@ -125,45 +135,42 @@ int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct= task_struct *idle) =20 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu, bool is_alive) { - long status; + union secondary_status status; =20 if (is_alive) return; =20 - secondary_data.task =3D NULL; - status =3D READ_ONCE(secondary_data.status); - if (status =3D=3D CPU_MMU_OFF) - status =3D READ_ONCE(__early_cpu_boot_status); - /* A CPU has failed to boot. Try to figure out what happened. */ - switch (status & CPU_BOOT_STATUS_MASK) { - default: - pr_err("CPU%u: failed in unknown state : 0x%lx\n", - cpu, status); - cpus_stuck_in_kernel++; - break; - case CPU_KILL_ME: - if (cpumask_test_cpu(cpu, &secondary_data.cpu_died_early_mask)) - set_cpu_present(cpu, false); + if (smp_parallel_bringup) + pr_warn_once("Parallel CPU bringup failed; consider passing \"cpuhp.para= llel=3Doff\" for a more accurate diagnosis.\n"); + else + secondary_data.task =3D NULL; + + status.val =3D READ_ONCE(__early_cpu_boot_status); + if (status.early_flags[EARLY_CPU_STUCK_REASON_52_BIT_VA]) { + pr_crit_once("CPU%u detected lack of support for 52-bit VAs\n", + cpu); + } + + if (status.early_flags[EARLY_CPU_STUCK_REASON_NO_GRAN]) { + pr_crit_once("CPU%u detected lack of support for %luK granules\n", + cpu, PAGE_SIZE / SZ_1K); + } + + status =3D READ_ONCE(secondary_data.status); + if (status.flags[CPU_PANIC_KERNEL]) + panic("CPU%u detected unsupported configuration\n", cpu); + + if (cpumask_test_cpu(cpu, &secondary_data.cpu_died_early_mask)) { + set_cpu_present(cpu, false); if (!op_cpu_kill(cpu)) { pr_crit("CPU%u: died during early boot\n", cpu); - break; + return; } - pr_crit("CPU%u: may not have shut down cleanly\n", cpu); - fallthrough; - case CPU_STUCK_IN_KERNEL: - pr_crit("CPU%u: is stuck in kernel\n", cpu); - if (status & CPU_STUCK_REASON_52_BIT_VA) - pr_crit("CPU%u: does not support 52-bit VAs\n", cpu); - if (status & CPU_STUCK_REASON_NO_GRAN) { - pr_crit("CPU%u: does not support %luK granule\n", - cpu, PAGE_SIZE / SZ_1K); - } - cpus_stuck_in_kernel++; - break; - case CPU_PANIC_KERNEL: - panic("CPU%u detected unsupported configuration\n", cpu); } + + pr_crit_once("CPUs may be stuck in kernel\n"); + cpus_stuck_in_kernel =3D true; } =20 static void init_gic_priority_masking(void) @@ -407,12 +414,8 @@ void __noreturn cpu_die_early(void) =20 cpumask_set_cpu(cpu, &secondary_data.cpu_died_early_mask); =20 - if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { - update_cpu_boot_status(CPU_KILL_ME); + if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) __cpu_try_die(cpu); - } - - update_cpu_boot_status(CPU_STUCK_IN_KERNEL); =20 cpu_park_loop(); } diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 79d90226fd5d..59e572a09304 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -61,7 +61,7 @@ static bool rodata_is_rw __ro_after_init =3D true; * The booting CPU updates the failed status @__early_cpu_boot_status, * with MMU turned off. */ -long __section(".mmuoff.data.write") __early_cpu_boot_status; +long __section(".mmuoff.data.write") __early_cpu_boot_status =3D 0; =20 static DEFINE_SPINLOCK(swapper_pgdir_lock); static DEFINE_MUTEX(fixmap_lock); --=20 2.55.0.979.g7e5102b832-goog From nobody Fri Sep 25 23:08:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC13F524AEA for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J2uS/ZFe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5322E1F00A3A; Mon, 7 Sep 2026 16:41:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799289; bh=FnJS5sPm/eEb7Whkt9kcxmirJFvVGPcXcBd/GmZPmro=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=J2uS/ZFegs2bPuppfq4q61wHXjhXSfLLRSdpBWZhH+w4+qVa8fOQW9/6o2TzJkOtQ FZT65VPKHBt+GTZ62Y2E+HYvukB6UTZNrolpdxuUCKppoYZX9aoL1jpAgd5wbXtaXf 2CIjKaPMrrXBp/fONa3f3cxwVC+3HUn8odmkz/lAd+NwG9GuE/5+0TMNIwNqZolVxV 4rFuseffS6u/SNKlmxqiXdtwlktQ0aYKUVl4TImp55PEb/JyceUhmIAXZ8fTyViHt1 Cbie8UGD6cfA+G8Mu3rNCoMxDTxeNdiyaAYkGJPxtH7Sh5v45F+a4qygfL1WBZwQgz Zg2DoDSRIiCog== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Thomas Gleixner , Catalin Marinas , Borislav Petkov , Lorenzo Pieralisi , Jinjie Ruan , Mark Rutland , David Woodhouse , Peter Zijlstra , Marc Zyngier Subject: [PATCH 19/19] arm64: smp: Harden parallel CPU bringup against broken PSCI firmware Date: Mon, 7 Sep 2026 17:40:22 +0100 Message-ID: <20260907164024.17164-20-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907164024.17164-1-will@kernel.org> References: <20260907164024.17164-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since firmware has occasionally been known to get things wrong, harden our parallel CPU bringup code against a PSCI implementation that passes the CPU_ON argument to an incorrect CPU. The primary CPU writes the MPIDR of the incoming CPU to the end of its task stack and this is then checked against the MPIDR_EL1 register during early kernel entry. A mismatch is reported via the existing failure reporting mechanism and the CPU is not brought online. Suggested-by: David Woodhouse Signed-off-by: Will Deacon --- arch/arm64/include/asm/smp.h | 4 +++- arch/arm64/kernel/asm-offsets.c | 1 + arch/arm64/kernel/head.S | 39 ++++++++++++++++++++++++++++----- arch/arm64/kernel/smp.c | 11 ++++++++-- 4 files changed, 46 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 3decb42164aa..1ecfa4fa4f82 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -15,7 +15,9 @@ /* Offsets for late (i.e. MMU-enabled) CPU boot reasons */ /* Fatal system error detected by secondary CPU, crash the system */ #define CPU_PANIC_KERNEL (0) -#define CPU_STATUS_FLAGS_MAX (1) +/* The PSCI v0.2+ implementation passed the wrong argument */ +#define CPU_BROKEN_PSCI_ARG (1) +#define CPU_STATUS_FLAGS_MAX (2) =20 #ifndef __ASSEMBLER__ =20 diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offset= s.c index 9c853ed3ceab..0cbd10af13ac 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -97,6 +97,7 @@ int main(void) BLANK(); #endif DEFINE(CPU_BOOT_TASK, offsetof(struct secondary_data, task)); + DEFINE(CPU_BOOT_STATUS_FLAGS, offsetof(struct secondary_data, status.fla= gs)); BLANK(); DEFINE(FTR_OVR_VAL_OFFSET, offsetof(struct arm64_ftr_override, val)); DEFINE(FTR_OVR_MASK_OFFSET, offsetof(struct arm64_ftr_override, mask)); diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index bec4bc1b12db..56deeb9673d6 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -192,11 +192,21 @@ SYM_CODE_END(preserve_boot_args) * its location in the task stack. We reserve the entire pt_regs space * for consistency with user tasks and kthreads. */ - .macro init_cpu_task tsk, tmp1, tmp2 + .macro init_cpu_task tsk, tmp1, tmp2, check_mpidr=3D msr sp_el0, \tsk =20 ldr \tmp1, [\tsk, #TSK_STACK] - add sp, \tmp1, #THREAD_SIZE + mov sp, \tmp1 + .ifnb \check_mpidr + mov_q \tmp1, MPIDR_HWID_BITMASK + mrs \tmp2, mpidr_el1 + and \tmp2, \tmp2, \tmp1 + ldr \tmp1, [sp] + sub \tmp1, \tmp1, \tmp2 + cbnz \tmp1, __cpu_secondary_broken_psci_arg + .endif + + add sp, sp, #THREAD_SIZE sub sp, sp, #PT_REGS_SIZE =20 stp xzr, xzr, [sp, #S_STACKFRAME] @@ -401,11 +411,12 @@ SYM_FUNC_START_LOCAL(__secondary_switched) cbnz x2, 1f adr_l x0, secondary_data ldr x2, [x0, #CPU_BOOT_TASK] - cbz x2, __secondary_too_slow - -1: init_cpu_task x2, x1, x3 - + cbnz x2, 2f + b __secondary_too_slow +1: + init_cpu_task x2, x1, x3, check_mpidr=3D1 +2: #ifdef CONFIG_ARM64_PTR_AUTH ptrauth_keys_init_cpu x2, x3, x4, x5 #endif @@ -451,6 +462,22 @@ SYM_FUNC_END(set_cpu_boot_mode_flag) dc ivac, \tmp1 // Invalidate potentially stale cache line .endm =20 + .macro update_cpu_boot_status status, tmp1, tmp2 + adr_l \tmp1, secondary_data + add \tmp1, \tmp1, #CPU_BOOT_STATUS_FLAGS + \status + mov \tmp2, #1 + strb w\tmp2, [\tmp1] + .endm + +SYM_FUNC_START_LOCAL(__cpu_secondary_broken_psci_arg) + update_cpu_boot_status CPU_BROKEN_PSCI_ARG, x0, x1 +1: + wfe + wfi + b 1b +SYM_FUNC_END(__cpu_secondary_broken_psci_arg) + + /* * Enable the MMU. * diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index d5da44949671..95af5384885b 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -119,10 +119,12 @@ int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct= task_struct *idle) * We need to tell the secondary core where to find its stack and the * page tables. */ - if (smp_parallel_bringup) + if (smp_parallel_bringup) { + *((u64 *)idle->stack) =3D cpu_logical_map(cpu); arg =3D idle; - else + } else { secondary_data.task =3D idle; + } =20 /* Now bring the CPU into our world */ if (ops->cpu_boot) @@ -158,6 +160,11 @@ void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu, boo= l is_alive) } =20 status =3D READ_ONCE(secondary_data.status); + if (status.flags[CPU_BROKEN_PSCI_ARG]) { + pr_crit_once("CPU%u detected broken PSCI v0.2+ CPU_ON argument passing\n= ", + cpu); + } + if (status.flags[CPU_PANIC_KERNEL]) panic("CPU%u detected unsupported configuration\n", cpu); =20 --=20 2.55.0.979.g7e5102b832-goog