From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10C07490BE0 for ; Mon, 7 Sep 2026 16:37:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799067; cv=none; b=VCSdr8//TA4vvHIlDCEiOaxYr9jfKhkqOX/TAoFyNHAAdIItmPHyj9+qPsd7tfI2ERiXHhFqKpvphg5gcFJ+MkgC3/VLLD25XAjFjkbR3DijmS2RMhl31HPfUt5H3Kert4Hr1PpWV9pqbPEczjU4xpqLNrjUQagaQyTMQXai65w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799067; c=relaxed/simple; bh=SHiaRDgAbRogSCrDgqQFHN5EjCO5q58zZZmwYQDZJFY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CAyMm0GGlLuq7HREdZK4iTkqA9cshc+LHwGiBuNPwgBR9YkSm5IvIxkGHT9xn9DN2gAYkqMwJLFgAoerhNPKmlCKCMKErr0X1ewVHa4Kr0yubn9Hg5wD1JH1o7zmPK6ZmoI7UylcTDDaivUO+6cx4fTFgZWFBF4MqCFqFF47DOE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kj9ZlutW; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kj9ZlutW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31BB61F00A3D; Mon, 7 Sep 2026 16:37:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799063; bh=YqRz7kh9GA65pE9byU4+133n1tljEOvpx8kOxD8+E2s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=kj9ZlutWEW+hsUIPXmKg+enJK5UF3ivS1PX6eBAbwSJLQxjWFIrG6T+cZYCJdEipJ pApIwfPKHrWIXuVU4ioqDqg5BpZaeOpulEoiUwtw/wYHIyY5cYvzpWI8Y/JVNgNgYf c3Y2gI7w0QT/tUyiI0UcIBbOSR7zZvz8w4cFdTZLngGb3sqpZEJt4dl14DtrKTSJIX xNsejXmNUprfgbdQTUnNdyI9Wzg7wZ4T/b4R6EocHKmCiwbpMO9rnJ9kpi7hYonKm6 cme+a2sIz9PRgnNMVv3dv3a/3+9S2bJ15P3akcE61aILDqj+YCYgVNnLHyizFr/Ys7 PQiaKlG8AvYow== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 01/14] selftests/arm64: Remove big-endian support Date: Mon, 7 Sep 2026 17:37:12 +0100 Message-ID: <20260907163726.17104-2-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Big-endian support on arm64 depends on BROKEN, so the arm64 selftests do not need to worry about testing this configuration any more. Remove the 128-bit byte-swapping helper from the fp-ptrace test and the big-endian definition of RSEQ_SIG_DATA from the rseq test. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- tools/testing/selftests/arm64/fp/fp-ptrace.c | 19 +------------------ tools/testing/selftests/rseq/rseq-arm64.h | 5 ----- 2 files changed, 1 insertion(+), 23 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.c b/tools/testing/s= elftests/arm64/fp/fp-ptrace.c index b435837c8c0e..9b184d78f4fd 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.c +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.c @@ -115,23 +115,6 @@ static void handle_alarm(int sig, siginfo_t *info, voi= d *context) got_alarm =3D true; } =20 -#ifdef CONFIG_CPU_BIG_ENDIAN -static __uint128_t arm64_cpu_to_le128(__uint128_t x) -{ - u64 a =3D swab64(x); - u64 b =3D swab64(x >> 64); - - return ((__uint128_t)a << 64) | b; -} -#else -static __uint128_t arm64_cpu_to_le128(__uint128_t x) -{ - return x; -} -#endif - -#define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x) - static bool sve_supported(void) { return getauxval(AT_HWCAP) & HWCAP_SVE; @@ -932,7 +915,7 @@ static void fpsimd_to_sve(__uint128_t *v, char *z, int = vl) =20 for (i =3D 0; i < __SVE_NUM_ZREGS; i++) { p =3D (__uint128_t *)&z[__SVE_ZREG_OFFSET(vq, i)]; - *p =3D arm64_cpu_to_le128(v[i]); + *p =3D v[i]; } } =20 diff --git a/tools/testing/selftests/rseq/rseq-arm64.h b/tools/testing/self= tests/rseq/rseq-arm64.h index 21e1626a7235..f9fecf941bf2 100644 --- a/tools/testing/selftests/rseq/rseq-arm64.h +++ b/tools/testing/selftests/rseq/rseq-arm64.h @@ -12,12 +12,7 @@ * matches code endianness. */ #define RSEQ_SIG_CODE 0xd428bc00 /* BRK #0x45E0. */ - -#ifdef __AARCH64EB__ -#define RSEQ_SIG_DATA 0x00bc28d4 /* BRK #0x45E0. */ -#else #define RSEQ_SIG_DATA RSEQ_SIG_CODE -#endif =20 #define RSEQ_SIG RSEQ_SIG_DATA =20 --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E7EC46DFF7 for ; Mon, 7 Sep 2026 16:37:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799068; cv=none; b=fKKXahEIR+ciZbv+FCSCFoNBlLGisJxURH62fJXEFD76d2dBxvqs7q95t766cuIstak2M36+5LZcTK9T08RVlIEElxShcIeNGEX6CS5KYJJhb+aXu/vFGtfLieUPbNV1FpdTiPB6XjRK4SJQpSUdtcKHcGhKskcPOEVyiB2iCfw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799068; c=relaxed/simple; bh=Wyg1eN4jUdiTv0KZSQpmP1+a7E8NW+RZZqVlC/RfMl0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UCPbglSXKwMFoHd/YAlCfr57V/AF23PZaLLQwgyOOA3kKAlxCWYKLNlqFqDpDchj7R3fbnZm70d89P6VG2m+RmyUHn26wes4RMCZhmuCJ4ncyM+8d+NJE67EaJd5dqnepgSETalXKJgGIbGdsYGaki97mXQDd1L3AATLE4PCwbo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OllL8Lp0; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OllL8Lp0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1EFFE1F00A3F; Mon, 7 Sep 2026 16:37:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799066; bh=6dpWxBNfInUaNyuOgfIBwdLimXQZBIeRnLQ9BgIWjOg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=OllL8Lp00Z8nr/h17b8SYnuzFy/hSbyCf+Tvwy7p8L64bUGwMcN1nd6DGRDIN8fGd lWzugKZ5CfdasfuwMRAZ4X9N3lClg+/7LBF5/p/hNytQOm3Vz4We/rmTvM3Iu4PCYB H2dMwLJk55RtPvHCi2AUwjDzslaFvZrbSkIqGZBTJPQfmhoM/HLlkcZkHaZoMq2Yo3 lEIN43ThUvvn57i2gwSxBuGjYPXcHMyzxCZ6cEnzA4acvaVkXHp78mV1kAPMLgzcta D7C3U9bEQJwqskOVZ+iclXqumAGaVnnGaPg8OuU06FZL3Swsv0O5vBvj+c51/grdLi kFU3ux3+qnSXA== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 02/14] arm64: bpf: Remove big-endian support from the JIT compiler Date: Mon, 7 Sep 2026 17:37:13 +0100 Message-ID: <20260907163726.17104-3-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Big-endian support on arm64 depends on BROKEN. In preparation for removing the dead code altogether, remove the big-endian-specific support from the arm64 BPF JIT backend. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon Acked-by: Alexei Starovoitov --- arch/arm64/net/bpf_jit_comp.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index c18e005a41db..a5634428fdd5 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -1439,13 +1439,8 @@ static int build_insn(const struct bpf_verifier_env = *env, const struct bpf_insn case BPF_ALU | BPF_END | BPF_FROM_LE: case BPF_ALU | BPF_END | BPF_FROM_BE: case BPF_ALU64 | BPF_END | BPF_FROM_LE: -#ifdef CONFIG_CPU_BIG_ENDIAN - if (BPF_CLASS(code) =3D=3D BPF_ALU && BPF_SRC(code) =3D=3D BPF_FROM_BE) - goto emit_bswap_uxt; -#else /* !CONFIG_CPU_BIG_ENDIAN */ if (BPF_CLASS(code) =3D=3D BPF_ALU && BPF_SRC(code) =3D=3D BPF_FROM_LE) goto emit_bswap_uxt; -#endif switch (imm) { case 16: emit(A64_REV16(is64, dst, dst), ctx); @@ -2559,15 +2554,9 @@ static void clear_garbage(struct jit_ctx *ctx, int r= eg, int effective_bytes) { if (effective_bytes) { int garbage_bits =3D 64 - 8 * effective_bytes; -#ifdef CONFIG_CPU_BIG_ENDIAN - /* garbage bits are at the right end */ - emit(A64_LSR(1, reg, reg, garbage_bits), ctx); - emit(A64_LSL(1, reg, reg, garbage_bits), ctx); -#else /* garbage bits are at the left end */ emit(A64_LSL(1, reg, reg, garbage_bits), ctx); emit(A64_LSR(1, reg, reg, garbage_bits), ctx); -#endif } } =20 --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43B7F490BE0 for ; Mon, 7 Sep 2026 16:37:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799074; cv=none; b=QFoeKjMXAhJsaCwy0DefnWCO5as1pfuKBocKxV6LgJzzRYbzcO2k1gsL2xnC6OEwsxQsQvZjJirqqJjarA/mivHWQAVMh/nsgQxsApeQwAOpCWpeW3ZjaLXiqQHNy6cgV43IheLkOQUYE+nGquU982gnAlJ87RilVQ3uNwk1MXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799074; c=relaxed/simple; bh=Ta0BJoV366QjGLuB04AG6vFYi50SNgDk3/hcfWm2/KY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nuYz+ALrpyHoHtHRvyglJss8OqTpJevHv1MzSHKpJPn8iRpzZkri5qgVmWFY6Mcq2lcbnveozLf7tN78TgI9DkDLnEjZI2qxAfwjWm69xHTbxeeo0IVNoZLaRFfSN4wP4i16sPPenICp2K1cpZ14gcTgmyV6bBSQhUTN1Jv79tI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JXq9/SeA; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JXq9/SeA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 38E1A1F00A3D; Mon, 7 Sep 2026 16:37:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799069; bh=lPrkfAXnyVR+sgg/nvBW0HnQu9CN1G6qPn9X/cZtdc8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=JXq9/SeANohjjJelBr1h9+h1jcvGFIKikZivAEx270yKOhUq1H3cqMfDkTsf0xF0j uB8g5B7q3bEGtOK6qxsJtM1MqL/lm6O3jNtwdwsALNunbWDtW8CWH2JV5RUfig/jje g5ofEbvI1pH6RCZiHq/1jd0NoIx/krybQIRQtYC7KP/wjU7EXtaLQbticQphfmrVAh EVzla3MToO4W228msz497wKYEGSgaaVDQPMvU/vHjVyKSq/LIUyiY+lko6MJq6NDtf aVQmfHFkTS+iHHh4qHPBVe495I9qVjHJYrCqWeSOaAtryYoUa5N1bo6yq7pG9Ljg1e nnfP3GkFPLm8w== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 03/14] arm64: crypto: Assume a little-endian kernel Date: Mon, 7 Sep 2026 17:37:14 +0100 Message-ID: <20260907163726.17104-4-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 5276ea17a23c ("lib/crc: arm64: Assume a little-endian kernel") removed all usage of the CPU_LE()/CPU_BE() macros from the arm64 CRC assembly now that big-endian support depends on BROKEN. Do the same for the crypto assembly code. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- arch/arm64/crypto/aes-ce-ccm-core.S | 4 ++-- arch/arm64/crypto/aes-neonbs-core.S | 4 ++-- arch/arm64/crypto/ghash-ce-core.S | 6 +++--- arch/arm64/crypto/sm4-ce-cipher-core.S | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/crypto/aes-ce-ccm-core.S b/arch/arm64/crypto/aes-ce= -ccm-core.S index f2624238fd95..c2e8f500da14 100644 --- a/arch/arm64/crypto/aes-ce-ccm-core.S +++ b/arch/arm64/crypto/aes-ce-ccm-core.S @@ -50,7 +50,7 @@ ld1 {v0.16b}, [x5] /* load mac */ cbz x2, ce_aes_ccm_final ldr x8, [x6, #8] /* load lower ctr */ -CPU_LE( rev x8, x8 ) /* keep swabbed ctr in reg */ + rev x8, x8 /* keep swabbed ctr in reg */ 0: /* outer loop */ ld1 {v1.8b}, [x6] /* load upper ctr */ prfm pldl1strm, [x1] @@ -73,7 +73,7 @@ CPU_LE( rev x8, x8 ) /* keep swabbed ctr in reg */ eor v0.16b, v0.16b, v2.16b /* xor mac with pt ^ rk[last] */ st1 {v6.16b}, [x0], #16 /* write output block */ bne 0b -CPU_LE( rev x8, x8 ) + rev x8, x8 str x8, [x6, #8] /* store lsb end of ctr (BE) */ cbnz x7, ce_aes_ccm_final st1 {v0.16b}, [x5] /* store mac */ diff --git a/arch/arm64/crypto/aes-neonbs-core.S b/arch/arm64/crypto/aes-ne= onbs-core.S index baf450717b24..ba1f981a5464 100644 --- a/arch/arm64/crypto/aes-neonbs-core.S +++ b/arch/arm64/crypto/aes-neonbs-core.S @@ -824,8 +824,8 @@ SYM_FUNC_START(aesbs_ctr_encrypt) frame_push 0 ldp x7, x8, [x5] ld1 {v0.16b}, [x5] -CPU_LE( rev x7, x7 ) -CPU_LE( rev x8, x8 ) + rev x7, x7 + rev x8, x8 adds x8, x8, #1 adc x7, x7, xzr =20 diff --git a/arch/arm64/crypto/ghash-ce-core.S b/arch/arm64/crypto/ghash-ce= -core.S index 33772d8fe6b5..ba350d57fc76 100644 --- a/arch/arm64/crypto/ghash-ce-core.S +++ b/arch/arm64/crypto/ghash-ce-core.S @@ -148,7 +148,7 @@ SYM_FUNC_START(pmull_ghash_update_p64) sub w0, w0, #1 =20 3: /* multiply XL by SHASH in GF(2^128) */ -CPU_LE( rev64 T1.16b, T1.16b ) + rev64 T1.16b, T1.16b =20 ext T2.16b, XL.16b, XL.16b, #8 ext IN1.16b, T1.16b, T1.16b, #8 @@ -272,7 +272,7 @@ SYM_FUNC_END(pmull_ghash_update_p64) cbz x0, 3f // tag only? =20 ldr w8, [x5, #12] // load lower counter -CPU_LE( rev w8, w8 ) + rev w8, w8 =20 0: mov w9, #4 // max blocks per round add x10, x0, #0xf @@ -380,7 +380,7 @@ CPU_LE( rev w8, w8 ) ret =20 5: -CPU_LE( rev w8, w8 ) + rev w8, w8 str w8, [x5, #12] // store lower counter st1 {XL.2d}, [x4] b 4b diff --git a/arch/arm64/crypto/sm4-ce-cipher-core.S b/arch/arm64/crypto/sm4= -ce-cipher-core.S index 4ac6cfbc5797..1682d727e097 100644 --- a/arch/arm64/crypto/sm4-ce-cipher-core.S +++ b/arch/arm64/crypto/sm4-ce-cipher-core.S @@ -18,7 +18,7 @@ SYM_FUNC_START(sm4_ce_do_crypt) ld1 {v8.4s}, [x2] ld1 {v0.4s-v3.4s}, [x0], #64 -CPU_LE( rev32 v8.16b, v8.16b ) + rev32 v8.16b, v8.16b ld1 {v4.4s-v7.4s}, [x0] sm4e v8.4s, v0.4s sm4e v8.4s, v1.4s @@ -30,7 +30,7 @@ CPU_LE( rev32 v8.16b, v8.16b ) sm4e v8.4s, v7.4s rev64 v8.4s, v8.4s ext v8.16b, v8.16b, v8.16b, #8 -CPU_LE( rev32 v8.16b, v8.16b ) + rev32 v8.16b, v8.16b st1 {v8.4s}, [x1] ret SYM_FUNC_END(sm4_ce_do_crypt) --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBD9C5111BB for ; Mon, 7 Sep 2026 16:37:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799074; cv=none; b=KGOmaBiTwZEMuC3Sh8DQOEIGfsCW4BOUj1TlHTXKAtgyXgo2+X0bXT7J5u/hypkrdOOGy7Xt1JAHR49RptnA+9ArwRpbS4AaaGQUt7nRRlyKfeZVSG53XnvyFzFuQ0qcpINvB0QvnR3abrykEfrvUWwlTk4wFKz24MuaaTXCyIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799074; c=relaxed/simple; bh=xL8nbXc27K6K3JzIWcZLfCM08Hca7UMiw9iCWFD5el8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D1tRXCkZ14a9U8Ds23TVxJFxt/Tq04s07Jhe8h5K3nWHm4obUP47DCAqGE1ryA24Er0rr241yvL0E3seMrhMKuIsmItW8ZaOqfURYt4/ERLM+EaRPsWf4kRv+CRQC0Zp+T4JECfdi+dfyottLxIDWdXwXm4REFHsGRWBQi8GFrI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cfkjQWhp; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cfkjQWhp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 741AB1F00A3F; Mon, 7 Sep 2026 16:37:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799072; bh=TT541hKGyh+ei1aXxPgKteRsVAhuovdnfEyfNk8AuJ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=cfkjQWhp9Hr9trinJOMrZTL8kUPE4qIulRsdrA4igFxnzqInJt+5iW+OpPvKgJBoB OekcjCsmQ9ccOtiN0NPAiceILkd9AKrGYbvs1xX/ozYD9k6fWRjgBbsuC2+CMPTQJ5 BGxYRWzqLcSUohijRdEOHuRcAhqb+iQ5hqX52Eo9IY96wy3lFaZoNcUJce8e9XXTWE JBizLBq88E/m1CDX+svpmxjBO2+6uDJMpGLKKgECUFeQFbu97upkgHEa02Zomev47E /hiyc+tueHfPwLoCHo2YNAlowdQFrUPafjPEosSN2BkXq8dXmLcHCgBlPvci3xEKiG 9XOjp93rj/kWw== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 04/14] arm64: lib: Assume a little-endian kernel in custom library routines Date: Mon, 7 Sep 2026 17:37:15 +0100 Message-ID: <20260907163726.17104-5-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 5276ea17a23c ("lib/crc: arm64: Assume a little-endian kernel") removed all usage of the CPU_LE()/CPU_BE() macros from the arm64 CRC assembly now that big-endian support depends on BROKEN. Do the same for the rest of the custom arm64 library code, as well as removing all usage of the '__LITTLE_ENDIAN' macro. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- arch/arm64/lib/csum.c | 17 ----------------- arch/arm64/lib/memchr.S | 2 +- 2 files changed, 1 insertion(+), 18 deletions(-) diff --git a/arch/arm64/lib/csum.c b/arch/arm64/lib/csum.c index 2432683e48a6..75db718e5b6a 100644 --- a/arch/arm64/lib/csum.c +++ b/arch/arm64/lib/csum.c @@ -47,11 +47,7 @@ unsigned int __no_sanitize_address do_csum(const unsigne= d char *buff, int len) */ shift =3D offset * 8; data =3D *ptr++; -#ifdef __LITTLE_ENDIAN data =3D (data >> shift) << shift; -#else - data =3D (data << shift) >> shift; -#endif =20 /* * Body: straightforward aligned loads from here on (the paired loads @@ -94,13 +90,8 @@ unsigned int __no_sanitize_address do_csum(const unsigne= d char *buff, int len) len -=3D 16; ptr +=3D 2; =20 -#ifdef __LITTLE_ENDIAN data =3D tmp >> 64; sum64 =3D accumulate(sum64, tmp); -#else - data =3D tmp; - sum64 =3D accumulate(sum64, tmp >> 64); -#endif } if (len > 0) { sum64 =3D accumulate(sum64, data); @@ -112,11 +103,7 @@ unsigned int __no_sanitize_address do_csum(const unsig= ned char *buff, int len) * preserving odd/even alignment. */ shift =3D len * -8; -#ifdef __LITTLE_ENDIAN data =3D (data << shift) >> shift; -#else - data =3D (data >> shift) << shift; -#endif sum64 =3D accumulate(sum64, data); =20 /* Finally, folding */ @@ -140,11 +127,7 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, dst =3D *(const __uint128_t *)daddr->s6_addr; =20 sum +=3D (__force u32)htonl(len); -#ifdef __LITTLE_ENDIAN sum +=3D (u32)proto << 24; -#else - sum +=3D proto; -#endif src +=3D (src >> 64) | (src << 64); dst +=3D (dst >> 64) | (dst << 64); =20 diff --git a/arch/arm64/lib/memchr.S b/arch/arm64/lib/memchr.S index 37a9f2a4f7f4..b14b27cb8419 100644 --- a/arch/arm64/lib/memchr.S +++ b/arch/arm64/lib/memchr.S @@ -63,7 +63,7 @@ L(byte_loop): sub srcin, srcin, #1 ret L(found_word): -CPU_LE( rev tmp, tmp) + rev tmp, tmp clz tmp, tmp sub tmp, tmp, #64 add result, srcin, tmp, asr #3 --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4019451D513 for ; Mon, 7 Sep 2026 16:37:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799078; cv=none; b=i/w9r8V3n1PSK5g1QSWMWWku+Sahth2gQe8LzJqXk3CO7YcFF5ZLY8D0eJI54BaL6dr66ittM/SFUcBZoGO3Hih8tl56+qF6vrf9O2AIrYWBEuXXa4swmWslpAjkdIEBgFfaNMOvtPeA/06X+5MOVJ+sbM4HSVZ1rIqjViggMes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799078; c=relaxed/simple; bh=nSRnYinFWJonPEqYY/Di9VLBcOqhAzgRPPriJhW1Oec=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MwbxSrIeKk2nkf6mJNMw/x9hGNAWm8vGzzsrdku1MsO/DohNlsdayjI9eWkzDG/5xi+QES4jE2eZVo7NjtwRU45noF9N0qkS2PDmencm6g74kbsA762ISr3L8VOWYgCeijlBwxTpWYJsXkRn9iLiUkQP2afsJB8hhlTTtzsKEPU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=R38Yn9MY; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="R38Yn9MY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53A661F00A3A; Mon, 7 Sep 2026 16:37:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799075; bh=VHT/QTdnjo8aK5fA7c82B8ZTGy+6XW4yo9QmbjyZo7o=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=R38Yn9MYHuQyrY0IZHNaND54pteMVzWQqA3smrrk5FbuYnTo1WvY5Ulj1hOoxRS6v 8uPzrVZsva+Ll//Ow60ktfBqF88lg+9liqo38gk+LBfDG09y4Mj3+UoBXwhg6+8ZVL 4hWKmzr0FvY80IG0Dh7O0gts/aIBUkfbxg9zF/p5/btihZ5X/1Wdn+D+idmZKKznhM G7S3O41ZhmNTw1w7i2zP4p7mUMER/ytiwbcF/j53IXP3449/kHBGl3H9hhrP7UgTJo 0DUHfyQFZNacq2hX4LidOtvsGGbelIusHen2CwBdnZL8xZzpS5aSndfTgIHixsex0z CG7Jz+PPTs0aA== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 05/14] arm64: lib: Assume a little-endian kernel in optimised string routines Date: Mon, 7 Sep 2026 17:37:16 +0100 Message-ID: <20260907163726.17104-6-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Big-endian support on arm64 depends on BROKEN. In preparation for removing the dead code altogether, remove the big-endian-specific support from the arm64 optimised string routines. Although these started life as a fork of Arm's "cortex strings" library and later got updated with the "optimized-routines" code, the in-kernel implementation has always been different enough that removing the unused big-endian portion still makes sense. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- arch/arm64/lib/memcmp.S | 2 - arch/arm64/lib/strcmp.S | 34 +-------------- arch/arm64/lib/strlen.S | 26 ----------- arch/arm64/lib/strncmp.S | 93 +++------------------------------------- arch/arm64/lib/strnlen.S | 16 +------ 5 files changed, 8 insertions(+), 163 deletions(-) diff --git a/arch/arm64/lib/memcmp.S b/arch/arm64/lib/memcmp.S index a5ccf2c55f91..1f528ce046e4 100644 --- a/arch/arm64/lib/memcmp.S +++ b/arch/arm64/lib/memcmp.S @@ -103,10 +103,8 @@ L(last_bytes): =20 /* Compare data bytes and set return value to 0, -1 or 1. */ L(return): -#ifndef __AARCH64EB__ rev data1, data1 rev data2, data2 -#endif cmp data1, data2 L(ret_eq): cset result, ne diff --git a/arch/arm64/lib/strcmp.S b/arch/arm64/lib/strcmp.S index 9b89b4533607..2389b47dca22 100644 --- a/arch/arm64/lib/strcmp.S +++ b/arch/arm64/lib/strcmp.S @@ -38,14 +38,6 @@ #define shift x9 #define off2 x10 =20 -/* On big-endian early bytes are at MSB and on little-endian LSB. - LS_FW means shifting towards early bytes. */ -#ifdef __AARCH64EB__ -# define LS_FW lsl -#else -# define LS_FW lsr -#endif - /* NUL detection works on the principle that (X - 1) & (~X) & 0x80 (=3D> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and can be done in parallel across the entire word. @@ -67,28 +59,17 @@ L(loop_aligned): ldr data2, [src1, off2] ldr data1, [src1], 8 L(start_realigned): -#ifdef __AARCH64EB__ - rev tmp, data1 - sub has_nul, tmp, zeroones - orr tmp, tmp, REP8_7f -#else sub has_nul, data1, zeroones orr tmp, data1, REP8_7f -#endif bics has_nul, has_nul, tmp /* Non-zero if NUL terminator. */ ccmp data1, data2, 0, eq b.eq L(loop_aligned) -#ifdef __AARCH64EB__ - rev has_nul, has_nul -#endif eor diff, data1, data2 orr syndrome, diff, has_nul L(end): -#ifndef __AARCH64EB__ rev syndrome, syndrome rev data1, data1 rev data2, data2 -#endif clz shift, syndrome /* The most-significant-non-zero bit of the syndrome marks either the first bit that is different, or the top bit of the first zero byte. @@ -113,7 +94,7 @@ L(mutual_align): ldr data1, [src1], 8 neg shift, src2, lsl 3 /* Bits to alignment -64. */ mov tmp, -1 - LS_FW tmp, tmp, shift + lsr tmp, tmp, shift orr data1, data1, tmp orr data2, data2, tmp b L(start_realigned) @@ -135,9 +116,6 @@ L(src1_aligned): neg shift, src2, lsl 3 bic src2, src2, 7 ldr data3, [src2], 8 -#ifdef __AARCH64EB__ - rev data3, data3 -#endif lsr tmp, zeroones, shift orr data3, data3, tmp sub has_nul, data3, zeroones @@ -152,9 +130,6 @@ L(src1_aligned): L(loop_unaligned): ldr data3, [src1, off1] ldr data2, [src1, off2] -#ifdef __AARCH64EB__ - rev data3, data3 -#endif sub has_nul, data3, zeroones orr tmp, data3, REP8_7f ldr data1, [src1], 8 @@ -163,9 +138,6 @@ L(loop_unaligned): b.eq L(loop_unaligned) =20 lsl tmp, has_nul, shift -#ifdef __AARCH64EB__ - rev tmp, tmp -#endif eor diff, data1, data2 orr syndrome, diff, tmp cbnz syndrome, L(end) @@ -174,10 +146,6 @@ L(tail): neg shift, shift lsr data2, data3, shift lsr has_nul, has_nul, shift -#ifdef __AARCH64EB__ - rev data2, data2 - rev has_nul, has_nul -#endif eor diff, data1, data2 orr syndrome, diff, has_nul b L(end) diff --git a/arch/arm64/lib/strlen.S b/arch/arm64/lib/strlen.S index 4919fe81ae54..a8c49a3886f6 100644 --- a/arch/arm64/lib/strlen.S +++ b/arch/arm64/lib/strlen.S @@ -85,14 +85,6 @@ SYM_FUNC_START(__pi_strlen) cmp tmp1, MIN_PAGE_SIZE - 16 b.gt L(page_cross) ldp data1, data2, [srcin] -#ifdef __AARCH64EB__ - /* For big-endian, carry propagation (if the final byte in the - string is 0x01) means we cannot use has_nul1/2 directly. - Since we expect strings to be small and early-exit, - byte-swap the data now so has_null1/2 will be correct. */ - rev data1, data1 - rev data2, data2 -#endif sub tmp1, data1, zeroones orr tmp2, data1, REP8_7f sub tmp3, data2, zeroones @@ -144,19 +136,7 @@ L(page_cross_entry): =20 /* Enter with C =3D has_nul1 =3D=3D 0. */ L(tail): -#ifdef __AARCH64EB__ - /* For big-endian, carry propagation (if the final byte in the - string is 0x01) means we cannot use has_nul1/2 directly. The - easiest way to get the correct byte is to byte-swap the data - and calculate the syndrome a second time. */ - csel data1, data1, data2, cc - rev data1, data1 - sub tmp1, data1, zeroones - orr tmp2, data1, REP8_7f - bic has_nul1, tmp1, tmp2 -#else csel has_nul1, has_nul1, has_nul2, cc -#endif sub len, src, srcin rev has_nul1, has_nul1 add tmp2, len, 8 @@ -194,13 +174,7 @@ L(page_cross): ldp data1, data2, [src] lsl tmp1, srcin, 3 mov tmp4, -1 -#ifdef __AARCH64EB__ - /* Big-endian. Early bytes are at MSB. */ - lsr tmp1, tmp4, tmp1 /* Shift (tmp1 & 63). */ -#else - /* Little-endian. Early bytes are at LSB. */ lsl tmp1, tmp4, tmp1 /* Shift (tmp1 & 63). */ -#endif orr tmp1, tmp1, REP8_80 orn data1, data1, tmp1 orn tmp2, data2, tmp1 diff --git a/arch/arm64/lib/strncmp.S b/arch/arm64/lib/strncmp.S index fe7bbc0b42a7..e4fde8586089 100644 --- a/arch/arm64/lib/strncmp.S +++ b/arch/arm64/lib/strncmp.S @@ -45,19 +45,6 @@ #define offset pos #define neg_offset x15 =20 -/* Define endian dependent shift operations. - On big-endian early bytes are at MSB and on little-endian LSB. - LS_FW means shifting towards early bytes. - LS_BK means shifting towards later bytes. - */ -#ifdef __AARCH64EB__ -#define LS_FW lsl -#define LS_BK lsr -#else -#define LS_FW lsr -#define LS_BK lsl -#endif - SYM_FUNC_START(__pi_strncmp) cbz limit, L(ret0) eor tmp1, src1, src2 @@ -86,7 +73,6 @@ L(start_realigned): /* End of main loop */ =20 L(full_check): -#ifndef __AARCH64EB__ orr syndrome, diff, has_nul add limit, limit, 8 /* Rewind limit to before last subs. */ L(syndrome_check): @@ -105,55 +91,6 @@ L(syndrome_check): sub result, data1, data2, lsr #56 csel result, result, xzr, hi ret -#else - /* Not reached the limit, must have found the end or a diff. */ - tbz limit, #63, L(not_limit) - add tmp1, limit, 8 - cbz limit, L(not_limit) - - lsl limit, tmp1, #3 /* Bits -> bytes. */ - mov mask, #~0 - lsr mask, mask, limit - bic data1, data1, mask - bic data2, data2, mask - - /* Make sure that the NUL byte is marked in the syndrome. */ - orr has_nul, has_nul, mask - -L(not_limit): - /* For big-endian we cannot use the trick with the syndrome value - as carry-propagation can corrupt the upper bits if the trailing - bytes in the string contain 0x01. */ - /* However, if there is no NUL byte in the dword, we can generate - the result directly. We can't just subtract the bytes as the - MSB might be significant. */ - cbnz has_nul, 1f - cmp data1, data2 - cset result, ne - cneg result, result, lo - ret -1: - /* Re-compute the NUL-byte detection, using a byte-reversed value. */ - rev tmp3, data1 - sub tmp1, tmp3, zeroones - orr tmp2, tmp3, #REP8_7f - bic has_nul, tmp1, tmp2 - rev has_nul, has_nul - orr syndrome, diff, has_nul - clz pos, syndrome - /* The most-significant-non-zero bit of the syndrome marks either the - first bit that is different, or the top bit of the first zero byte. - Shifting left now will bring the critical information into the - top bits. */ -L(end_quick): - lsl data1, data1, pos - lsl data2, data2, pos - /* But we need to zero-extend (char is unsigned) the value and then - perform a signed 32-bit subtraction. */ - lsr data1, data1, #56 - sub result, data1, data2, lsr #56 - ret -#endif =20 L(mutual_align): /* Sources are mutually aligned, but are not currently at an @@ -167,7 +104,7 @@ L(mutual_align): neg tmp3, count, lsl #3 /* 64 - bits(bytes beyond align). */ ldr data2, [src2], #8 mov tmp2, #~0 - LS_FW tmp2, tmp2, tmp3 /* Shift (count & 63). */ + lsr tmp2, tmp2, tmp3 /* Shift (count & 63). */ /* Adjust the limit and ensure it doesn't overflow. */ adds limit, limit, count csinv limit, limit, xzr, lo @@ -236,15 +173,15 @@ L(src1_aligned): neg neg_offset, offset ldr data1, [src1], #8 ldp tmp1, tmp2, [src2], #16 - LS_BK mask, mask, neg_offset + lsl mask, mask, neg_offset and neg_offset, neg_offset, #63 /* Need actual value for cmp later. */ /* Skip the first compare if data in tmp1 is irrelevant. */ tbnz offset, 6, L(misaligned_mid_loop) =20 L(loop_misaligned): /* STEP_A: Compare full 8 bytes when there is enough data from SRC2.*/ - LS_FW data2, tmp1, offset - LS_BK tmp1, tmp2, neg_offset + lsr data2, tmp1, offset + lsl tmp1, tmp2, neg_offset subs limit, limit, #8 orr data2, data2, tmp1 /* 8 bytes from SRC2 combined from two regs.*/ sub has_nul, data1, zeroones @@ -258,23 +195,12 @@ L(loop_misaligned): ldr data1, [src1], #8 L(misaligned_mid_loop): /* STEP_B: Compare first part of data1 to second part of tmp2. */ - LS_FW data2, tmp2, offset -#ifdef __AARCH64EB__ - /* For big-endian we do a byte reverse to avoid carry-propagation - problem described above. This way we can reuse the has_nul in the - next step and also use syndrome value trick at the end. */ - rev tmp3, data1 - #define data1_fixed tmp3 -#else + lsr data2, tmp2, offset #define data1_fixed data1 -#endif sub has_nul, data1_fixed, zeroones orr tmp3, data1_fixed, #REP8_7f eor diff, data2, data1 /* Non-zero if differences found. */ bic has_nul, has_nul, tmp3 /* Non-zero if NUL terminator. */ -#ifdef __AARCH64EB__ - rev has_nul, has_nul -#endif cmp limit, neg_offset, lsr #3 orr syndrome, diff, has_nul bic syndrome, syndrome, mask /* Ignore later bytes. */ @@ -284,7 +210,7 @@ L(misaligned_mid_loop): /* STEP_C: Compare second part of data1 to first part of tmp1. */ ldp tmp1, tmp2, [src2], #16 cmp limit, #8 - LS_BK data2, tmp1, neg_offset + lsl data2, tmp1, neg_offset eor diff, data2, data1 /* Non-zero if differences found. */ orr syndrome, diff, has_nul and syndrome, syndrome, mask /* Ignore earlier bytes. */ @@ -295,13 +221,6 @@ L(misaligned_mid_loop): sub limit, limit, #8 b L(loop_misaligned) =20 -#ifdef __AARCH64EB__ -L(syndrome_check): - clz pos, syndrome - cmp pos, limit, lsl #3 - b.lo L(end_quick) -#endif - L(ret0): mov result, #0 ret diff --git a/arch/arm64/lib/strnlen.S b/arch/arm64/lib/strnlen.S index d5ac0e10a01d..b20011d559f1 100644 --- a/arch/arm64/lib/strnlen.S +++ b/arch/arm64/lib/strnlen.S @@ -91,22 +91,10 @@ SYM_FUNC_START(__pi_strnlen) */ sub len, src, srcin cbz has_nul1, .Lnul_in_data2 -CPU_BE( mov data2, data1 ) /*perpare data to re-calculate the syndrome*/ =20 sub len, len, #8 mov has_nul2, has_nul1 .Lnul_in_data2: - /* - * For big-endian, carry propagation (if the final byte in the - * string is 0x01) means we cannot use has_nul directly. The - * easiest way to get the correct byte is to byte-swap the data - * and calculate the syndrome a second time. - */ -CPU_BE( rev data2, data2 ) -CPU_BE( sub tmp1, data2, zeroones ) -CPU_BE( orr tmp2, data2, #REP8_7f ) -CPU_BE( bic has_nul2, tmp1, tmp2 ) - sub len, len, #8 rev has_nul2, has_nul2 clz pos, has_nul2 @@ -139,10 +127,8 @@ CPU_BE( bic has_nul2, tmp1, tmp2 ) lsl tmp4, tmp4, #3 /* Bytes beyond alignment -> bits. */ =20 mov tmp2, #~0 - /* Big-endian. Early bytes are at MSB. */ -CPU_BE( lsl tmp2, tmp2, tmp4 ) /* Shift (tmp1 & 63). */ /* Little-endian. Early bytes are at LSB. */ -CPU_LE( lsr tmp2, tmp2, tmp4 ) /* Shift (tmp1 & 63). */ + lsr tmp2, tmp2, tmp4 /* Shift (tmp1 & 63). */ =20 cmp tmp1, #8 =20 --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7022C4D2EEC for ; Mon, 7 Sep 2026 16:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799088; cv=none; b=EEfDfRHnyFvRxyC7qIIKRyfTvUcHCqzyrBQlFmLBnp8XrK3TDH2uSvUyG1WvXFVyA3dexZFBnD/vcOuKT2HJgJndbBN+NcuGS6loF1sVj3x1lpcFnvd+Pt9HKNbZZcG9fEbnhX4jdJsjdX23gXWNhVb4wdlZv10DTJItjWNIQUc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799088; c=relaxed/simple; bh=liz77i/89QQKXV+6l33zXfgvWGjxMFbvMbLGZo6I93M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MY/Yzn1idgu5C83fr7KXbBgyFMYMFv8PZPvO9/BmYC8dkZbD68qiFxPP7Mu6zg7WRkgmBcesTAqNY6H2A7m3Huo0BnltOcN893wvYEqGNIs9nwuSa8eoweaeYWTsegErbIujCFNXkq8W8N6jMnlKAtRLdOeSovT9i4w1DOtJYbI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Jf4xvxp7; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Jf4xvxp7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 64EF41F00A3E; Mon, 7 Sep 2026 16:37:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799078; bh=Zll3jkAF+tLjIy1FB2YfJYKG7wnrj2w3ollIYbYKORY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Jf4xvxp7r/Z8Z39ZlKwoSaMvTsC0e+lKBYm3NWf/FPYaYgKfZMTNvmcic8JgOjGxd vXb6tHu7nsCQ2xzwdo9tfZBWH4wRuj6AY2iNHfAY7OnduTVKH1wVcoQMgPYteqQAJ9 trYap4SyCn0zzjlJfJG4zUM/nvdatWZinV00zEnsu0Z7DyB3yjOT16oB6rSFGi49OF JlnegUf/ULgd7lnDNOS8AqffgOpG7iFHQ5/tg/70iDMUYSAGqSW2MaRC5YRAc/5j1+ tnW0QXfIY1KVRARAnik6nY6uZjbL86G2yYCTTIE5I9omzuF10KyS22fYD3PK6Uq1V+ FbrQDX93yhOEA== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 06/14] arm64: assembler: Remove endianness helper macros Date: Mon, 7 Sep 2026 17:37:17 +0100 Message-ID: <20260907163726.17104-7-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CPU_LE()/CPU_BE() helper macros are only used by head.S. Since big-endian support depends on BROKEN, remove the last users along with the macro definitions. The unused regs_to_64() assembly macro, which somewhat bizarrely behaves differently depend on the endianness, is also removed. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- arch/arm64/include/asm/assembler.h | 31 ------------------------------ arch/arm64/kernel/head.S | 3 +-- 2 files changed, 1 insertion(+), 33 deletions(-) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/as= sembler.h index 0b58b550e8dc..42a167a75486 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -129,37 +129,6 @@ lr .req x30 // link register b \label .endm =20 -/* - * Select code when configured for BE. - */ -#ifdef CONFIG_CPU_BIG_ENDIAN -#define CPU_BE(code...) code -#else -#define CPU_BE(code...) -#endif - -/* - * Select code when configured for LE. - */ -#ifdef CONFIG_CPU_BIG_ENDIAN -#define CPU_LE(code...) -#else -#define CPU_LE(code...) code -#endif - -/* - * Define a macro that constructs a 64-bit value by concatenating two - * 32-bit registers. Note that on big endian systems the order of the - * registers is swapped. - */ -#ifndef CONFIG_CPU_BIG_ENDIAN - .macro regs_to_64, rd, lbits, hbits -#else - .macro regs_to_64, rd, hbits, lbits -#endif - orr \rd, \lbits, \hbits, lsl #32 - .endm - /* * Pseudo-ops for PC-relative adr/ldr/str , where * is within the range +/- 4 GB of the PC. diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 87a822e5c4ca..8951ce693552 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -138,8 +138,7 @@ SYM_CODE_START_LOCAL(record_mmu_state) b.ne 0f mrs x19, sctlr_el2 0: -CPU_LE( tbnz x19, #SCTLR_ELx_EE_SHIFT, 1f ) -CPU_BE( tbz x19, #SCTLR_ELx_EE_SHIFT, 1f ) + tbnz x19, #SCTLR_ELx_EE_SHIFT, 1f tst x19, #SCTLR_ELx_C // Z :=3D (C =3D=3D 0) and x19, x19, #SCTLR_ELx_M // isolate M bit csel x19, xzr, x19, eq // clear x19 if Z --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72BFC51D50B for ; Mon, 7 Sep 2026 16:38:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799087; cv=none; b=r0e8oXwOFCWinNNCrrfU8vvXFSQLJf0mbUnBFo4hhQgKMq4Gkn/6yiJtO2LE+1Uvzp1JYVxrruizb24RFJbsTouPQkPP+7vnqUfST35fLq95mwpvDbhdlZlAzrirYFcQUWghyFlTRiLT96o1hKntpe69jKX2x7Gy7XGiZwsvw54= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799087; c=relaxed/simple; bh=MnRPA9AN2CdwXmQGgMxKMsHnto++QWhAOF8Mj15Zo0E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o4QvwgKV8CyuYo+LV/bbN311Fbd9f/9w8Kql9ypeVHLpat8ERpXO4QIw45mlx90dziVso6gnAib8BHi1Ih5x46Nc59B1GAhhre0Np+41D/FHwPx0pkI9eZAyFGNIaUM8SOFZ5StToQeNmH+rv/5dkfkNjRow8D3KuRINsTOuchU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WpfsWqlr; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WpfsWqlr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48FF71F00A3F; Mon, 7 Sep 2026 16:37:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799081; bh=KGGBej+SQ1I6McGtzO0CVbCK2WO3o2hwjiZoBeg1MN0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=WpfsWqlrMUwBRR1EH5ZCqpwogDEm/CJPNWtWBEtBuooS4VzUmdPlxEaUpushCM7H3 4RMuouTvrtIiPlTeuOAPOLGdjR/y25iJ+JgiPnehcL99HHqvkRoOgsZUZD6+ODyN64 X4DqP50cqC+NYF5B1jLZcMFCvdPZRr5HiZiRhUdzjyRsWgboCMoekZ8atcIt4X/RA6 cFZI4IrN4aYpfO3mobi1Oei/S0m7KtXOtkDe2skzhJqGRepY7kmhVrfiK4VqOwUVyb N8Lz4JPqQ01wgGQbH69mXYZZqbJR/ozVLBeaNHWUkqujrdE+kHmkSUdO1RrE6Z99uK ZojZErFH/0zLg== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 07/14] arm64: head: Force little-endian early during boot Date: Mon, 7 Sep 2026 17:37:18 +0100 Message-ID: <20260907163726.17104-8-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 2ced0f30a426 ("arm64: head: Switch endianness before populating the ID map") configured SCTLR_ELx.EE at boot according to the endianness of the kernel in case the bootloader had entered the image in the wrong endianness. Additionally, if the MMU was enabled in such a case, logic was added to turn it back off to prevent the hardware walker from misinterpreting the idmap page-table. Given that the MMU is only expected to be enabled when booting EFI, EFI only supports little-endian and arm64 kernels cannot be built as big-endian images, we can rip out this handling and simply force SCTLR_ELx.EE to 0 (little-endian). Suggested-by: Ard Biesheuvel Signed-off-by: Will Deacon --- arch/arm64/kernel/head.S | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 8951ce693552..d5c1ea0c5b3c 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -138,29 +138,11 @@ SYM_CODE_START_LOCAL(record_mmu_state) b.ne 0f mrs x19, sctlr_el2 0: - tbnz x19, #SCTLR_ELx_EE_SHIFT, 1f + bic x19, x19, #SCTLR_ELx_EE // Force little-endian tst x19, #SCTLR_ELx_C // Z :=3D (C =3D=3D 0) and x19, x19, #SCTLR_ELx_M // isolate M bit csel x19, xzr, x19, eq // clear x19 if Z ret - - /* - * Set the correct endianness early so all memory accesses issued - * before init_kernel_el() occur in the correct byte order. Note that - * this means the MMU must be disabled, or the active ID map will end - * up getting interpreted with the wrong byte order. - */ -1: eor x19, x19, #SCTLR_ELx_EE - bic x19, x19, #SCTLR_ELx_M - b.ne 2f - pre_disable_mmu_workaround - msr sctlr_el2, x19 - b 3f -2: pre_disable_mmu_workaround - msr sctlr_el1, x19 -3: isb - mov x19, xzr - ret SYM_CODE_END(record_mmu_state) =20 /* --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B17151D528 for ; Mon, 7 Sep 2026 16:38:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799089; cv=none; b=BT3asH+ATq2P8NsxNCHzJ7DlsUPKn44YstRHhfjOWLVllPvVUGrLwL5Kh/Xp8uIsvdR+PqI9BKT/ZLbYI8Im7Q+Xep0kPzRKgDLF1slNpe52teooYaziLCY+63BK5n8XIcXRoBaJxI/mD9IpdC/Typ+RclJc5xmfaTHaHzRVqzM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799089; c=relaxed/simple; bh=p4M6lxpHCBw3T7rMN4mFvzOcMlbgI5M8bXkMstTaB+M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uXQ+n83AX/2iDpGn/Ejr9rr4z3TpiEIc/4iinO+roJugNuPtpWtiBPxkHRVf3mTo08qpFLY93YIdTchlRUUbkAJbNRf1QIplNUbuXrErFtgcB4tR3PgkO05gFMp4BpWE6Qe8qq1J56s5V4jP/Hx2MUF5ymFLfJUPQvPAabInF1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PwXXppz8; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PwXXppz8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5E9F91F00A3A; Mon, 7 Sep 2026 16:38:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799084; bh=+JfwpOYvAv8ZYnfU3oq0MU6ImzI/HXu9p9BUtiuN48U=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=PwXXppz8RiCXsg/CuFuJF0bBs9LDVedC1gXhgY5HBFLvAcscR8NH11AAGkm+CkuCA hBq0lhTVQECU9NWzI5G1gy7A7cGRhhafyU/9l7NJpTFaP28H96V6eaQcN+3CLZqNDn DcNII+pNZNz/QdNTYhYnAHmGLQma0Rk17zm4Svm4m/C9ucEZ6OlgE06YD9D08Ls0Eq 3xtosPAj6UlWRoIaKwnner/gYH0QdlJfmX5VNb1s6PrKLfDC45oLPfS0OJ4O7kuNOZ nu53RvlGLQ1BxVPY/yWQly0VFRbe1wQrGeyHHzXqUXUrLOhOASpnj9I7IDaDol9fvp GY+R/B89W0+zA== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 08/14] arm64: vdso32: Always build compat vDSO object as little-endian Date: Mon, 7 Sep 2026 17:37:19 +0100 Message-ID: <20260907163726.17104-9-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Big-endian support on arm64 depends on BROKEN. In preparation for removing the dead code altogether, remove support for building a big-endian 32-bit vDSO. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- arch/arm64/kernel/vdso32/Makefile | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/kernel/vdso32/Makefile b/arch/arm64/kernel/vdso32/M= akefile index bea3675fa668..00efdc5d2354 100644 --- a/arch/arm64/kernel/vdso32/Makefile +++ b/arch/arm64/kernel/vdso32/Makefile @@ -45,11 +45,7 @@ endif # From arm Makefile VDSO_CAFLAGS +=3D $(call cc32-option,-fno-dwarf2-cfi-asm) VDSO_CAFLAGS +=3D -mabi=3Daapcs-linux -mfloat-abi=3Dsoft -ifeq ($(CONFIG_CPU_BIG_ENDIAN), y) -VDSO_CAFLAGS +=3D -mbig-endian -else VDSO_CAFLAGS +=3D -mlittle-endian -endif =20 # From arm vDSO Makefile VDSO_CAFLAGS +=3D -fPIC -fno-builtin -fno-stack-protector --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED58051D530 for ; Mon, 7 Sep 2026 16:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799089; cv=none; b=rpW/yLOX5NOtEf8snsWaTFw6NlfhKprsPCY+gqMkBoy5fROBqld2JOi/mvcfe1BRYm8qgTSzalgHdAgZYkls3E5f8Hu61uYPJ2yU0364wj0ZTBl+LMnTbXVFsbGaUD9WvwXYos0iWv56YupsaPE0ZHripbMs2FkSrPHMw7m1ka0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799089; c=relaxed/simple; bh=lRU37Z3CS5Ukfa/69eEFglkL3ie2C/ZZ/lu9FPU2XP8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jpFR92weU7shrBKw7Lbpch6Q5WvkzBCYj+0ZhLNGnY4NUD9x+Tikxa/2cVZeREkjQcDxex800Ca8XKhJ8gfBz8DCbMIHCEZc4GjWX9wQzPqXPS3D42TEPvH6mUcEcK0TtXWcpeU6BEOoEpACT3HKH/vz6Ui/RVqTQ7G9sQzCW8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IHkUFoHA; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IHkUFoHA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F46D1F00A3D; Mon, 7 Sep 2026 16:38:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799087; bh=cW6vuPa9TzUzmzyF3037nhED0lin8odzpcp8o8tSD7Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=IHkUFoHAWoATMA9skBKckKJbiStepXVxgZlqQCyIApc8bvESREAz3EHmC8ixRVLIA /5ddaccV3CJw9u9CAMQF9S0c3nglJ2Xjm6FzHoTAx3jRy9ljbsVhj1ahzn284lqe9P BlcWMsBiCGq6JQ54fR1INvZp42VCQk8ebmWheedEH1C/WXQ+zSwEZneae0ZyXKsAm+ /9wqMcALM9ld9E4ZtZtWhEnMbVGAsMFCrHwsgd5gCAJ2MERzur3eTzxpG5H1vuzmzj 3igibfbDMp2YRH3rTve/RNHBPr0SReAPZ3eXY7/fXCZHy17r3Nvv3p17bXqToTEucv sdG8qa9f02vQA== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 09/14] KVM: arm64: Remove support for a big-endian hypervisor object Date: Mon, 7 Sep 2026 17:37:20 +0100 Message-ID: <20260907163726.17104-10-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Big-endian support on arm64 depends on BROKEN. In preparation for removing the dead code altogether, remove the support for generating ELF relocations for a big-endian hypervisor object and drop the unused big-endian spinlock definition from nVHE. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- arch/arm64/kvm/hyp/include/nvhe/spinlock.h | 4 ---- arch/arm64/kvm/hyp/nvhe/gen-hyprel.c | 16 ---------------- 2 files changed, 20 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/nvhe/spinlock.h b/arch/arm64/kvm/hy= p/include/nvhe/spinlock.h index 7c7ea8c55405..b6978f03e86a 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/spinlock.h +++ b/arch/arm64/kvm/hyp/include/nvhe/spinlock.h @@ -20,11 +20,7 @@ typedef union hyp_spinlock { u32 __val; struct { -#ifdef __AARCH64EB__ - u16 next, owner; -#else u16 owner, next; -#endif }; } hyp_spinlock_t; =20 diff --git a/arch/arm64/kvm/hyp/nvhe/gen-hyprel.c b/arch/arm64/kvm/hyp/nvhe= /gen-hyprel.c index b63f4e1c1033..99243e0fefb0 100644 --- a/arch/arm64/kvm/hyp/nvhe/gen-hyprel.c +++ b/arch/arm64/kvm/hyp/nvhe/gen-hyprel.c @@ -139,28 +139,12 @@ static struct { const char *sh_string; } elf; =20 -#if defined(CONFIG_CPU_LITTLE_ENDIAN) - #define elf16toh(x) le16toh(x) #define elf32toh(x) le32toh(x) #define elf64toh(x) le64toh(x) =20 #define ELFENDIAN ELFDATA2LSB =20 -#elif defined(CONFIG_CPU_BIG_ENDIAN) - -#define elf16toh(x) be16toh(x) -#define elf32toh(x) be32toh(x) -#define elf64toh(x) be64toh(x) - -#define ELFENDIAN ELFDATA2MSB - -#else - -#error PDP-endian sadly unsupported... - -#endif - #define fatal_error(fmt, ...) \ ({ \ fprintf(stderr, "error: %s: " fmt "\n", \ --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 250F44398EE for ; Mon, 7 Sep 2026 16:38:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799092; cv=none; b=R52dX+uZZLOqcF2rCN62NjdyT3lT64lZI6KnlNQUfbD5WBBb2YFj4bzjDcooepanVQW8bgDh5MkiRq2snmxc5uKr7sFt6XY+mU5RarRLzGmby0JlpB8oeS789ADMFfQBsBRz55b68V2mXR1Z05mryLpIntthNuBgB4Mnci9GX+U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799092; c=relaxed/simple; bh=aP1uj4CdL8RqzqzTtuGEodoCDeFReiq1PaxnYnpCrec=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iVqhkJMBEhClqCf8Vk0ZPHDTyDrkHvI4p46tCKvzh3+VGULscF2MpcdZ9sPNvmu2T6sIdDn5079bGKyGDISskEA8Io4EolPDB1jReIalBC2JvID7FVpA68INF50nRWBgjHBeVaJ29YTj25Q1dGkQxe2H87jfAFINgY2k5bzjVOc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HWahDZET; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HWahDZET" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3CC701F00A3F; Mon, 7 Sep 2026 16:38:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799090; bh=L14OBfSRxgf7xskaSgwM0z3QIgQdsVQKhcz3k5MRfv4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HWahDZETTD/Aq1zo2TTmzJovV/4KecmI7M5t5/nl+58+ABq88kh/5HNes05XmcPdc 0BaFP4qwmFXjSfxhw8hajNuxVW0+jcbHCDXRwYykRrfmGReiYYw/+ib+JoAHjspUqL jRb0RhTsbNbHwTj6Joc8hq5TnQ3sHZhfUsRJ37X+BBde5BV2+cwYB1aMkozCofnhfP ie8b6tEUJmkkd7l+K9APlYP2wKVGrVXeJcWGA9wM+BAf2wpbIdSxF9SUZdRsxZUcu/ JftcF24ytcVicOr/B2yVv4TfNhVZxXyUradIJjLJckp4xuVxz3M2IfkHmWrDl6a8oG vdhfDGcIcfgpg== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 10/14] arm64: Remove all usage of CONFIG_CPU_BIG_ENDIAN Date: Mon, 7 Sep 2026 17:37:21 +0100 Message-ID: <20260907163726.17104-11-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Big-endian support on arm64 depends on BROKEN. In preparation for removing the dead code altogether, remove all usage of CONFIG_CPU_BIG_ENDIAN from the arm64 kernel port. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- arch/arm64/include/asm/processor.h | 2 -- arch/arm64/include/asm/ptrace.h | 6 ---- arch/arm64/include/asm/sysreg.h | 50 ++++++++-------------------- arch/arm64/include/asm/thread_info.h | 5 --- arch/arm64/kernel/fpsimd.c | 21 ++---------- arch/arm64/kernel/image.h | 18 ++-------- arch/arm64/kernel/kexec_image.c | 5 ++- arch/arm64/kernel/kgdb.c | 6 +--- arch/arm64/kernel/ptrace.c | 8 ++--- arch/arm64/kernel/signal32.c | 3 -- arch/arm64/kernel/sys32.c | 5 --- 11 files changed, 23 insertions(+), 106 deletions(-) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/pr= ocessor.h index 6dfbcacd9ba0..481f1999f7c1 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -351,8 +351,6 @@ static inline void compat_start_thread(struct pt_regs *= regs, unsigned long pc, unsigned long pstate =3D PSR_AA32_MODE_USR; if (pc & 1) pstate |=3D PSR_AA32_T_BIT; - if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) - pstate |=3D PSR_AA32_E_BIT; =20 start_thread_common(regs, pc, pstate); spectre_v4_enable_task_mitigation(current); diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrac= e.h index f7dc5fb9427d..57c98c775aca 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -66,12 +66,6 @@ #define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */ #define PSR_AA32_GE_MASK 0x000f0000 =20 -#ifdef CONFIG_CPU_BIG_ENDIAN -#define PSR_AA32_ENDSTATE PSR_AA32_E_BIT -#else -#define PSR_AA32_ENDSTATE 0 -#endif - /* AArch32 CPSR bits, as seen in AArch32 */ #define COMPAT_PSR_DIT_BIT 0x00200000 =20 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 7aa08d59d494..f97c60b5dfca 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -62,19 +62,10 @@ =20 #else /* CONFIG_BROKEN_GAS_INST */ =20 -#ifndef CONFIG_CPU_BIG_ENDIAN -#define __INSTR_BSWAP(x) (x) -#else /* CONFIG_CPU_BIG_ENDIAN */ -#define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ - (((x) << 8) & 0x00ff0000) | \ - (((x) >> 8) & 0x0000ff00) | \ - (((x) >> 24) & 0x000000ff)) -#endif /* CONFIG_CPU_BIG_ENDIAN */ - #ifdef __ASSEMBLER__ -#define __emit_inst(x) .long __INSTR_BSWAP(x) +#define __emit_inst(x) .long (x) #else /* __ASSEMBLER__ */ -#define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" +#define __emit_inst(x) ".long " __stringify(x) "\n\t" #endif /* __ASSEMBLER__ */ =20 #endif /* CONFIG_BROKEN_GAS_INST */ @@ -835,39 +826,26 @@ #define SCTLR_ELx_A (BIT(1)) #define SCTLR_ELx_M (BIT(0)) =20 -#ifdef CONFIG_CPU_BIG_ENDIAN -#define ENDIAN_SET_EL2 SCTLR_ELx_EE -#else -#define ENDIAN_SET_EL2 0 -#endif - #define INIT_SCTLR_EL2_MMU_ON \ (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ - SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \ - SCTLR_ELx_ITFSB | SCTLR_ELx_EIS | SCTLR_ELx_EOS | SCTLR_EL2_RES1) + SCTLR_ELx_IESB | SCTLR_ELx_WXN | SCTLR_ELx_ITFSB | \ + SCTLR_ELx_EIS | SCTLR_ELx_EOS | SCTLR_EL2_RES1) =20 -#define INIT_SCTLR_EL2_MMU_OFF \ - (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) +#define INIT_SCTLR_EL2_MMU_OFF (SCTLR_EL2_RES1) =20 /* SCTLR_EL1 specific flags. */ -#ifdef CONFIG_CPU_BIG_ENDIAN -#define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) -#else -#define ENDIAN_SET_EL1 0 -#endif - #define INIT_SCTLR_EL1_MMU_OFF \ - (ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \ - SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) + (SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ + SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) =20 #define INIT_SCTLR_EL1_MMU_ON \ - (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \ - SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \ - SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \ - SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ - ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | \ - SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ - SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) + (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \ + SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \ + SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \ + SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ + SCTLR_EL1_UCI | SCTLR_EL1_EPAN | SCTLR_EL1_LSMAOE | \ + SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | \ + SCTLR_EL1_EOS) =20 /* MAIR_ELx memory attributes (used by Linux) */ #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/= thread_info.h index 5d7fe3e153c8..161b91762e93 100644 --- a/arch/arm64/include/asm/thread_info.h +++ b/arch/arm64/include/asm/thread_info.h @@ -29,13 +29,8 @@ struct thread_info { union { u64 preempt_count; /* 0 =3D> preemptible, <0 =3D> bug */ struct { -#ifdef CONFIG_CPU_BIG_ENDIAN - u32 need_resched; - u32 count; -#else u32 count; u32 need_resched; -#endif } preempt; }; #ifdef CONFIG_SHADOW_CALL_STACK diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index e7f1682a3059..65e7147067aa 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -621,23 +621,6 @@ static int __init sme_sysctl_init(void) { return 0; } #define ZREG(sve_state, vq, n) ((char *)(sve_state) + \ (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET)) =20 -#ifdef CONFIG_CPU_BIG_ENDIAN -static __uint128_t arm64_cpu_to_le128(__uint128_t x) -{ - u64 a =3D swab64(x); - u64 b =3D swab64(x >> 64); - - return ((__uint128_t)a << 64) | b; -} -#else -static __uint128_t arm64_cpu_to_le128(__uint128_t x) -{ - return x; -} -#endif - -#define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x) - static void __fpsimd_to_sve(struct arm64_sve_state *sst, struct user_fpsimd_state const *fst, unsigned int vq) @@ -647,7 +630,7 @@ static void __fpsimd_to_sve(struct arm64_sve_state *sst, =20 for (i =3D 0; i < SVE_NUM_ZREGS; ++i) { p =3D (__uint128_t *)ZREG(sst, vq, i); - *p =3D arm64_cpu_to_le128(fst->vregs[i]); + *p =3D fst->vregs[i]; } } =20 @@ -702,7 +685,7 @@ static inline void sve_to_fpsimd(struct task_struct *ta= sk) vq =3D sve_vq_from_vl(vl); for (i =3D 0; i < SVE_NUM_ZREGS; ++i) { p =3D (__uint128_t const *)ZREG(sst, vq, i); - fst->vregs[i] =3D arm64_le128_to_cpu(*p); + fst->vregs[i] =3D *p; } } =20 diff --git a/arch/arm64/kernel/image.h b/arch/arm64/kernel/image.h index 7bc3ba897901..5c10ca773363 100644 --- a/arch/arm64/kernel/image.h +++ b/arch/arm64/kernel/image.h @@ -24,28 +24,14 @@ * when PIE is in effect. So we need to split them up in 32-bit high and l= ow * words. */ -#ifdef CONFIG_CPU_BIG_ENDIAN -#define DATA_LE32(data) \ - ((((data) & 0x000000ff) << 24) | \ - (((data) & 0x0000ff00) << 8) | \ - (((data) & 0x00ff0000) >> 8) | \ - (((data) & 0xff000000) >> 24)) -#else -#define DATA_LE32(data) ((data) & 0xffffffff) -#endif - #define DEFINE_IMAGE_LE64(sym, data) \ - sym##_lo32 =3D DATA_LE32((data) & 0xffffffff); \ - sym##_hi32 =3D DATA_LE32((data) >> 32) + sym##_lo32 =3D (data) & 0xffffffff; \ + sym##_hi32 =3D (data) >> 32 =20 #define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \ ARM64_IMAGE_FLAG_##field##_SHIFT) =20 -#ifdef CONFIG_CPU_BIG_ENDIAN -#define __HEAD_FLAG_BE ARM64_IMAGE_FLAG_BE -#else #define __HEAD_FLAG_BE ARM64_IMAGE_FLAG_LE -#endif =20 #define __HEAD_FLAG_PAGE_SIZE ((PAGE_SHIFT - 10) / 2) =20 diff --git a/arch/arm64/kernel/kexec_image.c b/arch/arm64/kernel/kexec_imag= e.c index b70f4df15a1a..b8d0fb0a9daf 100644 --- a/arch/arm64/kernel/kexec_image.c +++ b/arch/arm64/kernel/kexec_image.c @@ -40,7 +40,7 @@ static void *image_load(struct kimage *image, { struct arm64_image_header *h; u64 flags, value; - bool be_image, be_kernel; + bool be_image; struct kexec_buf kbuf =3D {}; unsigned long text_offset, kernel_segment_number; struct kexec_segment *kernel_segment; @@ -58,8 +58,7 @@ static void *image_load(struct kimage *image, /* Check cpu features */ flags =3D le64_to_cpu(h->flags); be_image =3D arm64_image_flag_field(flags, ARM64_IMAGE_FLAG_BE); - be_kernel =3D IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); - if ((be_image !=3D be_kernel) && !system_supports_mixed_endian()) + if (be_image && !system_supports_mixed_endian()) return ERR_PTR(-EINVAL); =20 value =3D arm64_image_flag_field(flags, ARM64_IMAGE_FLAG_PAGE_SIZE); diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c index 968324a79a89..3426d0908973 100644 --- a/arch/arm64/kernel/kgdb.c +++ b/arch/arm64/kernel/kgdb.c @@ -60,11 +60,7 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =3D { * 32-bits. Look for the big comment in asm/kgdb.h for more * detail. */ - { "pstate", 4, offsetof(struct pt_regs, pstate) -#ifdef CONFIG_CPU_BIG_ENDIAN - + 4 -#endif - }, + { "pstate", 4, offsetof(struct pt_regs, pstate)}, { "v0", 16, -1 }, { "v1", 16, -1 }, { "v2", 16, -1 }, diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index f743cbec1c3a..7405c76724bf 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -2517,12 +2517,8 @@ static int valid_compat_regs(struct user_pt_regs *re= gs) { regs->pstate &=3D ~SPSR_EL1_AARCH32_RES0_BITS; =20 - if (!system_supports_mixed_endian_el0()) { - if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) - regs->pstate |=3D PSR_AA32_E_BIT; - else - regs->pstate &=3D ~PSR_AA32_E_BIT; - } + if (!system_supports_mixed_endian_el0()) + regs->pstate &=3D ~PSR_AA32_E_BIT; =20 if (user_mode(regs) && (regs->pstate & PSR_MODE32_BIT) && (regs->pstate & PSR_AA32_A_BIT) =3D=3D 0 && diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c index bb3b526ff43f..5edcab50f753 100644 --- a/arch/arm64/kernel/signal32.c +++ b/arch/arm64/kernel/signal32.c @@ -334,9 +334,6 @@ static void compat_setup_return(struct pt_regs *regs, s= truct k_sigaction *ka, /* The IT state must be cleared for both ARM and Thumb-2 */ spsr &=3D ~PSR_AA32_IT_MASK; =20 - /* Restore the original endianness */ - spsr |=3D PSR_AA32_ENDSTATE; - if (ka->sa.sa_flags & SA_RESTORER) { retcode =3D ptr_to_compat(ka->sa.sa_restorer); } else { diff --git a/arch/arm64/kernel/sys32.c b/arch/arm64/kernel/sys32.c index 12a948f3a504..8ac07aeb018d 100644 --- a/arch/arm64/kernel/sys32.c +++ b/arch/arm64/kernel/sys32.c @@ -59,12 +59,7 @@ COMPAT_SYSCALL_DEFINE6(aarch32_mmap2, unsigned long, add= r, unsigned long, len, return ksys_mmap_pgoff(addr, len, prot, flags, fd, off_4k); } =20 -#ifdef CONFIG_CPU_BIG_ENDIAN -#define arg_u32p(name) u32, name##_hi, u32, name##_lo -#else #define arg_u32p(name) u32, name##_lo, u32, name##_hi -#endif - #define arg_u64(name) (((u64)name##_hi << 32) | name##_lo) =20 COMPAT_SYSCALL_DEFINE6(aarch32_pread64, unsigned int, fd, char __user *, b= uf, --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D4BB51D51D for ; Mon, 7 Sep 2026 16:38:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799098; cv=none; b=ZShxFA6DMoPLQOA+HhKcdYKRaHjZJ8tl+dAjHAD0sDv02tjFTGUydvPtQIA9TRvGM5Zn7drAMRtE3vmsvrkjzAvIz9smxA8A/OFYK4YmuHqU+EobAsuvPpLEnl0DEGcvYQkUFkm1P7HHZdnl3EBrMBVjQPdnsfCegnGNLji/9/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799098; c=relaxed/simple; bh=gTpWtQ5Q3/5Fk0L9cI5xsEhVG2z6qO6B3LElJi0KjCo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pXgkeZJp1hKFnR6l4CSexkzjaHc2ZA7LFFClQNeCTbpAqthEN+kD3EjuG/7pQYfxzZ6pPhH3SrQtVu6+rX5XMRF8eAgJbvxpFfUJF2bOSldxMbNSUdHamaW/hpEkIoyNP+Fn8V7Fxeu2/fcDpS5qX4g7BI/eREgTrhuEHEQ+ytA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AmsdiHiF; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AmsdiHiF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1EF721F00A3A; Mon, 7 Sep 2026 16:38:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799093; bh=Cv+v7XHv2TlDNTrYXK9zazof0KYVxlWwE1l3xHcWTHc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=AmsdiHiFP7IjPqEajLOTGCA8jzjbA7C9cB0aU5qDRdWaOAxF+rGAV//qTvWAMy3Bn 72LpNHhDJ2YKJurrCFElXrr2V8t694Iv1ws0vt4mBWDW51K72L+Zg+4d7ziTcz5GSi U46Epsnpek0B8Iq7Q+e+ZP/VWFdQU/TSy4pIpiRvbLlsmT8JNDtiU5rBLtEllx4ljh mOh43a9fTQiilkZZdqKLmlHgZuiAz4T3V0bt+ltlkkCJQZtjQWAII2liKcNF7cNJfx XBcjTNFYOn3fJjknrBCDF/HflqIykRgp2dz76Su1PTaiyUYsVake0Vkk4KWHZA9yeG 5SJCs0Vs4tn2w== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 11/14] arm64: Remove all usage of __AARCH64EB__ Date: Mon, 7 Sep 2026 17:37:22 +0100 Message-ID: <20260907163726.17104-12-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Big-endian support on arm64 depends on BROKEN. In preparation for removing the dead code altogether, remove all usage of __AARCH64EB__ from the arm64 kernel port. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- arch/arm64/include/asm/compat.h | 14 -------------- arch/arm64/include/asm/elf.h | 12 ------------ arch/arm64/include/asm/word-at-a-time.h | 6 ------ arch/arm64/include/uapi/asm/byteorder.h | 4 ---- arch/arm64/kernel/signal32.c | 10 ---------- arch/arm64/mm/extable.c | 5 ----- 6 files changed, 51 deletions(-) diff --git a/arch/arm64/include/asm/compat.h b/arch/arm64/include/asm/compa= t.h index ae904a1ad529..5e4cc4d2f872 100644 --- a/arch/arm64/include/asm/compat.h +++ b/arch/arm64/include/asm/compat.h @@ -28,34 +28,20 @@ typedef u16 compat_ipc_pid_t; #include #include =20 -#ifdef __AARCH64EB__ -#define COMPAT_UTS_MACHINE "armv8b\0\0" -#else #define COMPAT_UTS_MACHINE "armv8l\0\0" -#endif =20 typedef u16 __compat_uid16_t; typedef u16 __compat_gid16_t; typedef s32 compat_nlink_t; =20 struct compat_stat { -#ifdef __AARCH64EB__ - short st_dev; - short __pad1; -#else compat_dev_t st_dev; -#endif compat_ino_t st_ino; compat_mode_t st_mode; compat_ushort_t st_nlink; __compat_uid16_t st_uid; __compat_gid16_t st_gid; -#ifdef __AARCH64EB__ - short st_rdev; - short __pad2; -#else compat_dev_t st_rdev; -#endif compat_off_t st_size; compat_off_t st_blksize; compat_off_t st_blocks; diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h index d2779d604c7b..5a0bd3d38b1a 100644 --- a/arch/arm64/include/asm/elf.h +++ b/arch/arm64/include/asm/elf.h @@ -72,11 +72,7 @@ * These are used to set parameters in the core dumps. */ #define ELF_CLASS ELFCLASS64 -#ifdef __AARCH64EB__ -#define ELF_DATA ELFDATA2MSB -#else #define ELF_DATA ELFDATA2LSB -#endif #define ELF_ARCH EM_AARCH64 =20 /* @@ -85,11 +81,7 @@ * intent than poking at uname or /proc/cpuinfo. */ #define ELF_PLATFORM_SIZE 16 -#ifdef __AARCH64EB__ -#define ELF_PLATFORM ("aarch64_be") -#else #define ELF_PLATFORM ("aarch64") -#endif =20 /* * This is used to ensure we don't load something for the wrong architectu= re. @@ -195,11 +187,7 @@ extern int arch_setup_additional_pages(struct linux_bi= nprm *bprm, #define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12)) #endif =20 -#ifdef __AARCH64EB__ -#define COMPAT_ELF_PLATFORM ("v8b") -#else #define COMPAT_ELF_PLATFORM ("v8l") -#endif =20 /* AArch32 registers. */ #define COMPAT_ELF_NGREG 18 diff --git a/arch/arm64/include/asm/word-at-a-time.h b/arch/arm64/include/a= sm/word-at-a-time.h index 824ca6987a51..d7a3b69dc8c6 100644 --- a/arch/arm64/include/asm/word-at-a-time.h +++ b/arch/arm64/include/asm/word-at-a-time.h @@ -7,8 +7,6 @@ =20 #include =20 -#ifndef __AARCH64EB__ - #include #include =20 @@ -36,10 +34,6 @@ static inline unsigned long zero_bytemask(unsigned long = bits) return bits >> 7; } =20 -#else /* __AARCH64EB__ */ -#include -#endif - /* * Load an unaligned word from kernel space. * diff --git a/arch/arm64/include/uapi/asm/byteorder.h b/arch/arm64/include/u= api/asm/byteorder.h index ca9cfdab33fc..b078e60f0506 100644 --- a/arch/arm64/include/uapi/asm/byteorder.h +++ b/arch/arm64/include/uapi/asm/byteorder.h @@ -17,10 +17,6 @@ #ifndef __ASM_BYTEORDER_H #define __ASM_BYTEORDER_H =20 -#ifdef __AARCH64EB__ -#include -#else #include -#endif =20 #endif /* __ASM_BYTEORDER_H */ diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c index 5edcab50f753..3e1ce0b00a68 100644 --- a/arch/arm64/kernel/signal32.c +++ b/arch/arm64/kernel/signal32.c @@ -70,22 +70,12 @@ static inline int get_sigset_t(sigset_t *set, =20 /* * VFP save/restore code. - * - * We have to be careful with endianness, since the fpsimd context-switch - * code operates on 128-bit (Q) register values whereas the compat ABI - * uses an array of 64-bit (D) registers. Consequently, we need to swap - * the two halves of each Q register when running on a big-endian CPU. */ union __fpsimd_vreg { __uint128_t raw; struct { -#ifdef __AARCH64EB__ - u64 hi; - u64 lo; -#else u64 lo; u64 hi; -#endif }; }; =20 diff --git a/arch/arm64/mm/extable.c b/arch/arm64/mm/extable.c index 6e0528831cd3..299a244f68e6 100644 --- a/arch/arm64/mm/extable.c +++ b/arch/arm64/mm/extable.c @@ -79,12 +79,7 @@ ex_handler_load_unaligned_zeropad(const struct exception= _table_entry *ex, addr &=3D ~0x7UL; =20 data =3D *(unsigned long*)addr; - -#ifndef __AARCH64EB__ data >>=3D 8 * offset; -#else - data <<=3D 8 * offset; -#endif =20 pt_regs_write_reg(regs, reg_data, data); =20 --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDFAB51FCB5 for ; Mon, 7 Sep 2026 16:38:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799099; cv=none; b=Bo66SmgGLoqffetjt9Ajphynw0HPbJEA7lpnzIAa8o9nXnIzXt6hXFrQGgc4aH4MeS2wh/VjhkmmnU94kh2c7OYWB+abbPwSMlS2LpzIjOpxt3QnwiZ6iYdbOFrCxW5D0hPWru5RGss0Ejo+lEcM06fROSbQjS4GRldAYSMD3x0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799099; c=relaxed/simple; bh=ht/J+KgrJNdHsVyi5zxPYSI6hx89hWR1lAg3J3UNuDI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=caMoxo1BYWS/7g5HdkkjWe214BlPXNnlbjSCGuk9eN5PgO+Hv/RuxnDWRRcfUx9Kyx6W31MZOB6lHGWB80bJ/cen8F86g8P2tqs1Vr89KrurMLTzO3tJ1JzB8ESq+si7NMucyqQupyQ42H7jwSEzoj9VXX4yNgHkLHLAlSYaujQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ir3y2FjA; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ir3y2FjA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B68B1F00AC4; Mon, 7 Sep 2026 16:38:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799096; bh=cJrqXzm1RgA1zc/T2scZywYeVxqva7PTGuSCFxHRGhQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ir3y2FjAD4kEffnFLSp0BzrQ5G5MO5Cc/NdZaerNSQgN2sUO2a3qYvD/uhkkXlaRw lUuqQI9JlbZVx2hqjitH60UOmJo4obI7OTFa8s7KzuINzGhPp8pV/+LkiKtvrKXxuS RY0gUlh6flyXo2H3MlynsNwwY73dx7GR61EiSDYvTpfLyssJpYIbVKn5HMYXEitklr iVxQC5UDMVR2ACHAi30NqMCTwgKs+85usUVnPc+QP9WUvyd8N0ZxoJpvFI9JCS1CGW W+cugKLWwm9QavwEqLJWUdvoonSjFky0xKPLNqHqZmYzFCEE9F7jQONzdXgJuw3XiO EdNKmFIXeBAfA== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 12/14] arm64: image: Remove endianness handling for generating image header Date: Mon, 7 Sep 2026 17:37:23 +0100 Message-ID: <20260907163726.17104-13-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since big-endian support for arm64 depends on BROKEN, we don't need to bother jumping through hoops to generate a little-endian kernel image header for a big-endian target. We can just ignore the possibility instead. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- arch/arm64/include/asm/assembler.h | 11 ----------- arch/arm64/kernel/head.S | 4 ++-- arch/arm64/kernel/image.h | 24 ++---------------------- 3 files changed, 4 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/as= sembler.h index 42a167a75486..43bc5037c234 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -521,17 +521,6 @@ alternative_else_nop_endif #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name) #endif =20 - /* - * Emit a 64-bit absolute little endian symbol reference in a way that - * ensures that it will be resolved at build time, even when building a - * PIE binary. This requires cooperation from the linker script, which - * must emit the lo32/hi32 halves individually. - */ - .macro le64sym, sym - .long \sym\()_lo32 - .long \sym\()_hi32 - .endm - /* * mov_q - move an immediate constant into a 64-bit register using * between 2 and 4 movz/movk instructions (depending on the diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index d5c1ea0c5b3c..0b9c973a5327 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -61,8 +61,8 @@ efi_signature_nop // special NOP to identity as PE/COFF executable b primary_entry // branch to kernel start, magic .quad 0 // Image load offset from start of RAM, little-endian - le64sym _kernel_size_le // Effective size of kernel image, little-endian - le64sym _kernel_flags_le // Informative flags, little-endian + .quad _kernel_size_le // Effective size of kernel image, little-endian + .quad _kernel_flags_le // Informative flags, little-endian .quad 0 // reserved .quad 0 // reserved .quad 0 // reserved diff --git a/arch/arm64/kernel/image.h b/arch/arm64/kernel/image.h index 5c10ca773363..208843f96b4d 100644 --- a/arch/arm64/kernel/image.h +++ b/arch/arm64/kernel/image.h @@ -13,21 +13,6 @@ =20 #include =20 -/* - * There aren't any ELF relocations we can use to endian-swap values known= only - * at link time (e.g. the subtraction of two symbol addresses), so we must= get - * the linker to endian-swap certain values before emitting them. - * - * Note that, in order for this to work when building the ELF64 PIE execut= able - * (for KASLR), these values should not be referenced via R_AARCH64_ABS64 - * relocations, since these are fixed up at runtime rather than at build t= ime - * when PIE is in effect. So we need to split them up in 32-bit high and l= ow - * words. - */ -#define DEFINE_IMAGE_LE64(sym, data) \ - sym##_lo32 =3D (data) & 0xffffffff; \ - sym##_hi32 =3D (data) >> 32 - #define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \ ARM64_IMAGE_FLAG_##field##_SHIFT) =20 @@ -41,13 +26,8 @@ __HEAD_FLAG(PAGE_SIZE) | \ __HEAD_FLAG(PHYS_BASE)) =20 -/* - * These will output as part of the Image header, which should be little-e= ndian - * regardless of the endianness of the kernel. While constant values could= be - * endian swapped in head.S, all are done here for consistency. - */ #define HEAD_SYMBOLS \ - DEFINE_IMAGE_LE64(_kernel_size_le, _end - _text); \ - DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS); + _kernel_size_le =3D _end - _text; \ + _kernel_flags_le =3D __HEAD_FLAGS; =20 #endif /* __ARM64_KERNEL_IMAGE_H */ --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B67FC51D512 for ; Mon, 7 Sep 2026 16:38:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799103; cv=none; b=gVGs8ICMGaDPQNRdvJ70qmiHlv4HoKpRhwgFq563V7852wQBaK6BN6n4jizg7a51R4L24HnuNfEzY+Ge+OIjnMNQeY/SPsgu9+lgDi4rInoyfhX6UPRbJNCDsK1A1cCSYNWMRMidgJJJ6gqAx9k753q2iWRGhfCbu+iHFKI67Po= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799103; c=relaxed/simple; bh=VAr8AxPPEj3FLsU4fsWXo7n7fLtMSu4gN4ae85pi/0w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HbaOWF0W55JXqATPNpPQA8ZN56l1Oz6+/azzIXf3usm3RRaOmBKLnYOeI1ExTa8awz57KZHJS0K0DUGpC5uvJtVVAXEJZwq4GofnvePMuu07X9VxSBqjNtb36iLtJE+V5DsJpxd7p0P055/bvoMEOhWNp/kGebTNnnE0aRfUyyM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Jk70/5d/; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Jk70/5d/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 014771F00A3D; Mon, 7 Sep 2026 16:38:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799099; bh=yw1P9vOFsqivhB5iGao14JrGpmYpz1xeNiJ0ljEBsf4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Jk70/5d/128aQs/mpfdWWCrMyTDcEfzYH1dlokTueYgxQr5AcY1f+UutB8Ve0ZqFa tDyJ+GSvwau4BUGgo7sbYDe7449H4UCMS7pti7NAPVYErHyYQd/4vCKSy6DA9tiJSS kitRXcwORdksX/81HE+me9avbmnUUGEMi6IsQIc+CUKpoUJRo6rjldlWlWCS5ChO5G +8Z3PnQLFZBxTkJR+/VnCzLdxYieq1RfZsVw9ezazQgx+/czXvEGcHeEei314etfqF S4JRy6YjZi2A1bNaHo+cCXWlBMkJWo/x6WS+RM8ecss+hvPP7Hz6KT8H8UZTHLlZqZ d2zVTSNZ2KjRw== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 13/14] arm64: Kbuild: Remove vestigial big-endian support Date: Mon, 7 Sep 2026 17:37:24 +0100 Message-ID: <20260907163726.17104-14-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since 1cf89b6bf660 ("arm64: Kconfig: Make CPU_BIG_ENDIAN depend on BROKEN"), CONFIG_CPU_BIG_ENDIAN has depended on BROKEN for arm64. Remove the last traces of its existence and unconditionally force a little-endian kernel build. Acked-by: Catalin Marinas Acked-by: Arnd Bergmann Acked-by: Marc Zyngier Acked-by: Eric Biggers Signed-off-by: Will Deacon --- arch/arm64/Kconfig | 35 ++++------------------------------- arch/arm64/Makefile | 12 ++---------- 2 files changed, 6 insertions(+), 41 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b5a51b0ef944..766410827f3c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -73,7 +73,7 @@ config ARM64 select ARCH_SUPPORTS_HUGETLBFS select ARCH_SUPPORTS_MEMORY_FAILURE select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK - select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN + select ARCH_SUPPORTS_LTO_CLANG select ARCH_SUPPORTS_LTO_CLANG_THIN select ARCH_SUPPORTS_CFI select ARCH_SUPPORTS_ATOMIC_RMW @@ -224,7 +224,7 @@ config ARM64 select HAVE_FUNCTION_ARG_ACCESS_API select MMU_GATHER_RCU_TABLE_FREE select HAVE_RSEQ - select HAVE_RUST if RUSTC_SUPPORTS_ARM64 + select HAVE_RUST select HAVE_STACKPROTECTOR select HAVE_STATIC_CALL if CFI select HAVE_SYSCALL_TRACEPOINTS @@ -263,10 +263,6 @@ config ARM64 help ARM 64-bit (AArch64) Linux support. =20 -config RUSTC_SUPPORTS_ARM64 - def_bool y - depends on CPU_LITTLE_ENDIAN - config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS def_bool CC_IS_CLANG # https://github.com/ClangBuiltLinux/linux/issues/1507 @@ -1596,28 +1592,6 @@ config ARM64_LPA2 def_bool y depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES =20 -choice - prompt "Endianness" - default CPU_LITTLE_ENDIAN - help - Select the endianness of data accesses performed by the CPU. Userspace - applications will need to be compiled and linked for the endianness - that is selected here. - -config CPU_BIG_ENDIAN - bool "Build big-endian kernel" - depends on BROKEN - help - Say Y if you plan on running a kernel with a big-endian userspace. - -config CPU_LITTLE_ENDIAN - bool "Build little-endian kernel" - help - Say Y if you plan on running a kernel with a little-endian userspace. - This is usually the case for distributions targeting arm64. - -endchoice - config NR_CPUS int "Maximum number of CPUs (2-4096)" range 2 4096 @@ -1855,7 +1829,6 @@ config KUSER_HELPERS =20 config COMPAT_VDSO bool "Enable vDSO for 32-bit applications" - depends on !CPU_BIG_ENDIAN depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" !=3D "" default y help @@ -2319,7 +2292,7 @@ menu "ARMv9.6 architectural features" config ARM64_LSUI bool "Support Unprivileged Load Store Instructions (LSUI)" default y - depends on AS_HAS_LSUI && !CPU_BIG_ENDIAN + depends on AS_HAS_LSUI help The Unprivileged Load Store Instructions (LSUI) provides variants load/store instructions that access user-space memory @@ -2524,7 +2497,7 @@ config EFI_STUB =20 config EFI bool "UEFI runtime support" - depends on OF && !CPU_BIG_ENDIAN + depends on OF depends on KERNEL_MODE_NEON select ARCH_SUPPORTS_ACPI select LIBFDT diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index 6b005c8fef70..04e1a0d12f8f 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -119,20 +119,12 @@ KBUILD_CFLAGS +=3D -ffixed-x18 KBUILD_RUSTFLAGS +=3D -Zfixed-x18 endif =20 -ifeq ($(CONFIG_CPU_BIG_ENDIAN), y) -KBUILD_CPPFLAGS +=3D -mbig-endian -CHECKFLAGS +=3D -D__AARCH64EB__ -# Prefer the baremetal ELF build target, but not all toolchains include -# it so fall back to the standard linux version if needed. -KBUILD_LDFLAGS +=3D -EB $(call ld-option, -maarch64elfb, -maarch64linuxb -= z norelro) -UTS_MACHINE :=3D aarch64_be -else KBUILD_CPPFLAGS +=3D -mlittle-endian CHECKFLAGS +=3D -D__AARCH64EL__ -# Same as above, prefer ELF but fall back to linux target if needed. +# Prefer the baremetal ELF build target, but not all toolchains include +# it so fall back to the standard linux version if needed. KBUILD_LDFLAGS +=3D -EL $(call ld-option, -maarch64elf, -maarch64linux -z = norelro) UTS_MACHINE :=3D aarch64 -endif =20 ifeq ($(CONFIG_LD_IS_LLD), y) KBUILD_LDFLAGS +=3D -z norelro --=20 2.55.0.979.g7e5102b832-goog From nobody Wed Sep 9 10:35:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5D464398EE for ; Mon, 7 Sep 2026 16:38:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799107; cv=none; b=DLjZc8SMb74FR+Sfwtkp+wKhLt3zYctrsnKgFAEYLP+kTF1lUP/rOr99f2+TzS0PzqQklBSyU4b0SjUsm2lZxP42hUbNkyvkOVMMqdmbRsZNnMUtZwvvCjT4ZqgWLHMsw3J1jNRpGfmcRaHyuOmheM1LvhvvH0Tf/mk7MoMMlNo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788799107; c=relaxed/simple; bh=W5UwLSfWc9QDDceRAm4JfS+roNCeZvLDiHeD4TXui+g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GsPcuzRAxKk/VWso92rb2N9sRxQQv6D/C/RQWq+AKljKwBo0VhXVvVVwinQ17g+Jx7rk2WOcXcTqva6Mbjl4+9jTwLKyKuIo/6zDeTeBgmyFw3kXl+OpHweeHBlnLZdCrMmA2qJm0QPUFZr7pWXh0w64I8zuYKSlmFW4pArCS1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FFMGgLBd; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FFMGgLBd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D81481F00A3A; Mon, 7 Sep 2026 16:38:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788799102; bh=6pHk/hPGGOdk5BOs4bGnqFo2AynNXfu7gPSxw1mavzc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=FFMGgLBda19SYh+eB9lpR3Gr82pybmSpXdCjzi4fW+gISsVPxsXUxFFOfmz9/o/nh qGgGeqkioOUKV1/VE32SZ7s1YaofJwzfMphhx5awWoawF2z4pAgMZ1yDEt4No7Q3Zy Wn+cKHWYa5+0gNZE+FKL1Jkn8RidPOM59kK1L158qLYdPWxp+4FVNQBlCrzJ44HwPm dnQ/a1Tyr5vIdTveEOMvn0RBdM6NTU474XsyjLP9T/Nzytn6DKkRW1XljcKlbEUKTW tVmKLdCB5v0DdsPB0hixaj/hb2cu5VN+gzVIctIeBOc5oSFt3u/g62i0rwAsQPwziK Hw6UVnj9JEQHw== From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Arnd Bergmann , Ard Biesheuvel , Eric Biggers , Daniel Borkmann , Catalin Marinas , Alexei Starovoitov , Oliver Upton , Herbert Xu , Marc Zyngier Subject: [PATCH v2 14/14] drivers: Kconfig: Simplify dependencies on ARM64 && !CPU_BIG_ENDIAN Date: Mon, 7 Sep 2026 17:37:25 +0100 Message-ID: <20260907163726.17104-15-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260907163726.17104-1-will@kernel.org> References: <20260907163726.17104-1-will@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that arm64 no longer supports a big-endian kernel, simplify some driver Kconfig entries so that the dependency on a little-endian kernel no longer needs to be called out explicitly. Suggested-by: Arnd Bergmann Signed-off-by: Will Deacon --- drivers/hv/Kconfig | 3 +-- drivers/misc/vmw_vmci/Kconfig | 2 +- drivers/net/ethernet/microsoft/Kconfig | 2 +- drivers/soc/tegra/Kconfig | 5 ----- 4 files changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/hv/Kconfig b/drivers/hv/Kconfig index aa11bcefddf2..36445c2619ed 100644 --- a/drivers/hv/Kconfig +++ b/drivers/hv/Kconfig @@ -4,8 +4,7 @@ menu "Microsoft Hyper-V guest support" =20 config HYPERV bool "Microsoft Hyper-V core hypervisor support" - depends on (X86 && X86_LOCAL_APIC && HYPERVISOR_GUEST) \ - || (ARM64 && !CPU_BIG_ENDIAN) + depends on (X86 && X86_LOCAL_APIC && HYPERVISOR_GUEST) || ARM64 select PARAVIRT select X86_HV_CALLBACK_VECTOR if X86 select OF_EARLY_FLATTREE if OF diff --git a/drivers/misc/vmw_vmci/Kconfig b/drivers/misc/vmw_vmci/Kconfig index b6d4d7fd686a..ca03cbfdab1e 100644 --- a/drivers/misc/vmw_vmci/Kconfig +++ b/drivers/misc/vmw_vmci/Kconfig @@ -5,7 +5,7 @@ =20 config VMWARE_VMCI tristate "VMware VMCI Driver" - depends on (X86 || ARM64) && !CPU_BIG_ENDIAN && PCI + depends on (X86 || ARM64) && PCI help This is VMware's Virtual Machine Communication Interface. It enables high-speed communication between host and guest in a virtual diff --git a/drivers/net/ethernet/microsoft/Kconfig b/drivers/net/ethernet/= microsoft/Kconfig index e9be18c92ca5..c4ad3d85875a 100644 --- a/drivers/net/ethernet/microsoft/Kconfig +++ b/drivers/net/ethernet/microsoft/Kconfig @@ -18,7 +18,7 @@ if NET_VENDOR_MICROSOFT config MICROSOFT_MANA tristate "Microsoft Azure Network Adapter (MANA) support" depends on PCI_MSI - depends on X86_64 || (ARM64 && !CPU_BIG_ENDIAN) + depends on X86_64 || ARM64 depends on PCI_HYPERV select AUXILIARY_BUS select DIMLIB diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 8b6fdb9ad1ea..318e7b604342 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -102,7 +102,6 @@ config ARCH_TEGRA_210_SOC config ARCH_TEGRA_186_SOC bool "NVIDIA Tegra186 SoC" default ARCH_TEGRA - depends on !CPU_BIG_ENDIAN select PINCTRL_TEGRA186 select MAILBOX select SOC_TEGRA_PMC @@ -117,7 +116,6 @@ config ARCH_TEGRA_186_SOC config ARCH_TEGRA_194_SOC bool "NVIDIA Tegra194 SoC" default ARCH_TEGRA - depends on !CPU_BIG_ENDIAN select MAILBOX select PINCTRL_TEGRA194 select SOC_TEGRA_PMC @@ -127,7 +125,6 @@ config ARCH_TEGRA_194_SOC config ARCH_TEGRA_234_SOC bool "NVIDIA Tegra234 SoC" default ARCH_TEGRA - depends on !CPU_BIG_ENDIAN select MAILBOX select PINCTRL_TEGRA234 select SOC_TEGRA_PMC @@ -137,7 +134,6 @@ config ARCH_TEGRA_234_SOC config ARCH_TEGRA_238_SOC bool "NVIDIA Tegra238 SoC" default ARCH_TEGRA - depends on !CPU_BIG_ENDIAN select MAILBOX select SOC_TEGRA_PMC help @@ -152,7 +148,6 @@ config ARCH_TEGRA_241_SOC config ARCH_TEGRA_264_SOC bool "NVIDIA Tegra264 SoC" default ARCH_TEGRA - depends on !CPU_BIG_ENDIAN select MAILBOX select SOC_TEGRA_PMC help --=20 2.55.0.979.g7e5102b832-goog