From nobody Fri Sep 25 23:08:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9726E4FB9D9 for ; Mon, 7 Sep 2026 15:30:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788795060; cv=none; b=Or/TPNYhVm5jgDc2pzaU+qBL5d9dOFjfQClfX+zLHdWGp3s6eqYuxDzpy8nGijErQEmx7rGZFJMyWyBh6fh3+szr1RvRpCyR71ysMi8Nhb21qtAbHyENoEW5q3eSR/tVSiDRmcH0ekYnFm0/ZJpbkdmHyOMLVSZtOd8W2iz7Nss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788795060; c=relaxed/simple; bh=1QsG25l8O2VLEuh25KrJgG3bL6h9kYPyJ9RRUufkS8U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QIFSFV7xMRwzcXOH2MkjnghsOIwlPhrZ+x1Xt9Xn2zpyXk7LnJeCnFEgCi9xwoNTivhl/5Y35y5Uxd9VFkOuYphpk5M8dpfeUoiAE9Wq6uHj7q7BDVEhi8O1dtNnZ3mDUWRUdMww1L//taGLomlBYM0iaqGuiNVTAecQtah1tdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WinvTtgF; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WinvTtgF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 71EC91F00A3D; Mon, 7 Sep 2026 15:30:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788795059; bh=WvJFOaQphIvH9VnjYWr9Zi/URbyT/0/TQJJh1ji7GNg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=WinvTtgFjsSvUMJkutVN78b2uPtVLCxQGgdANfz/jYwye8YpZcqq8eYtvL2gF8mbV HoYiwyhK1OYrDwGMNH1yO79xbNfTFTqQMEnkbzb+OMGiK9s4XCPD3DkQYhtdQ/NqgU cvJFvTRDidGczKbvv/v150iqiG1HTdBCe++xp68PSdURPpWC1/IYkxP2bG/ukWy+30 Bntrh1AqXUs1BqDKDaFD+frW30Zo40tDGRSm+DTr6EICD8hm+N0ACInODCaY+fKRxD JYooH2cbZX5NLxZK80iu/UHV6wtFAB7+hNwGlWgIAWRfSqHNYQ0ERhKl6p6tF2BAa8 IWl0b4W1FH6aQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Nam Cao Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] riscv: word-at-a-time: improve find_zero() for !RISCV_ISA_ZBB Date: Mon, 7 Sep 2026 23:11:06 +0800 Message-ID: <20260907151108.7538-2-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260907151108.7538-1-jszhang@kernel.org> References: <20260907151108.7538-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current find_zero() heavily depends on fls64() for calculation. This bring non-optimal code when !RISCV_ISA_ZBB. But in word-at-a-time case, we don't have to go with fls64() code path, instead, we can fallback to the generic word-at-a-time implementaion. What's more, the fls64() brings non-necessary zero bits couting for RV32. In fact, fls() is enough. Before the patch: 0000000000000000 : 0: c529 beqz a0,4a <.L1> 2: 577d li a4,-1 4: 9301 srli a4,a4,0x20 6: 03f00793 li a5,63 a: 00a76463 bltu a4,a0,12 <.L3> e: 1502 slli a0,a0,0x20 10: 47fd li a5,31 0000000000000012 <.L3>: 12: 577d li a4,-1 14: 8341 srli a4,a4,0x10 16: 00a76463 bltu a4,a0,1e <.L4> 1a: 37c1 addiw a5,a5,-16 1c: 0542 slli a0,a0,0x10 000000000000001e <.L4>: 1e: 577d li a4,-1 20: 8321 srli a4,a4,0x8 22: 00a76463 bltu a4,a0,2a <.L5> 26: 37e1 addiw a5,a5,-8 28: 0522 slli a0,a0,0x8 000000000000002a <.L5>: 2a: 577d li a4,-1 2c: 8311 srli a4,a4,0x4 2e: 00a76463 bltu a4,a0,36 <.L6> 32: 37f1 addiw a5,a5,-4 34: 0512 slli a0,a0,0x4 0000000000000036 <.L6>: 36: 577d li a4,-1 38: 8309 srli a4,a4,0x2 3a: 00a76463 bltu a4,a0,42 <.L7> 3e: 37f9 addiw a5,a5,-2 40: 050a slli a0,a0,0x2 0000000000000042 <.L7>: 42: 00054563 bltz a0,4c <.L12> 46: 4037d51b sraiw a0,a5,0x3 000000000000004a <.L1>: 4a: 8082 ret 000000000000004c <.L12>: 4c: 2785 addiw a5,a5,1 4e: 4037d51b sraiw a0,a5,0x3 52: 8082 ret After the patch: 0000000000000000 : 0: 102037b7 lui a5,0x10203 4: 0792 slli a5,a5,0x4 6: 40578793 addi a5,a5,1029 # 10203405 <.L4+0x102033c5> a: 07c2 slli a5,a5,0x10 c: 60878793 addi a5,a5,1544 10: 02f50533 mul a0,a0,a5 14: 9161 srli a0,a0,0x38 16: 8082 ret 33 instructions vs 8 instructions! And this kind of instructions reducing dramatically improves the performance of below micro-benchmark: $ cat tt.c #inlcude #inlcude "word-at-a-time.h" // copy and modify, eg. remove other headers int main() { int i; unsigned long ret =3D 0; for (i =3D 0; i < 100000000; i++) ret |=3D find_zero(0xabcd123 + i); printf("%ld\n", ret); } $ gcc -O tt.c $ time ./a.out Per my test, the above micro-benchmark is improved by about 1150%! Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/word-at-a-time.h | 29 ++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/a= sm/word-at-a-time.h index 3802cda71ab7..1dcac57a73dd 100644 --- a/arch/riscv/include/asm/word-at-a-time.h +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -39,9 +39,36 @@ static inline unsigned long create_zero_mask(unsigned lo= ng bits) return bits >> 7; } =20 +#ifdef CONFIG_64BIT +/* + * Jan Achrenius on G+: microoptimized version of + * the simpler "(mask & ONEBYTES) * ONEBYTES >> 56" + * that works for the bytemasks without having to + * mask them first. + */ +static inline long count_masked_bytes(unsigned long mask) +{ + return mask*0x0001020304050608ul >> 56; +} + +#else /* 32-bit case */ + +/* Carl Chatfield / Jan Achrenius G+ version for 32-bit */ +static inline long count_masked_bytes(long mask) +{ + /* (000000 0000ff 00ffff ffffff) -> ( 1 1 2 3 ) */ + long a =3D (0x0ff0001+mask) >> 23; + /* Fix the 1 for 00 case */ + return a & mask; +} +#endif + static inline unsigned long find_zero(unsigned long mask) { - return fls64(mask) >> 3; + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB)) + return fls64(mask) >> 3; + + return count_masked_bytes(mask); } =20 /* The mask we created is directly usable as a bytemask */ --=20 2.53.0 From nobody Fri Sep 25 23:08:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41080509EF9 for ; Mon, 7 Sep 2026 15:31:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788795063; cv=none; b=WYG7hctYzFgA7/lS6+5xouavgbGmLzpxvDe9Uzux+BZBOlu4om+j1Bup266JgKyyhSg99gC+yyE1wAs//9GnFaVkNFt1pERyEr6QaWu+BV36EYSMcYwZaCWby87zWQLAGV3Q8kGGxTAALG4Xtdtm85yNSDCn+KTK+CJDIQLEVFc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788795063; c=relaxed/simple; bh=xNviF0x+9Ezvq2RBwqqfdR68vwj/iGmWyIWY9YebzMc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aIQbCyfkm25cUDyk5ovJpS26zkF9SyWHUaiMu1CGOeo5XyvK6jSaCB7zilZ2H3Cuo6t4ixTdZ76c93FGFGdtPGL0ZBtA+1hrlREr0zPKTSBAA/2tM9UKAeMQKKg/o62xZgf9yPH4jRJjR2ypHN7Oe3TYsEb1LwRugszplNcm8fw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HVw6X8N+; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HVw6X8N+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A27EA1F00A3A; Mon, 7 Sep 2026 15:30:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788795061; bh=gPSXCb0eA8BM+P5Y//s4nfh/kZxqoCvqmOhim53CK5s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HVw6X8N+utM+7JDNNFBTJ6314EnGppkvDrdoo/DJ1cIgh6HQDf5/ltQfz0/YndugQ nxlxrNvSvSBJKNPilHQ9ielMzQezBDtSBJhcpX/61E+WFuFtqgoOfGOudln2bnsRsL cH54ofASFpHzZdw91vaozCCtLniOPSFJGd7IKIqB8gguLvElxkUCs+dpbuOcfseq9x 2l8C6AewxhCpYJMR/FvK8ND1kM7kxEKIAV0A68s6XYLJj2qNCKfloNrLCYqhwotUNd Qpc87G04ZhZJUYHVFqTt+t5LbHaEsOcA4KfEbeJcSC4xSiHlfDvQFD26XYn/21N2Pq 8FoIExiR5SThA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Nam Cao Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] riscv: word-at-a-time: improve find_zero() without Zbb Date: Mon, 7 Sep 2026 23:11:07 +0800 Message-ID: <20260907151108.7538-3-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260907151108.7538-1-jszhang@kernel.org> References: <20260907151108.7538-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Previous commit improved the find_zero() performance for !RISCV_ISA_ZBB. What about RISCV_ISA_ZBB=3Dy but the HW doesn't support Zbb? We have the same heavy generic fls64() issue. Let's improve this situation by checking Zbb extension and fall back to generic count_masked_bytes() if Zbb isn't supported. To remove non-necessary zero bits couting on RV32, we also replace the 'fls64(mask) >> 3' with '!mask ? 0 : ((__fls(mask) + 1) >> 3);' We will get similar performance improvement as previous commit for RISCV_ISA_ZBB=3Dy but HW doesn't support Zbb. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/word-at-a-time.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/a= sm/word-at-a-time.h index 1dcac57a73dd..f2d16c1eea8d 100644 --- a/arch/riscv/include/asm/word-at-a-time.h +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -65,8 +65,9 @@ static inline long count_masked_bytes(long mask) =20 static inline unsigned long find_zero(unsigned long mask) { - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB)) - return fls64(mask) >> 3; + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB) && + riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return !mask ? 0 : ((__fls(mask) + 1) >> 3); =20 return count_masked_bytes(mask); } --=20 2.53.0 From nobody Fri Sep 25 23:08:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F0DB4C0433 for ; Mon, 7 Sep 2026 15:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788795066; cv=none; b=psANtF2W28iUE7EWwHA/7AQzxh5KApS2dEMhrmKF/VhKzSzAUzRd3MvysgsaGI1LnxfnRz6VZFXz5ttog0ApL1BNWtevQc7ix9myevmWrRRAA9kMFx8K8ZkgqQPl4itVZ8wTVblgkjmhLLWYSnq/8Dpb5ibmkWU3f3ts0b+sqS4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788795066; c=relaxed/simple; bh=ZK1O7KYuEr3rzcB8WPP1+gyGYb3hDxuJ9CWbYDMMmNs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TlXNbUjcdaC0/t/dwnOU+wS4TdtvUGsnHFYu33R4apCmWlDoG8wB4bjw3tf/psJ3HtAx9CFUIrgun+cNhkcMtSCLLMI+pZiRA3c9uHTSte0uPbzUTghsh1UC2F3qLnngA7leWVjsZL+etDg4BBXsA5b8QRg+7hQNdCFdF+Asr2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nsBrDlCP; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nsBrDlCP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 921231F00A3D; Mon, 7 Sep 2026 15:31:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788795064; bh=U1/4nM4HTUPSSUQ1nie+OmGSZKZ9RR8PG8T23avywYE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=nsBrDlCPzbfm8aeLoJScIP5W4Js0JngNl5haBXUNqCRbYFl4ygb92NtuebaX4clA1 Ly9gbYjyhs8Z+EQDiz/bfu+XIwRYtpdFNrNfAFelm6x8hb6kx7ISRR8OOzIqwPtAcG BgFHyl81e1myd1CjLRVark2OB9BeOoB/ANnAQRz8ssFaVSFILzuC4OWaRACfgkrbVE bgjlL1yDR6a6LbR+4MH9Y3giC09yF1LKoMcHqvtve8cJv0TVv8k4U1YR00VemCsT5J vVCJwczftku8UEGy8VKPgv9YmgXt1J8qDarNs18ud4MD+WtVB8QKW1yoGtks5cDHqN V0qfZprSaubbA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Nam Cao Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] riscv: word-at-a-time: improve find_zero() for Zbb Date: Mon, 7 Sep 2026 23:11:08 +0800 Message-ID: <20260907151108.7538-4-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260907151108.7538-1-jszhang@kernel.org> References: <20260907151108.7538-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In commit f915a3e5b018 ("arm64: word-at-a-time: improve byte count calculations for LE"), Linus improved the find_zero() for arm64 LE. Do the same optimization as he did: "do __ffs() on the intermediate value that found whether there is a zero byte, before we've actually computed the final byte mask.", so that we share the similar improvements: "The difference between the old and the new implementation is that "count_zero()" ends up scheduling better because it is being done on a value that is available earlier (before the final mask). But more importantly, it can be implemented without the insane semantics of the standard bit finding helpers that have the off-by-one issue and have to special-case the zero mask situation." Before the patch: 0000000000000000 : 0: c909 beqz a0,12 <.L1> 2: 60051793 clz a5,a0 6: 03f00513 li a0,63 a: 8d1d sub a0,a0,a5 c: 2505 addiw a0,a0,1 e: 4035551b sraiw a0,a0,0x3 0000000000000012 <.L1>: 12: 8082 ret After the patch: 0000000000000000 : 0: 60151513 ctz a0,a0 4: 810d srli a0,a0,0x3 6: 8082 ret 7 instructions vs 3 instructions! As can be seen, on RV64 w/ Zbb, the new "find_zero()" ends up just "ctz" plus the shift right that then ends up being subsumed by the "add to final length". But I have no HW platform which supports Zbb, so I can't get the performance improvement numbers by the last patch, only built and tested the patch on QEMU. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/word-at-a-time.h | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/a= sm/word-at-a-time.h index f2d16c1eea8d..31240133eccd 100644 --- a/arch/riscv/include/asm/word-at-a-time.h +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -35,6 +35,10 @@ static inline unsigned long prep_zero_mask(unsigned long= val, =20 static inline unsigned long create_zero_mask(unsigned long bits) { + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB) && + riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return bits; + bits =3D (bits - 1) & ~bits; return bits >> 7; } @@ -67,13 +71,21 @@ static inline unsigned long find_zero(unsigned long mas= k) { if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) - return !mask ? 0 : ((__fls(mask) + 1) >> 3); + return __ffs(mask) >> 3; =20 return count_masked_bytes(mask); } =20 -/* The mask we created is directly usable as a bytemask */ -#define zero_bytemask(mask) (mask) +static inline unsigned long zero_bytemask(unsigned long bits) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB) && + riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { + bits =3D (bits - 1) & ~bits; + return bits >> 7; + } + + return bits; +} =20 #ifdef CONFIG_DCACHE_WORD_ACCESS =20 --=20 2.53.0