From nobody Fri Sep 25 23:09:47 2026 Received: from mxd.seznam.cz (mxd.seznam.cz [77.75.76.210]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 930F44AA003; Mon, 7 Sep 2026 13:52:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=77.75.76.210 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788789143; cv=none; b=ENSFUo98+KrthH4ARwmDsOCco634wtuabDWtfidY8YgMMfiPcQFNXSItltrcC+kMsp8tH45V/ORkULEQzpKK4Yc/XwOLVkvMBvfRL2W0PMbJ2m6hxuw0KbVnojHVdduRA1EKGVdd+TCr2BRn2d8Qgl3W/Oze/sWYUucrQzHnpL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788789143; c=relaxed/simple; bh=n5mHZO2dtuZjdZ9S9QtPa1SGWE5JjpGaKWTuV8yEV6s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kObZgV70H8oc33gRLx72D3/UgQeM97QvtaDZoomxrx1TdgYcSnXJ6lmZq02aCxSj1kAiNizK2ANRlkpf+gWQOBnefH4JEkV3C2dAS6En79/7iIm0q2EzV2fvikxe5g+O2iOwAodkEzXXOR5F1jiUS89f/pB2Vcg9ic2XuSdbeUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=email.cz; spf=pass smtp.mailfrom=email.cz; dkim=pass (2048-bit key) header.d=email.cz header.i=@email.cz header.b=GLpYcuvX; arc=none smtp.client-ip=77.75.76.210 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=email.cz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=email.cz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=email.cz header.i=@email.cz header.b="GLpYcuvX" Received: from email.seznam.cz by smtpc-mxd-8df7dc6f5-w2xkj (smtpc-mxd-8df7dc6f5-w2xkj [2a02:598:128:8a00::1000:a0a]) id 40e0e4c1c0078e5c4294daaf; Mon, 07 Sep 2026 15:52:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=email.cz; s=szn1; t=1788789136; bh=bhyTkY15bsw02prmRZjnmef4XjP33gI3tw1ZFD52sDU=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version: Content-Transfer-Encoding; b=GLpYcuvX8CwDeRo0LpSsYh9YZ8lGeYZ/iaEhAEX1iUJGqXcEtwOd3mYpkigQeIpBI Sx6mSayRpD7d8IS0eYahizMMNvSJC/ZPDKsf7GDqIF30NzhHz9wTC6/iarVKz5yLxp e/jrjpzZWE3gF0v7ubkVUYUqedHVLGCUqGpRlfMYHZxGk84bvMCXx3hG5BWFJqs32s ne9hoeMGJWFvjpkuqTEb3J2VOL1agmu0n8oVbxP6l4hHDGpXgEb5RFciV7EgxJNSbr 12tM+TtZdM3zzGxPCl3hoTzMy8fBsYbBAkKyr+PgzFnza7IhfEQXDBVJLRh0ctcOtu ExoDSmQYdLsKQ== Received: from arch-zen ([2a02:8308:b086:3c00:3636:4bcf:b8c2:e5cf]) by smtpd-relay-6ffbffc97b-l7tfj (szn-email-smtpd/2.0.82) with ESMTPA id b95f2925-7f48-4fac-8166-846b8cb56ea2; Mon, 07 Sep 2026 15:49:46 +0200 From: "Jan Havran (Advantech Czech)" To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "David S. Miller" Cc: Daniel Golle , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, "Jan Havran (Advantech Czech)" Subject: [PATCH net 1/3] net: dsa: mxl-gsw1xx: set SerDes NCO rate before SGMII reset Date: Mon, 7 Sep 2026 15:48:16 +0200 Message-ID: <20260907134818.16670-2-havran.jan@email.cz> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907134818.16670-1-havran.jan@email.cz> References: <20260907134818.16670-1-havran.jan@email.cz> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" gsw1xx_pcs_config() releases the SGMII shell from reset via gsw1xx_pcs_reset() and only afterwards programs NCO_CTRL to select the SerDes clock rate (1G NCO1 vs 2.5G NCO2). The chip boot loader uses the other order: NCO_CTRL -> RST_REQ -> SGMII_PHY_HWBU_CTRL (GSW145 data sheet, section 3.2.8, table 13). Program NCO_CTRL before gsw1xx_pcs_reset() to follow that order. On an Armada 7040 board driving a GSW145 whose switch comes up at 2.5G (pin strap PS_SUBTYPE_MD[2] =3D 1, pin LED42 / PS1 bit 14; GSW145 data sheet tables 23 and 25), a 1 Gbps SGMII link only carried traffic with this change. It matters when the rate the switch is left at - by the straps or by the boot loader - differs from the rate the driver selects, which is likely why it has not been seen before. Fixes: 22335939ec90 ("net: dsa: add driver for MaxLinear GSW1xx switch fami= ly") Signed-off-by: Jan Havran (Advantech Czech) Reviewed-by: Daniel Golle Reviewed-by: Maxime Chevallier --- drivers/net/dsa/lantiq/mxl-gsw1xx.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index a1104b2f92a92..b8d8fefaa3a15 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -352,8 +352,22 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, = unsigned int neg_mode, /* mark PCS configuration as incomplete */ priv->tbi_interface =3D PHY_INTERFACE_MODE_NA; =20 - if (!reconf) + if (!reconf) { + /* setup SerDes clock speed */ + if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) + nco_ctrl =3D GSW1XX_SGMII_2G5 | GSW1XX_SGMII_2G5_NCO2; + else + nco_ctrl =3D GSW1XX_SGMII_1G | GSW1XX_SGMII_1G_NCO1; + + ret =3D regmap_update_bits(priv->clk, GSW1XX_CLK_NCO_CTRL, + GSW1XX_SGMII_HSP_MASK | + GSW1XX_SGMII_SEL, + nco_ctrl); + if (ret) + return ret; + ret =3D gsw1xx_pcs_reset(priv, interface); + } =20 if (ret) return ret; @@ -423,19 +437,6 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, = unsigned int neg_mode, return ret; =20 if (!reconf) { - /* setup SerDes clock speed */ - if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) - nco_ctrl =3D GSW1XX_SGMII_2G5 | GSW1XX_SGMII_2G5_NCO2; - else - nco_ctrl =3D GSW1XX_SGMII_1G | GSW1XX_SGMII_1G_NCO1; - - ret =3D regmap_update_bits(priv->clk, GSW1XX_CLK_NCO_CTRL, - GSW1XX_SGMII_HSP_MASK | - GSW1XX_SGMII_SEL, - nco_ctrl); - if (ret) - return ret; - ret =3D gsw1xx_pcs_phy_xaui_write(priv, 0x30, 0x80); if (ret) return ret; --=20 2.39.5 From nobody Fri Sep 25 23:09:47 2026 Received: from mxd.seznam.cz (mxd.seznam.cz [77.75.76.210]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 753E04EE87D; Mon, 7 Sep 2026 13:52:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=77.75.76.210 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788789147; cv=none; b=NjloIxDs51vjCZTKjZQ6hhc1hyV6zeXR6a0pzYUYiwfJKnzsunLN11kqcsV+SjI1JIfiCP+XLYCl8cqKpI8no8+sdeZB3X8t8cjcAnR+m67MxOLorHTLrZMUH7g4GV7uJb37g9SsVNAW/etsLfdj9s4oWbTVgnOZyMylrQ3a6LQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788789147; c=relaxed/simple; bh=VmmIwWAZs2XrvDioz2ricI1w5TvCiE3nFAqpoSKdN1Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZqJ2vf+xhe5XCJJ6UYTCOfrCLkBLtJF1kdrGdnNGXHguMwYf7KVOYZXJmYLYH/e/5PJxEMgUQkdUJixBKT1GJJc/RRPWl0K4WxUqhoicy4BK/UUqRFhp/nshKGLb1FfLttLVEu4rh0o1blBfgySxu7zZP6ViVWhmj+DaZ0rtxDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=email.cz; spf=pass smtp.mailfrom=email.cz; dkim=pass (2048-bit key) header.d=email.cz header.i=@email.cz header.b=jEcXE4eT; arc=none smtp.client-ip=77.75.76.210 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=email.cz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=email.cz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=email.cz header.i=@email.cz header.b="jEcXE4eT" Received: from email.seznam.cz by smtpc-mxd-8df7dc6f5-mtdcb (smtpc-mxd-8df7dc6f5-mtdcb [2a02:598:96:8a00::1200:70a]) id 4ea4a271ce43c8ec4cd09c1f; Mon, 07 Sep 2026 15:52:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=email.cz; s=szn1; t=1788789138; bh=hO6PQptaqnXduKDymaVKrGlalUDM+bzewjF/ziNZ60A=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version: Content-Transfer-Encoding; b=jEcXE4eThq0ndabPp4k2YJEUkrGEZStXPH8V1wnjFkEN/ijRr04HX/ZYkRcKcQv30 u9sZWVVvC1bGeVSC/9drQ2aY4lYjXmS5435R6UZ9rYf9wTERDRxgNGFSWLFm3pfGT4 mxM/kNA1ELgrCEHvEFijkL6W8Rwx4b/VavSvuCb6sbu2nqnbz/i4SPUCM4mnF8mkLr J8oDJ/8rZ970aShRFe1nAdQC8/4T1MFpqfIUWOKHJAcINMh7UhHMt9MPCNAlqjnWQT NWYVX+ECI7SngqA97FvEc4gEYrG4FTQjKhAnl4xeLmY4DZ2ehoiuQHNyt62KGfUpA+ Jjlexg+JujlWw== Received: from arch-zen ([2a02:8308:b086:3c00:3636:4bcf:b8c2:e5cf]) by smtpd-relay-6ffbffc97b-l7tfj (szn-email-smtpd/2.0.82) with ESMTPA id 7ac88cff-13b6-4dc0-ac43-2373edc9c4d7; Mon, 07 Sep 2026 15:49:47 +0200 From: "Jan Havran (Advantech Czech)" To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "David S. Miller" Cc: Daniel Golle , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, "Jan Havran (Advantech Czech)" Subject: [PATCH net 2/3] net: dsa: lantiq_gswip: handle SPEED_2500 in gswip_port_set_speed() Date: Mon, 7 Sep 2026 15:48:17 +0200 Message-ID: <20260907134818.16670-3-havran.jan@email.cz> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907134818.16670-1-havran.jan@email.cz> References: <20260907134818.16670-1-havran.jan@email.cz> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mxl-gsw1xx driver advertises 2500BASE-X on its SGMII port (via supports_2500m and gsw1xx_phylink_get_caps()), but the shared gswip_port_set_speed() has no SPEED_2500 case: at 2.5G every field keeps its initializer, so mdio_phy =3D 0 pins the MDIO speed override to 10 Mbps and no data passes. At the MAC/MDIO level 2500BASE-X is identical to 1 Gbps (same wide GMII datapath, same speed override); the rate itself is set in the PCS and SerDes, not here. This matches the boot loader's PHY_ADDR_4 =3D 0x32A4 for the 2.5G strap ("1 Gbps or above"), whose SPEED field is GSWIP_MDIO_PHY_SPEED_G1 (the field has no encoding above G1). Share the SPEED_1000 arm via a stacked case label. Its mii_cfg value is a no-op for 2.5G: gswip_mii_mask_cfg() writes it only for the RGMII port (mii_cfg[SGMII port] =3D=3D -1), which cannot reach 2.5G anyway. Fixes: 22335939ec90 ("net: dsa: add driver for MaxLinear GSW1xx switch fami= ly") Signed-off-by: Jan Havran (Advantech Czech) Reviewed-by: Daniel Golle Reviewed-by: Maxime Chevallier --- drivers/net/dsa/lantiq/lantiq_gswip_common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip_common.c b/drivers/net/dsa= /lantiq/lantiq_gswip_common.c index 0e8eedf64d3a3..6150dc3ffb641 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip_common.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip_common.c @@ -1339,6 +1339,7 @@ static void gswip_port_set_speed(struct gswip_priv *p= riv, int port, int speed, break; =20 case SPEED_1000: + case SPEED_2500: mdio_phy =3D GSWIP_MDIO_PHY_SPEED_G1; =20 mii_cfg =3D GSWIP_MII_CFG_RATE_M125; --=20 2.39.5 From nobody Fri Sep 25 23:09:47 2026 Received: from mxd.seznam.cz (mxd.seznam.cz [77.75.76.210]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B33DD4D98EF; Mon, 7 Sep 2026 13:53:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=77.75.76.210 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788789203; cv=none; b=huBmbvij4LAFDURZXZdJd4GSXhNdR9pjIqYwXvTggkBiU/8rz6Q4LOa1xA2NxYU9j/nVHQdo9VdpXB/KuUL0zuGlgqMnWIXUHwrGs4V4rhaq0+towFtenweJlvscfJwEbuYXXNg+HIQNSODOal9i8jHn8YW2aqr8vvhxmZD8nYo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788789203; c=relaxed/simple; bh=6XAhUDHRh00qK7xNcGVH+kIrArDv7jC8q4bwjpDHnTw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R5yW1OsRYaBkxx8Xf+eJAnimtnXMECTARGx1bBjIXRSeh/v3JWnSyopKQ0MRDceL86P7RMta/9CpfmPZ/VIlj8nlx4yqPInlgWKspX4teZl083mDK1vAMT9whQMs/STth1fvjzjdzLdF6DIOk8ANhBIYJ1eaBtdun9XqwqEIfvM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=email.cz; spf=pass smtp.mailfrom=email.cz; dkim=pass (2048-bit key) header.d=email.cz header.i=@email.cz header.b=Jjjef6aG; arc=none smtp.client-ip=77.75.76.210 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=email.cz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=email.cz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=email.cz header.i=@email.cz header.b="Jjjef6aG" Received: from email.seznam.cz by smtpc-mxd-8df7dc6f5-mtdcb (smtpc-mxd-8df7dc6f5-mtdcb [2a02:598:96:8a00::1200:70a]) id 595cf1d7d9bb9b4a5b28cfb9; Mon, 07 Sep 2026 15:53:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=email.cz; s=szn1; t=1788789195; bh=KbfbAnfKkMJRLguqz6jlFQXIkEF6dh+uEy2whayqEFE=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version: Content-Transfer-Encoding; b=Jjjef6aGwdkmy9hf/5QW9noXODNIHXbsPKzNrjwNKBU14ws1IdI6XR5/BB0Y9WePF LFkaWQvzZ+oE1M66ziVE/OQ6TvxEMLWLhPl/M5SQewGJsjFcyM1BnPNjEr0Iyhj8id HwkKx60Wkj7ChqKKQaWayEj2FV6vB2xAF0AVySg7MMVQliYKyMUvFUNk3FllcUqdLP LTt2hTjdwsKRLrTr15BfqULV0imWfGmXDQ/PiFQ1fIUQ9wVnleMPWb5hOrnemDgjLQ K1h7pbK68zkoloc/fU7kgMEAlfLm1Gmr23wfWhndpFF9Q3SJxbzfGI4k0AoETjaqGn phpIZCUAuiYaw== Received: from arch-zen ([2a02:8308:b086:3c00:3636:4bcf:b8c2:e5cf]) by smtpd-relay-6ffbffc97b-l7tfj (szn-email-smtpd/2.0.82) with ESMTPA id 1c7a8d14-1b8b-4ec9-aa20-1ee60de1e924; Mon, 07 Sep 2026 15:49:49 +0200 From: "Jan Havran (Advantech Czech)" To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "David S. Miller" Cc: Daniel Golle , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, "Jan Havran (Advantech Czech)" Subject: [PATCH net 3/3] net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value Date: Mon, 7 Sep 2026 15:48:18 +0200 Message-ID: <20260907134818.16670-4-havran.jan@email.cz> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907134818.16670-1-havran.jan@email.cz> References: <20260907134818.16670-1-havran.jan@email.cz> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Per the GSW145 data sheet, the FCONTX (bits 8:7) and FCONRX (bits 6:5) flow-control fields of the PHY_ADDR_n register both encode 00 =3D AUTO, 01 =3D EN, 10 =3D reserved, 11 =3D DIS. GSWIP_MDIO_PHY_FCONTX_EN was 0x0100, i.e. field value 10 (the reserved encoding), instead of 0x0080 (01 =3D EN); FCONRX_EN is already 0x0020 (01). Enabling tx flow control therefore wrote the reserved value. Set FCONTX_EN to 0x0080. The register is shared by all supported parts. Fixes: 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Signed-off-by: Jan Havran (Advantech Czech) Reviewed-by: Daniel Golle Reviewed-by: Maxime Chevallier --- drivers/net/dsa/lantiq/lantiq_gswip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq= /lantiq_gswip.h index bc3686faad0d6..0b75be14dc109 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h @@ -42,7 +42,7 @@ #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 -#define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 +#define GSWIP_MDIO_PHY_FCONTX_EN 0x0080 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 --=20 2.39.5