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[94.253.164.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2622a7c677sm366362766b.9.2026.09.07.06.26.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 06:26:30 -0700 (PDT) From: Robert Marko To: ulfh@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, adrian.hunter@intel.com, aubin.constans@microchip.com, ehristev@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko , Conor Dooley Subject: [PATCH v2 1/6] dt-bindings: mmc: atmel,sama5d2-sdhci: add LAN969x compatible Date: Mon, 7 Sep 2026 15:25:29 +0200 Message-ID: <20260907132617.1198548-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907132617.1198548-1-robert.marko@sartura.hr> References: <20260907132617.1198548-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SDHCI controller in the LAN969x family uses the same register layout as the SAM9X60 implementation. Add the microchip,lan9691-sdhci compatible with microchip,sam9x60-sdhci as its fallback. Signed-off-by: Robert Marko Acked-by: Conor Dooley --- Changes in v2: * Clarify the relationship between the LAN969x and SAM9X60 controllers. * Add Conor Dooley's Acked-by. Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml= b/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml index ba75623b7778..af1c66a1f882 100644 --- a/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml @@ -21,6 +21,7 @@ properties: - microchip,sam9x60-sdhci - items: - enum: + - microchip,lan9691-sdhci - microchip,sam9x7-sdhci - microchip,sama7d65-sdhci - microchip,sama7g5-sdhci --=20 2.55.0 From nobody Fri Sep 25 23:10:23 2026 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 294A44E80D1 for ; Mon, 7 Sep 2026 13:26:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; 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[94.253.164.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2622a7c677sm366362766b.9.2026.09.07.06.26.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 06:26:31 -0700 (PDT) From: Robert Marko To: ulfh@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, adrian.hunter@intel.com, aubin.constans@microchip.com, ehristev@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v2 2/6] mmc: sdhci-of-at91: add option to keep clocks enabled Date: Mon, 7 Sep 2026 15:25:30 +0200 Message-ID: <20260907132617.1198548-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907132617.1198548-1-robert.marko@sartura.hr> References: <20260907132617.1198548-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" sdhci_at91_set_clks_presets() both enables the controller clocks and programs its capabilities and preset registers. This prevents callers from restoring the registers without changing the clock enable counts. Move clock enablement to callers and add a SoC data flag for controllers that must keep their clocks enabled. Use it in the runtime PM paths while keeping register restoration separate from clock enablement. Signed-off-by: Robert Marko drivers/mmc/host/sdhci-of-at91.c | 39 +++++++++++++++++++------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-a= t91.c index 7c4ac65f247d..b7e2a89da348 100644 --- a/drivers/mmc/host/sdhci-of-at91.c +++ b/drivers/mmc/host/sdhci-of-at91.c @@ -38,6 +38,7 @@ struct sdhci_at91_soc_data { const struct sdhci_pltfm_data *pdata; bool baseclk_is_generated_internally; + bool keep_clks_on; unsigned int divider_for_baseclk; }; =20 @@ -164,7 +165,7 @@ static const struct of_device_id sdhci_at91_dt_match[] = =3D { }; MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); =20 -static int sdhci_at91_set_clks_presets(struct device *dev) +static void sdhci_at91_set_clks_presets(struct device *dev) { struct sdhci_host *host =3D dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -174,7 +175,6 @@ static int sdhci_at91_set_clks_presets(struct device *d= ev) unsigned int gck_rate, clk_base_rate; unsigned int preset_div; =20 - clk_prepare_enable(priv->hclock); caps0 =3D readl(host->ioaddr + SDHCI_CAPABILITIES); caps1 =3D readl(host->ioaddr + SDHCI_CAPABILITIES_1); =20 @@ -222,11 +222,6 @@ static int sdhci_at91_set_clks_presets(struct device *= dev) preset_div =3D DIV_ROUND_UP(gck_rate, 50000000) - 1; writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, host->ioaddr + SDHCI_PRESET_FOR_DDR50); - - clk_prepare_enable(priv->mainck); - clk_prepare_enable(priv->gck); - - return 0; } =20 static int sdhci_at91_suspend(struct device *dev) @@ -254,9 +249,11 @@ static int sdhci_at91_runtime_suspend(struct device *d= ev) if (host->tuning_mode !=3D SDHCI_TUNING_MODE_3) mmc_retune_needed(host->mmc); =20 - clk_disable_unprepare(priv->gck); - clk_disable_unprepare(priv->hclock); - clk_disable_unprepare(priv->mainck); + if (!priv->soc_data->keep_clks_on) { + clk_disable_unprepare(priv->gck); + clk_disable_unprepare(priv->hclock); + clk_disable_unprepare(priv->mainck); + } =20 return 0; } @@ -269,14 +266,23 @@ static int sdhci_at91_runtime_resume(struct device *d= ev) int ret; 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[94.253.164.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2622a7c677sm366362766b.9.2026.09.07.06.26.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 06:26:33 -0700 (PDT) From: Robert Marko To: ulfh@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, adrian.hunter@intel.com, aubin.constans@microchip.com, ehristev@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v2 3/6] mmc: sdhci-of-at91: add LAN969x support Date: Mon, 7 Sep 2026 15:25:31 +0200 Message-ID: <20260907132617.1198548-4-robert.marko@sartura.hr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907132617.1198548-1-robert.marko@sartura.hr> References: <20260907132617.1198548-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LAN969x uses the same internally generated base clock layout as SAM9X60, but its SDMMC controller stops responding when runtime PM gates its clocks. Software resets then fail to complete and the internal SDHCI clock never stabilises, causing subsequent I/O requests to time out. Add LAN969x-specific SoC data using the SAM9X60 clock layout and select the option to leave its clocks enabled across runtime suspend. Signed-off-by: Robert Marko drivers/mmc/host/sdhci-of-at91.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-a= t91.c index b7e2a89da348..e7affca8da25 100644 --- a/drivers/mmc/host/sdhci-of-at91.c +++ b/drivers/mmc/host/sdhci-of-at91.c @@ -158,9 +158,17 @@ static const struct sdhci_at91_soc_data soc_data_sam9x= 60 =3D { .divider_for_baseclk =3D 2, }; =20 +static const struct sdhci_at91_soc_data soc_data_lan969x =3D { + .pdata =3D &sdhci_sama5d2_pdata, + .baseclk_is_generated_internally =3D true, + .keep_clks_on =3D true, + .divider_for_baseclk =3D 2, +}; + static const struct of_device_id sdhci_at91_dt_match[] =3D { { .compatible =3D "atmel,sama5d2-sdhci", .data =3D &soc_data_sama5d2 }, { .compatible =3D "microchip,sam9x60-sdhci", .data =3D &soc_data_sam9x60 = }, + { .compatible =3D "microchip,lan9691-sdhci", .data =3D &soc_data_lan969x = }, {} }; MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); --=20 2.55.0 From nobody Fri Sep 25 23:10:23 2026 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA7684EBADC for ; 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[94.253.164.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2622a7c677sm366362766b.9.2026.09.07.06.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 06:26:35 -0700 (PDT) From: Robert Marko To: ulfh@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, adrian.hunter@intel.com, aubin.constans@microchip.com, ehristev@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v2 4/6] arm64: dts: microchip: lan969x: add SDMMC nodes Date: Mon, 7 Sep 2026 15:25:32 +0200 Message-ID: <20260907132617.1198548-5-robert.marko@sartura.hr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907132617.1198548-1-robert.marko@sartura.hr> References: <20260907132617.1198548-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for both SDMMC controllers. Connect their bus interface clock to the fabric clock and their core clock to the corresponding generated clock. Configure SDMMC0 with a 100 MHz generated clock for 50 MHz eMMC DDR operation. Configure SDMMC1 with an exact 50 MHz generated clock so the integer base clock encoded in the SDHCI capabilities remains accurate and the identification clock does not exceed 400 kHz. Keep both nodes ordered by unit address. Signed-off-by: Robert Marko Reviewed-by: Aubin Constans Reviewed-by: Claudiu Beznea --- Changes in v2: * Use the fabric clock for the SDMMC bus interface clock. * Configure SDMMC1 with an exact 50 MHz generated clock. * Move the SDMMC1 node to preserve unit-address ordering. * Explain the selected clock rates in the commit description. arch/arm64/boot/dts/microchip/lan9691.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/lan9691.dtsi b/arch/arm64/boot/d= ts/microchip/lan9691.dtsi index a8541c6a098d..5e330d5fab50 100644 --- a/arch/arm64/boot/dts/microchip/lan9691.dtsi +++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi @@ -414,6 +414,18 @@ qspi0: spi@e0804000 { status =3D "disabled"; }; =20 + sdmmc0: mmc@e0830000 { + compatible =3D "microchip,lan9691-sdhci", + "microchip,sam9x60-sdhci"; + reg =3D <0xe0830000 0x00000300>; + interrupts =3D ; + clocks =3D <&fabric_clk>, <&clks GCK_ID_SDMMC0>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&clks GCK_ID_SDMMC0>; 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[94.253.164.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2622a7c677sm366362766b.9.2026.09.07.06.26.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 06:26:36 -0700 (PDT) From: Robert Marko To: ulfh@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, adrian.hunter@intel.com, aubin.constans@microchip.com, ehristev@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v2 5/6] arm64: dts: microchip: ev23x71a: enable QSPI Date: Mon, 7 Sep 2026 15:25:33 +0200 Message-ID: <20260907132617.1198548-6-robert.marko@sartura.hr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907132617.1198548-1-robert.marko@sartura.hr> References: <20260907132617.1198548-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the QSPI controller and describe the onboard SPI NOR flash. Signed-off-by: Robert Marko .../arm64/boot/dts/microchip/lan9696-ev23x71a.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts b/arch/arm6= 4/boot/dts/microchip/lan9696-ev23x71a.dts index 4012ea7d07bb..985ca31e74e7 100644 --- a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts +++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts @@ -463,6 +463,21 @@ phy27: phy@27 { }; }; =20 +&qspi0 { + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <100000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + spi-tx-bus-width =3D <1>; + spi-rx-bus-width =3D <4>; + m25p,fast-read; + }; +}; + &serdes { status =3D "okay"; }; --=20 2.55.0 From nobody Fri Sep 25 23:10:23 2026 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F5F7472F67 for ; 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[94.253.164.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2622a7c677sm366362766b.9.2026.09.07.06.26.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 06:26:38 -0700 (PDT) From: Robert Marko To: ulfh@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, adrian.hunter@intel.com, aubin.constans@microchip.com, ehristev@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v2 6/6] arm64: dts: microchip: ev23x71a: enable eMMC Date: Mon, 7 Sep 2026 15:25:34 +0200 Message-ID: <20260907132617.1198548-7-robert.marko@sartura.hr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907132617.1198548-1-robert.marko@sartura.hr> References: <20260907132617.1198548-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the non-removable eMMC connected to SDMMC0. Configure its 8-bit bus for 1.8 V DDR operation. Signed-off-by: Robert Marko Reviewed-by: Aubin Constans Reviewed-by: Claudiu Beznea --- Changes in v2: * Remove the unnecessary maximum-frequency property. * Expand the commit description. arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts b/arch/arm6= 4/boot/dts/microchip/lan9696-ev23x71a.dts index 985ca31e74e7..89a161b87d6f 100644 --- a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts +++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts @@ -478,6 +478,16 @@ flash@0 { }; }; =20 +&sdmmc0 { + pinctrl-0 =3D <&emmc_sd_pins>; + pinctrl-names =3D "default"; + bus-width =3D <8>; + mmc-ddr-1_8v; + non-removable; + disable-wp; + status =3D "okay"; +}; + &serdes { status =3D "okay"; }; --=20 2.55.0