From nobody Fri Sep 25 23:54:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 507EC4503EA; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; cv=none; b=lPMrPe7z5BNm6FFWIvFGc+MZk/sJrNZFqE/usDI2LZgWwg1XE+99vw+z2KmXMivCwD6Z679k9Pr1E6oZOlxjys9EJkv9sqMMlcNvZkH0yRqf+5FpjoKjILia93ti1GcRfKTyu+NAtUiMPqjMmTFKJccodhW5Pr9jTII/1YE1Tuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; c=relaxed/simple; bh=jx8p4XoDCEmHkARz3LvR8mZjbN2RulpuK3cx8pTILlM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e6dA37+OIsTbKX2u79aqLbEJk5Y6PLZdAdD1d29EaL5TGiUwQtGVky4OcKgJk+DRx7+wGMI7Py/gM6OrdvM9sQ7ySh2wfnVwaWXv42+5VgJhWuC3VLuGj3JqAek+FMUOZst2W+TjOvw0P3JPQ3QgBFIBJh4DhGEePieWRmbzJa4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CUO6ibPB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CUO6ibPB" Received: by smtp.kernel.org (Postfix) with ESMTPS id DF860C2BCFA; Mon, 7 Sep 2026 09:58:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788775106; bh=jx8p4XoDCEmHkARz3LvR8mZjbN2RulpuK3cx8pTILlM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CUO6ibPBnRIJ6br9N1+tglZAtiCQb54P+xFBHtVbEeHzlX7CCIYEohoJJxP2aCOVF rhWyA78DUPUPbC3nqZv25YVRlFygwkTF5HKV9hJ46PPgTlYc+wX3jRITtn2jRUTokB 1jhxo/x3/bzHyxynHeE7NA8eVcKOlxGcyFxKjs5FxfIGtDybOkxLB+8UudHOr/P1fB kyUXoE5DfLyeAj5lNm6CyvJorHlvlCSZCEJN1JDlJ/iRsWMEsHA8Jseny5+0tIvPLv 9jtDXPQlC7drisbr1plgBltwYk02ojwsytr/REnf07GLVb3xoxh4ObJiqqag8Cnap1 LqrQlM99gmGKw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BECEDC79F89; Mon, 7 Sep 2026 09:58:25 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 07 Sep 2026 17:54:40 +0800 Subject: [PATCH v2 01/10] dt-bindings: vendor-prefixes: Add shenrongda Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-ultrarisc-dts-v2-1-5eb4c97477c5@ultrarisc.com> References: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> In-Reply-To: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jia Wang , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org, Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788775103; l=887; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=e/Kow+cCHmWBpSOP+t1oxwgy4BH4snNIyYRmuufij+E=; b=CR9ZckKOmzRgkynMxxjsH9rH+5MRkkuyyO5RWGoWCZBgJ9+mRHevzyy21zSGICPYhWEoToO9w 2Kmphmkzo25Bfj0HIxEXWJH+ogZkWr5HtF7yOJTdXD+dM6ShhURhDZS X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add Shenzhen Rongda Computer Co., Ltd. to the vendor prefixes. Link: http://www.shenrongda.com/ Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index ba2002969373..e100f3993e57 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1507,6 +1507,8 @@ patternProperties: description: SGX Sensortech "^sharp,.*": description: Sharp Corporation + "^shenrongda,.*": + description: Shenzhen Rongda Computer Co., Ltd. "^shift,.*": description: SHIFT GmbH "^shimafuji,.*": --=20 2.34.1 From nobody Fri Sep 25 23:54:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6631C450409; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; cv=none; b=c8Jg30jOQIPXqwdNBrIFucDHsAlZmZz2cZLD2WG9pVdlO3QsJQWfNXz0teDRv6ZZtd4aWWTGPZFnCbaU0fhJ0tRyJvYoRJcgitbTi4swZ/pBGOpoeGHVz6LMMr9Wm4XKuRtRI2R93iSCPrwrRG3EWDtIHPhxxfM1FGUOq2SjyhE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; c=relaxed/simple; bh=UH/9tXjtdEDMWx49kupssMJS31sfLv7FO0+FnXYwDuo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QNQCl/pwsa2qvbheu/Cky5XIavLu+2AvyT5WMPMrHnl/+7xh+1PgvlnQMN2rd0eHqPqrfdYUjmNSMlfZ7lajtImF/AkakXVVvbmlxeLqUtD4SLOt55OFBVhU9SztqaYKuOmbmvqpD90q5HVmFBrUYj5vyMr9oZ6byDnGp5v81Jk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lOImjtQZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lOImjtQZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id F1836C2BCFD; Mon, 7 Sep 2026 09:58:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788775106; bh=UH/9tXjtdEDMWx49kupssMJS31sfLv7FO0+FnXYwDuo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lOImjtQZiTPNgO4Q4752FBzubu4AgFranaYsBLYxqgQ/B8Mq28asI1WZxZ3Gms1fb Vnh9kTHcIRY99yjryZomLF9Jin+IsU1yCfpiybxqCb7idbAGx0ZXgmwp5CCYRJUWCj /FzWKbdCRWiYK2YGCbsCYfV892Tlu6CYIoY5niTUJ3ZZoHhyma7HTO7m+Ftnfb9irb xMlh1PjHf3ObD7nDJHrfoEzN9gLdIJErMB1A4HRatunp5RyQqj5foCUVshXnnNAr2H 5r08lNQRC79zt//jjiKdK3erv/vA06Qh/gT35a4sjsHxgDoVJTyqfwikH8Z+9uBJKi 5gdpWOMNAN57g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D256FC79F9F; Mon, 7 Sep 2026 09:58:25 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 07 Sep 2026 17:54:41 +0800 Subject: [PATCH v2 02/10] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-ultrarisc-dts-v2-2-5eb4c97477c5@ultrarisc.com> References: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> In-Reply-To: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jia Wang , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org, Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788775103; l=804; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=4TAyfkBcv/s6Kdb5vlK3fVOCoBkGrwHfHTtS6V/To4w=; b=04IAVKJmYQ28f7nAGz0dHm9GO1Vgegc5GElVxIZXoj7fRUuKnABRoMqHm7KL3iCfc2B9IICMH gryMZxqSeskCmFYBsg07DsCpnu0Sg1xVQaOwwDeG2iF1Nf/RU9+lFN0 X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Document the UltraRISC CP100 CPU compatible. The CP100 CPU is used in the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 0da219ae6769..85adf72899c9 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -67,6 +67,7 @@ properties: - thead,c908 - thead,c910 - thead,c920 + - ultrarisc,cp100 - const: riscv - items: - enum: --=20 2.34.1 From nobody Fri Sep 25 23:54:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A1D145041C; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; cv=none; b=iuhe/U/yYtnv2I9UThYyTkDWtKRtrEkK9VeM7CjXPnOvWHDkVyltCJoGFOL7JN3qJabbrb/Mwh57q/1TL2vfa0Fun1KNmWTGJzQGFxwIOyEBk1iAB5vGyi2OaLgWdvf8BcHv8umnYCDpUeooeGyW9jRzNuvJ/dJg06otV6cQkUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; c=relaxed/simple; bh=3o63M8GLJhdOwUiejYCoJC1fYY15kJrll06waHGvMoA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j/sltv1qZ4LXjVWzuYybnSL/9lyJ3XX4et5R+M0ArqN/HMDfYcuUH+yAdzZk166XZkhVOsdg7ISqHyDcNLabFXBhGsLbDR6pOWNzS73RTdRA52aY5yZq1Z7FQ1WNZscs2lTt4LTVgmPU/7yXwmcra40LNcpDcSgCoy8UG2s+Qi8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JJVKbroy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JJVKbroy" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0B6D8C2BD04; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788775106; bh=3o63M8GLJhdOwUiejYCoJC1fYY15kJrll06waHGvMoA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JJVKbroyJjOnt1IxC+JFMuVfAvlA1hgUfpIyZxt9d2W61g0nnKPHWPp2lMqVIWGw1 kj9bVSa+NS0rb9s5hfDmdRXDctzkvqJor6CF0+DsXwWFEw5kErB6SlPzdNhXKhVUwt hY+sk0X9126nh7pewxRzRl1iUdBaVa9A+SXhWeeA/YlQrL7erIzj41Ggiap4uU3cTP DR0nPlZfT80oJdIy0sz3zngUHrVO1d6BPc2ZK0S+tHkcrV5VSX+x+h2VkN4zk/Vbp9 fGMoOlgPHDPQ++qB5txQM+byb387ToTEenwndtzGwvRYaAlAbMr+Cw5jXwh41CTutJ TUVUvHmvncTiQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5F11C79FA0; Mon, 7 Sep 2026 09:58:25 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 07 Sep 2026 17:54:42 +0800 Subject: [PATCH v2 03/10] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-ultrarisc-dts-v2-3-5eb4c97477c5@ultrarisc.com> References: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> In-Reply-To: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jia Wang , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org, Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788775103; l=1942; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=0AlvsDRQTM/16/SNeo0QtnySbLZ7dH8R2EB+6wrTmkU=; b=N34b9VnVbzUmghkdWvy/qCTaeByHAlvv+aKJzBty5aEVhPdhZHAX5Jsim7dSq1dpTRqgGaRAY 5RalDm+jtoyB32OoRT8Qk06kDC9B/DrovyokPhYAFujVIpqQG6Z8S82 X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Document the compatibles for the Shenzhen Rongda M0 and Milk-V Titan boards, both based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/ultrarisc.yaml | 27 ++++++++++++++++++= ++++ MAINTAINERS | 7 ++++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Docum= entation/devicetree/bindings/riscv/ultrarisc.yaml new file mode 100644 index 000000000000..a51e63dbeca3 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC SoC-based boards + +maintainers: + - Jia Wang + +description: + UltraRISC DP1000 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - shenrongda,m0 + - milkv,titan + - const: ultrarisc,dp1000 + +additionalProperties: true +... diff --git a/MAINTAINERS b/MAINTAINERS index d6fb876227e9..eb7a9caaa225 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23637,6 +23637,13 @@ F: include/dt-bindings/power/thead,th1520-power.h F: include/dt-bindings/reset/thead,th1520-reset.h F: include/linux/firmware/thead/thead,th1520-aon.h =20 +RISC-V ULTRARISC SoC SUPPORT +M: Jia Wang +L: linux-riscv@lists.infradead.org +S: Supported +T: git https://github.com/ultrarisc/linux.git +F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang --=20 2.34.1 From nobody Fri Sep 25 23:54:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83B4F455176; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; cv=none; b=GC2XLcvKM+KIAaah38+JQUBnmjiNOdO8VdGUuojDP45lImmWM1q/Mlrp+VCQmKLRQVe390e29e5qTajp5Yyw8i7O6AI2gQDU/mLB+9zhe0DNYbPLtc2ny3a4aMqITewu0jnj5H6eevHQjuc5A+sO1uFTVlbbRP9237VUplgjgUU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; c=relaxed/simple; bh=osJ1peGPbLMwCs9cQfspS5sCiI02TKIU/UTXsG1stLI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GmlQ8JQY964Jz0oyOBfwtRi/Hdf3iJiFcuvne4lJV43JBVqU8CyV2D6GpmkL74IRM6Zl82EwPR43MEFsQThI1ttbJzU9Dp95CvwNVWj0guF87y7GWFs3ObhZHQcSiAYxnBddqf4aQ/djDWbQQIE8CUwxLfGNVXY3rP/OiV19Hgk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IBv5EzfR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IBv5EzfR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1B371C2BD05; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788775106; bh=osJ1peGPbLMwCs9cQfspS5sCiI02TKIU/UTXsG1stLI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=IBv5EzfRtJ2tPJE+q6J/2aqN18z3MvgJJonLv09RekmAYzXwLVsMrQ44QWKwWfyE7 fJNmBFwGG9fdasbThw0Bwlj+Y7Hl0uY9M047IGR5mozh02SqyqFwz+4o44s09ljgdq U3PUszsV6ltO65Z4Pt/N2fmp9FsBBjMGaeIYvvRpvkboSzv83rZi6MJFBbJI5Tt4NR nLMXZsVAJPGULlAO2UUcYZYZUggRoKQiBlsBSJAIxhKyGBIb/3VfN50zUZxoCeunCf cqAhSLTNzTBv30xKtNORW3i/pJ+C6eCvsNIeToOzV6oMmoH0YHKZnXKaswziUH8GEh Snwt0FNII1x4Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03ECDC79FA7; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 07 Sep 2026 17:54:43 +0800 Subject: [PATCH v2 04/10] dt-bindings: timer: Add UltraRISC DP1000 CLINT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-ultrarisc-dts-v2-4-5eb4c97477c5@ultrarisc.com> References: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> In-Reply-To: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jia Wang , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org, Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788775103; l=964; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=H5nCeqGhgsZIHGD5OQKUEdhmWR2MLVPLwQY1q4JBFrk=; b=qZtQO6xJbyoxFeLqeiG+vgTPNhUyPEuYbIwJnEzAzbJcXnokLi+XQS2BFd26iySduD/N/wyv/ yYBn2YXqHC6Br7I/x7XTpSZr6fcB0ViDdeu7/ewOh278fFgD6mTrBWB X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add compatible string for UltraRISC DP1000 CLINT. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index 3673836e14de..878f267d089b 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -40,6 +40,7 @@ properties: - starfive,jh8100-clint # StarFive JH8100 - starfive,jhb100-clint # StarFive JHB100 - tenstorrent,blackhole-clint # Tenstorrent Blackhole + - ultrarisc,dp1000-clint # UltraRISC DP1000 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - {} --=20 2.34.1 From nobody Fri Sep 25 23:54:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89F78455177; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; cv=none; b=KzN11VZu6EnN2Fl6z2qvxyQHI6U9FgnJBd98czFNytN792AaJpbnXF8+iRSFIS9Rv5tV6Z3VrUbhQg2CkFxQidMsk12CNieaXo3zhgfgPmm1Tiex1KCJNLzlwnxMDeq4g1jlyw+AmjKn0+NuQTwR8/q0UHqgEycx45o8NEn295Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; c=relaxed/simple; bh=6CZneFBn+qYzCyZ4soOnwEiAxpmztku5TRHKpXHT0OQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DcfsY6cFZjqyPdKfqEH+H6B5E5Oq+1G2T5lrT07HHLnXbhLC07lJcOvKbdN9R7xsu7VI5MzXtYmKDIgLpz24eOkM0y0q+MWpqz0eM9JAccUL2wdyLV5D+HIcFuJDhk7kquzGPYGEGic2m57BpReQRox+SK7MM2vttzvs0yWTILM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A3kGGpHe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A3kGGpHe" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2AA6CC4AF0D; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788775106; bh=6CZneFBn+qYzCyZ4soOnwEiAxpmztku5TRHKpXHT0OQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=A3kGGpHeyQTsnep0/+XHzgYiulMqnkfmqjW+aBpkYo2V5if/QcqNx9xBBopOfo6bf NZH4onhDJUCQcdCQ8kZuqkT/b635VAlcoSjZtm6udjdPAJdUzC0lVP3os0IhDmi0/H 5yuZ6xq6yGZOjMBGVzddbKXMzxOGkO8ddtV5fRGXehHDSC2TedEphhyZlniFLLy4YD LfxJxMq6Juvvgh6zoDqyiAVSMrUPPKuTEnQLadKY7YeMEbwvuaSxipXEZftr7DBkGJ QhDYRO0lPAd8djL0dCBp8A+k95bsX5umPX8yPq+BymdpUHIzNXYF6VKm1ZtXUaB9Ox ZCg0Hw3zDlcPg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 164DBC79F99; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 07 Sep 2026 17:54:44 +0800 Subject: [PATCH v2 05/10] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for UltraRISC DP1000 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-ultrarisc-dts-v2-5-5eb4c97477c5@ultrarisc.com> References: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> In-Reply-To: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jia Wang , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788775103; l=1663; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=MXexzfKaPsc1YI5omohzcuM1x6URdiZA7ZlibFWo5PY=; b=jHfiWF3egeJiK4FJHG5XZJ1nRggFi5xxHcKkEwd489i11A9dsyBbH2WRxwI0hbTImifyHwAIs albED9FdwPtDjWNaBmhG8DAPlQojzHWfV20BSgWMUNeSwi3TMJrs+A8 X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add the SoC-specific compatible string and use the generic one as fallback for the UltraRISC DP1000 SPI controller. The DP1000 integrates two SPI controllers. SPI0 supports standard, dual and quad transfers with three native chip-select signals. SPI1 supports standard transfers with four native chip-select signals. Both controllers have one register range and separate reference and APB interface clocks. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 16 ++++++++++++= ++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/D= ocumentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 1e70c6804d5d..e8d6d5d858b6 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -44,6 +44,21 @@ allOf: else: properties: starfive,sfc-filter-syscon: false + - if: + properties: + compatible: + contains: + const: ultrarisc,dp1000-spi + then: + properties: + reg: + maxItems: 1 + clocks: + minItems: 2 + clock-names: + minItems: 2 + required: + - clock-names =20 properties: compatible: @@ -63,6 +78,7 @@ properties: - mscc,jaguar2-spi - sophgo,sg2042-spi - thead,th1520-spi + - ultrarisc,dp1000-spi - const: snps,dw-apb-ssi - description: Vendor controllers compatible with v1.01a items: --=20 2.34.1 From nobody Fri Sep 25 23:54:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5646455634; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-ultrarisc-dts-v2-6-5eb4c97477c5@ultrarisc.com> References: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> In-Reply-To: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jia Wang , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788775103; l=1475; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=qmmOpiZIekiFaSTyRs9mX7I+f5uExLbikMi5zvQgBR0=; b=MwErmEoUN1yX+JIVBc+ba5Q2dXErRpQto0sss5j0hElQVOqMJXvvTtPalWZh+m4BTBf8Jq3Wl ENt8lFxCQsdB9c679906QjzeLeprXsiAtbyMOtMiuyYTnY914Vc6KyM X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang The DP1000 integrates four DesignWare APB I2C controllers. I2C1 supports SMBus, while I2C0, I2C2, and I2C3 support standard I2C transfers. Each controller has one register range and uses separate reference and APB interface clocks. Add the DP1000-specific compatible string with the generic one as a fallback. Signed-off-by: Jia Wang Acked-by: Conor Dooley Acked-by: Mika Westerberg --- .../devicetree/bindings/i2c/snps,designware-i2c.yaml | 15 +++++++++++= ++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml= b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml index 467bdcbb8538..8a7c0a44601b 100644 --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml @@ -21,6 +21,20 @@ allOf: properties: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + const: ultrarisc,dp1000-i2c + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + required: + - clocks + - clock-names =20 properties: compatible: @@ -44,6 +58,7 @@ properties: - mscc,ocelot-i2c - sophgo,sg2044-i2c - thead,th1520-i2c + - ultrarisc,dp1000-i2c - const: snps,designware-i2c =20 reg: --=20 2.34.1 From nobody Fri Sep 25 23:54:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C83BC456E10; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; cv=none; b=bO10kda96vxwn2PyWKnRzt11p67bbKpzLTcmZhASotFRMlENKRCQ+TVvmWC2Re0Jy/Z0YMfUB/DIwlF1y91A0GzatUDtaQFloHBPKydhbHsofiRHVxQ5gmxuIlNpFZQ31NCBrCZqg76VMFQfSS9sw79LhaC+gGTXRinRh8weekg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775106; c=relaxed/simple; bh=jbMzoob+yfp28o1fkQLtsSQu9lgIRg09JA0lafc+WTI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PICy1ak3RCCijUyqcKKB3RqCUdJY/jovKgPww+cElgjWzP59jcEdU9MREo5NaZOLsnOtn34W3uANoB/RD0Pgr/erqR7HJWf7HnAZb1gzR8hdYRsbJBGpYyF7JVMfHSkCRN8OwHc/phwoiKyRFFyD9TVvMfBj2loGqYSogxFk/Bo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iyiovwlB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iyiovwlB" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4D60AC4AF11; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788775106; bh=jbMzoob+yfp28o1fkQLtsSQu9lgIRg09JA0lafc+WTI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=iyiovwlBBuEOAq4Xon/s5M71gn3gz/X0/Q0muVMM7NDmpzqsDt+MEASEgykjuXV16 jkoUUZ4WC07E1GAF+5UDLZQEiX0OOTqu8TyOYXnsgO4sxaYeGqrTZ7ioOe7sPbB5ul fPxpBgJwGRw1YwrB6fdQB7ZgBISYWLnrwawdAlXDHLuCkV6bDWmYScWPs24qDqtf3V OTidh+RJnBG5uTKxiJLF3Gkv1rZe7V7sdluVeJbgaRAwMF62cxu1Kkk9yu97QPr+hC O1mHb8hg+fskHqBWz7BGzBror3FPaSTiGUNB2WypiiR9HgaSlZGhww95IgTQ+Itpdo NdymIhLtWNgOg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A3DAC79FA0; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 07 Sep 2026 17:54:46 +0800 Subject: [PATCH v2 07/10] dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-ultrarisc-dts-v2-7-5eb4c97477c5@ultrarisc.com> References: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> In-Reply-To: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jia Wang , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788775103; l=1419; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=ENFwCaDg2Es24T1JPD8nJSb6K6VohaYxMboKPZolvgI=; b=MyRA9jGZrwxWJ4/f/ssvZI6lzGtLrFdRbrj04uuCN0+jhnwxhnZs36ZCQyo03NHkrgeKwTgY7 meq5UYXIU1ZARPkIWze/XzKIuDOOQniuZ47xHauQ0/IYsaJTuP473O7 X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang The DP1000 integrates a DMA controller. Add its SoC-specific compatible with the generic fallback. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 22 ++++++++++++++++++= ++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/= Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 0a30a455b0ee..bfd6d67a98e6 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -14,6 +14,27 @@ description: =20 allOf: - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + const: ultrarisc,dp1000-axi-dma + then: + properties: + reg: + maxItems: 1 + interrupts: + minItems: 8 + dma-channels: + const: 8 + snps,dma-masters: + const: 1 + snps,data-width: + const: 4 + snps,priority: + minItems: 8 + snps,block-size: + minItems: 8 =20 properties: compatible: @@ -27,6 +48,7 @@ properties: - enum: - altr,agilex5-axi-dma - sophgo,cv1800b-axi-dma + - ultrarisc,dp1000-axi-dma - const: snps,axi-dma-1.01a =20 reg: --=20 2.34.1 From nobody Fri Sep 25 23:54:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C96734570CD; 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a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add the base device tree for the UltraRISC DP1000 SoC. It describes eight CP100 CPU cores, their cache topology, and essential peripherals including CLINT, PLIC, the clock controller, pinctrl, GPIO, UART, SPI, I2C, PCIe, GMAC, and the DMA controller. Signed-off-by: Jia Wang --- MAINTAINERS | 1 + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 899 ++++++++++++++++++++++++++= ++++ 2 files changed, 900 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index eb7a9caaa225..443d5398fb51 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23643,6 +23643,7 @@ L: linux-riscv@lists.infradead.org S: Supported T: git https://github.com/ultrarisc/linux.git F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml +F: arch/riscv/boot/dts/ultrarisc/ =20 RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dt= s/ultrarisc/dp1000.dtsi new file mode 100644 index 000000000000..5c51fddaeb2b --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi @@ -0,0 +1,899 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +/dts-v1/; + +#include + +/ { + compatible =3D "ultrarisc,dp1000"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <10000000>; + + cpu0: cpu@0 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x0>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache0>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache0: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu1: cpu@1 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x1>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache1>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache1: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu2: cpu@2 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x2>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache2>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache2: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu3: cpu@3 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x3>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache3>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache3: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu4: cpu@10 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x10>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache4>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache4: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + cpu5: cpu@11 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x11>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache5>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache5: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + cpu6: cpu@12 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x12>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache6>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu6_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache6: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + + cpu7: cpu@13 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x13>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache7>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu7_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache7: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + + cluster0_l3: l3-cache0 { + /* + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <3>; + cache-size =3D <0x400000>; + cache-sets =3D <0x1000>; + cache-unified; + next-level-cache =3D <&l4_cache>; + }; + + cluster1_l3: l3-cache1 { + /* + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <3>; + cache-size =3D <0x400000>; + cache-sets =3D <0x1000>; + cache-unified; + next-level-cache =3D <&l4_cache>; + }; + }; + + l4_cache: l4-cache { + /* + * L4 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 16MB + * shared by the SoC. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <4>; + cache-size =3D <0x1000000>; + cache-sets =3D <0x4000>; + cache-unified; + }; + + osc_24m: clock-24m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clint: clint@8000000 { + compatible =3D "ultrarisc,dp1000-clint", "sifive,clint0"; + reg =3D <0x0 0x8000000 0x0 0x100000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + plic: plic@9000000 { + compatible =3D "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; + reg =3D <0x0 0x9000000 0x0 0x4000000>; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu0_intc 10= >, + <&cpu1_intc 11>, <&cpu1_intc 9>, <&cpu1_intc 10>, + <&cpu2_intc 11>, <&cpu2_intc 9>, <&cpu2_intc 10>, + <&cpu3_intc 11>, <&cpu3_intc 9>, <&cpu3_intc 10>, + <&cpu4_intc 11>, <&cpu4_intc 9>, <&cpu4_intc 10>, + <&cpu5_intc 11>, <&cpu5_intc 9>, <&cpu5_intc 10>, + <&cpu6_intc 11>, <&cpu6_intc 9>, <&cpu6_intc 10>, + <&cpu7_intc 11>, <&cpu7_intc 9>, <&cpu7_intc 10>; + riscv,ndev =3D <160>; + }; + + clkc: clock-controller@11080000 { + compatible =3D "ultrarisc,dp1000-clk"; + reg =3D <0x0 0x11080000 0x0 0x1000>; + clocks =3D <&osc_24m>; + #clock-cells =3D <1>; + }; + + pinctrl: pinctrl@11081000 { + compatible =3D "ultrarisc,dp1000-pinctrl"; + reg =3D <0x0 0x11081000 0x0 0x1000>; + }; + + gpio: gpio@20200000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x0 0x20200000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "bus", "db"; + clocks =3D <&clkc DP1000_CLK_SUBSYS>, + <&clkc DP1000_CLK_SUBSYS>; + + gpio_a: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <16>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&plic>; + interrupts =3D <34>; + gpio-ranges =3D <&pinctrl 0 0 16>; + }; + + gpio_b: gpio-port@1 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <1>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <8>; + gpio-ranges =3D <&pinctrl 0 16 8>; + }; + + gpio_c: gpio-port@2 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <8>; + gpio-ranges =3D <&pinctrl 0 24 8>; + }; + + gpio_d: gpio-port@3 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <3>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <8>; + gpio-ranges =3D <&pinctrl 0 32 8>; + }; + }; + + uart0: serial@20300000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0x20300000 0x0 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <17>; + clocks =3D <&clkc DP1000_CLK_UART0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "baudclk", "apb_pclk"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + }; + + uart1: serial@20310000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0x20310000 0x0 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <18>; + clocks =3D <&clkc DP1000_CLK_UART1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "baudclk", "apb_pclk"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + }; + + uart2: serial@20400000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0x20400000 0x0 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <25>; + clocks =3D <&clkc DP1000_CLK_UART2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "baudclk", "apb_pclk"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + }; + + uart3: serial@20410000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0x20410000 0x0 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <26>; + clocks =3D <&clkc DP1000_CLK_UART3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "baudclk", "apb_pclk"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + }; + + spi0: spi@20320000 { + compatible =3D "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg =3D <0x0 0x20320000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc DP1000_CLK_SPI0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ssi_clk", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <19>; + num-cs =3D <3>; + }; + + spi1: spi@20420000 { + compatible =3D "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg =3D <0x0 0x20420000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc DP1000_CLK_SPI1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ssi_clk", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <27>; + num-cs =3D <4>; + }; + + i2c0: i2c@20330000 { + compatible =3D "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x20330000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&clkc DP1000_CLK_I2C0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ref", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <20>; + }; + + i2c1: i2c@20340000 { + compatible =3D "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x20340000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&clkc DP1000_CLK_I2C1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ref", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <21>; + }; + + i2c2: i2c@20430000 { + compatible =3D "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x20430000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&clkc DP1000_CLK_I2C2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ref", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <28>; + }; + + i2c3: i2c@20440000 { + compatible =3D "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x20440000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&clkc DP1000_CLK_I2C3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ref", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <29>; + }; + + pcie_x16: pcie@21000000 { + compatible =3D "ultrarisc,dp1000-pcie"; + reg =3D <0x0 0x21000000 0x0 0x1000000>, + <0x0 0x4fff0000 0x0 0x10000>; + reg-names =3D "dbi", "config"; + clocks =3D <&clkc DP1000_CLK_PCIEX16_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names =3D "core", "dbi", "aux"; + ranges =3D <0x81000000 0x0 0x00000000 0x0 0x4fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + bus-range =3D <0x0 0xff>; + num-lanes =3D <16>; + interrupt-parent =3D <&plic>; + interrupts =3D <43>, <44>, <45>, <46>, <47>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + + status =3D "disabled"; + }; + + pcie_x4a: pcie@23000000 { + compatible =3D "ultrarisc,dp1000-pcie"; + reg =3D <0x0 0x23000000 0x0 0x1000000>, + <0x0 0x6fff0000 0x0 0x10000>; + reg-names =3D "dbi", "config"; + clocks =3D <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names =3D "core", "dbi", "aux"; + ranges =3D <0x81000000 0x0 0x00000000 0x0 0x6fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, + <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + bus-range =3D <0x0 0xff>; + num-lanes =3D <4>; + interrupt-parent =3D <&plic>; + interrupts =3D <63>, <64>, <65>, <66>, <67>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 64>, + <0x0 0x0 0x0 0x2 &plic 65>, + <0x0 0x0 0x0 0x3 &plic 66>, + <0x0 0x0 0x0 0x4 &plic 67>; + + status =3D "disabled"; + }; + + pcie_x4b: pcie@24000000 { + compatible =3D "ultrarisc,dp1000-pcie"; + reg =3D <0x0 0x24000000 0x0 0x1000000>, + <0x0 0x7fff0000 0x0 0x10000>; + reg-names =3D "dbi", "config"; + clocks =3D <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names =3D "core", "dbi", "aux"; + ranges =3D <0x81000000 0x0 0x00000000 0x0 0x7fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, + <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + bus-range =3D <0x0 0xff>; + num-lanes =3D <4>; + interrupt-parent =3D <&plic>; + interrupts =3D <73>, <74>, <75>, <76>, <77>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 74>, + <0x0 0x0 0x0 0x2 &plic 75>, + <0x0 0x0 0x0 0x3 &plic 76>, + <0x0 0x0 0x0 0x4 &plic 77>; + + status =3D "disabled"; + }; + + ethernet: ethernet@38000000 { + compatible =3D "ultrarisc,dp1000-gmac", "snps,dwmac-5.20"; + reg =3D <0x0 0x38000000 0x0 0x1000000>; + clocks =3D <&clkc DP1000_CLK_GMAC>; + clock-names =3D "stmmaceth"; + interrupt-parent =3D <&plic>; + interrupts =3D <84>; + interrupt-names =3D "macirq"; + snps,txpbl =3D <8>; + snps,rxpbl =3D <8>; + + status =3D "disabled"; + }; + + dmac: dma-controller@39000000 { + compatible =3D "ultrarisc,dp1000-axi-dma", "snps,axi-dma-1.01a"; + reg =3D <0x0 0x39000000 0x0 0x400>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-ultrarisc-dts-v2-9-5eb4c97477c5@ultrarisc.com> References: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> In-Reply-To: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jia Wang , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788775103; l=6533; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=FLco8EKil9coXfOOohEgx8XQNQE43bTkwaWzTcrXeQk=; b=ye0m+TrSyVpAJGhkYnRwU6z7Kn7KiyEpvVoTDFL9tkaqm774+r8urYzlRB0NfQIysLgLtmZJP E5MagVHP736CtVl0J8bzS6aLi1T6Gr2rrGfMKrAtSyx0uN4CDa8Y8Iv X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Shenzhen Rongda M0 is an mATX motherboard based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h | 63 ++++++++++++ .../ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi | 79 ++++++++++++++ .../boot/dts/ultrarisc/dp1000-shenrongda-m0.dts | 113 +++++++++++++++++= ++++ 5 files changed, 258 insertions(+) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 69d8751fb17c..702882974251 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -12,3 +12,4 @@ subdir-y +=3D spacemit subdir-y +=3D starfive subdir-y +=3D tenstorrent subdir-y +=3D thead +subdir-y +=3D ultrarisc diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/u= ltrarisc/Makefile new file mode 100644 index 000000000000..454d849a6ce4 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) +=3D dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/bo= ot/dts/ultrarisc/dp1000-pinctrl.h new file mode 100644 index 000000000000..4668e45d2335 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#ifndef _DP1000_PINCTRL_H +#define _DP1000_PINCTRL_H + +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PC0 24 +#define PC1 25 +#define PC2 26 +#define PC3 27 +#define PC4 28 +#define PC5 29 +#define PC6 30 +#define PC7 31 +#define PD0 32 +#define PD1 33 +#define PD2 34 +#define PD3 35 +#define PD4 36 +#define PD5 37 +#define PD6 38 +#define PD7 39 +#define LPC0 40 +#define LPC1 41 +#define LPC2 42 +#define LPC3 43 +#define LPC4 44 +#define LPC5 45 +#define LPC6 46 +#define LPC7 47 +#define LPC8 48 +#define LPC9 49 +#define LPC10 50 +#define LPC11 51 +#define LPC12 52 + +#endif /* _DP1000_PINCTRL_H */ diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dts= i b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi new file mode 100644 index 000000000000..ab927c6cd614 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c1_pins: i2c1-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c2_pins: i2c2-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c3_pins: i2c3-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + spi0_pins: spi0-pins { + pins =3D ; + function =3D "spi"; + bias-pull-up; + drive-strength =3D <33>; + }; + + spi1_pins: spi1-pins { + pins =3D ; + function =3D "spi"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart0_pins: uart0-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart1_pins: uart1-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart2_pins: uart2-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart3_pins: uart3-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/= riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts new file mode 100644 index 000000000000..43f713bcea25 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-shenrongda-m0-pinctrl.dtsi" +#include + +/ { + model =3D "Shenzhen Rongda M0 Board"; + compatible =3D "shenrongda,m0", "ultrarisc,dp1000"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + + rtc@32 { + compatible =3D "whwave,sd3078"; + reg =3D <0x32>; + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; +}; + +&spi1 { + num-cs =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3_pins>; +}; + +&pcie_x16 { + status =3D "okay"; +}; + +&pcie_x4a { + status =3D "okay"; +}; + +&pcie_x4b { + status =3D "okay"; +}; + +ðernet { + phy-handle =3D <&phy0>; + /* + * The PCB does not add RGMII TX or RX clock delays. The DP1000 + * integration adds fixed delays in both directions. + */ + phy-mode =3D "rgmii-id"; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy0: phy@0 { + reg =3D <0>; + }; + }; +}; --=20 2.34.1 From nobody Fri Sep 25 23:54:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFA4E4582C7; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775107; cv=none; b=AMQjqzgQ948mna6Tzl/Z+H2Oj4mwJH8hAfcreMAy0owAqbXOHj3NKEzvDJzgYfvkTNuF27vheGRiO/jz1tjd/fdlVuPWrLIK+bJ7noDsUDNUDlFuM1ylln+1vRsn3GNmBK0O1YEUFf6c/hqGxOPZbVtbqI5eP96SyYnYhoJf/bA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775107; c=relaxed/simple; bh=stFWnGr8qituroDzzylkIvteQb6/v1UMCo2xAmzSvDs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VlJeByHPxVnmEQxQXKs8ItW0DKo8y90hYQX4VBkQia1P7veHYsFHLFC1UvQNfYJY3VUeuxp19x4u0ECI7hD26WZjkIkgZnIUWhP1M7/8NlpbmRN8dVTl5Yy0TPBIH8RdSHOdI90dq8+nX83Emxc3eGPcvGpiydo/+fNkAkw8siU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m4TyiU7T; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m4TyiU7T" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8AB6DC4AF1A; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788775106; bh=stFWnGr8qituroDzzylkIvteQb6/v1UMCo2xAmzSvDs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=m4TyiU7TwJ+ifibBW0Zkb4Hf+zypQ0r4ecQslRWV8KChBMBY0R25JHqmrwYKtjKVA YNEguJmMhqlHLh2vgu1Ttc4wGHY7267eABjlDm0qeaLJQaoPKq3dqheCv8GMCpo5ye ZjMjEedu5l0bSxJP5vy7flCkWh/DzAFL0fBz28F7IA4hIjL8xD0ol59MFn2Fizli11 NWjTfDubEr3hA9AR4Th9M2oMHv6OYTEGuzYIVUhuUww5hTMrTHHCkuh+ZDpyYSH8LC BrxJ3z3fJwWNhg0z4eYG3DtNft1noH1s7lWqDpHEJKgm+GsmYTS75C/+VjlpVttivk dyG8zJd6u8JSg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76834C79F89; Mon, 7 Sep 2026 09:58:26 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 07 Sep 2026 17:54:49 +0800 Subject: [PATCH v2 10/10] riscv: dts: ultrarisc: Add Milk-V Titan board device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-ultrarisc-dts-v2-10-5eb4c97477c5@ultrarisc.com> References: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> In-Reply-To: <20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jia Wang , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788775103; l=7334; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=dAtkSFZr6AV1hMUKbe3Hu73EzYFoZ2u8+96QxJOEsCA=; b=yiRYYozF6HckWerWPKKZ2H+6+zbHMo+ifuvwcDW8yRYvlrtHo+QDOPpQFDR53zeLCFz8j8EQg aAkJEqwaT8RDt/2foEZMiwYIBbE6mWhYR+i05lAfc2VHQk+Nl3iAbWw X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Milk-V Titan is an ITX motherboard based on the UltraRISC DP1000 SoC. Link: https://milkv.io/docs/titan/overview Signed-off-by: Jia Wang --- arch/riscv/boot/dts/ultrarisc/Makefile | 1 + .../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 108 +++++++++++ .../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 203 +++++++++++++++++= ++++ 3 files changed, 312 insertions(+) diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/u= ltrarisc/Makefile index 454d849a6ce4..dfd15c064d07 100644 --- a/arch/riscv/boot/dts/ultrarisc/Makefile +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) +=3D dp1000-milkv-titan.dtb dtb-$(CONFIG_ARCH_ULTRARISC) +=3D dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi = b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi new file mode 100644 index 000000000000..7a812e40a249 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c1_pins: i2c1-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c2_pins: i2c2-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c3_pins: i2c3-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + io_pins: io-pins { + pins =3D ; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <33>; + }; + + gpio_keys_pins: gpio-keys-pins { + pins =3D ; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <33>; + }; + + mux_dcdc_i2c_pins: mux-dcdc-i2c-pins { + pins =3D ; + function =3D "gpio"; + }; + + mux_i2c3_pins: mux-i2c3-pins { + pins =3D ; + function =3D "gpio"; + }; + + mux_uart0_pins: mux-uart0-pins { + pins =3D ; + function =3D "gpio"; + }; + + spi0_pins: spi0-pins { + pins =3D ; + function =3D "spi"; + bias-pull-up; + drive-strength =3D <33>; + }; + + spi1_pins: spi1-pins { + pins =3D ; + function =3D "spi"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart0_pins: uart0-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart1_pins: uart1-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart2_pins: uart2-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart3_pins: uart3-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/ri= scv/boot/dts/ultrarisc/dp1000-milkv-titan.dts new file mode 100644 index 000000000000..59edd8157221 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-milkv-titan-pinctrl.dtsi" +#include +#include +#include +#include +#include + +/ { + model =3D "Milk-V Titan"; + compatible =3D "milkv,titan", "ultrarisc,dp1000"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio_keys_pins>; + + key-wakeup-0 { + label =3D "Wake-Up"; + gpios =3D <&gpio_a 14 GPIO_ACTIVE_LOW>; + linux,code =3D ; + linux,input-type =3D ; + debounce-interval =3D <10>; + wakeup-source; + wakeup-event-action =3D ; + }; + + key-wakeup-1 { + label =3D "Power"; + gpios =3D <&gpio_a 11 GPIO_ACTIVE_LOW>; + linux,code =3D ; + linux,input-type =3D ; + debounce-interval =3D <10>; + wakeup-source; + wakeup-event-action =3D ; + }; + + key-wakeup-2 { + label =3D "Wake-Up-by-USB"; + interrupts-extended =3D <&gpio_a 4 IRQ_TYPE_EDGE_FALLING>; + linux,code =3D ; + linux,input-type =3D ; + debounce-interval =3D <10>; + wakeup-source; + }; + }; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + + rtc@68 { + compatible =3D "st,m41t11"; + reg =3D <0x68>; + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; +}; + +&spi1 { + num-cs =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3_pins>; +}; + +&pcie_x16 { + status =3D "okay"; +}; + +&pcie_x4a { + status =3D "okay"; +}; + +&pcie_x4b { + status =3D "okay"; +}; + +&gpio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&io_pins &mux_dcdc_i2c_pins &mux_i2c3_pins &mux_uart0_pins= >; +}; + +&gpio_a { + dcdc-i2c-mux-hog { + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "dcdc-i2c-mux"; + }; + + i2c3-mux-hog { + gpio-hog; + gpios =3D <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "i2c3-mux"; + }; + + uart0-mux-hog { + gpio-hog; + gpios =3D <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "uart0-mux"; + }; +}; + +ðernet { + phy-handle =3D <&phy0>; + /* + * The PCB does not add RGMII TX or RX clock delays. The DP1000 + * integration adds fixed delays in both directions. + */ + phy-mode =3D "rgmii-id"; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy0: phy@0 { + reg =3D <0>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@1 { + label =3D "eth-link"; + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + default-state =3D "keep"; + linux,default-trigger =3D "netdev"; + }; + + led@2 { + label =3D "eth-activity"; + reg =3D <2>; + color =3D ; + function =3D LED_FUNCTION_ACTIVITY; + default-state =3D "keep"; + linux,default-trigger =3D "netdev"; + }; + }; + }; + }; +}; --=20 2.34.1