From nobody Fri Sep 25 23:09:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3B28373BE7; Mon, 7 Sep 2026 18:05:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788804307; cv=none; b=L/w9Z8wXqcng3zqfaCIKfpr3MEXMphvdDI2Ss8i5l6dlX++L6PL2nUHv/u7xazVRgF7g8j15eOlQHzbG0EmcPnGYoRpLXpDojHIvwjTR/Qljjy+5nH/ykWr445OUUfzNnhjnPakLtAbRGHWxEVAjyL1Y22xNekadUyVRaJIrsfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788804307; c=relaxed/simple; bh=HRKfDnU7fpe4hKYsO1qj++xJuTiGlwZYM7a7gsCq21Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YxjXn5geSzneLNuYfznCQwM1krzpQmXad5Jikj21cyxDI/0Mz+qsNw6H2xi+POHrlII/rMflA9vZMTpulpmIH9Wqjnpiva1rKiE1XmeYnMs9FUe7Hr/lFRK7MDcIyuoqTXAKFaghmxhe4RLdQyxbgZ/otyhgJ9BPkz+t2/swT1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q6w8fsQR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q6w8fsQR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 544F8C2BCFC; Mon, 7 Sep 2026 18:05:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788804307; bh=HRKfDnU7fpe4hKYsO1qj++xJuTiGlwZYM7a7gsCq21Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Q6w8fsQREm1eCpIPHDmn+hdFxAHEh88vOFEOJaFm5Niv3iB+YTyiPwVIwkHFlZU7z nKvaNlzGixY7NJOQuOHDzu0YraARtU5Q1JK//7vG+77TqN7qIBYGNxpkJogsDySee8 irL8lp/MIaDXeQ8Un8Ei98cm6Gggb6173PJajhIWe7nnpbNL/IR4hdWivHQBEupdih 8Q/zB3lnp1wl+UARMyr5lNhi5nPS+DrsBUEdPG3Bx18tjsuiqtl+SAnD+XyWCEQOa2 DM4Kx4fna2SvaS11aLvQxg4ynQRrSvgaN9jWdnGqdu3dg37LOKQ9QcC3hju3ZVC8Ny p9Um2+3NKsL0w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3052BC79F99; Mon, 7 Sep 2026 18:05:07 +0000 (UTC) From: Roman Vivchar via B4 Relay Date: Mon, 07 Sep 2026 21:03:05 +0300 Subject: [PATCH v2 1/3] dt-bindings: mailbox: mediatek,gce-mailbox: add mt6572 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-6572-gce-v2-1-412a5b037290@protonmail.com> References: <20260907-6572-gce-v2-0-412a5b037290@protonmail.com> In-Reply-To: <20260907-6572-gce-v2-0-412a5b037290@protonmail.com> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Houlong Wei Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Roman Vivchar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788804305; l=2822; i=rva333@protonmail.com; s=20260510; h=from:subject:message-id; bh=/tLOb7ev/WM/LwpIpJ2zPo9FlE7c2orfGWi2CVoRzjw=; b=3Oxrmkyz4/yIStLEu203OBakaNbk1L4OkD0Yt892uXJuGpzqi8MbwMB6NCflV2Xjl3WBtwYlF N27vLwsUqavD26aiumMKqa2lhGVhXtZSqXSAgMboSAIksIKr1WuTUG6 X-Developer-Key: i=rva333@protonmail.com; a=ed25519; pk=zww/nWjBGoQ4POXCG0BV6fx2iuXK6jx77rsKPA5YK5Y= X-Endpoint-Received: by B4 Relay for rva333@protonmail.com/20260510 with auth_id=777 X-Original-From: Roman Vivchar Reply-To: rva333@protonmail.com From: Roman Vivchar Add a compatible string and a header for the GCE constants. Signed-off-by: Roman Vivchar Reviewed-by: AngeloGioacchino Del Regno --- There's also 'other' subsystem which covers 0x16XXXXXX range, however mt6572 doesn't seem to have any MMIO there. It's not included in this patch. --- .../bindings/mailbox/mediatek,gce-mailbox.yaml | 1 + include/dt-bindings/mailbox/mediatek,mt6572-gce.h | 52 ++++++++++++++++++= ++++ 2 files changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox= .yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml index 587126d03fc6..d6e93010bb94 100644 --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml @@ -18,6 +18,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt6572-gce - mediatek,mt6779-gce - mediatek,mt8173-gce - mediatek,mt8183-gce diff --git a/include/dt-bindings/mailbox/mediatek,mt6572-gce.h b/include/dt= -bindings/mailbox/mediatek,mt6572-gce.h new file mode 100644 index 000000000000..94eb6ea97542 --- /dev/null +++ b/include/dt-bindings/mailbox/mediatek,mt6572-gce.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2026 Roman Vivchar + */ + +#ifndef _DT_BINDINGS_GCE_MT6572_H +#define _DT_BINDINGS_GCE_MT6572_H + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_NORMAL 0 +#define CMDQ_THR_PRIO_HIGHEST 1 + +/* GCE SUBSYS */ +#define SUBSYS_14XXXXXX 0 +#define SUBSYS_15XXXXXX 1 + +/* GCE HW EVENT */ +#define CMDQ_EVENT_MUTEX0 0 +#define CMDQ_EVENT_MUTEX1 1 +#define CMDQ_EVENT_MUTEX2 2 +#define CMDQ_EVENT_MUTEX3 3 +#define CMDQ_EVENT_MUTEX4 4 +#define CMDQ_EVENT_MUTEX5 5 +#define CMDQ_EVENT_MUTEX6 6 +#define CMDQ_EVENT_MUTEX7 7 + +#define CMDQ_EVENT_DISP_WDMA_EOF 12 +#define CMDQ_EVENT_DISP_RDMA_EOF 13 +#define CMDQ_EVENT_DISP_BLS_EOF 14 +#define CMDQ_EVENT_DISP_COLOR_EOF 15 +#define CMDQ_EVENT_DISP_OVL_EOF 16 +#define CMDQ_EVENT_MDP_TDSHP_EOF 17 +#define CMDQ_EVENT_MDP_RSZ1_EOF 18 +#define CMDQ_EVENT_MDP_RSZ0_EOF 19 +#define CMDQ_EVENT_MDP_RDMA_EOF 20 +#define CMDQ_EVENT_MDP_WDMA_EOF 21 +#define CMDQ_EVENT_MDP_WROT_EOF 22 + +#define CMDQ_EVENT_MDP_WROT_SOF 24 +#define CMDQ_EVENT_MDP_RSZ0_SOF 25 +#define CMDQ_EVENT_MDP_RSZ1_SOF 26 +#define CMDQ_EVENT_DISP_OVL_SOF 27 +#define CMDQ_EVENT_MDP_WDMA_SOF 28 +#define CMDQ_EVENT_MDP_RDMA_SOF 29 +#define CMDQ_EVENT_DISP_WDMA_SOF 30 +#define CMDQ_EVENT_DISP_COLOR_SOF 31 +#define CMDQ_EVENT_MDP_TDSHP_SOF 32 +#define CMDQ_EVENT_DISP_BLS_SOF 33 +#define CMDQ_EVENT_DISP_RDMA_SOF 34 +#define CMDQ_EVENT_CAM_MDP 35 + +#endif --=20 2.55.0 From nobody Fri Sep 25 23:09:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A77593876CD; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-6572-gce-v2-2-412a5b037290@protonmail.com> References: <20260907-6572-gce-v2-0-412a5b037290@protonmail.com> In-Reply-To: <20260907-6572-gce-v2-0-412a5b037290@protonmail.com> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Houlong Wei Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Roman Vivchar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788804305; l=3889; i=rva333@protonmail.com; s=20260510; h=from:subject:message-id; bh=Uu3P5wuRY5/ZH17+b4JdmrxQxerJafFFRwJH5TYZehQ=; b=op39buDZAmJXgQKhtDaF+BBWSb5/59ftXLIn4uk1/rRHSDVAcd2MP8LZBqLZo5x0gvsWCF3RI QYmIsKafIvgAeYjaZyc3uedOWfGMF47v0yrrO2G/mQ82kf/6JSmXgii X-Developer-Key: i=rva333@protonmail.com; a=ed25519; pk=zww/nWjBGoQ4POXCG0BV6fx2iuXK6jx77rsKPA5YK5Y= X-Endpoint-Received: by B4 Relay for rva333@protonmail.com/20260510 with auth_id=777 X-Original-From: Roman Vivchar Reply-To: rva333@protonmail.com From: Roman Vivchar Some SoCs, such as mt6572, have different WRITE and POLL instruction encoding. Instead of 16-bit offset and 8-bit subsystem ID, old GCEs have 22-bit offset and 2-bit subsystem ID. Extend cmdq_instruction struct with additional union and struct to hold the legacy format of instruction encoding. Add legacy_isa to select legacy GCE ISA when writing instruction. Finally, add special handing for legacy_isa cases. Also correct comment about PA writes, because it's incorrect for legacy ISA. Only v2 (mt8167, 8173) and v3 (mt8168, 6768, 6779, 6785, etc) have GPRs and SPRs for PA writes. While mt6572 GCE supports 22-bit offsets, the parameter type for offset remains 16 bit, because all mt6572 GCE mmsys consumers are in the 0xffff range. Signed-off-by: Roman Vivchar Acked-by: AngeloGioacchino Del Regno Reviewed-by: AngeloGioacchino Del Regno --- This change doesn't bring any functional change for mt6572. mt6572 uses subsystem ID 0 for display, alongside with 16-bit offsets, so layout is still compatible with v2/v3 GCEs. However, it's better to properly describe layout. --- drivers/soc/mediatek/mtk-cmdq-helper.c | 57 ++++++++++++++++++++++------= ---- include/linux/mailbox/mtk-cmdq-mailbox.h | 1 + 2 files changed, 40 insertions(+), 18 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/= mtk-cmdq-helper.c index f8ee6c9ade89..fb82f2a85a21 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -31,18 +31,27 @@ struct cmdq_instruction { }; }; union { - u16 offset; - u16 event; - u16 reg_dst; - }; - union { - u8 subsys; struct { - u8 sop:5; - u8 arg_c_t:1; - u8 src_t:1; - u8 dst_t:1; - }; + union { + u16 offset; + u16 event; + u16 reg_dst; + }; + union { + u8 subsys; + struct { + u8 sop:5; + u8 arg_c_t:1; + u8 src_t:1; + u8 dst_t:1; + }; + }; + } __packed; + + struct { + u32 offset_legacy:22; + u32 subsys_legacy:2; + } __packed; }; u8 op; }; @@ -86,7 +95,7 @@ int cmdq_dev_get_client_reg(struct device *dev, client_reg->subsys =3D CMDQ_SUBSYS_INVALID; =20 /* - * All GCEs support writing register PA with mask without subsys, + * GCE v2/v3 support writing register PA with mask without subsys, * but this requires extra GCE instructions to convert the PA into * a format that GCE can handle, which is less performance than * directly using subsys. Therefore, when subsys is available, @@ -219,10 +228,16 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u= 16 offset, u32 value) { struct cmdq_instruction inst =3D { .op =3D CMDQ_CODE_WRITE, - .value =3D value, - .offset =3D offset, - .subsys =3D subsys + .value =3D value }; + + if (pkt->priv.legacy_isa) { + inst.offset_legacy =3D offset; + inst.subsys_legacy =3D subsys; + } else { + inst.offset =3D offset; + inst.subsys =3D subsys; + } return cmdq_pkt_append_command(pkt, inst); } EXPORT_SYMBOL(cmdq_pkt_write); @@ -459,10 +474,16 @@ int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, { struct cmdq_instruction inst =3D { .op =3D CMDQ_CODE_POLL, - .value =3D value, - .offset =3D offset, - .subsys =3D subsys + .value =3D value }; + + if (pkt->priv.legacy_isa) { + inst.offset_legacy =3D offset; + inst.subsys_legacy =3D subsys; + } else { + inst.offset =3D offset; + inst.subsys =3D subsys; + } return cmdq_pkt_append_command(pkt, inst); } EXPORT_SYMBOL(cmdq_pkt_poll); diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailb= ox/mtk-cmdq-mailbox.h index 07c1bfbdb8c4..9fcebc4ca864 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -72,6 +72,7 @@ struct cmdq_cb_data { =20 struct cmdq_mbox_priv { u8 shift_pa; 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Mon, 7 Sep 2026 18:05:07 +0000 (UTC) From: Roman Vivchar via B4 Relay Date: Mon, 07 Sep 2026 21:03:07 +0300 Subject: [PATCH v2 3/3] mailbox: mtk-cmdq: add mt6572 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-6572-gce-v2-3-412a5b037290@protonmail.com> References: <20260907-6572-gce-v2-0-412a5b037290@protonmail.com> In-Reply-To: <20260907-6572-gce-v2-0-412a5b037290@protonmail.com> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Houlong Wei Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Roman Vivchar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788804305; l=1755; i=rva333@protonmail.com; s=20260510; h=from:subject:message-id; bh=MP44FydKmOzCKLnDrKX8Goxp+gVfwj/6kJhGpboIwQY=; b=AFArNDjBCHtPbXmI8WLL+9005tldLqFATBpTrGGwjgF1zedsNeADjzyeHTvLdWYspGaWlW8zv c0WTFDjYzXQDTjvHNlVu/U2iKDUSySCaB0Hy5+OrCWnNsT7mWIYs7Gl X-Developer-Key: i=rva333@protonmail.com; a=ed25519; pk=zww/nWjBGoQ4POXCG0BV6fx2iuXK6jx77rsKPA5YK5Y= X-Endpoint-Received: by B4 Relay for rva333@protonmail.com/20260510 with auth_id=777 X-Original-From: Roman Vivchar Reply-To: rva333@protonmail.com From: Roman Vivchar Add legacy_isa field forwarding to the cmdq helper and a platform data for the mt6572 GCE. Signed-off-by: Roman Vivchar Reviewed-by: AngeloGioacchino Del Regno --- drivers/mailbox/mtk-cmdq-mailbox.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index e523c84b4808..5e7bc52baaa1 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -99,6 +99,7 @@ struct gce_plat { bool control_by_sw; bool sw_ddr_en; bool gce_vm; + bool legacy_isa; u32 gce_num; }; =20 @@ -119,6 +120,7 @@ void cmdq_get_mbox_priv(struct mbox_chan *chan, struct = cmdq_mbox_priv *priv) struct cmdq *cmdq =3D container_of(chan->mbox, struct cmdq, mbox); =20 priv->shift_pa =3D cmdq->pdata->shift; + priv->legacy_isa =3D cmdq->pdata->legacy_isa; priv->mminfra_offset =3D cmdq->pdata->mminfra_offset; } EXPORT_SYMBOL(cmdq_get_mbox_priv); @@ -787,6 +789,14 @@ static const struct dev_pm_ops cmdq_pm_ops =3D { cmdq_runtime_resume, NULL) }; =20 +static const struct gce_plat gce_plat_mt6572 =3D { + .thread_nr =3D 14, + .shift =3D 0, + .control_by_sw =3D false, + .legacy_isa =3D true, + .gce_num =3D 1 +}; + static const struct gce_plat gce_plat_mt6779 =3D { .thread_nr =3D 24, .shift =3D 3, @@ -848,6 +858,7 @@ static const struct gce_plat gce_plat_mt8196 =3D { }; =20 static const struct of_device_id cmdq_of_ids[] =3D { + {.compatible =3D "mediatek,mt6572-gce", .data =3D (void *)&gce_plat_mt657= 2}, {.compatible =3D "mediatek,mt6779-gce", .data =3D (void *)&gce_plat_mt677= 9}, {.compatible =3D "mediatek,mt8173-gce", .data =3D (void *)&gce_plat_mt817= 3}, {.compatible =3D "mediatek,mt8183-gce", .data =3D (void *)&gce_plat_mt818= 3}, --=20 2.55.0