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charset="utf-8" Add device tree binding for the per-controller RCSU register regions of the CIX Sky1 USBSSP controllers. The regions are exposed as syscon nodes; USBSSP glue nodes reference their per-controller registers through the cix,usb-rcsu phandle with register offsets. The per-controller RCSU control and status registers live in a shared RCSU region described by the cix,sky1-usbss-rcsu binding and are referenced through the cix,usb-rcsu phandle. Signed-off-by: Hongliang Yang --- .../bindings/usb/cix,sky1-usbss-rcsu.yaml | 46 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/cix,sky1-usbss-rc= su.yaml diff --git a/Documentation/devicetree/bindings/usb/cix,sky1-usbss-rcsu.yaml= b/Documentation/devicetree/bindings/usb/cix,sky1-usbss-rcsu.yaml new file mode 100644 index 000000000000..d0c54fd2cd5f --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cix,sky1-usbss-rcsu.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cix,sky1-usbss-rcsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 USBSSP RCSU system controller + +maintainers: + - Hongliang Yang + +description: + The CIX Sky1 USBSSP controllers integrate their per-instance glue + registers (AXI bus attribute configuration and controller status) + inside a shared RCSU register region in the SoC system control + aperture. This binding describes that region as a syscon, so USBSSP + glue nodes can reference their register offsets through the + cix,usb-rcsu phandle (see cix,sky1-usbssp.yaml). + +properties: + compatible: + items: + - const: cix,sky1-usbss-rcsu + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + syscon@91c0300 { + compatible =3D "cix,sky1-usbss-rcsu", "syscon"; + reg =3D <0x00 0x091c0300 0x00 0x200>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 15011f5752a9..1408b89607ff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2775,6 +2775,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix.git F: Documentation/devicetree/bindings/arm/cix.yaml F: Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml +F: Documentation/devicetree/bindings/usb/cix,sky1-usbss-rcsu.yaml F: arch/arm64/boot/dts/cix/ F: drivers/mailbox/cix-mailbox.c K: \bcix\b --=20 2.54.0 From nobody Sat Sep 26 01:54:43 2026 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023142.outbound.protection.outlook.com [52.101.127.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FE7037A834; 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charset="utf-8" Add device tree binding for the CIX Sky1 Cadence USBSSP controller glue layer. The integration adds glue registers and mode strap controls in the Sky1 S5 system controller. The CIX glue node wraps a Cadence USBSSP core as a child node. The per-controller RCSU control and status registers live in a shared RCSU region described by the cix,sky1-usbss-rcsu binding and are referenced through the cix,usb-rcsu phandle. The per-controller RCSU registers are accessed through a syscon regmap referenced by the cix,usb-rcsu phandle. Signed-off-by: Hongliang Yang --- .../bindings/usb/cix,sky1-usbssp.yaml | 144 ++++++++++++++++++ MAINTAINERS | 3 + 2 files changed, 147 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/cix,sky1-usbssp.y= aml diff --git a/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml b/D= ocumentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml new file mode 100644 index 000000000000..8e66dea50fa7 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cix,sky1-usbssp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 Cadence USBSSP Controller + +maintainers: + - Hongliang Yang + +description: + The CIX Sky1 USBSSP controller is based on the Cadence USBSSP DRD + controller. The integration adds glue registers and mode strap controls + in the Sky1 S5 system controller. The CIX glue node wraps a Cadence + USBSSP core as a child node. The per-controller RCSU control/status + registers live in a shared RCSU region and are accessed through the + cix,usb-rcsu phandle. + +properties: + compatible: + const: cix,sky1-usbssp + + cix,usb-rcsu: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + A phandle to the USBSSP RCSU system controller region (see + cix,sky1-usbss-rcsu.yaml) followed by two cells: the offset of + the AXI property configuration register and the offset of the + controller status register, both relative to the RCSU region. + items: + items: + - description: phandle to the USBSSP RCSU syscon node + - description: offset of the AXI property configuration register + - description: offset of the controller status register + + clocks: + items: + - description: Start-of-frame clock + - description: AXI bus clock + - description: Low-power mode clock + - description: APB register interface clock + + clock-names: + items: + - const: sof + - const: axi + - const: lpm + - const: apb + + resets: + items: + - description: APB register reset + - description: Controller reset + + reset-names: + items: + - const: apb + - const: core + + cix,usb-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the Sky1 S5 system controller used to program USB mode + strap controls. + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: cdns,usb3.yaml# + +required: + - compatible + - cix,usb-rcsu + - clocks + - clock-names + - resets + - reset-names + - cix,usb-syscon + - "#address-cells" + - "#size-cells" + - ranges + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + rcsu: syscon@91c0300 { + compatible =3D "cix,sky1-usbss-rcsu", "syscon"; + reg =3D <0x00 0x091c0300 0x00 0x200>; + }; + + usb-4 { + compatible =3D "cix,sky1-usbssp"; + ranges; + #address-cells =3D <2>; + + clocks =3D <&scmi_clk CLK_TREE_USB3A_H0_CLK_SOF>, + <&scmi_clk CLK_TREE_USB3A_0_AXI_GATE>, + <&scmi_clk CLK_TREE_USB3A_H0_CLK_LPM>, + <&scmi_clk CLK_TREE_USB3A_0_APB_GATE>; + clock-names =3D "sof", "axi", "lpm", "apb"; + resets =3D <&src SKY1_USBC_SS2_PRST_N>, + <&src SKY1_USBC_SS2_RST_N>; + reset-names =3D "apb", "core"; + #size-cells =3D <2>; + cix,usb-syscon =3D <&src>; + cix,usb-rcsu =3D <&rcsu 0x14 0x100>; + + usb@91d0000 { + compatible =3D "cdns,usb3"; + reg =3D <0x00 0x91d0000 0x00 0x4000>, + <0x00 0x91d8000 0x00 0x8000>, + <0x00 0x91d4000 0x00 0x4000>; + reg-names =3D "otg", "xhci", "dev"; + dr_mode =3D "otg"; + + interrupts =3D , + , + , + ; + interrupt-names =3D "host", "peripheral", "otg", "wakeup"; + maximum-speed =3D "super-speed-plus"; + + phys =3D <&usb3_phy4_0>, <&usb2_phy6>; + phy-names =3D "cdns3,usb3-phy", "cdns3,usb2-phy"; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 1408b89607ff..8899a010fece 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2775,9 +2775,12 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix.git F: Documentation/devicetree/bindings/arm/cix.yaml F: Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml +F: Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml F: Documentation/devicetree/bindings/usb/cix,sky1-usbss-rcsu.yaml +F: Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml F: arch/arm64/boot/dts/cix/ F: drivers/mailbox/cix-mailbox.c +F: drivers/phy/cix/ K: \bcix\b =20 ARM/CLKDEV SUPPORT --=20 2.54.0 From nobody Sat Sep 26 01:54:43 2026 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023098.outbound.protection.outlook.com [52.101.127.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADF8B3672B0; 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charset="utf-8" Add a glue layer driver for the Cadence USBSSP controller integrated in the CIX Sky1 SoC. The driver manages the controller clocks, resets, and the mode strap controls located in the Sky1 S5 system controller. The per-controller RCSU control and status registers live in a shared RCSU region described by the cix,sky1-usbss-rcsu binding and are referenced through the cix,usb-rcsu phandle. The per-controller RCSU registers are accessed through a syscon regmap referenced by the cix,usb-rcsu phandle. The shared RCSU slice of the two controllers is described by a syscon node; each controller references its registers through the cix,usb-rcsu phandle with offsets. Signed-off-by: Hongliang Yang --- drivers/usb/cdns3/Kconfig | 13 + drivers/usb/cdns3/Makefile | 1 + drivers/usb/cdns3/cdnsp-sky1.c | 726 +++++++++++++++++++++++++++++++++ drivers/usb/cdns3/cdnsp-sky1.h | 129 ++++++ 4 files changed, 869 insertions(+) create mode 100644 drivers/usb/cdns3/cdnsp-sky1.c create mode 100644 drivers/usb/cdns3/cdnsp-sky1.h diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig index 39ad23d1ada8..03d8e170a98a 100644 --- a/drivers/usb/cdns3/Kconfig +++ b/drivers/usb/cdns3/Kconfig @@ -77,6 +77,19 @@ config USB_CDNSP_PCI If you choose to build this driver as module it will be dynamically linked and module will be called cdnsp-pci.ko =20 +config USB_CDNSP_SKY1 + tristate "Cadence USB3 support on CIX Sky1 SoC platforms" + depends on USB_CDNS3 + depends on ARCH_CIX || COMPILE_TEST + default USB_CDNS3 + help + Glue driver for the Cadence USB dual-role controllers on CIX Sky1 + (device tree compatible cix,sky1-usb3). It enables clocks and resets + from the SoC, then uses the shared cdns3 platform core (cdns.ko). + + If built as a module, the module is named cdnsp-sky1.ko and must be + loaded after the cdns core module when both are loadable modules. + config USB_CDNS3_TI tristate "Cadence USB3 support on TI platforms" depends on ARCH_K3 || COMPILE_TEST diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile index b2e4ba6a49a3..ab813aaf9940 100644 --- a/drivers/usb/cdns3/Makefile +++ b/drivers/usb/cdns3/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_USB_CDNSP_PCI) +=3D cdnsp-pci.o obj-$(CONFIG_USB_CDNS3_TI) +=3D cdns3-ti.o obj-$(CONFIG_USB_CDNS3_IMX) +=3D cdns3-imx.o obj-$(CONFIG_USB_CDNS3_STARFIVE) +=3D cdns3-starfive.o +obj-$(CONFIG_USB_CDNSP_SKY1) +=3D cdnsp-sky1.o diff --git a/drivers/usb/cdns3/cdnsp-sky1.c b/drivers/usb/cdns3/cdnsp-sky1.c new file mode 100644 index 000000000000..1618b2783a80 --- /dev/null +++ b/drivers/usb/cdns3/cdnsp-sky1.c @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * cdnsp-sky1.c - CIX Sky1 glue for Cadence USBSSP DRD controller + * + * Copyright (C) 2026 CIX Technology Group Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "cdnsp-sky1.h" +#include "core.h" + +static const char *cix_usb_clk_names[CIX_USB_CLK_NUM] =3D { + "sof", + "axi", + "lpm", + "apb", +}; + +struct cdnsp_sky1_strap_signal { + unsigned int offset, bit; +}; + +static const struct cdnsp_sky1_strap_signal strap_signals[SKY1_USB_S5_NUM]= =3D { + /* usb config in s5 domain */ + [U3_TYPEC_DRD_ID] =3D { USB_MODE_STRAP_S5_DOMAIN, U3_TYPEC_DRD_MODE_STRAP= _BIT }, + [U3_TYPEC_HOST0_ID] =3D { USB_MODE_STRAP_S5_DOMAIN, U3_TYPEC_HOST0_MODE_S= TRAP_BIT }, + [U3_TYPEC_HOST1_ID] =3D { USB_MODE_STRAP_S5_DOMAIN, U3_TYPEC_HOST1_MODE_S= TRAP_BIT }, + [U3_TYPEC_HOST2_ID] =3D { USB_MODE_STRAP_S5_DOMAIN, U3_TYPEC_HOST2_MODE_S= TRAP_BIT }, + [U3_TYPEA_CTRL0_ID] =3D { USB_MODE_STRAP_S5_DOMAIN, U3_TYPEA_CTRL0_MODE_S= TRAP_BIT }, + [U3_TYPEA_CTRL1_ID] =3D { USB_MODE_STRAP_S5_DOMAIN, U3_TYPEA_CTRL1_MODE_S= TRAP_BIT}, + [U2_HOST0_ID] =3D { USB_MODE_STRAP_S5_DOMAIN, U2_HOST0_MODE_STRAP_BIT }, + [U2_HOST1_ID] =3D { USB_MODE_STRAP_S5_DOMAIN, U2_HOST1_MODE_STRAP_BIT }, + [U2_HOST2_ID] =3D { USB_MODE_STRAP_S5_DOMAIN, U2_HOST2_MODE_STRAP_BIT }, + [U2_HOST3_ID] =3D { USB_MODE_STRAP_S5_DOMAIN, U2_HOST3_MODE_STRAP_BIT }, +}; + +static int cdnsp_sky1_set_mode_by_id(struct device *dev, int mode) +{ + struct cdnsp_sky1 *data =3D dev_get_drvdata(dev); + + return regmap_update_bits(data->usb_syscon, + strap_signals[data->id].offset, + GENMASK(strap_signals[data->id].bit + 1, + strap_signals[data->id].bit), + mode << strap_signals[data->id].bit); +} + +/** + * cdnsp_sky1_clk_enable_all() - enable all clocks for usb controller + * @dev: Pointer to the device of platform_device + * + */ + +static int cdnsp_sky1_clk_enable_all(struct device *dev) +{ + int i, ret =3D 0; + struct cdnsp_sky1 *data =3D dev_get_drvdata(dev); + struct clk **cix_usb_clks =3D data->cix_usb_clks; + + for (i =3D 0; i < CIX_USB_CLK_NUM; i++) { + cix_usb_clks[i] =3D devm_clk_get(dev, cix_usb_clk_names[i]); + if (IS_ERR(cix_usb_clks[i])) { + ret =3D dev_err_probe(dev, PTR_ERR(cix_usb_clks[i]), + "could not get %s clock\n", + cix_usb_clk_names[i]); + goto err_usb_clks; + } + ret =3D clk_prepare_enable(cix_usb_clks[i]); + if (ret) { + dev_err(dev, "%s enable failed:%d\n", cix_usb_clk_names[i], ret); + goto err_usb_clks; + } + } + dev_dbg(dev, "enable sky1 USB clock done\n"); + return ret; + +err_usb_clks: + while (--i >=3D 0) + clk_disable_unprepare(cix_usb_clks[i]); + return ret; +}; + +/** + * cdnsp_sky1_clk_disable_all() - disable all clocks for usb controller + * @dev: Pointer to the device of platform_device + * + */ + +static void cdnsp_sky1_clk_disable_all(struct device *dev) +{ + int i; + struct cdnsp_sky1 *data =3D dev_get_drvdata(dev); + struct clk **cix_usb_clks =3D data->cix_usb_clks; + + for (i =3D 0; i < CIX_USB_CLK_NUM; i++) + clk_disable_unprepare(cix_usb_clks[i]); +}; + +/** + * cdnsp_sky1_clk_enable_resume() - enable the clocks that are turned + * off while suspend + * @dev: Pointer to the device of platform_device + * + */ + +static int cdnsp_sky1_clk_enable_resume(struct device *dev) +{ + int i, ret; + struct cdnsp_sky1 *data =3D dev_get_drvdata(dev); + struct clk **cix_usb_clks =3D data->cix_usb_clks; + + for (i =3D 0; i < CIX_USB_CLK_OFF_NUM; i++) { + ret =3D clk_prepare_enable(cix_usb_clks[i]); + if (ret) { + dev_err(dev, "failed to enable clock %s: %d\n", + cix_usb_clk_names[i], ret); + goto err_usb_clks; + } + } + return 0; + +err_usb_clks: + while (--i >=3D 0) + clk_disable_unprepare(cix_usb_clks[i]); + return ret; +}; + +/** + * cdnsp_sky1_clk_disable_suspend() - disable the clocks which are not + * needed when suspend + * @dev: Pointer to the device of platform_device + * + */ + +static void cdnsp_sky1_clk_disable_suspend(struct device *dev) +{ + int i; + struct cdnsp_sky1 *data =3D dev_get_drvdata(dev); + struct clk **cix_usb_clks =3D data->cix_usb_clks; + + for (i =3D 0; i < CIX_USB_CLK_OFF_NUM; i++) + clk_disable_unprepare(cix_usb_clks[i]); +}; + +static int sky1_rcsu_handshake(struct cdnsp_sky1 *data, u32 mask, u32 done, + u64 timeout_us) +{ + u32 result; + int ret; + + ret =3D regmap_read_poll_timeout(data->rcsu, data->rcsu_ctst_off, result, + (result & mask) =3D=3D done || + result =3D=3D U32_MAX, + 10, timeout_us); + if (result =3D=3D U32_MAX) /* card removed */ + return -ENODEV; + return ret; +} + +static int cdns_sky1_platform_suspend(struct device *dev, + bool suspend, bool wakeup) +{ + struct cdns *cdns =3D dev_get_drvdata(dev); + struct platform_device *xhci_dev =3D cdns->host_dev; + struct usb_hcd *hcd; + struct device *parent =3D cdns->dev->parent; + struct cdnsp_sky1 *data =3D dev_get_drvdata(parent); + u32 value; + int poll; + int ret =3D 0; + int count =3D 3; + + data->wakeup =3D wakeup; + + if (cdns->role !=3D USB_ROLE_HOST) + return 0; + + if (!xhci_dev) { + dev_dbg(dev, "host controller has not been registered\n"); + return 0; + } + + hcd =3D dev_get_drvdata(&xhci_dev->dev); + if (!hcd) { + dev_dbg(dev, "host controller have not registered\n"); + return 0; + } + + if (suspend) { + while (count--) { + value =3D readl(hcd->regs + XECP_PM_PMCSR); + value &=3D ~PS_MASK; + value |=3D PS_D3 | PS_PME_En; + writel(value, hcd->regs + XECP_PM_PMCSR); + /* After controller enters D3, disable AXI and SOF + * until AXI valid flag changes to 0. + */ + if (sky1_rcsu_handshake(data, AXI_CLOCK_VALID, 0, + 100ULL * 1000)) { + u32 ctst; + + regmap_read(data->rcsu, data->rcsu_ctst_off, &ctst); + dev_dbg(dev, "enter D3 failed, register value:%x\n", + ctst); + } else { + break; + } + } + if (count < 0) { + u32 ctst; + + regmap_read(data->rcsu, data->rcsu_ctst_off, &ctst); + dev_err(dev, "enter D3 failed after retries, register value:%x\n", + ctst); + } + } else { + while (count--) { + value =3D readl(hcd->regs + XECP_PM_PMCSR); + value &=3D ~PS_MASK; + value |=3D PS_D0; + value &=3D ~PS_PME_En; + writel(value, hcd->regs + XECP_PM_PMCSR); + /* Wait power state back to D0 */ + poll =3D readl_poll_timeout(hcd->regs + XECP_PM_PMCSR, + value, + (value & PS_MASK) =3D=3D 0 || + value =3D=3D U32_MAX, + 10, 100ULL * 1000); + if (poll) { + dev_dbg(dev, "exit D3 timeout, power state=3D0x%lx\n", + value & PS_MASK); + } else { + break; + } + } + if (count < 0) { + dev_err(dev, "exit D3 timeout after retries, power state=3D0x%lx\n", + value & PS_MASK); + } + } + + return ret; +} + +static void cdnsp_sky1_configure_controller(struct cdnsp_sky1 *data) +{ + int clk; + int v0, v1, v2; + u32 val =3D 0; + + if (data->u3_disable) { + dev_dbg(data->dev, "disable u3 port\n"); + writel(D_XEC_CFG_3XPORT_MODE_VALUE, data->device_base + + D_XEC_CFG_3XPORT_MODE); + } + writel(AXI_HALT, data->device_base + D_XEC_AXI_CAP); + writel(AXI_HALT, data->xhci_base + D_XEC_AXI_CAP); + writel(data->axi_bmax_value, data->device_base + D_XEC_AXI_CTRL0); + writel(data->axi_bmax_value, data->xhci_base + D_XEC_AXI_CTRL0); + writel((~(u32)(AXI_HALT)), data->device_base + D_XEC_AXI_CAP); + writel((~(u32)(AXI_HALT)), data->xhci_base + D_XEC_AXI_CAP); + clk =3D data->sof_clk_freq; + v0 =3D 25 * clk / 100000000; + v1 =3D clk / 10000; + v2 =3D clk / 10; + writel(((v0 > 1) ? v0 - 1 : 1), data->device_base + + D_XEC_PRE_REG_250NS); + writel((unsigned int)((v1 / 100 > 1) > 0 ? (v1 / 100) - 1 : 1), + data->device_base + D_XEC_PRE_REG_1US); + writel((unsigned int)((v1 / 10 > 1) > 0 ? (v1 / 10) - 1 : 1), + data->device_base + D_XEC_PRE_REG_10US); + writel(((v1) > 1 ? v1 - 1 : 1), data->device_base + + D_XEC_PRE_REG_100US); + writel((unsigned int)((125 * clk / 1000000) > 1 ? (125 * clk / 1000000) := 1), + data->device_base + D_XEC_PRE_REG_125US); + writel(((v2 / 100 > 1) ? (v2 / 100) - 1 : 1), data->device_base + + D_XEC_PRE_REG_1MS); + writel(((v2 / 10 > 1) ? (v2 / 10) - 1 : 1), data->device_base + + D_XEC_PRE_REG_10MS); + writel((v2 > 1 ? v2 - 1 : 1), data->device_base + + D_XEC_PRE_REG_100MS); + dev_dbg(data->dev, "readl:%x, %x ,%x, %x, %x, %x, %x, %x\n", + readl(data->device_base + D_XEC_PRE_REG_250NS), + readl(data->device_base + D_XEC_PRE_REG_1US), + readl(data->device_base + D_XEC_PRE_REG_10US), + readl(data->device_base + D_XEC_PRE_REG_100US), + readl(data->device_base + D_XEC_PRE_REG_125US), + readl(data->device_base + D_XEC_PRE_REG_1MS), + readl(data->device_base + D_XEC_PRE_REG_10MS), + readl(data->device_base + D_XEC_PRE_REG_100MS)); + clk =3D data->lpm_clk_freq; + v0 =3D 25 * clk / 100000000; + v1 =3D clk / 10000; + v2 =3D clk / 10; + writel(((v0 > 1) ? v0 - 1 : 1), data->device_base + + D_XEC_LPM_PRE_REG_250NS); + writel((unsigned int)((v1 / 100 > 1) > 0 ? (v1 / 100) - 1 : 1), data->dev= ice_base + + D_XEC_LPM_PRE_REG_1US); + writel((unsigned int)((v1 / 10 > 1) > 0 ? (v1 / 10) - 1 : 1), data->devic= e_base + + D_XEC_LPM_PRE_REG_10US); + writel(((v1) > 1 ? v1 - 1 : 1), data->device_base + + D_XEC_LPM_PRE_REG_100US); + writel((unsigned int)((125 * clk / 1000000) > 1 ? (125 * clk / 1000000) := 1), + data->device_base + D_XEC_LPM_PRE_REG_125US); + writel(((v2 / 100 > 1) ? (v2 / 100) - 1 : 1), data->device_base + + D_XEC_LPM_PRE_REG_1MS); + writel(((v2 / 10 > 1) ? (v2 / 10) - 1 : 1), data->device_base + + D_XEC_LPM_PRE_REG_10MS); + writel((v2 > 1 ? v2 - 1 : 1), data->device_base + + D_XEC_LPM_PRE_REG_100MS); + v0 =3D readl(data->xhci_base + XEC_USBSSP_CHICKEN_BITS_3); + v0 &=3D ~(CFG_APB_TIMEOUT_PSLVERR_EN | CFG_APB_PSLVERR_EN); + writel(v0, data->xhci_base + XEC_USBSSP_CHICKEN_BITS_3); + if (data->u3_disable) { + dev_dbg(data->dev, "disable u3 port\n"); + writel(XEC_CFG_3XPORT_MODE_VALUE, data->xhci_base + + XEC_CFG_3XPORT_MODE); + } else if (data->ssp_disable) { + dev_dbg(data->dev, "disable ssp\n"); + v0 =3D readl(data->xhci_base + XEC_CFG_3XPORT_MODE); + writel(v0 & CFG_3XPORT_MODE_DIS_SSP, data->xhci_base + + XEC_CFG_3XPORT_MODE); + } + clk =3D data->sof_clk_freq; + v0 =3D 25 * clk / 100000000; + v1 =3D clk / 10000; + v2 =3D clk / 10; + writel(((v0 > 1) ? v0 - 1 : 0), data->xhci_base + + XEC_PRE_REG_250NS); + writel((unsigned int)((v1 / 100 > 1) > 0 ? (v1 / 100) - 1 : 0), data->xhc= i_base + + XEC_PRE_REG_1US); + writel((unsigned int)((v1 / 10 > 1) > 0 ? (v1 / 10) - 1 : 0), data->xhci_= base + + XEC_PRE_REG_10US); + writel(((v1) > 1 ? v1 - 1 : 0), data->xhci_base + + XEC_PRE_REG_100US); + writel((unsigned int)((125 * clk / 1000000) > 1 ? (125 * clk / 1000000) := 0), + data->xhci_base + XEC_PRE_REG_125US); + writel(((v2 / 100 > 1) ? (v2 / 100) - 1 : 0), data->xhci_base + + XEC_PRE_REG_1MS); + writel(((v2 / 10 > 1) ? (v2 / 10) - 1 : 0), data->xhci_base + + XEC_PRE_REG_10MS); + writel((v2 > 1 ? v2 - 1 : 0), data->xhci_base + + XEC_PRE_REG_100MS); + clk =3D data->lpm_clk_freq; + v0 =3D 25 * clk / 100000000; + v1 =3D clk / 10000; + v2 =3D clk / 10; + writel(((v0 > 1) ? v0 - 1 : 0), data->xhci_base + + XEC_LPM_PRE_REG_250NS); + writel((unsigned int)((v1 / 100 > 1) > 0 ? (v1 / 100) - 1 : 0), data->xhc= i_base + + XEC_LPM_PRE_REG_1US); + writel((unsigned int)((v1 / 10 > 1) > 0 ? (v1 / 10) - 1 : 0), data->xhci_= base + + XEC_LPM_PRE_REG_10US); + writel(((v1) > 1 ? v1 - 1 : 0), data->xhci_base + + XEC_LPM_PRE_REG_100US); + writel((unsigned int)((125 * clk / 1000000) > 1 ? (125 * clk / 1000000) := 0), + data->xhci_base + XEC_LPM_PRE_REG_125US); + writel(((v2 / 100 > 1) ? (v2 / 100) - 1 : 0), data->xhci_base + + XEC_LPM_PRE_REG_1MS); + writel(((v2 / 10 > 1) ? (v2 / 10) - 1 : 0), data->xhci_base + + XEC_LPM_PRE_REG_10MS); + writel((v2 > 1 ? v2 - 1 : 0), data->xhci_base + + XEC_LPM_PRE_REG_100MS); + val =3D readl(data->xhci_base + XEC_USBSSP_CLK_GATING_CTRL); + val |=3D HOST20_ACLK_GATING_DISABLE | HOST20_UTMI_GATING_DISABLE; + writel(val, data->xhci_base + XEC_USBSSP_CLK_GATING_CTRL); +} + +static int cdnsp_sky1_drd_init(struct cdnsp_sky1 *data) +{ + int ret =3D 0; + + reset_control_assert(data->reset); + reset_control_assert(data->preset); + cdnsp_sky1_clk_disable_all(data->dev); + ret =3D cdnsp_sky1_clk_enable_all(data->dev); + if (ret) + return ret; + regmap_write(data->rcsu, data->rcsu_axi_off, CIX_USB_AXI_WR_CACHE_VALUE); + cdnsp_sky1_set_mode_by_id(data->dev, MODE_STRAP_OTG); + reset_control_deassert(data->preset); + cdnsp_sky1_configure_controller(data); + reset_control_deassert(data->reset); + return ret; +} + +static void __iomem *sky1_of_get_addr_by_name(struct device_node *parent, = const char *name) +{ + void __iomem *addr =3D NULL; + struct device_node *node; + int index; + + for_each_child_of_node(parent, node) { + index =3D of_property_match_string(node, "reg-names", name); + if (index >=3D 0) { + addr =3D of_iomap(node, index); + of_node_put(node); + break; + } + } + + return addr; +} + +static void __iomem *sky1_get_addr_by_name(struct device *dev, const char = *name) +{ + return sky1_of_get_addr_by_name(dev->of_node, name); +} + +static void sky1_put_addr(void __iomem *regs) +{ + if (regs) + iounmap(regs); +} + +static int cdnsp_sky1_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->of_node; + struct of_dev_auxdata cdns_sky1_auxdata[] =3D { + { .compatible =3D "cdns,usb3", }, + {}, + }; + struct cdnsp_sky1 *data; + struct cdns3_platform_data *cdns_sky1_pdata; + struct of_phandle_args rcsu_args; + int ret =3D 0; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + ret =3D of_parse_phandle_with_fixed_args(node, "cix,usb-rcsu", 2, 0, + &rcsu_args); + if (ret) { + dev_err(dev, "failed to parse cix,usb-rcsu: %d\n", ret); + return ret; + } + data->rcsu =3D syscon_regmap_lookup_by_phandle(node, "cix,usb-rcsu"); + if (IS_ERR(data->rcsu)) { + ret =3D PTR_ERR(data->rcsu); + dev_err(dev, "Unable to get cix,usb-rcsu regmap"); + return ret; + } + data->rcsu_axi_off =3D rcsu_args.args[0]; + data->rcsu_ctst_off =3D rcsu_args.args[1]; + data->reset =3D devm_reset_control_get_exclusive(&pdev->dev, "core"); + if (IS_ERR(data->reset)) { + ret =3D PTR_ERR(data->reset); + dev_err(dev, "get reset error:%d\n", ret); + return ret; + } + data->preset =3D devm_reset_control_get_exclusive(&pdev->dev, "apb"); + if (IS_ERR(data->preset)) { + ret =3D PTR_ERR(data->preset); + dev_err(dev, "get reset error:%d\n", ret); + return ret; + } + platform_set_drvdata(pdev, data); + data->dev =3D dev; + ret =3D of_alias_get_id(dev->of_node, "usb"); + if (ret =3D=3D -ENODEV) { + if (device_property_read_u32(dev, "id", &ret)) + ret =3D -ENODEV; + } + if (ret < 0 || ret >=3D SKY1_USB_S5_NUM) { + dev_err(dev, "get alias failed.\n"); + return ret; + } + data->id =3D ret; + data->usb_syscon =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "cix,usb-syscon"); + if (IS_ERR(data->usb_syscon)) { + dev_err(dev, "Unable to get cix,usb-syscon regmap"); + return PTR_ERR(data->usb_syscon); + } + data->u3_disable =3D device_property_read_bool(dev, "u3-port-disable"); + data->ssp_disable =3D device_property_read_bool(dev, "ssp-disable"); + data->sof_clk_freq =3D CIX_USB_CLK_8M; + data->lpm_clk_freq =3D CIX_USB_CLK_32K; + data->axi_bmax_value =3D AXI_BMAX_VALUE_DEFAULT; + data->xhci_base =3D sky1_get_addr_by_name(dev, "xhci"); + if (!data->xhci_base) { + ret =3D -ENODEV; + goto err_put_xhci; + } + data->device_base =3D sky1_get_addr_by_name(dev, "dev"); + if (!data->device_base) { + ret =3D -ENODEV; + goto err_put_addrs; + } + ret =3D cdnsp_sky1_drd_init(data); + if (ret =3D=3D -ETIMEDOUT) + ret =3D -EPROBE_DEFER; + if (ret) { + /* + * drd_init() leaves the clocks disabled and the resets + * asserted on failure; only the address mappings are + * left to release. + */ + goto err_put_addrs; + } + data->oc_gpio =3D devm_gpiod_get_optional(data->dev, "oc", GPIOD_IN); + if (IS_ERR(data->oc_gpio)) { + dev_err(data->dev, "can not get oc_gpio\n"); + ret =3D PTR_ERR(data->oc_gpio); + goto err_quiesce; + } + if (data->oc_gpio) { + ret =3D gpiod_direction_input(data->oc_gpio); + if (ret < 0) + dev_err(data->dev, "set oc_gpio input failed:%d\n", ret); + } + /* + * The platform data is devm-allocated, so it stays alive as long as + * this device; the child devices are depopulated before it is freed. + */ + cdns_sky1_pdata =3D devm_kzalloc(dev, sizeof(*cdns_sky1_pdata), GFP_KERNE= L); + if (!cdns_sky1_pdata) { + ret =3D -ENOMEM; + goto err_quiesce; + } + cdns_sky1_pdata->platform_suspend =3D cdns_sky1_platform_suspend; + cdns_sky1_pdata->quirks =3D CDNS3_DEFAULT_PM_RUNTIME_ALLOW; + cdns_sky1_auxdata[0].platform_data =3D cdns_sky1_pdata; + ret =3D of_platform_populate(node, NULL, cdns_sky1_auxdata, dev); + if (ret) { + dev_err(dev, "failed to create children: %d\n", ret); + goto err_quiesce; + } + device_set_wakeup_capable(dev, true); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + return 0; + +err_quiesce: + reset_control_assert(data->reset); + reset_control_assert(data->preset); + cdnsp_sky1_clk_disable_all(dev); +err_put_addrs: + sky1_put_addr(data->device_base); +err_put_xhci: + sky1_put_addr(data->xhci_base); + return ret; +} + +static void cdnsp_sky1_remove(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cdnsp_sky1 *data =3D dev_get_drvdata(dev); + + pm_runtime_get_sync(dev); + of_platform_depopulate(dev); + sky1_put_addr(data->xhci_base); + sky1_put_addr(data->device_base); + reset_control_assert(data->reset); + reset_control_assert(data->preset); + cdnsp_sky1_clk_disable_all(dev); + pm_runtime_disable(dev); + pm_runtime_set_suspended(dev); + pm_runtime_put_noidle(dev); +} + +/* + * Because the wake-up interrupt and host interrupt are the same interrupt, + * closing the axi and sof clock will result in the inability to generate + * port status change interrupt. + */ +static int cdnsp_sky1_system_suspend(struct device *dev) +{ + struct cdnsp_sky1 *data =3D dev_get_drvdata(dev); + + if (!data->wakeup) { + reset_control_assert(data->reset); + reset_control_assert(data->preset); + } + cdnsp_sky1_clk_disable_suspend(dev); + return 0; +} + +static int cdnsp_sky1_system_resume(struct device *dev) +{ + int ret =3D 0; + struct cdnsp_sky1 *data =3D dev_get_drvdata(dev); + + ret =3D cdnsp_sky1_clk_enable_resume(dev); + if (ret) + return ret; + if (!data->wakeup) { + regmap_write(data->rcsu, data->rcsu_axi_off, + CIX_USB_AXI_WR_CACHE_VALUE); + cdnsp_sky1_set_mode_by_id(data->dev, MODE_STRAP_OTG); + reset_control_deassert(data->preset); + cdnsp_sky1_configure_controller(data); + reset_control_deassert(data->reset); + } + return 0; +} + +static const struct dev_pm_ops cdnsp_sky1_pm_ops =3D { + SYSTEM_SLEEP_PM_OPS(cdnsp_sky1_system_suspend, cdnsp_sky1_system_resume) +}; + +static const struct of_device_id cdns_sky1_of_match[] =3D { + { .compatible =3D "cix,sky1-usbssp", }, + {}, +}; +MODULE_DEVICE_TABLE(of, cdns_sky1_of_match); + +static int cdnsp_sky1_find_cdns_dev(struct device *dev, void *data) +{ + struct device **cdns_dev =3D data; + + if (dev->of_node && of_device_is_compatible(dev->of_node, "cdns,usb3")) { + /* keep a reference: the pointer is used after the iteration */ + *cdns_dev =3D get_device(dev); + return 1; + } + return 0; +} + +static int cdnsp_sky1_find_gadget_match(struct device *dev, void *data) +{ + struct device **gadget_dev =3D data; + const char *name =3D dev_name(dev); + static const char gadget_prefix[] =3D "gadget."; + + /* + * The gadget device is registered on the gadget bus with name + * "gadget.%d" (see usb_add_gadget_udc -> dev_set_name). + * It sits on the gadget bus and has the function driver bound to it. + * Verify the device is on the gadget bus by checking the bus name. + * This prevents matching devices that happen to have "gadget." prefix + * in their name but are not real gadget devices, and also avoids + * NULL pointer dereference when device bus is being removed. + */ + if (name && dev->bus && !strcmp(dev->bus->name, "gadget") && + !strncmp(name, gadget_prefix, sizeof(gadget_prefix) - 1)) { + /* keep a reference: the pointer is used after the iteration */ + *gadget_dev =3D get_device(dev); + return 1; + } + return 0; +} + +static void cdnsp_sky1_shutdown(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cdnsp_sky1 *data =3D dev_get_drvdata(dev); + struct device *cdns_dev =3D NULL; + struct device *gadget_dev =3D NULL; + struct cdns *cdns =3D NULL; + + if (!device_may_wakeup(dev)) { + /* + * Find the cdns3 child device, then find its gadget device + * and release the function driver before disabling clocks. + * This ensures all register accesses in gadget_unbind_driver + * complete before clocks are turned off. + */ + device_for_each_child(dev, &cdns_dev, cdnsp_sky1_find_cdns_dev); + if (cdns_dev) + cdns =3D dev_get_drvdata(cdns_dev); + if (cdns) + device_for_each_child(cdns_dev, &gadget_dev, + cdnsp_sky1_find_gadget_match); + if (gadget_dev) + device_release_driver(gadget_dev); + if (cdns && cdns->host_dev) { + struct usb_hcd *hcd =3D platform_get_drvdata(cdns->host_dev); + + if (hcd && hcd->irq > 0) { + /* + * Clear HCD_FLAG_HW_ACCESSIBLE before disable_irq. + * This prevents usb_hcd_irq from calling xhci_irq + * (which reads USBSTS) after clocks are disabled. + */ + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + disable_irq(hcd->irq); + synchronize_irq(hcd->irq); + } + } + reset_control_assert(data->reset); + reset_control_assert(data->preset); + cdnsp_sky1_clk_disable_all(dev); + put_device(gadget_dev); + put_device(cdns_dev); + } +} + +static struct platform_driver cdnsp_sky1_driver =3D { + .probe =3D cdnsp_sky1_probe, + .remove =3D cdnsp_sky1_remove, + .shutdown =3D cdnsp_sky1_shutdown, + .driver =3D { + .name =3D "cdnsp-sky1", + .of_match_table =3D cdns_sky1_of_match, + .pm =3D pm_sleep_ptr(&cdnsp_sky1_pm_ops), + }, +}; + +module_platform_driver(cdnsp_sky1_driver); + +MODULE_ALIAS("platform:cdnsp-sky1"); +MODULE_DESCRIPTION("CIX Sky1 Cadence USBSSP DRD glue driver"); +MODULE_AUTHOR("Hongliang Yang "); +MODULE_LICENSE("GPL"); diff --git a/drivers/usb/cdns3/cdnsp-sky1.h b/drivers/usb/cdns3/cdnsp-sky1.h new file mode 100644 index 000000000000..2405d01dd5a4 --- /dev/null +++ b/drivers/usb/cdns3/cdnsp-sky1.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _CDNSP_SKY1_H +#define _CDNSP_SKY1_H +#include +#include +#include +#include + +#define USB_MODE_STRAP_S5_DOMAIN 0x424 + +#define MODE_STRAP_OTG 0 + +#define U3_TYPEC_DRD_ID 0 +#define U3_TYPEC_HOST0_ID 1 +#define U3_TYPEC_HOST1_ID 2 +#define U3_TYPEC_HOST2_ID 3 +#define U3_TYPEA_CTRL0_ID 4 +#define U3_TYPEA_CTRL1_ID 5 +#define U2_HOST0_ID 6 +#define U2_HOST1_ID 7 +#define U2_HOST2_ID 8 +#define U2_HOST3_ID 9 +#define SKY1_USB_S5_NUM 10 + +#define U3_TYPEC_DRD_MODE_STRAP_BIT 12 +#define U3_TYPEC_HOST0_MODE_STRAP_BIT 14 +#define U3_TYPEC_HOST1_MODE_STRAP_BIT 16 +#define U3_TYPEC_HOST2_MODE_STRAP_BIT 18 +#define U3_TYPEA_CTRL0_MODE_STRAP_BIT 8 +#define U3_TYPEA_CTRL1_MODE_STRAP_BIT 10 +#define U2_HOST0_MODE_STRAP_BIT 0 +#define U2_HOST1_MODE_STRAP_BIT 2 +#define U2_HOST2_MODE_STRAP_BIT 4 +#define U2_HOST3_MODE_STRAP_BIT 6 + +#define AXI_HALT BIT(31) +#define AXI_BMAX_VALUE_DEFAULT 0x7 + +#define D_XEC_CFG_3XPORT_MODE 0x2040 +#define D_XEC_AXI_CAP 0x2174 +#define D_XEC_AXI_CTRL0 0x217C +#define D_XEC_PRE_REG_250NS 0x21E8 +#define D_XEC_PRE_REG_1US 0x21EC +#define D_XEC_PRE_REG_10US 0x21F0 +#define D_XEC_PRE_REG_100US 0x21F4 +#define D_XEC_PRE_REG_125US 0x21F8 +#define D_XEC_PRE_REG_1MS 0x21FC +#define D_XEC_PRE_REG_10MS 0x2200 +#define D_XEC_PRE_REG_100MS 0x2204 +#define D_XEC_LPM_PRE_REG_250NS 0x2208 +#define D_XEC_LPM_PRE_REG_1US 0x220C +#define D_XEC_LPM_PRE_REG_10US 0x2210 +#define D_XEC_LPM_PRE_REG_100US 0x2214 +#define D_XEC_LPM_PRE_REG_125US 0x2218 +#define D_XEC_LPM_PRE_REG_1MS 0x221C +#define D_XEC_LPM_PRE_REG_10MS 0x2220 +#define D_XEC_LPM_PRE_REG_100MS 0x2224 + +#define XEC_CFG_3XPORT_MODE 0x2040 +#define XEC_PRE_REG_250NS 0x21E8 +#define XEC_PRE_REG_1US 0x21EC +#define XEC_PRE_REG_10US 0x21F0 +#define XEC_PRE_REG_100US 0x21F4 +#define XEC_PRE_REG_125US 0x21F8 +#define XEC_PRE_REG_1MS 0x21FC +#define XEC_PRE_REG_10MS 0x2200 +#define XEC_PRE_REG_100MS 0x2204 +#define XEC_LPM_PRE_REG_250NS 0x2208 +#define XEC_LPM_PRE_REG_1US 0x220C +#define XEC_LPM_PRE_REG_10US 0x2210 +#define XEC_LPM_PRE_REG_100US 0x2214 +#define XEC_LPM_PRE_REG_125US 0x2218 +#define XEC_LPM_PRE_REG_1MS 0x221C +#define XEC_LPM_PRE_REG_10MS 0x2220 +#define XEC_LPM_PRE_REG_100MS 0x2224 +#define XEC_USBSSP_CHICKEN_BITS_3 0x2230 +#define XEC_USBSSP_CLK_GATING_CTRL 0x2234 +#define XECP_PM_PMCSR 0x2240 + +/* XEC_USBSSP_CLK_GATING_CTRL */ +#define HOST20_ACLK_GATING_DISABLE BIT(4) +#define HOST20_UTMI_GATING_DISABLE BIT(5) + +/* XECP_PM_PMCSR */ +#define PS_MASK GENMASK(1, 0) +#define PS_D0 0 +#define PS_D3 3 +#define PS_PME_En BIT(8) + +#define D_XEC_CFG_3XPORT_MODE_VALUE 0xa0031e07 +#define XEC_CFG_3XPORT_MODE_VALUE 0xa0031e07 +#define CFG_3XPORT_MODE_DIS_SSP (~BIT(31)) + +#define CFG_APB_TIMEOUT_PSLVERR_EN BIT(22) +#define CFG_APB_PSLVERR_EN BIT(23) + +#define CIX_USB_CLK_NUM (4) +#define CIX_USB_CLK_OFF_NUM (2) +#define CIX_USB_AXI_WR_CACHE_VALUE 0x33 +#define CIX_USB_CLK_32K 32000 +#define CIX_USB_CLK_8M 8000000 + +#define AXI_CLOCK_VALID BIT(1) + +struct cdnsp_sky1 { + struct device *dev; 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charset="utf-8" Add USB4 and USB5 controller nodes for the CIX Sky1 SoC. Enable USB4 and USB5 in host mode on the Radxa Orion O6 board. The per-controller RCSU registers are accessed through a syscon regmap referenced by the cix,usb-rcsu phandle. The shared RCSU slice of the two controllers is described by a syscon node; each controller references its registers through the cix,usb-rcsu phandle with offsets. Signed-off-by: Hongliang Yang --- arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 42 +++++++++++ arch/arm64/boot/dts/cix/sky1.dtsi | 88 +++++++++++++++++++++++ 2 files changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dt= s/cix/sky1-orion-o6.dts index b152942aaa60..4f47e8cd70fc 100644 --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -80,6 +80,22 @@ pins { =20 }; }; + + pinctrl_usb4: usb4-power-on-cfg { + pins { + bias-pull-down; + drive-strength =3D <8>; + pinmux =3D ; + }; + }; + + pinctrl_usb5: usb5-power-on-cfg { + pins { + bias-pull-down; + drive-strength =3D <8>; + pinmux =3D ; + }; + }; }; =20 &pcie_x8_rc { @@ -118,6 +134,32 @@ &uart2 { status =3D "okay"; }; =20 +&usb4 { + pinctrl-0 =3D <&pinctrl_usb4>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&usbss_4 { + dr_mode =3D "host"; + + status =3D "okay"; +}; + +&usb5 { + pinctrl-0 =3D <&pinctrl_usb5>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&usbss_5 { + dr_mode =3D "host"; + + status =3D "okay"; +}; + &usb3_phy4 { status =3D "okay"; =20 diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 478c726fae96..2fe9e8244447 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -15,6 +15,11 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + usb4 =3D &usb4; + usb5 =3D &usb5; + }; + cpus { #address-cells =3D <2>; #size-cells =3D <0>; @@ -576,6 +581,89 @@ mbox_ap2sfh: mailbox@80a0000 { cix,mbox-dir =3D "tx"; }; =20 + usbss_rcsu45: syscon@91c0300 { + compatible =3D "cix,sky1-usbss-rcsu", "syscon"; + reg =3D <0x00 0x091c0300 0x00 0x200>; + }; + + usb4: usb-4 { + compatible =3D "cix,sky1-usbssp"; + ranges; + #address-cells =3D <2>; + clocks =3D <&scmi_clk CLK_TREE_USB3A_H0_CLK_SOF>, + <&scmi_clk CLK_TREE_USB3A_0_AXI_GATE>, + <&scmi_clk CLK_TREE_USB3A_H0_CLK_LPM>, + <&scmi_clk CLK_TREE_USB3A_0_APB_GATE>; + clock-names =3D "sof", "axi", "lpm", "apb"; + resets =3D <&s5_syscon SKY1_USBC_SS2_PRST_N>, + <&s5_syscon SKY1_USBC_SS2_RST_N>; + reset-names =3D "apb", "core"; + #size-cells =3D <2>; + cix,usb-rcsu =3D <&usbss_rcsu45 0x14 0x100>; + cix,usb-syscon =3D <&s5_syscon>; + + status =3D "disabled"; + + usbss_4: usb@91d0000 { + compatible =3D "cdns,usb3"; + reg =3D <0x00 0x91d0000 0x00 0x4000>, + <0x00 0x91d8000 0x00 0x8000>, + <0x00 0x91d4000 0x00 0x4000>; + reg-names =3D "otg", "xhci", "dev"; + dr_mode =3D "otg"; + interrupts =3D , + , + , + ; + interrupt-names =3D "host", "peripheral", + "otg", "wakeup"; + maximum-speed =3D "super-speed-plus"; + phys =3D <&usb3_phy4_0>; + phy-names =3D "cdns3,usb3-phy"; + + status =3D "disabled"; + }; + }; + + usb5: usb-5 { + compatible =3D "cix,sky1-usbssp"; + ranges; + #address-cells =3D <2>; + clocks =3D <&scmi_clk CLK_TREE_USB3A_H1_CLK_SOF>, + <&scmi_clk CLK_TREE_USB3A_1_AXI_GATE>, + <&scmi_clk CLK_TREE_USB3A_H1_CLK_LPM>, + <&scmi_clk CLK_TREE_USB3A_1_APB_GATE>; + clock-names =3D "sof", "axi", "lpm", "apb"; + resets =3D <&s5_syscon SKY1_USBC_SS3_PRST_N>, + <&s5_syscon SKY1_USBC_SS3_RST_N>; + reset-names =3D "apb", "core"; + #size-cells =3D <2>; + cix,usb-rcsu =3D <&usbss_rcsu45 0x24 0x110>; + cix,usb-syscon =3D <&s5_syscon>; + + status =3D "disabled"; + + usbss_5: usb@91e0000 { + compatible =3D "cdns,usb3"; + reg =3D <0x00 0x91e0000 0x00 0x4000>, + <0x00 0x91e8000 0x00 0x8000>, + <0x00 0x91e4000 0x00 0x4000>; + reg-names =3D "otg", "xhci", "dev"; + dr_mode =3D "otg"; + interrupts =3D , + , + , + ; + interrupt-names =3D "host", "peripheral", + "otg", "wakeup"; + maximum-speed =3D "super-speed-plus"; + phys =3D <&usb3_phy4_1>; + phy-names =3D "cdns3,usb3-phy"; + + status =3D "disabled"; + }; + }; + usb3_phy4: usb-phy@9210000 { compatible =3D "cix,sky1-usb3-phy"; reg =3D <0x00 0x09210000 0x00 0x40000>; --=20 2.54.0