From nobody Sat Sep 26 03:14:43 2026 Received: from sender5-op-o12.zoho.com (sender5-op-o12.zoho.com [165.173.182.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 299E72116F4; Sun, 6 Sep 2026 07:07:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.182.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788678454; cv=pass; b=qpLa63eBmrrts+rPpaf/w8XA1xYuzhKgKyrFTl9cYHpLmIQqRx6q8zWJTYI9q+ptEZYEbsM2hZvuvvJcs7Fy64YlrhfQ0RloWboTmxiu6+nt7zvCjCsn2w5F3xgEIUcwK6eLtao37pbYc9bytCMynQQKRP9t/lyWHVXO73DL3yA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788678454; c=relaxed/simple; bh=3rliFb59kMUShQX5C/SuuQHnHhhNnJ/BJJbg/03BpRA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jKd/fjvwxMMjs60S6Bwe5/H6xVfn3tBYsDsIJ6B58FQQYuHeaLgEwQJ1hvm6w3jIpK5PCkkvRfPpmhgJLz9FBpSAj0Nu782ZC0urvo5YVsIN3rgfD9vIEpJ6Js5NqMG4pWvV0k55QNPv4Po/hrc90ey1jQInClglR3iilqN+Znc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=e4GZpIUN; arc=pass smtp.client-ip=165.173.182.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="e4GZpIUN" ARC-Seal: i=1; a=rsa-sha256; t=1788678435; cv=none; d=zohomail.com; s=zohoarc; b=XzkrWwNXhmHhgXTfmUzzt15a2E9fsLY2rFdEk14IYJI1gEKvNJPkVtIsizH0TwtE9qWQReSsZ+8nBbaS7oMCbPyEio6q+4Pi7lmDNH0NXMivtEX3kwAvwL9JnSj41zCnoWJcuJhFqC8uEChVzHA7kuReaC3XOIQKtOSBB6PfPOg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788678435; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=5kwa35a71ZPo+sybP/X3LF88saD0zkIeKsdxVVsoYRc=; b=Jz1o7dVcwzHVVyFhgrRFd4dl7kHH0eUMXpa8gjr/V7dBUEF2J8J3UkG4Xm48mmTn5s9Fnf0lDW94qtkmfXJJXj5n6Fdg4M8AH4poDJLTIjVVc8CEH5z57XZ0zQyTYLTUYPMn679PnbJTC+ByiGu5XDHv8HQdYJnazae9xArOU0c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1788678435; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=5kwa35a71ZPo+sybP/X3LF88saD0zkIeKsdxVVsoYRc=; b=e4GZpIUNO+9/o7O7Sj/ffZDp183c2wndBjiT1qSC+s71d1S+UViWzJrtcMnzheJ2 KYiyA6eptpPPqoAV59FSz0+d9ZaXMwuEwpdz9kbmnwgHQp50dip2qwzwLuOhEz63hyJ hjvVI8z9MZ8cxnb5+Q+3paaTe3togU8ClJ7ot/40= Received: by mx.zohomail.com with SMTPS id 1788678433543920.0568449569804; Sun, 6 Sep 2026 00:07:13 -0700 (PDT) From: Junhui Liu Date: Sun, 06 Sep 2026 15:06:38 +0800 Subject: [PATCH 1/4] clk: sunxi-ng: div: Add feature support to M clock macro Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-sunxi-clk-no-p-v1-1-cbde21c9fe69@pigmoral.tech> References: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> In-Reply-To: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Junhui Liu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1897; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=3rliFb59kMUShQX5C/SuuQHnHhhNnJ/BJJbg/03BpRA=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLLmCnLcyTm2+cFksZqfO+8eV1sztzjZM3mL6nKz60c1a xOSdkz27ShlYRDjYpAVU2Th8hf/Z63D8+2IQOt9mDmsTCBDGLg4BWAi1RUMf+UNLhh8YtTMeXhp 8er8/4xZeiv/hYcJ276cubDtb/nuBG2Gf8pBl3J5DiTlq2anXV4RynN4H5dTvGf3BKFlukc8L+T e4AEA X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External Add a variant of SUNXI_CCU_M_DATA_WITH_MUX_GATE() that accepts CCU feature flags, such as CCU_FEATURE_UPDATE_BIT. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu_div.h | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h index a30a92780a05..6d3541a3b519 100644 --- a/drivers/clk/sunxi-ng/ccu_div.h +++ b/drivers/clk/sunxi-ng/ccu_div.h @@ -212,16 +212,17 @@ struct ccu_div { SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ _mshift, _mwidth, 0, _flags) =20 -#define SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ - _mshift, _mwidth, \ - _muxshift, _muxwidth, \ - _gate, _flags) \ +#define SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, _reg= , \ + _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags, _features) \ struct ccu_div _struct =3D { \ .enable =3D _gate, \ .div =3D _SUNXI_CCU_DIV(_mshift, _mwidth), \ .mux =3D _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ .common =3D { \ .reg =3D _reg, \ + .features =3D _features, \ .hw.init =3D CLK_HW_INIT_PARENTS_DATA(_name, \ _parents, \ &ccu_div_ops, \ @@ -229,6 +230,15 @@ struct ccu_div { }, \ } =20 +#define SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) \ + SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags, 0) + #define SUNXI_CCU_M_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ _mshift, _mwidth, \ _muxshift, _muxwidth, \ --=20 2.55.0 From nobody Sat Sep 26 03:14:43 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D123F39E9CB; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-sunxi-clk-no-p-v1-2-cbde21c9fe69@pigmoral.tech> References: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> In-Reply-To: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Junhui Liu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3217; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=sx6BJ1JsCbiIy8jm4gR7Z3AI1Jw4H0UuT/5mJyKCVds=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLLmCnL/FcvceERrrnjPiqn+Kx85S18/1bgokbf53hLfP Z55dUtlOkpZGMS4GGTFFFm4/MX/WevwfDsi0HofZg4rE8gQBi5OAZjIKmdGhj0BzNz3NH9q1oQ1 F1hbrXuT7Ls8p3pGQIJb0ZZnf1bOdmP4K3hRQyFZVELXZ9lHjiuBrDfcv/nxPNi5oKCvTzHg+uE QPgA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External The MBUS, IOMMU, and DRAM clocks only have an M divider, but are currently modeled as MP clocks with a zero-width P divider. ccu_mp_set_rate() generates an invalid mask for the zero-width P divider, clearing unrelated register fields. It also ignores CCU_FEATURE_UPDATE_BIT, so the new divider value does not take effect. Model these clocks as M-only clocks instead. This avoids accessing a nonexistent P divider and uses ccu_div_set_rate(), which handles the update bit. Fixes: 74b0443a0d0a ("clk: sunxi-ng: a523: add system mod clocks") Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 45 ++++++++++++++++--------------= ---- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.c index 20dad06b37ca..9bc3ff0ab12d 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -380,14 +380,13 @@ static const struct clk_parent_data mbus_parents[] = =3D { { .hw =3D &pll_periph1_150M_clk.hw }, { .fw_name =3D "hosc" }, }; -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, - 0x540, - 0, 5, /* M */ - 0, 0, /* no P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - CLK_IS_CRITICAL, - CCU_FEATURE_UPDATE_BIT); +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, + 0x540, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL, + CCU_FEATURE_UPDATE_BIT); =20 static const struct clk_hw *mbus_hws[] =3D { &mbus_clk.common.hw }; =20 @@ -584,14 +583,13 @@ static const struct clk_parent_data iommu_parents[] = =3D { { .fw_name =3D "hosc" }, }; =20 -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_pare= nts, - 0x7b0, - 0, 5, /* M */ - 0, 0, /* no P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - CLK_SET_RATE_PARENT, - CCU_FEATURE_UPDATE_BIT); +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_paren= ts, + 0x7b0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT, + CCU_FEATURE_UPDATE_BIT); =20 static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws, 0x7bc, BIT(0), 0); @@ -603,14 +601,13 @@ static const struct clk_parent_data dram_parents[] = =3D { { .hw =3D &pll_periph0_400M_clk.hw }, { .hw =3D &pll_periph0_150M_clk.hw }, }; -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents, - 0x800, - 0, 5, /* M */ - 0, 0, /* no P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - CLK_IS_CRITICAL, - CCU_FEATURE_UPDATE_BIT); +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents, + 0x800, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL, + CCU_FEATURE_UPDATE_BIT); =20 static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws, 0x804, BIT(0), 0); --=20 2.55.0 From nobody Sat Sep 26 03:14:43 2026 Received: from sender5-op-o12.zoho.com (sender5-op-o12.zoho.com [165.173.182.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B9D22116F4; Sun, 6 Sep 2026 07:07:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.182.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788678462; cv=pass; b=VnG+aSYiYe7s1MWk5yKU7M18hH6bUJT+OzCu4FyawcgMOM4d2dXGT5tinYTa1G2s6fxTLgb5RvBOy//OHUo0x3uxvSH2hrzZPkuoQFJXyRXGLxqQvk6P17cq+iMI873eqqzOgNfezZXAmLxTv1O57GVZex+q38o1cYcPjsnmNKk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788678462; c=relaxed/simple; bh=/1LOQjYt1FbY4EQLxeXf6XqbouFzXGxErt4sP9upvBk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Sun, 6 Sep 2026 00:07:25 -0700 (PDT) From: Junhui Liu Date: Sun, 06 Sep 2026 15:06:40 +0800 Subject: [PATCH 3/4] clk: sunxi-ng: sun55i-a523-ccu: Use P-only clocks for high-speed timers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-sunxi-clk-no-p-v1-3-cbde21c9fe69@pigmoral.tech> References: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> In-Reply-To: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Junhui Liu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3809; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=/1LOQjYt1FbY4EQLxeXf6XqbouFzXGxErt4sP9upvBk=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLLmCvJFqKw2zf+8b3HXXb7w5MoTdhyVwSquH3qUcgq+G nbpmG3oKGVhEONikBVTZOHyF/9nrcPz7YhA632YOaxMIEMYuDgFYCJLshkZmlkmuMTMuqBVNaF0 uWe0ePa2Y6tz3eT6qp6xpb231RQ6zMiwblmIGpd3UvvOB8UNNq/1bpyfdvdvWF5r+Yyg3X821MY xAwA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External The high-speed timer clocks only have a P divider, but are currently modeled as MP clocks with a zero-width M divider. ccu_mp_set_rate() generates an invalid mask for the zero-width M divider, clearing unrelated register fields. Model these clocks as P-only clocks to avoid accessing a nonexistent M divider. Fixes: 74b0443a0d0a ("clk: sunxi-ng: a523: add system mod clocks") Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 83 +++++++++++++++---------------= ---- 1 file changed, 36 insertions(+), 47 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.c index 9bc3ff0ab12d..0714090cc3b0 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -512,58 +512,47 @@ static const struct clk_parent_data hstimer_parents[]= =3D { { .fw_name =3D "losc" }, { .hw =3D &pll_periph0_200M_clk.hw }, }; -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0", - hstimer_parents, 0x730, - 0, 0, /* M */ - 0, 3, /* P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0", + hstimer_parents, 0x730, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); =20 -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer1_clk, "hstimer1", - hstimer_parents, - 0x734, - 0, 0, /* M */ - 0, 3, /* P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer1_clk, "hstimer1", + hstimer_parents, 0x734, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); =20 -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer2_clk, "hstimer2", - hstimer_parents, - 0x738, - 0, 0, /* M */ - 0, 3, /* P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer2_clk, "hstimer2", + hstimer_parents, 0x738, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); =20 -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer3_clk, "hstimer3", - hstimer_parents, - 0x73c, - 0, 0, /* M */ - 0, 3, /* P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer3_clk, "hstimer3", + hstimer_parents, 0x73c, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); =20 -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer4_clk, "hstimer4", - hstimer_parents, - 0x740, - 0, 0, /* M */ - 0, 3, /* P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer4_clk, "hstimer4", + hstimer_parents, 0x740, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); =20 -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer5_clk, "hstimer5", - hstimer_parents, - 0x744, - 0, 0, /* M */ - 0, 3, /* P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer5_clk, "hstimer5", + hstimer_parents, 0x744, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); =20 static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws, 0x74c, BIT(0), 0); --=20 2.55.0 From nobody Sat Sep 26 03:14:43 2026 Received: from sender6-op-o12.zoho.com (sender6-op-o12.zoho.com [165.173.180.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AD38233956; Sun, 6 Sep 2026 07:07:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.180.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788678471; cv=pass; b=tWatfQ9MhDejhNdfH2MomoIB/M9kWNSOEPG5WtdQ1dMAiUPhrT2MGq/JxuAfqDLKHBWzWvbHhUVnQfJCUyNNvJlFpZzwQY+pMK4pWhX+0aXV6nA6YRzyzn969F+Uy97UW9BLouwxfkPOjhHEl9Jrrl5geNfRifCKi+KmtWWzp2s= ARC-Message-Signature: i=2; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=IeNOG/fyhyW08X+c9FOeZI3cRdPDCI7EfAS9OrYLb8o=; b=MvZpfBlIbI4tiaYJfwYdI6Wyz1RfXx2c9mlkcFBiTMGEwb108EG5L2erpxgfvh+X y3Yv8FnVWMGcyqFkS4UACgxPFJ6X1LVdT9GUSFKAKANRIdZRSF20Pw2KrmW0u04hily fnnagx1+pGndXBcfGThhbFtFvcp//R18Rv21X3zg= Received: by mx.zohomail.com with SMTPS id 1788678452458799.045213868163; Sun, 6 Sep 2026 00:07:32 -0700 (PDT) From: Junhui Liu Date: Sun, 06 Sep 2026 15:06:41 +0800 Subject: [PATCH 4/4] clk: sunxi-ng: sun55i-a523-r-ccu: Use P-only clocks for timers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-sunxi-clk-no-p-v1-4-cbde21c9fe69@pigmoral.tech> References: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> In-Reply-To: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Junhui Liu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2310; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=w/ethCL/2gAqTdxAZVO9TFIwPKiMkbxjk7GgSv1iGNo=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLLmCgodfq0cfVtu8Qldz1kHfqtEZVZeNdw5wy5N/lDLm 72Kq8N4O0pZGMS4GGTFFFm4/MX/WevwfDsi0HofZg4rE8gQBi5OAZgIy35GhnXZRdctn7UwfO3f sv952nKVmq3ya52S30aL3Pq/h1fx91FGhgmPahacb/e4znI4Lqo4ZrtYdWHCJEuBM+uyXl3ouWP 4lAkA X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External The R timer clocks only have a P divider, but are currently modeled as MP clocks with a zero-width M divider. ccu_mp_set_rate() generates an invalid mask for the zero-width M divider, clearing unrelated register fields. Model these clocks as P-only clocks to avoid accessing a nonexistent M divider. Fixes: 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU= ") Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 37 +++++++++++++++-------------= ---- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c b/drivers/clk/sunxi-n= g/ccu-sun55i-a523-r.c index db0e36d8838e..349230e28c1c 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c @@ -43,27 +43,24 @@ static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1", 24, 3, /* mux */ 0); =20 -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0", - r_ahb_apb_parents, 0x100, - 0, 0, /* no M */ - 1, 3, /* P */ - 4, 3, /* mux */ - BIT(0), +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0", + r_ahb_apb_parents, 0x100, + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1", + r_ahb_apb_parents, 0x104, + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2", + r_ahb_apb_parents, 0x108, + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), 0); -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1", - r_ahb_apb_parents, 0x104, - 0, 0, /* no M */ - 1, 3, /* P */ - 4, 3, /* mux */ - BIT(0), - 0); -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2", - r_ahb_apb_parents, 0x108, - 0, 0, /* no M */ - 1, 3, /* P */ - 4, 3, /* mux */ - BIT(0), - 0); =20 static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common= .hw, 0x11c, BIT(0), 0); --=20 2.55.0