From nobody Sat Sep 26 02:00:33 2026 Received: from mout-p-201.mailbox.org (mout-p-201.mailbox.org [80.241.56.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBF0E3B7751; Sat, 5 Sep 2026 21:27:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788643634; cv=none; b=W6ht0G4SK8soi1rstk3jmEyRVFkDHzB/V2ORy1i/lEU81jKq2oEu9tb8Kre9RL/IA62xyKJe/RB/dkZJ61kMWBlOjbyRdR6ZQ3hJLzcurLsqFGO/JMlmQOAiDYCFjx/ul81vq8dgKu1mqb2wbpAg6mP+E21se5od4tVVtdxIai0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788643634; c=relaxed/simple; bh=dLygP1rIAJKNigeZ7e/nNg+lBDv26kZIT+sBpz+ohnE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CGBfQwZoHOrJnGk0q6tNitBq7dvI4WQMcJUeyVpE+v5FXWnfXLgfIYh0tSleM+trwXyXEEwLnZaTrQoIuXYxd06/Y+abU7cVkhwJKJIFBDLtzaBczrU5pqXnv93SulWyymFjNB7MDBGMXQTZQzKHEKJxiXUrKTXFDMZzhtYdQPY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=QvvA4wm5; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=OnVdxBPH; arc=none smtp.client-ip=80.241.56.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="QvvA4wm5"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="OnVdxBPH" Received: from smtp1.mailbox.org (smtp1.mailbox.org [10.196.197.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-201.mailbox.org (Postfix) with ESMTPS id 4hcmcm3BGJzMlMm; Sat, 05 Sep 2026 23:27:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1788643624; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TFGqPv7518oxfyRKgyOMWLwit0f/6hz7cdvLez14UXE=; b=QvvA4wm5S+/0cT94oDQvuS4EjI+lJz/VeNV6qBJ5PNj4hO+2G2+5aqbetn+CLppYQIX7f+ FpcL8u9UnZlUFw5oP1bR1KJpPG7ptapQeoNRHLEyH9Nuyd9NiAS4FQxhClgJy3rCUdcnZl ZilRMhrxK/9FfDSshuOI3nmu+WL5bBPa8KzuiP/ekkuDKvQYEvVFa4DrLPIyPCwzE1WeCi iToZqwZxBaB3sPCB7hz1kcLxsYY5Fa0JyzQ2MN+M/aH0lMKtW8i/FOFC/PyEzTiKqcoWdu UjKPnoRUsmqQoF7En5Oc8WG41R8B3ctK2OOuhiY2Mf0p1hCjuA7b1Bti6290xQ== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1788643622; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TFGqPv7518oxfyRKgyOMWLwit0f/6hz7cdvLez14UXE=; b=OnVdxBPHFs5hPk8VXwIpRrYkGhcdBRM/G+spLu9MXclzxbSl/sKrANP8TkGDQ6V76UehBP At22alefIQfUdtuI7Rl1a+ElPnYvuKi3YVAmd1G0pYX9Luxob1ttOT3oE3whp9Hqf+PL7M RfaSOkcwAW01c2UJijgMi1/itom3D8WnRgi84ztneMpWMA8rHe3uXqXDKygKnJoRWC2F10 6UblTbaq536Pz7MdnyT45jnVVWgvlDPUCmSx5dp8uhcOsBKBbNFasNxOUG9S+Ing/BC/y7 YrZjrase+9/+q1RNp6Aca3h8i+9SfyTaIWHniGqABOQWtSraoQu7Xk0C9KtfgA== To: linux-pci@vger.kernel.org Cc: Marek Vasut , Krzysztof Kozlowski , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 1/6] dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car X5H PCIe4 compatible Date: Sat, 5 Sep 2026 23:26:22 +0200 Message-ID: <20260905212649.360498-2-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> References: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-META: 4qw1gow7hcagq1oqtg6s5uais4m7e8gb X-MBO-RS-ID: 0959f9cd66d0f78b749 Document bindings for R-Car X5H (R8A78000) PCIe4 host module. The binding document is deliberately using "renesas,rcar-gen5-pcie4" DT compatible string to discern R-Car X5H PCIe4 controller supported by this binding, from R-Car X5H PCIe6 controller which will use a separate binding. The R-Car X5H PCIe4 controller does no longer include PHY register range, the PHY is now a separate IP and referenced via the 'phy' DT property. The 'reg' and 'reg-names' DT properties therefore differ between R-Car Gen4 PCIe and R-Car X5H PCIe4, and the difference is handled in the allOf section. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: Add RB from Krzysztof V3: No change V4: Rebase on next-20260904 --- .../bindings/pci/rcar-gen4-pci-host.yaml | 74 +++++++++++++------ 1 file changed, 52 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml = b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml index 64f456c6a75a1..9767a52f3904e 100644 --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -10,30 +10,20 @@ title: Renesas R-Car Gen4 PCIe Host maintainers: - Yoshihiro Shimoda =20 -allOf: - - $ref: snps,dw-pcie.yaml# - properties: compatible: - items: - - enum: - - renesas,r8a779f0-pcie # R-Car S4-8 - - renesas,r8a779g0-pcie # R-Car V4H - - renesas,r8a779h0-pcie # R-Car V4M - - const: renesas,rcar-gen4-pcie # R-Car Gen4 - - reg: - maxItems: 7 - - reg-names: - items: - - const: dbi - - const: dbi2 - - const: atu - - const: dma - - const: app - - const: phy - - const: config + oneOf: + - items: + - enum: + - renesas,r8a779f0-pcie # R-Car S4-8 + - renesas,r8a779g0-pcie # R-Car V4H + - renesas,r8a779h0-pcie # R-Car V4M + - const: renesas,rcar-gen4-pcie # R-Car Gen4 + + - items: + - enum: + - renesas,r8a78000-pcie4 # R-Car X5H PCIe4 + - const: renesas,rcar-gen5-pcie4 # R-Car Gen5 PCIe4 =20 interrupts: maxItems: 4 @@ -84,6 +74,46 @@ required: - resets - reset-names =20 +allOf: + - $ref: snps,dw-pcie.yaml# + - if: + properties: + compatible: + contains: + const: renesas,rcar-gen4-pcie + then: + properties: + reg: + maxItems: 7 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: app + - const: phy + - const: config + - if: + properties: + compatible: + contains: + const: renesas,rcar-gen5-pcie4 + then: + properties: + reg: + maxItems: 6 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: app + - const: config + unevaluatedProperties: false =20 examples: --=20 2.53.0 From nobody Sat Sep 26 02:00:33 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDE6E36F8F1; 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s=mail20150812; t=1788643626; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=P9N+he9sxxtxrNIn22r4COJqbJUj6mIguKAX03JG3t8=; b=vtRk4dk0c2ACWdchK3oX65YZUYr7fGaOu50rOgu+jrwyWic35QH3YwqA8tfI3ozPbZppiZ Raq/1xkPI63ZYS62yMpos3sfEb5PmodjzIRpBJ+LhJR/72+QhoUH/5SvZUiUKcLsRKXi8l V4VtF7jdJb43ZTyvy5wkUrtHTTmtFrtkt5AvC47nHn3Zge9LNlfo4azNsk9qoytzheEnK1 yIxhbKJ3KIEXqDgEHD1oY0PCzB7Kc3+qqjbCO11jYhLTnDMyrEqJ1KxmePl4eNua3hy77V UxKhqFzSVw17v6Owt+UdizhZojPjEigojuEmVW+R6lc4VDX+qVGd8zXWGStwjw== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 2/6] PCI: dwc: rcar-gen4: Rework rcar_gen4_pcie_drvdata .additional_common_init into .init Date: Sat, 5 Sep 2026 23:26:23 +0200 Message-ID: <20260905212649.360498-3-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> References: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-META: n1u1dmjpyj4g3cuizzmkefmgwcui6apa X-MBO-RS-ID: cb659758d2db5ef1c3a X-Rspamd-Queue-Id: 4hcmcq4h6szKvwt Rework the current complicated initialization callchain that invokes host_init->common_init->additional_common_init() for host and ep_init->common_init->additional_common_init() for endpoint into simpler host_init->init() and ep_init->init() . The init callback is now always implmented for all R-Car Gen4 SoCs, therefore there is no need to check whether the callback is not NULL. For R-Car S4 the .init callback is rcar_gen4_pcie_common_init(), for R-Car V4H and V4M the .init callback is implemented using a new function rcar_gen4_v4h_v4m_pcie_init() which calls the common rcar_gen4_pcie_common_init() followed by R-Car V4H and V4M specific hardware initialization. The hardware initialization sequence remains unchanged. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: Rename additional_common_init to init, reworked from previous patch PCI: dwc: rcar-gen4: Return error code from .additional_common_init V3: No change V4: Rebase on next-20260904 --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 56 ++++++++++++--------- 1 file changed, 32 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 5a076aa3f4904..a19ebbab2f8c3 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -87,7 +87,7 @@ MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME); =20 struct rcar_gen4_pcie; struct rcar_gen4_pcie_drvdata { - void (*additional_common_init)(struct rcar_gen4_pcie *rcar); + int (*init)(struct rcar_gen4_pcie *rcar); int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable); enum dw_pcie_device_mode mode; }; @@ -241,9 +241,6 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_= pcie *rcar) reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc); fsleep(1000); =20 - if (rcar->drvdata->additional_common_init) - rcar->drvdata->additional_common_init(rcar); - return 0; =20 err_unprepare: @@ -252,6 +249,31 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4= _pcie *rcar) return ret; } =20 +static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen4_pcie *rcar) +{ + struct dw_pcie *dw =3D &rcar->dw; + u32 val; + int ret; + + /* R-Car Gen4 common initialization. */ + ret =3D rcar_gen4_pcie_common_init(rcar); + if (ret) + return ret; + + /* R-Car V4H and V4M specific additional initialization. */ + val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); + val &=3D ~PORT_LANE_SKEW_INSERT_MASK; + if (dw->num_lanes < 4) + val |=3D BIT(6); + dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); + + val =3D readl(rcar->base + PCIEPWRMNGCTRL); + val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN; + writel(val, rcar->base + PCIEPWRMNGCTRL); + + return 0; +} + static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar) { struct dw_pcie *dw =3D &rcar->dw; @@ -474,7 +496,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) =20 gpiod_set_value_cansleep(dw->pe_rst, 1); =20 - ret =3D rcar_gen4_pcie_common_init(rcar); + ret =3D rcar->drvdata->init(rcar); if (ret) return ret; =20 @@ -543,7 +565,7 @@ static int rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep= *ep) =20 writel(0, rcar->base + PCIEDMAINTSTSEN); =20 - ret =3D rcar_gen4_pcie_common_init(rcar); + ret =3D rcar->drvdata->init(rcar); if (ret) return ret; =20 @@ -739,22 +761,6 @@ static int r8a779f0_pcie_ltssm_control(struct rcar_gen= 4_pcie *rcar, bool enable) return 0; } =20 -static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *r= car) -{ - struct dw_pcie *dw =3D &rcar->dw; - u32 val; - - val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); - val &=3D ~PORT_LANE_SKEW_INSERT_MASK; - if (dw->num_lanes < 4) - val |=3D BIT(6); - dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); - - val =3D readl(rcar->base + PCIEPWRMNGCTRL); - val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN; - writel(val, rcar->base + PCIEPWRMNGCTRL); -} - static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar, u32 offset, u32 mask, u32 val) { @@ -906,23 +912,25 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_g= en4_pcie *rcar, bool enable } =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie =3D { + .init =3D rcar_gen4_pcie_common_init, .ltssm_control =3D r8a779f0_pcie_ltssm_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep =3D { + .init =3D rcar_gen4_pcie_common_init, .ltssm_control =3D r8a779f0_pcie_ltssm_control, .mode =3D DW_PCIE_EP_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie =3D { - .additional_common_init =3D rcar_gen4_pcie_additional_common_init, + .init =3D rcar_gen4_v4h_v4m_pcie_init, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep =3D { - .additional_common_init =3D rcar_gen4_pcie_additional_common_init, + .init =3D rcar_gen4_v4h_v4m_pcie_init, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, .mode =3D DW_PCIE_EP_TYPE, }; --=20 2.53.0 From nobody Sat Sep 26 02:00:33 2026 Received: from mout-p-202.mailbox.org (mout-p-202.mailbox.org [80.241.56.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95A2739A7E7; Sat, 5 Sep 2026 21:27:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788643643; cv=none; b=LnkaXIoQLO8A75eshdbfXA+sP+T5ZQp1O94IPEIg1GsqcHuCI+Wd8+VlnjCxCQ263a6g09jNdJjcDnyxoeTn9c+NP/BftCFykVlC3Q4/RfRhZlnpcoVJmeHMCNHK4m9LkCsYi2gktKBaYLP5xKbLOoY+iab8QEctyIwCtCkCDeY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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dkim=pass header.d=mailbox.org header.s=mail20150812 header.b=dG1zhXkG; spf=pass (outgoing_mbo_mout: domain of marek.vasut+renesas@mailbox.org designates 2001:67c:2050:b231:465::1 as permitted sender) smtp.mailfrom=marek.vasut+renesas@mailbox.org From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1788643629; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pxx//r+qXHCSbp41qag/smW8DUpTuk5+voGpx4l+T5c=; b=dG1zhXkGVvcUBeUS/zuicDwZy5r9Amrg2dhrlGVFt39booiNKYzHJAGqalack2fN05PssV f9Rufdgg0K5xtzWJErz6v8B8EMbacphm5DmrWIniygbiLpbHSBnq9vIgpO9sbWJUonDROL 91U6s5TIv15ykOWIihNb0f3nF/+pMz10lr+ZhDTL5B3WZ/D3VQn42fViqqA5CBk+okmmf9 9Up0p8DiVCWTLSXXRubvy91Rq1ZEKqguuyjFZBddsvy5XoOXDlifteaHH1j5Je1Hiimfns r//G19cPSl2oP+vhyEEsxO7dlDiGnz3Gx5D8uO4yNTpujXd0NaboP/opzMDbhw== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 3/6] PCI: dwc: rcar-gen4: Add .deinit callback Date: Sat, 5 Sep 2026 23:26:24 +0200 Message-ID: <20260905212649.360498-4-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> References: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-META: wfuuptgeofnddrdz3sb7a7nkmh9fnxga X-MBO-RS-ID: 4e9a5b1c4fa1f803f4c X-Rspamd-Queue-Id: 4hcmcv4kMRzMlGN Add .deinit callback in preparation for R-Car Gen5 support. The .deinit callback will be used to tear down the PHY on R-Car Gen5. Thus far, it does what rcar_gen4_pcie_common_deinit() used to do directly. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V3: New patch V4: Rebase on next-20260904 --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index a19ebbab2f8c3..04871ac11c348 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -88,6 +88,7 @@ MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME); struct rcar_gen4_pcie; struct rcar_gen4_pcie_drvdata { int (*init)(struct rcar_gen4_pcie *rcar); + void (*deinit)(struct rcar_gen4_pcie *rcar); int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable); enum dw_pcie_device_mode mode; }; @@ -520,7 +521,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) return 0; =20 err: - rcar_gen4_pcie_common_deinit(rcar); + rcar->drvdata->deinit(rcar); return ret; } =20 @@ -530,7 +531,7 @@ static void rcar_gen4_pcie_host_deinit(struct dw_pcie_r= p *pp) struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); =20 gpiod_set_value_cansleep(dw->pe_rst, 1); - rcar_gen4_pcie_common_deinit(rcar); + rcar->drvdata->deinit(rcar); } =20 static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops =3D { @@ -580,7 +581,7 @@ static void rcar_gen4_pcie_ep_post_deinit(struct dw_pci= e_ep *ep) struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); =20 writel(0, rcar->base + PCIEDMAINTSTSEN); - rcar_gen4_pcie_common_deinit(rcar); + rcar->drvdata->deinit(rcar); } =20 static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, @@ -913,24 +914,28 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_g= en4_pcie *rcar, bool enable =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie =3D { .init =3D rcar_gen4_pcie_common_init, + .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D r8a779f0_pcie_ltssm_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep =3D { .init =3D rcar_gen4_pcie_common_init, + .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D r8a779f0_pcie_ltssm_control, .mode =3D DW_PCIE_EP_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie =3D { .init =3D rcar_gen4_v4h_v4m_pcie_init, + .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep =3D { .init =3D rcar_gen4_v4h_v4m_pcie_init, + .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, .mode =3D DW_PCIE_EP_TYPE, }; --=20 2.53.0 From nobody Sat Sep 26 02:00:33 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D88363B14BD; Sat, 5 Sep 2026 21:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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bh=ZliHt37nl5oMm3AvjG0cWeJ3vscugv/s7js+m/4ZTJo=; b=VzJdl6Q7nDPaX2gcVQm28ZZR9D2Jim13tgwCSuQJfR/4c7RoYsf4WipdR+LlGtk6bWcAnM +AlToyH5BGjqgwRrWiDnPSsa5wEcTbmu6V67LhgfQt+Duem2WcL9SRW2SLuNWJt2fUvB86 BfKW8Zzmf7Aal75iK10JIVVK8Q78+DOpELiALXjdUwy3bxO3ph/eNtnG1/NSvJyydn2H2K DudVGE5fY1PGlycAO2OrnIKnAXP8EaxUKebQ9K3a6UZUHLC6TWt3R9J0WQZKpUuRU4ZwZh 0tVU+Ltsvt8ZPDogtVvRLd9bvWwBCXGcwIDcvhTpT5mxKsEvotUrEKIReJVqxg== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 4/6] PCI: dwc: rcar-gen4: Split .start_link into ltssm_control and speed_control Date: Sat, 5 Sep 2026 23:26:25 +0200 Message-ID: <20260905212649.360498-5-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> References: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-META: r86oqps6c3gd33uyh1mnretwhc5mjauz X-MBO-RS-ID: 0b6a4a716ab0c85bea1 X-Rspamd-Queue-Id: 4hcmcy73k9zKv2F Introduce new .speed_control callback and implement it on R-Car Gen4. The callback implements the second half of what is currently present in rcar_gen4_pcie_start_link(), and rcar_gen4_pcie_start_link() does call the .speed_control callback. This is a preparatory patch for R-Car Gen5 support, where the .speed_control implementation is different. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: No change V3: No change V4: Rebase on next-20260904 --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 39 ++++++++++++++------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 04871ac11c348..c768a9c7b3b76 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -90,6 +90,7 @@ struct rcar_gen4_pcie_drvdata { int (*init)(struct rcar_gen4_pcie *rcar); void (*deinit)(struct rcar_gen4_pcie *rcar); int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable); + int (*speed_control)(struct rcar_gen4_pcie *rcar); enum dw_pcie_device_mode mode; }; =20 @@ -141,20 +142,10 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie= *dw) return -ETIMEDOUT; } =20 -/* - * Enable LTSSM of this controller and manually initiate the speed change. - * Always return 0. - */ -static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) +static int rcar_gen4_pcie_speed_control(struct rcar_gen4_pcie *rcar) { - struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); - int i, changes, ret; - - if (rcar->drvdata->ltssm_control) { - ret =3D rcar->drvdata->ltssm_control(rcar, true); - if (ret) - return ret; - } + struct dw_pcie *dw =3D &rcar->dw; + int i, changes; =20 /* * Require direct speed change with retrying here if the max_link_speed @@ -178,6 +169,24 @@ static int rcar_gen4_pcie_start_link(struct dw_pcie *d= w) return 0; } =20 +/* + * Enable LTSSM of this controller and manually initiate the speed change. + * Always return 0. + */ +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) +{ + struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); + int ret; + + if (rcar->drvdata->ltssm_control) { + ret =3D rcar->drvdata->ltssm_control(rcar, true); + if (ret) + return ret; + } + + return rcar->drvdata->speed_control(rcar); +} + static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw) { struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); @@ -916,6 +925,7 @@ static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_p= cie =3D { .init =3D rcar_gen4_pcie_common_init, .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D r8a779f0_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 @@ -923,6 +933,7 @@ static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_p= cie_ep =3D { .init =3D rcar_gen4_pcie_common_init, .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D r8a779f0_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_EP_TYPE, }; =20 @@ -930,6 +941,7 @@ static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_= pcie =3D { .init =3D rcar_gen4_v4h_v4m_pcie_init, .deinit =3D rcar_gen4_pcie_common_deinit, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_RC_TYPE, }; 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dkim=pass header.d=mailbox.org header.s=mail20150812 header.b=M7ZcDZxG; spf=pass (outgoing_mbo_mout: domain of marek.vasut+renesas@mailbox.org designates 2001:67c:2050:b231:465::1 as permitted sender) smtp.mailfrom=marek.vasut+renesas@mailbox.org From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1788643636; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NPBg7uvQ9ZFY1YMPRuvWFBHgwtOg8wlJc5aCR+EfuKo=; b=M7ZcDZxGQvQMO9asB2s6qgl2g64GvV7+nwgovaamqYz1fq8ZA++0mgf2SRQIsvXQqjZjCu po7ipYIFa4YmwnyBonY1MxHCOExr05vGDFlFpYVHaDF4ZEMbs+uDtQu5rRUSWGmxn7WnK2 t1/AXH/Nogv/5vzFhN4vJyYSH29FX+LOKGfqbcDzw1WgQaRBiTqyyvgnlxzCVswc+9tODj K1tTHiOzk5TJMqkk02cg63mWVN+1C5/1gDtJ/qdCYHe1uKEIwlYrbMnIq0TPSsOJ59UdW7 AuF+imOs6ipVJKlsdmkgzVNQm6G1ffE49c29FRKm7bknCa1E0c/D/csq9gqvuQ== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 5/6] PCI: dwc: rcar-gen4: Handle PERST via reset subsystem Date: Sat, 5 Sep 2026 23:26:26 +0200 Message-ID: <20260905212649.360498-6-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> References: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-META: b8gkpzb65ai3kow5pj6swpuhyxzm6fpx X-MBO-RS-ID: edbf8358d2231558545 X-Rspamd-Queue-Id: 4hcmd16lbHzMlKk Handle PERST via both GPIO and reset subsystem. On R-Car Gen4, the PERST signal is operated as a GPIO, on R-Car Gen5 it might only be accessible via SCMI reset via reset subsystem. Support both options. This is a preparatory patch for R-Car Gen5 support. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: - Use dev_err_probe() for perst in rcar_gen4_pcie_get_resources() - Use of_get_next_available_child() to obtain root port OF node - Switch to of_reset_control_get_optional_exclusive() to deal with R-Car Gen4, where the PERST is handled as GPIO instead of reset - Rename rcar_gen4_pcie_host_perst() to rcar_gen4_pcie_host_perst_asser= t() and use bool type for assert and deassert selection - Add missing reset_control_put() into rcar_gen4_pcie_probe() fail path V3: - Handle controllers without root port DT node - Swap fail path order V4: Rebase on next-20260904 --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 44 +++++++++++++++++++-- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index c768a9c7b3b76..89472a4becc46 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -99,6 +99,7 @@ struct rcar_gen4_pcie { void __iomem *base; void __iomem *phy_base; struct platform_device *pdev; + struct reset_control *perst; const struct rcar_gen4_pcie_drvdata *drvdata; }; #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw) @@ -317,12 +318,27 @@ static void rcar_gen4_pcie_unprepare(struct rcar_gen4= _pcie *rcar) =20 static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar) { + struct device *dev =3D rcar->dw.dev; + struct device_node *root_port; + rcar->phy_base =3D devm_platform_ioremap_resource_byname(rcar->pdev, "phy= "); if (IS_ERR(rcar->phy_base)) return PTR_ERR(rcar->phy_base); =20 + root_port =3D of_get_next_available_child(dev->of_node, NULL); + if (root_port) { + rcar->perst =3D of_reset_control_get_optional_exclusive(root_port, "pers= t"); + of_node_put(root_port); + if (IS_ERR(rcar->perst)) + return dev_err_probe(dev, PTR_ERR(rcar->perst), "Failed to get PERST#\n= "); + } else { + rcar->perst =3D NULL; + } + /* Renesas-specific registers */ rcar->base =3D devm_platform_ioremap_resource_byname(rcar->pdev, "app"); + if (IS_ERR(rcar->base)) + reset_control_put(rcar->perst); =20 return PTR_ERR_OR_ZERO(rcar->base); } @@ -494,6 +510,22 @@ static int rcar_gen4_pcie_enable_device(struct pci_hos= t_bridge *bridge, return 0; } =20 +static void rcar_gen4_pcie_host_perst_assert(struct dw_pcie_rp *pp, bool a= ssert) +{ + struct dw_pcie *dw =3D to_dw_pcie_from_pp(pp); + struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); + + gpiod_set_value_cansleep(dw->pe_rst, assert); + + if (!rcar->perst) + return; + + if (assert) + reset_control_assert(rcar->perst); + else + reset_control_deassert(rcar->perst); +} + /* Host mode */ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp) { @@ -504,7 +536,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) if (pp->bridge) pp->bridge->enable_device =3D rcar_gen4_pcie_enable_device; =20 - gpiod_set_value_cansleep(dw->pe_rst, 1); + rcar_gen4_pcie_host_perst_assert(pp, true); =20 ret =3D rcar->drvdata->init(rcar); if (ret) @@ -525,7 +557,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) =20 msleep(PCIE_T_PVPERL_MS); /* pe_rst requires 100msec delay */ =20 - gpiod_set_value_cansleep(dw->pe_rst, 0); + rcar_gen4_pcie_host_perst_assert(pp, false); =20 return 0; =20 @@ -539,7 +571,7 @@ static void rcar_gen4_pcie_host_deinit(struct dw_pcie_r= p *pp) struct dw_pcie *dw =3D to_dw_pcie_from_pp(pp); struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); =20 - gpiod_set_value_cansleep(dw->pe_rst, 1); + rcar_gen4_pcie_host_perst_assert(pp, true); rcar->drvdata->deinit(rcar); } =20 @@ -713,7 +745,7 @@ static int rcar_gen4_pcie_probe(struct platform_device = *pdev) =20 err =3D rcar_gen4_pcie_prepare(rcar); if (err) - return err; + goto err_prepare; =20 err =3D rcar_gen4_add_dw_pcie(rcar); if (err) @@ -724,6 +756,9 @@ static int rcar_gen4_pcie_probe(struct platform_device = *pdev) err_unprepare: rcar_gen4_pcie_unprepare(rcar); =20 +err_prepare: + reset_control_put(rcar->perst); + return err; } =20 @@ -747,6 +782,7 @@ static void rcar_gen4_pcie_remove(struct platform_devic= e *pdev) =20 rcar_gen4_remove_dw_pcie(rcar); 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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1788643639; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PsmhGmDoVPWNpkrC7qli7jjIMg8FGWZuq/UVaBoua+I=; b=tMN3CWf2P2VuNNocFBHf3w3eTK5nZSDPp6+W90217ia9guDDoeXbqMWCLURLqOcIJdOT2p vAyj/RbXlHS59jBYIQEwDKZWCsu3wxTVG+SGyxTYIU880FdY6RYPvvGfPtXJbilHPz2VkM wFCUMYpsMNFss5cQ/miUfUcxCXd/Hvu0NYOWIFNWQDkI4rVYxlp7VjGLBbbZk32+Y2eVHH KUTN92uBUhJT04YpNpJBBmboJKuzH19KB95CXbaXVdvK2bjEodbF0L1wT5t6P58cPwF4bD LPJpHSy8W+ZorBU/GnYdUt9+SqZVMc6jp1uYjLKa2KSvQZoKRrHm4Rsz7tkwBQ== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 6/6] PCI: dwc: rcar-gen4: Add support for R-Car X5H PCIe4 Date: Sat, 5 Sep 2026 23:26:27 +0200 Message-ID: <20260905212649.360498-7-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> References: <20260905212649.360498-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: 50723f50b451b8bafdc X-MBO-RS-META: e6jbckg7b3bkb5wqutqgmpwpoqpm45ce X-Rspamd-Queue-Id: 4hcmd51ls6zMlH3 Add support for R8A78000 (R-Car X5H) PCIe4. This driver previously supported R-Car Gen4 S4/V4H/V4M. PCIe features of R-Car X5H PCIe4 are almost all the same. The controller initialization sequence is slightly different and is factored out into controller specific callbacks, in a manner similar to previous R-Car Gen4 handling. The controller does have a PHY attached to it, but the PHY is operated by a separate PHY driver, the PHY driver instance binding is handled in rcar_gen4_pcie_get_resources() and controlled in the aforementioned controller specific callbacks. The controller driver is deliberately using "renesas,rcar-gen5-pcie4" DT compatible string to discern R-Car X5H PCIe4 controller supported by this driver, from R-Car X5H PCIe6 controller which will most likely use a separate driver. The R-Car X5H PCIe4 controller embeds HDMA instead of EDMA embedded in the R-Car Gen4 PCIe controller, "dw-edma" driver supports both DMA variants. Endpoint mode is currently not implemented for R-Car Gen5 PCIe4. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: No change V3: - Disable clock in case of PHY init failure in rcar_gen5_pcie_init() - Add .deinit callback and tear down Gen5 PHY in it - Use 16bit accessors on LNKCTL register V4: Rebase on next-20260904 --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 128 +++++++++++++++++++- 1 file changed, 126 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 89472a4becc46..5c0d5fd686cb5 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,7 @@ =20 /* MSI Capability */ #define MSICAP0 0x0050 +#define MSICAP0_MMESCAP_MASK GENMASK(19, 17) #define MSICAP0_MSIE BIT(16) =20 /* PCIe Interrupt Status 0 */ @@ -74,6 +76,11 @@ #define PCIEPWRMNGCTRL 0x0070 #define APP_CLK_REQ_N BIT(11) #define APP_CLK_PM_EN BIT(10) +#define APP_READY_ENTR_L23 BIT(6) +#define APP_REQ_ENTR_L1 BIT(5) + +/* PCI Express capability */ +#define EXPCAP(x) (0x0070 + (x)) =20 #define RCAR_NUM_SPEED_CHANGE_RETRIES 10 #define RCAR_MAX_LINK_SPEED 4 @@ -98,6 +105,7 @@ struct rcar_gen4_pcie { struct dw_pcie dw; void __iomem *base; void __iomem *phy_base; + struct phy *phy; struct platform_device *pdev; struct reset_control *perst; const struct rcar_gen4_pcie_drvdata *drvdata; @@ -170,6 +178,35 @@ static int rcar_gen4_pcie_speed_control(struct rcar_ge= n4_pcie *rcar) return 0; } =20 +static int rcar_gen5_pcie_speed_control(struct rcar_gen4_pcie *rcar) +{ + struct dw_pcie *dw =3D &rcar->dw; + u32 lnkcap =3D dw_pcie_readl_dbi(dw, EXPCAP(PCI_EXP_LNKCAP)); + u32 lnksta =3D dw_pcie_readw_dbi(dw, EXPCAP(PCI_EXP_LNKSTA)); + u32 val, retries; + + if ((lnksta & PCI_EXP_LNKSTA_CLS) =3D=3D (lnkcap & PCI_EXP_LNKCAP_SLS)) + return 0; + + /* Retrain link */ + val =3D dw_pcie_readw_dbi(dw, EXPCAP(PCI_EXP_LNKCTL)); + val |=3D PCI_EXP_LNKCTL_RL; + dw_pcie_writew_dbi(dw, EXPCAP(PCI_EXP_LNKCTL), val); + + /* Wait for link retrain */ + for (retries =3D 0; retries <=3D 10; retries++) { + lnksta =3D dw_pcie_readw_dbi(dw, EXPCAP(PCI_EXP_LNKSTA)); + + /* Check retrain flag */ + if (!(lnksta & PCI_EXP_LNKSTA_LT)) + break; + + usleep_range(1000, 1100); + } + + return 0; +} + /* * Enable LTSSM of this controller and manually initiate the speed change. * Always return 0. @@ -285,6 +322,49 @@ static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen= 4_pcie *rcar) return 0; } =20 +static int rcar_gen5_pcie_init(struct rcar_gen4_pcie *rcar) +{ + struct dw_pcie *dw =3D &rcar->dw; + int ret; + u32 val; + + /* R-Car Gen4 and Gen5 common initialization. */ + ret =3D rcar_gen4_pcie_common_init(rcar); + if (ret) + return ret; + + /* R-Car Gen5 specific additional initialization. */ + ret =3D phy_init(rcar->phy); + if (ret) + goto err_unprepare; + + dw_pcie_dbi_ro_wr_en(dw); + + val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); + val &=3D ~PORT_LANE_SKEW_INSERT_MASK; + if (dw->num_lanes < 8) + val |=3D BIT(6); + dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); + + val =3D dw_pcie_readl_dbi(dw, MSICAP0); + FIELD_MODIFY(MSICAP0_MMESCAP_MASK, &val, 4); + dw_pcie_writel_dbi(dw, MSICAP0, val); + + dw_pcie_dbi_ro_wr_dis(dw); + + val =3D readl(rcar->base + PCIEPWRMNGCTRL); + val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN | + APP_READY_ENTR_L23 | APP_REQ_ENTR_L1; + writel(val, rcar->base + PCIEPWRMNGCTRL); + + return 0; + +err_unprepare: + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks); + + return ret; +} + static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar) { struct dw_pcie *dw =3D &rcar->dw; @@ -293,6 +373,12 @@ static void rcar_gen4_pcie_common_deinit(struct rcar_g= en4_pcie *rcar) clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks); } =20 +static void rcar_gen5_pcie_deinit(struct rcar_gen4_pcie *rcar) +{ + phy_exit(rcar->phy); + rcar_gen4_pcie_common_deinit(rcar); +} + static int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar) { struct device *dev =3D rcar->dw.dev; @@ -322,8 +408,12 @@ static int rcar_gen4_pcie_get_resources(struct rcar_ge= n4_pcie *rcar) struct device_node *root_port; =20 rcar->phy_base =3D devm_platform_ioremap_resource_byname(rcar->pdev, "phy= "); - if (IS_ERR(rcar->phy_base)) - return PTR_ERR(rcar->phy_base); + if (IS_ERR(rcar->phy_base)) { + rcar->phy_base =3D NULL; + rcar->phy =3D devm_phy_get(dev, NULL); + if (IS_ERR(rcar->phy)) + return PTR_ERR(rcar->phy); + } =20 root_port =3D of_get_next_available_child(dev->of_node, NULL); if (root_port) { @@ -807,6 +897,28 @@ static int r8a779f0_pcie_ltssm_control(struct rcar_gen= 4_pcie *rcar, bool enable) return 0; } =20 +static int rcar_gen5_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool = enable) +{ + u32 val; + + val =3D readl(rcar->base + PCIERSTCTRL1); + if (enable) { + val |=3D APP_LTSSM_ENABLE; + val &=3D ~APP_HOLD_PHY_RST; + } else { + val &=3D ~APP_LTSSM_ENABLE; + val |=3D APP_HOLD_PHY_RST; + } + writel(val, rcar->base + PCIERSTCTRL1); + + if (enable) + phy_power_on(rcar->phy); + else + phy_power_off(rcar->phy); + + return 0; +} + static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar, u32 offset, u32 mask, u32 val) { @@ -989,6 +1101,14 @@ static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen= 4_pcie_ep =3D { .mode =3D DW_PCIE_EP_TYPE, }; =20 +static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen5_pcie =3D { + .init =3D rcar_gen5_pcie_init, + .deinit =3D rcar_gen5_pcie_deinit, + .ltssm_control =3D rcar_gen5_pcie_ltssm_control, + .speed_control =3D rcar_gen5_pcie_speed_control, + .mode =3D DW_PCIE_RC_TYPE, +}; + static const struct of_device_id rcar_gen4_pcie_of_match[] =3D { { .compatible =3D "renesas,r8a779f0-pcie", @@ -1006,6 +1126,10 @@ static const struct of_device_id rcar_gen4_pcie_of_m= atch[] =3D { .compatible =3D "renesas,rcar-gen4-pcie-ep", .data =3D &drvdata_rcar_gen4_pcie_ep, }, + { + .compatible =3D "renesas,rcar-gen5-pcie4", + .data =3D &drvdata_rcar_gen5_pcie, + }, {}, }; MODULE_DEVICE_TABLE(of, rcar_gen4_pcie_of_match); --=20 2.53.0