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This stage is fed by its own gate clock and, when that clock is disabled, a controller that starts a DMA transfer can never complete it. Allow a fourth clock entry, named "pipeline", and require it for the amlogic,t7-mmc compatible. The other controllers of this family keep the existing three clocks. Assisted-by: Claude:claude-fable-5 Signed-off-by: Lucas Tanure Acked-by: Conor Dooley --- .../bindings/mmc/amlogic,meson-gx-mmc.yaml | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yam= l b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml index 976f36de2091..12342b1d78e5 100644 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml @@ -15,6 +15,23 @@ maintainers: =20 allOf: - $ref: mmc-controller.yaml# + - if: + properties: + compatible: + contains: + const: amlogic,t7-mmc + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + else: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 =20 properties: compatible: @@ -38,13 +55,23 @@ properties: - description: card detect =20 clocks: - maxItems: 3 + minItems: 3 + items: + - description: core clock + - description: clock input 0 of the internal mux + - description: clock input 1 of the internal mux + - description: + clock of the pipeline stage inserted in the bus path between + the controller and the DRAM. Without it, the controller cannot + complete DMA transfers. =20 clock-names: + minItems: 3 items: - const: core - const: clkin0 - const: clkin1 + - const: pipeline =20 resets: maxItems: 1 --=20 2.55.0 From nobody Sat Sep 26 01:59:50 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B1984B0C88 for ; Sat, 5 Sep 2026 15:32:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788622363; cv=none; b=YFsaZx9JC9k6AHxN12d0g3sP1mwfSIP05CbUSvadNglInHxeAvHnwMSjxRJQZSIJM1in+nNt8GyeTy4VpbJuzj3fDc4yJS1Cfrb0Y7+eoFTjPTrMaZgHSEHuPV0C72bFcLMOrYErY/qXcvijm/j9eA8yktBwA9e9rLzhKiQjky0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788622363; c=relaxed/simple; bh=oLDcY6kImT6VejPH+8oQ5pUx6Jmf88kTwnGUpUh8fuM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rLa42PrqH2EAmOp7wE1+QGDAEP1MCxSSd0PBKd47h6qUzldt9SQPsUEKklrsm5OXdpfOLpLPyvmSrN1Aq4+rP4QvBQEtI3e9HkBtVpdRDw7o4J8eFq6FA3qZHnPBCEpP6oOLJYIij+rH+VDYkZXlds6Cfo0athgptEv6k/aI9Is= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.com; spf=pass smtp.mailfrom=gmail.com; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-48441a2ba14so1776898f8f.1 for ; Sat, 05 Sep 2026 08:32:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788622358; x=1789227158; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=6cvLPMe39R/AaBDs2Mh5u5mXzrtCLtGEuv4B7IhLgiQ=; b=Yqs95Ap6NzUQhAfHVxaVFuTdQrXL3iXcyXb0jViEufI+moMKgsZ7JG1WN1p0xPn6R6 vR+R4DToeKh7rWQMMVlxE6NjnibPdJqqrocGwv/4dQqBzJ24EzHK9SaTD8gNnVZAa9+Z injUfAhR6cnWpKRg/BL1ORxkLey6VokB20MCTQ82Geoo7oB++J/e+f0mOn4aVhrMR2FS yQ0yi+ogy+4bmfuznFXWmSDz1HiGjI5w9dgjiiNHlhuvs9qUh6zcjZthGv10qiSn6KXV LPUSvxvniycsCmFIHZgklwjzSLfo6ANmCQNZ4UWf3hd5VogPsTL5bEEUon4m1BfY2oFx I94A== X-Forwarded-Encrypted: i=1; AKwUvByrHdCeBUjE9cq2uT4mlkPv6cxGLuLtFFQ7cKa2zKSV0vaok4b7aUa635i1gOEvARqcWuOCyyc6gh30fWI=@vger.kernel.org X-Gm-Message-State: AFuF++lF27J+LsGHFEHtJYwEsuLpP9xgvzPwPTmMqnjPgblgZZqfyXuk qjX8J+yU5p8Ytla2eAnaTzQCuEWikA/YH4pc2RfN4DYhexfudcRzapt1 X-Gm-Gg: AYBFou3VuNC62bOK1Tlham0Tre/k/0FQW0EKLiQu4dUPp+IWROQQdUa1oXW4ReNKlLI 1adOFfgOIuzAEy9rpvK6dg6gaXP9+V8G7c1T+9glyRERhHdhzlMuWDREgpQLlkT6mcSjnwqODJ4 hrOfrnJQjsuTLMq0UIAEQ869GqAV2kpqZ9x2aIlQD+euEpO6jZwp+w374I0GBOd91t0X6lW5t7k 5RctRuNzAHGrW2reTQwUnx0BoMAoOo9E53bM9IU4G4kxfS/DcgykMSj6wds8ZbwIWkFqtk27g7k KgJqdO8t8ep2kRk1D4Ie6t0PWm9kcbhDyv7LKqq667K1MkpbUj7vTAuOQ6ygN48CqpKXqNgfTHG BTfHuuFAMlYqmHGW+mrVlxTU13M0yUg/LgbHxp2p6gaboZmtscZvL7TvvCycvUw0BDudkmVmWgu H0PCyvSIKX3+PiH4dWXavYZ9jd+zZ2prQlGXb86wfEiKPrXAurPyFo6/dEShqtbrVE5JMlCklU1 wRViQwGaecIHA47CoQgzeOm+DxgMv9hoVhL X-Received: by 2002:a05:6000:470c:b0:485:8a46:705c with SMTP id ffacd0b85a97d-4858a4671b8mr11204628f8f.46.1788622357649; Sat, 05 Sep 2026 08:32:37 -0700 (PDT) Received: from threads.localdomain ([84.68.179.181]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-485883c6ba4sm16691913f8f.25.2026.09.05.08.32.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Sep 2026 08:32:37 -0700 (PDT) From: Lucas Tanure To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Stephen Boyd Cc: Brian Masney , Chuan Liu , Jian Hu , Ronald Claveau , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] mmc: meson-gx: enable the bus pipeline clock on T7 Date: Sat, 5 Sep 2026 16:32:32 +0100 Message-ID: <20260905153234.133217-3-tanure@linux.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260905153234.133217-1-tanure@linux.com> References: <20260905153234.133217-1-tanure@linux.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the T7 SoC, the bus path between the SD/eMMC controllers and the NIC_MATRIX fabric goes through a pipeline stage inserted by the hardware design to help timing closure. The stage has its own gate clock and, when that clock is disabled, a controller that starts a DMA transfer can never complete it, hanging the storage devices and, from there, the whole system. Add a dedicated match data for the amlogic,t7-mmc compatible that makes the driver claim and enable the "pipeline" clock for as long as the device is bound. The clock is deliberately not optional: the hardware cannot do DMA without it, and failing the probe with a clear error is preferable to booting and hitting an undiagnosable DMA hang later. Assisted-by: Claude:claude-fable-5 Signed-off-by: Lucas Tanure Reviewed-by: Neil Armstrong --- drivers/mmc/host/meson-gx-mmc.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mm= c.c index 694bb443d5f3..c0f1e929fc13 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -139,6 +139,7 @@ struct meson_mmc_data { unsigned int always_on; unsigned int adjust; unsigned int irq_sdio_sleep; + bool has_pipeline_clk; }; =20 struct sd_emmc_desc { @@ -1204,6 +1205,15 @@ static int meson_mmc_probe(struct platform_device *p= dev) if (IS_ERR(core_clk)) return PTR_ERR(core_clk); =20 + if (host->data->has_pipeline_clk) { + struct clk *pipe_clk; + + pipe_clk =3D devm_clk_get_enabled(&pdev->dev, "pipeline"); + if (IS_ERR(pipe_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(pipe_clk), + "missing pipeline clock\n"); + } + ret =3D meson_mmc_clk_init(host); if (ret) return ret; @@ -1322,12 +1332,22 @@ static const struct meson_mmc_data meson_axg_data = =3D { .irq_sdio_sleep =3D CLK_V3_IRQ_SDIO_SLEEP, }; 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Sat, 05 Sep 2026 08:32:38 -0700 (PDT) Received: from threads.localdomain ([84.68.179.181]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-485883c6ba4sm16691913f8f.25.2026.09.05.08.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Sep 2026 08:32:38 -0700 (PDT) From: Lucas Tanure To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Stephen Boyd Cc: Brian Masney , Chuan Liu , Jian Hu , Ronald Claveau , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/4] arm64: dts: amlogic: t7: add the pipeline clock to the MMC controllers Date: Sat, 5 Sep 2026 16:32:33 +0100 Message-ID: <20260905153234.133217-4-tanure@linux.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260905153234.133217-1-tanure@linux.com> References: <20260905153234.133217-1-tanure@linux.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SD/eMMC controllers reach the DRAM through a pipeline stage that the hardware design inserts in the bus path to the NIC_MATRIX fabric, clocked by CLKID_SYS_AMPIPE_NAND. When that clock is disabled, a controller that starts a DMA transfer can never complete it. Reference the clock from the three MMC controller nodes so the driver keeps it running, instead of relying on the clock being marked critical in the clock controller. Assisted-by: Claude:claude-fable-5 Signed-off-by: Lucas Tanure Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-t7.dtsi index c3dc479b137d..dbb4a95652c6 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -730,8 +730,9 @@ sd_emmc_a: mmc@88000 { interrupts =3D ; clocks =3D <&clkc_periphs CLKID_SYS_SD_EMMC_A>, <&clkc_periphs CLKID_SD_EMMC_A>, - <&scmi_clk CLKID_FCLK_DIV2>; - clock-names =3D "core", "clkin0", "clkin1"; + <&scmi_clk CLKID_FCLK_DIV2>, + <&clkc_periphs CLKID_SYS_AMPIPE_NAND>; + clock-names =3D "core", "clkin0", "clkin1", "pipeline"; resets =3D <&reset RESET_SD_EMMC_A>; assigned-clocks =3D <&clkc_periphs CLKID_SD_EMMC_A_SEL>; assigned-clock-parents =3D <&xtal>; @@ -744,8 +745,9 @@ sd_emmc_b: mmc@8a000 { interrupts =3D ; clocks =3D <&clkc_periphs CLKID_SYS_SD_EMMC_B>, <&clkc_periphs CLKID_SD_EMMC_B>, - <&scmi_clk CLKID_FCLK_DIV2>; - clock-names =3D "core", "clkin0", "clkin1"; + <&scmi_clk CLKID_FCLK_DIV2>, + <&clkc_periphs CLKID_SYS_AMPIPE_NAND>; + clock-names =3D "core", "clkin0", "clkin1", "pipeline"; resets =3D <&reset RESET_SD_EMMC_B>; assigned-clocks =3D <&clkc_periphs CLKID_SD_EMMC_B_SEL>; assigned-clock-parents =3D <&xtal>; @@ -758,8 +760,9 @@ sd_emmc_c: mmc@8c000 { interrupts =3D ; clocks =3D <&clkc_periphs CLKID_SYS_SD_EMMC_C>, <&clkc_periphs CLKID_SD_EMMC_C>, - <&scmi_clk CLKID_FCLK_DIV2>; - clock-names =3D "core", "clkin0", "clkin1"; + <&scmi_clk CLKID_FCLK_DIV2>, + <&clkc_periphs CLKID_SYS_AMPIPE_NAND>; + clock-names =3D "core", "clkin0", "clkin1", "pipeline"; resets =3D <&reset RESET_SD_EMMC_C>; assigned-clocks =3D <&clkc_periphs CLKID_SD_EMMC_C_SEL>; assigned-clock-parents =3D <&xtal>; --=20 2.55.0 From nobody Sat Sep 26 01:59:50 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72A8A4B2CD7 for ; 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Sat, 05 Sep 2026 08:32:39 -0700 (PDT) Received: from threads.localdomain ([84.68.179.181]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-485883c6ba4sm16691913f8f.25.2026.09.05.08.32.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Sep 2026 08:32:39 -0700 (PDT) From: Lucas Tanure To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Stephen Boyd Cc: Brian Masney , Chuan Liu , Jian Hu , Ronald Claveau , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/4] clk: meson: t7: don't mark sys_ampipe_nand as critical Date: Sat, 5 Sep 2026 16:32:34 +0100 Message-ID: <20260905153234.133217-5-tanure@linux.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260905153234.133217-1-tanure@linux.com> References: <20260905153234.133217-1-tanure@linux.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" sys_ampipe_nand clocks the pipeline stage inserted in the bus path between the SD/eMMC controllers and the NIC_MATRIX fabric. It does have identifiable consumers - the three MMC controllers - so marking it critical was the wrong tool: the clock should be referenced from the consumer nodes and claimed by the mmc driver instead. Drop the CLK_IS_CRITICAL flag and update the comment accordingly. sys_am2axi0..2 remain critical as they clock the AXI DMA bus itself and have no single identifiable consumer. Assisted-by: Claude:claude-fable-5 Signed-off-by: Lucas Tanure Reviewed-by: Neil Armstrong --- This patch depends on the MMC controllers actually referencing the clock: the dt-bindings, mmc driver and t7 DTS changes adding the "pipeline" clock must land before this patch, otherwise the boot hangs and memory corruption this clock caused are reintroduced. drivers/clk/meson/t7-peripherals.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peri= pherals.c index 55d09e78593b..2f429ea86796 100644 --- a/drivers/clk/meson/t7-peripherals.c +++ b/drivers/clk/meson/t7-peripherals.c @@ -945,13 +945,13 @@ static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, = 0); static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0); static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0); static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0); +static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0); +static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); /* - * NOTE: sys_ampipe_nand and sys_am2axi0..2 provide the clock to the AXI b= us - * used for DMA between the peripherals and the DRAM. After the clocks are - * disabled, a device that starts a transfer cannot complete it. + * NOTE: sys_am2axi0..2 provide the clock to the AXI bus used for DMA betw= een + * the peripherals and the DRAM. After the clocks are disabled, a device t= hat + * starts a transfer cannot complete it. */ -static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, CLK_IS_CRITICAL); -static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, CLK_IS_CRITICAL); --=20 2.55.0