From nobody Sat Sep 26 03:58:00 2026 Received: from ultrarisc.com (unknown [218.76.62.146]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A5A53378D9A; Sat, 5 Sep 2026 02:57:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=218.76.62.146 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788577042; cv=none; b=UF6DBtrgShTIayIIYJMi6IgNfMZfyYcBd5in/8JoxXsrHnD6iHeEcBw2zCf+Ut34MEOebhuSbC4fPJSty7tvN6qlc7lRljcn6bPRAG+SSRvJT7G3M9pzjm271ClOcdJKqK12m92up3cpHHrsyPa5Lftdpqu5FNt59R0UkFJum1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788577042; c=relaxed/simple; bh=Cz9oKUCkripl1kkQ1ee76SmB+4V9VAbTDsRNhilQOHQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gHqbAVV+XWynRt4gk2uaBlGXl/RhhQ3AKhwOHnyGSwslIlkugfOynWy2kz6FJSWmMNuhaGQDsM8rM6DOh3v8SJ0id05pOwDnThRCFnKUHcekkvW+KQxixgrq0RkZuSg/VbO7n0YJG7rr1R6pbiuXTzccbqFo7zX75tRx3OpHL+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ultrarisc.com; spf=pass smtp.mailfrom=ultrarisc.com; dkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com header.b=jezoKvSM; arc=none smtp.client-ip=218.76.62.146 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ultrarisc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ultrarisc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com header.b="jezoKvSM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ultrarisc.com; s=dkim; h=Received:From:To:Cc:Subject:Date: Message-Id:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding; bh=IdTG/sFDU/AU2CnhuWPPTMvHsTi/sQ5W6S Q8NCJt8Lk=; b=jezoKvSMyXMDfiAw6VmH19orZpgdRjEFcs0fNcJYFDmhz7PNU+ UKkxyFz2zeUo+zDsqZtV2TBmiU8IxFXyDu5tOIQv/lqyUTeHlZefembuOhgb35Em e5vnB4HCFFz3UpxrK52P6YIW9dF8W1sQGYTiSY6kCoXQ8oeByPxAqnuFE= Received: from leopard.. (unknown [192.168.100.1]) by localhost.localdomain (Coremail) with SMTP id AQAAfwDHQAcKhZtqDUQAAA--.300S3; Sat, 05 Sep 2026 10:57:28 +0800 (CST) From: Xincheng Zhang To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= Cc: Rob Herring , Bjorn Helgaas , Jia Wang , Niklas Cassel , Frank Li , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Xincheng Zhang Subject: [PATCH v2 1/2] PCI: dwc: Allow drivers to skip MEM outbound iATU setup Date: Sat, 5 Sep 2026 10:56:34 +0800 Message-Id: <20260905025635.211390-2-zhangxincheng@ultrarisc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260905025635.211390-1-zhangxincheng@ultrarisc.com> References: <20260905025635.211390-1-zhangxincheng@ultrarisc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwDHQAcKhZtqDUQAAA--.300S3 X-Coremail-Antispam: 1UD129KBjvJXoWxArW3Cr4Utw15Ar1kWF17Jrb_yoW5CFykpa y7tFWSyF1kJF43Zr43Z3WkZryYyas3AFWUGFZa934IvrW3uryjqr1rtFy7try3Gr40vry5 Kr4Yva4kGFs8J3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmm14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWUJVW8JwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkF7I0En4kS14v26r1q6r43MxkIecxEwVCm-wCF04k20xvY0x0EwIxGrwCFx2IqxVCF s4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r 1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWU JVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r 1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1U YxBIdaVFxhVjvjDU0xZFpf9x0JU2dgAUUUUU= X-CM-SenderInfo: x2kd0wp0lquxxhqjq3powut2xlvfhudrp/1tbiAQABDGqaaqQALgAAsc Content-Type: text/plain; charset="utf-8" Some DWC-based controllers do not require outbound iATU windows for MEM transactions. For those platforms, programming outbound iATU windows for host bridge MEM ranges is unnecessary and may constrain the available MEM aperture. The DWC PCIe RP Controller Databook v6.00a, section 3.12.2, describes the default outbound no-match behavior as pass-through. Section 3.12.5.6, "No Address Match Result", says the address is not translated and programmable TLP header fields come from the application transmit interface. This no-match path cannot translate between different parent-bus and PCI addresses, so require skipped MEM ranges to be identity-mapped. Add dw_pcie_rp::bypass_ob_mem_iatu so drivers can skip generic MEM iATU setup while using the common DWC host init path. Existing drivers keep the current behavior because the flag defaults to false. The I/O iATU setup does not use the MEM resource iterator, and the iterator may be uninitialized when MEM setup is skipped. Avoid using it in the I/O iATU error path. Signed-off-by: Xincheng Zhang --- .../pci/controller/dwc/pcie-designware-host.c | 17 +++++++++++++++-- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index f5a38e6fd8d79..b06797b4e31d2 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -918,6 +918,20 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) atu.parent_bus_addr =3D entry->res->start - pci->parent_bus_offset; atu.pci_addr =3D entry->res->start - entry->offset; =20 + if (pp->bypass_ob_mem_iatu) { + /* + * The no-match pass-through path preserves the correct + * PCI address only for identity-mapped MEM ranges. + */ + if (atu.parent_bus_addr !=3D atu.pci_addr) { + dev_err(pci->dev, + "Cannot bypass outbound iATU for non-identity MEM range %pr\n", + entry->res); + return -EINVAL; + } + continue; + } + /* Adjust iATU size if MSG TLP region was allocated before */ if (pp->msg_res && pp->msg_res->parent =3D=3D entry->res) res_size =3D resource_size(entry->res) - @@ -964,8 +978,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) =20 ret =3D dw_pcie_prog_outbound_atu(pci, &atu); if (ret) { - dev_err(pci->dev, "Failed to set IO range %pr\n", - entry->res); + dev_err(pci->dev, "Failed to set IO range\n"); return ret; } ob_iatu_index++; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 0735ae9409240..d89badcca2689 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -469,6 +469,7 @@ struct dw_pcie_rp { struct pci_config_window *cfg; bool ecam_enabled; bool native_ecam; + bool bypass_ob_mem_iatu; bool skip_l23_ready; bool skip_pwrctrl_off; }; --=20 2.34.1 From nobody Sat Sep 26 03:58:00 2026 Received: from ultrarisc.com (unknown [218.76.62.146]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B9A8D367B89; Sat, 5 Sep 2026 02:57:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=218.76.62.146 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788577049; cv=none; b=RQbPbtX5ltsTC2TG4IEULzq1oEM7H0IaclSXfftNP63jmJnV0UDxIPB/CYNW9Pl3rb9hjkHrweO+EYr8tv9erTzzRrkS8ARhe7xIBXC/GOkB9IC/ZqWRHfOKhrGKHpKFeL7ptrSkXkYPRwnwZLeQBd57IeJM11kMdTcU6dPNHwY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788577049; c=relaxed/simple; bh=xvMAxdykKJMrlWh+AEoP34z6GvzFoitid+x6KM2d6X4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=n/Om9nI5yTRzdRcgOFL2Es8R8+2WKLbgvtnp1qvwJ2FXhSSwpsSwenU3f8Cv5tRKPk9Swo05Hg7Db6T31oeFBGMSIR4EA2y3dGymZAggOk9vkhB+B6Dn7WWjP1+efD9uQn7Y/44VPPJzHGhZEw4+0oK2aFJM3KEPkclKCjj6d4A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ultrarisc.com; spf=none smtp.mailfrom=ultrarisc.com; dkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com header.b=mw7sp3cq; arc=none smtp.client-ip=218.76.62.146 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ultrarisc.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=ultrarisc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com header.b="mw7sp3cq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ultrarisc.com; s=dkim; h=Received:From:To:Cc:Subject:Date: Message-Id:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding; bh=4HuF45kaCua5XxLzD235BdFaTg40woHG3w Kmj9GKF40=; b=mw7sp3cqNwM+0h8QMe0eVtP+AWVci1rW9Sx0as5XXoe0cpt6a3 L+laQCJjHiZV7U5VlL94q6Ex6hDXCVF4imR7d9jZliER5Lr2L8D1mw6jTfOyDmb4 pQ8VbJ2hsXNZRj3d3H0MsqPLfT5XGmUJCfcliqt7lmWkYrc494SowKbVs= Received: from leopard.. (unknown [192.168.100.1]) by localhost.localdomain (Coremail) with SMTP id AQAAfwDHQAcKhZtqDUQAAA--.300S4; Sat, 05 Sep 2026 10:57:35 +0800 (CST) From: Xincheng Zhang To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= Cc: Rob Herring , Bjorn Helgaas , Jia Wang , Niklas Cassel , Frank Li , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Xincheng Zhang Subject: [PATCH v2 2/2] PCI: ultrarisc: Skip MEM outbound iATU setup on DP1000 Date: Sat, 5 Sep 2026 10:56:35 +0800 Message-Id: <20260905025635.211390-3-zhangxincheng@ultrarisc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260905025635.211390-1-zhangxincheng@ultrarisc.com> References: <20260905025635.211390-1-zhangxincheng@ultrarisc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwDHQAcKhZtqDUQAAA--.300S4 X-Coremail-Antispam: 1UD129KBjvJXoW7AF18Kr1kKw1UAFy5JF48tFb_yoW8CFWkpF 9rKw1UA3WDtFs8Ka1Iy3y8Z3WYvFsrAFWqgFnFkry7ua13u34UXryFkayYk3WDCwn5Zr1Y gr1YyryxJF13X37anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWUJVW8JwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkF7I0En4kS14v26r1q6r43MxkIecxEwVCm-wCF04k20xvY0x0EwIxGrwCFx2IqxVCF s4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r 1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWU JVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r 1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1U YxBIdaVFxhVjvjDU0xZFpf9x0JUQXo7UUUUU= X-CM-SenderInfo: x2kd0wp0lquxxhqjq3powut2xlvfhudrp/1tbiAQABDGqaaqQAMAAAsC Content-Type: text/plain; charset="utf-8" DP1000 has 16 outbound iATU windows and each window can map up to 4GB. One window is used for CFG accesses, one for I/O space and one for the 32-bit MEM aperture, leaving only 13 windows for the 64-bit MEM aperture. This limits the 64-bit MEM aperture that can be described with outbound iATU windows. DP1000 routes MEM transactions without using outbound iATU windows, so skip generic DWC MEM outbound iATU setup to allow a larger 64-bit MEM aperture. DP1000 does not use ECAM for this controller. Config space accesses keep using the normal DWC config access path and CFG outbound iATU programming. I/O space is also unchanged and still uses an outbound iATU window. The new flag only skips generic MEM-window programming. The DP1000 integration has SoC wrapper address decode for the PCIe MEM apertures described by the "ranges" property. CPU physical accesses to those MEM apertures are routed directly as PCIe MEM transactions with the corresponding PCIe bus address, without consuming outbound iATU windows. Set dw_pcie_rp::bypass_ob_mem_iatu for this controller. Signed-off-by: Xincheng Zhang --- drivers/pci/controller/dwc/pcie-ultrarisc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/cont= roller/dwc/pcie-ultrarisc.c index 51e89180490d4..0d4989a0f3afc 100644 --- a/drivers/pci/controller/dwc/pcie-ultrarisc.c +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c @@ -154,6 +154,12 @@ static int ultrarisc_pcie_probe(struct platform_device= *pdev) =20 pp =3D &pci->pp; =20 + /* + * DP1000 routes MEM transactions without outbound iATU windows, which + * avoids the 16-window/4GB-per-window aperture limit. + */ + pp->bypass_ob_mem_iatu =3D true; + platform_set_drvdata(pdev, ultra); =20 ret =3D ultrarisc_pcie_init_clks(ultra); --=20 2.34.1