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Fri, 04 Sep 2026 05:55:52 -0700 (PDT) Received: from localhost.localdomain ([78.40.184.2]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b61669aedesm524025e87.10.2026.09.04.05.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 05:55:51 -0700 (PDT) From: Roman Demidov To: Rob Clark Cc: Roman Demidov , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, lvc-project@linuxtesting.org Subject: [PATCH] drm/msm/a6xx: check pm_runtime_resume_and_get() during resume Date: Fri, 4 Sep 2026 15:55:21 +0300 Message-ID: <20260904125523.43813-1-roman.demidov.nn@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The return values of pm_runtime_resume_and_get() calls in a6xx_pm_resume() are not checked, which can lead to hardware access on suspended devices and PM reference underflows. Fix this by checking the return value of each pm_runtime_resume_and_get() call and properly unwinding the previously acquired resources on failure. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 5a903a44a984 ("drm/msm/a6xx: Introduce GMU wrapper support") Signed-off-by: Roman Demidov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 +++++++++++++++------------ 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index f9de9329dee3..0cf205ea744b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2175,44 +2175,48 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) opp =3D dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); if (IS_ERR(opp)) { ret =3D PTR_ERR(opp); - goto err_set_opp; + goto err_unlock; } dev_pm_opp_put(opp); =20 /* Set the core clock and bus bw, having VDD scaling in mind */ dev_pm_opp_set_opp(&gpu->pdev->dev, opp); =20 - pm_runtime_resume_and_get(gmu->dev); - pm_runtime_resume_and_get(gmu->gxpd); + ret =3D pm_runtime_resume_and_get(gmu->dev); + if (ret < 0) + goto err_opp_clear; + ret =3D pm_runtime_resume_and_get(gmu->gxpd); + if (ret < 0) + goto err_put_dev; =20 ret =3D clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); if (ret) - goto err_bulk_clk; + goto err_put_gxpd; =20 ret =3D clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); if (ret) { clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); - goto err_bulk_clk; + goto err_put_gxpd; } =20 if (adreno_is_a619_holi(adreno_gpu)) a6xx_sptprac_enable(gmu); =20 - /* If anything goes south, tear the GPU down piece by piece.. */ - if (ret) { -err_bulk_clk: - pm_runtime_put(gmu->gxpd); - pm_runtime_put(gmu->dev); - dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); - } -err_set_opp: mutex_unlock(&a6xx_gpu->gmu.lock); + msm_devfreq_resume(gpu); + a6xx_llc_activate(a6xx_gpu); =20 - if (!ret) { - msm_devfreq_resume(gpu); - a6xx_llc_activate(a6xx_gpu); - } + return 0; =20 + /* If anything goes south, tear the GPU down piece by piece.. */ +err_put_gxpd: + pm_runtime_put(gmu->gxpd); +err_put_dev: + pm_runtime_put(gmu->dev); +err_opp_clear: + dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); +err_unlock: + mutex_unlock(&a6xx_gpu->gmu.lock); return ret; } =20 --=20 2.53.0