From nobody Sat Sep 26 04:38:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29A3C492520; Fri, 4 Sep 2026 12:54:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788526481; cv=none; b=PXFQECohwscThWD+5strcO4DW6tGRIyL4APbamdQy5jK3qCS0mO6XZVR59Xo7V+kD6MdhUT0oKkd9n+50nGa1xdaNhKqor1TChCO34fgfkOTc+Bs9OTghzvStH2zfg6VDoPeXCg/pod3w+vNpXAJ8PuwDCB2Pxq6SnONzSSHISg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788526481; c=relaxed/simple; bh=hFtBdyoGhAuxW1TmQ1MzcHVKcuOGGi098ALkVBJlfQo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pKEPef2xO19YSeoH8j4lLzozOPPXs2j4R6R44/tjdMI97+mO4vFo0CdThP70sL3seJqpoCbDWAAP+c2WO01J2Y7DCuOxcY2LwudydHQyghysE8duq+k0GBv6FOweUN/AepV7n6l3AmUqxSAnQYkSUr8VKYCAdekknflCrfbXXPE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6F691F00A3E; Fri, 4 Sep 2026 12:54:35 +0000 (UTC) From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v7 1/5] pinctrl: renesas: rzg2l: Generalize the power source code Date: Fri, 4 Sep 2026 15:54:21 +0300 Message-ID: <20260904125425.412632-2-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260904125425.412632-1-claudiu.beznea+renesas@tuxon.dev> References: <20260904125425.412632-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The current functions used to get/set the pin power source check the OTHER_POC register, which is specific to the RZ/G3L SoC only. To allow the code to be extended for other power source functionalities (e.g. I3C on RZ/G3S), generalize the functions used to get/set the pin power source. For this, introduce the struct rzg2l_register_masks data structure whose purpose is to store SoC specific register bit masks. The members of this structure are then used in rzg2l_caps_to_pwr_reg() to retrieve the bitmask corresponding to a SoC specific power source capability. The conversion between HW specific power source values and SW specific power source values is now handled through rzg2l_pwr_reg_val_to_ps() and rzg2l_ps_to_pwr_reg_val(). Finally, to keep the code generic, the register update in rzg2l_set_power_source() was changed to a read-modify-write approach to cover all cases. Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v7: - none Changes in v6: - collected tags - rebased on top of the latest next Changes in v5: - in function rzg2l_ps_to_pwr_reg_val() return power source register value or negative error; due to this, in rzg2l_set_power_source() dropped the val local variable and use ret instead; due to this, to be able to use ret on register setup, moved the rzg2l_ps_to_pwr_reg_va= l() call after rzg2l_caps_to_pwr_reg() - dropped the tags - collected tags Changes in v4: - none Changes in v3: - collected tags Changes in v2: - none drivers/pinctrl/renesas/pinctrl-rzg2l.c | 182 +++++++++++++++--------- 1 file changed, 114 insertions(+), 68 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index e3e24ce917c9..40bf8f9e8f2f 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -187,6 +187,7 @@ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ #define PVDD_3300 0 /* I/O domain voltage >=3D 3.3V */ +#define PVDD_MASK 0x3 =20 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ @@ -271,6 +272,23 @@ struct rzg2l_register_offsets { u16 other_poc; }; =20 +/** + * struct rzg2l_register_masks - Masks for different RZ/G2L pinctrl functi= onalities + * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask + * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask + * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask + */ +struct rzg2l_register_masks { + union { + /* RZ/G3L masks */ + struct { + u8 other_poc_pvdd1833_oth_awo_poc; + u8 other_poc_pvdd1833_oth_iso_poc; + u8 other_poc_wdtovf_n_poc; + }; + }; +}; + /** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source @@ -291,6 +309,8 @@ enum rzg2l_iolh_index { /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @masks: hardware specific masks for various functionalities available in + * the registers described by regs * @iolh_groupa_ua: IOLH group A uA specific values * @iolh_groupb_ua: IOLH group B uA specific values * @iolh_groupc_ua: IOLH group C uA specific values @@ -304,6 +324,7 @@ enum rzg2l_iolh_index { */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + const struct rzg2l_register_masks masks; u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; @@ -1064,29 +1085,74 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinct= rl *pctrl, u32 offset, } =20 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, - u32 caps, u8 *mask) -{ - if (caps & PIN_CFG_IO_VMC_SD0) - return SD_CH(regs->sd_ch, 0); - if (caps & PIN_CFG_IO_VMC_SD1) - return SD_CH(regs->sd_ch, 1); - if (caps & PIN_CFG_IO_VMC_SD2) - return regs->sd_ch2; - if (caps & PIN_CFG_IO_VMC_ETH0) - return ETH_POC(regs->eth_poc, 0); - if (caps & PIN_CFG_IO_VMC_ETH1) - return ETH_POC(regs->eth_poc, 1); - if (caps & PIN_CFG_IO_VMC_QSPI) - return QSPI; + const struct rzg2l_register_masks *masks, + u32 caps, u16 *offset, u8 *mask) +{ + *mask =3D PVDD_MASK; + + if (caps & PIN_CFG_IO_VMC_SD0) { + *offset =3D SD_CH(regs->sd_ch, 0); + return 0; + } + if (caps & PIN_CFG_IO_VMC_SD1) { + *offset =3D SD_CH(regs->sd_ch, 1); + return 0; + } + if (caps & PIN_CFG_IO_VMC_SD2) { + *offset =3D regs->sd_ch2; + return 0; + } + if (caps & PIN_CFG_IO_VMC_ETH0) { + *offset =3D ETH_POC(regs->eth_poc, 0); + return 0; + } + if (caps & PIN_CFG_IO_VMC_ETH1) { + *offset =3D ETH_POC(regs->eth_poc, 1); + return 0; + } + if (caps & PIN_CFG_IO_VMC_QSPI) { + *offset =3D regs->qspi; + return 0; + } if (caps & PIN_CFG_OTHER_POC_MASK) { + *offset =3D regs->other_poc; if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) - *mask =3D BIT(0); + *mask =3D masks->other_poc_pvdd1833_oth_awo_poc; else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) - *mask =3D BIT(1); + *mask =3D masks->other_poc_pvdd1833_oth_iso_poc; else - *mask =3D BIT(2); + *mask =3D masks->other_poc_wdtovf_n_poc; + return 0; + } + + return -EINVAL; +} + +static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) +{ + switch (val) { + case PVDD_1800: + return 1800; + case PVDD_2500: + return 2500; + case PVDD_3300: + return 3300; + } =20 - return OTHER_POC; + return -EINVAL; +} + +static int rzg2l_ps_to_pwr_reg_val(u32 ps, u32 caps) +{ + switch (ps) { + case 1800: + return PVDD_1800; + case 2500: + if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) + return -EINVAL; + return PVDD_2500; + case 3300: + return PVDD_3300; } =20 return -EINVAL; @@ -1096,76 +1162,51 @@ static int rzg2l_get_power_source(struct rzg2l_pinc= trl *pctrl, u32 pin, u32 caps { const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - u8 val, mask; - int pwr_reg; + const struct rzg2l_register_masks *masks =3D &hwcfg->masks; + u8 mask, val; + u16 offset; + int ret; =20 if (caps & PIN_CFG_SOFT_PS) return pctrl->settings[pin].power_source; =20 - pwr_reg =3D rzg2l_caps_to_pwr_reg(regs, caps, &mask); - if (pwr_reg < 0) - return pwr_reg; + ret =3D rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask); + if (ret) + return ret; =20 - val =3D readb(pctrl->base + pwr_reg); - if (pwr_reg =3D=3D OTHER_POC) - val =3D field_get(mask, val); + val =3D readb(pctrl->base + offset); =20 - switch (val) { - case PVDD_1800: - return 1800; - case PVDD_2500: - return 2500; - case PVDD_3300: - return 3300; - default: - /* Should not happen. */ - return -EINVAL; - } + return rzg2l_pwr_reg_val_to_ps(field_get(mask, val), caps); } =20 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u3= 2 caps, u32 ps) { const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - u8 poc_val, val, mask; - int pwr_reg; + const struct rzg2l_register_masks *masks =3D &hwcfg->masks; + u16 offset; + u8 mask; + int ret; =20 if (caps & PIN_CFG_SOFT_PS) { pctrl->settings[pin].power_source =3D ps; return 0; } =20 - switch (ps) { - case 1800: - poc_val =3D PVDD_1800; - break; - case 2500: - if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) - return -EINVAL; - poc_val =3D PVDD_2500; - break; - case 3300: - poc_val =3D PVDD_3300; - break; - default: - return -EINVAL; - } + ret =3D rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask); + if (ret) + return ret; + + ret =3D rzg2l_ps_to_pwr_reg_val(ps, caps); + if (ret < 0) + return ret; =20 - pwr_reg =3D rzg2l_caps_to_pwr_reg(regs, caps, &mask); - if (pwr_reg < 0) - return pwr_reg; + scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { + u8 tmp =3D readb(pctrl->base + offset); =20 - if (pwr_reg =3D=3D OTHER_POC) { - scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { - val =3D readb(pctrl->base + pwr_reg); - if (poc_val) - val |=3D mask; - else - val &=3D ~mask; - writeb(val, pctrl->base + pwr_reg); - } - } else { - writeb(poc_val, pctrl->base + pwr_reg); + tmp &=3D ~mask; + tmp |=3D field_prep(mask, ret); + writeb(tmp, pctrl->base + offset); } =20 pctrl->settings[pin].power_source =3D ps; @@ -3821,6 +3862,11 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { .oen =3D 0x3018, .other_poc =3D OTHER_POC, }, + .masks =3D { + .other_poc_pvdd1833_oth_awo_poc =3D BIT(0), + .other_poc_pvdd1833_oth_iso_poc =3D BIT(1), + .other_poc_wdtovf_n_poc =3D BIT(2), + }, .iolh_groupa_ua =3D { /* 1v8 power source */ [RZG2L_IOLH_IDX_1V8] =3D 2200, 4400, 9000, 10000, --=20 2.43.0 From nobody Sat Sep 26 04:38:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D72A493625; Fri, 4 Sep 2026 12:54:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788526483; cv=none; b=gf7/P9ZdqJv7lgUS/xQi0Jz24uYr9eavvTctycjFRi6fSUxMtk1LU08JI6FW+7Eo8Mt/TWdJ25S3EYcW0gMkcrNB057UgY/VS6w8P2AIXfgEQaHE61XVnoMfsPNtWQqhYTnfqfaiR0/Su1i53oT29cj7v+L06tS7cIKf83qxtjg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788526483; c=relaxed/simple; bh=EZHUuCYC13eTwTAd6rF9n/kwhRy2E8mK4oirydJdfiU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dAQlWS867hcW0GtQPZ3DkRNxhSmpCTI90QZ4YPb01u78M58DmaGprcgsdBeP8QC3zODH8CdSfQZhCP5tqPguiJJD0n6OcTcpcK3FJtvCmt29RKr9D3GD3njWmb+FjhKsRdZK99EKnFTGirGcI+dSsGxbmG65qIjZgGzsu8pHuyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 098F41F00ACF; Fri, 4 Sep 2026 12:54:38 +0000 (UTC) From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v7 2/5] pinctrl: renesas: rzg2l: Drop defines present in struct rzg2l_hwcfg Date: Fri, 4 Sep 2026 15:54:22 +0300 Message-ID: <20260904125425.412632-3-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260904125425.412632-1-claudiu.beznea+renesas@tuxon.dev> References: <20260904125425.412632-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Drop the QSPI and OTHER_POC register defines, which are SoC specific and accessible through struct rzg2l_hwcfg::{qspi, other_poc}. While at it move the assignement of rzg2l_hwcfg->regs->qspi upper to have the initializations as sorted (by offsets) as possible. Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v7: - none Changes in v6: - collected tags Changes in v5: - collected tags Changes in v4: - none Changes in v3: - updated patch description - collected tags Changes in v2: - none drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 40bf8f9e8f2f..c17983aafcf5 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -181,8 +181,6 @@ #define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) -#define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */ -#define OTHER_POC (0x3028) /* known on RZ/G3L only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -3840,9 +3838,9 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg =3D { .regs =3D { .pwpr =3D 0x3014, .sd_ch =3D 0x3000, + .qspi =3D 0x3008, .eth_poc =3D 0x300c, .oen =3D 0x3018, - .qspi =3D QSPI, }, .iolh_groupa_ua =3D { /* 3v3 power source */ @@ -3860,7 +3858,7 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { .sd_ch2 =3D 0x3024, .eth_poc =3D 0x3010, .oen =3D 0x3018, - .other_poc =3D OTHER_POC, + .other_poc =3D 0x3028, }, .masks =3D { .other_poc_pvdd1833_oth_awo_poc =3D BIT(0), --=20 2.43.0 From nobody Sat Sep 26 04:38:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01EEC494A14; Fri, 4 Sep 2026 12:54:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788526488; cv=none; b=HSso6Txve6gW2PxA+gybQbvfrsfX3TFy5T/OsxwsjMmlpcG1Zjp7dysvePMswwMUmhSt95NYRmT2eZnc4lIqUDjc38+cl+g0YsraarCUrtGlVOP1S6GkJRllshwdPsSAJcm9b5D6UyzovXDW1SXqWXMq9bmwQbNmWKAgc4eRu/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788526488; c=relaxed/simple; bh=ZiVcTUeMITmXTlGAz2bBUq802YDnbmeJup+b/WKFkuo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RVxijCFfCc4MsK550qo+dNsvZ7rR582DsGi1c5z/lA21DPssxwW7KhM2eW1YdItnynDPzYf8A1Ujl09mW5rfCirD3uj3Wjuor4ce2lnslRjk95SPyuawuVw6W9G8XrKn0qZnZFiuhzgD+qMrTT1lKacOitVCXkbw50b2HWObeGs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4FB841F00AC4; Fri, 4 Sep 2026 12:54:42 +0000 (UTC) From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v7 3/5] pinctrl: renesas: rzg2l: Unify the power source handling Date: Fri, 4 Sep 2026 15:54:23 +0300 Message-ID: <20260904125425.412632-4-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260904125425.412632-1-claudiu.beznea+renesas@tuxon.dev> References: <20260904125425.412632-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The previous code handled power sources using a mixture of power source specific definitions and lookups in the available_ps[] array. Unify the power source handling by introducing struct rzg2l_pinctrl_ps_desc, whose purpose is to describe a power source through its power source value, associated register value, associated capabilities (e.g. Ethernet), and associated IOLH index. Introduce two new functions, rzg2l_ps_to_desc() and rzg2l_pwr_reg_val_to_desc(), using the RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC() macro, as their implementations are similar. These functions retrieve a power source descriptor based on either a power source value or a power source register value. Other functions that need to perform power source specific operations can call them to retrieve the corresponding power source descriptor. The register values for the soft power sources were kept to zero since they are not used across the driver's code. Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v7: - collected tags - dropped 2.5V voltage domains for SDHI and QSPI Changes in v6: - described all the available power sources in the available_ps[] array and dropped to wildcard approach to avoid letting the user selecting unavailable power source for pins - simplified RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC() - for these two points ^ didn't collect the Wolfram's Tb tag - dropped rzg2l_ps_is_supported() - used conditional operator in rzg2l_ps_to_iolh_idx() - adjusted the patch description Changes in v5: - none, this patch is new drivers/pinctrl/renesas/pinctrl-rzg2l.c | 162 ++++++++++++++++-------- 1 file changed, 108 insertions(+), 54 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index c17983aafcf5..6696e32909c3 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -182,9 +182,6 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) =20 -#define PVDD_2500 2 /* I/O domain voltage 2.5V */ -#define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ -#define PVDD_3300 0 /* I/O domain voltage >=3D 3.3V */ #define PVDD_MASK 0x3 =20 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ @@ -289,12 +286,14 @@ struct rzg2l_register_masks { =20 /** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays + * @RZG2L_IOLH_IDX_NA: index N/A (to be used for error checking) * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source * @RZG2L_IOLH_IDX_MAX: maximum index */ enum rzg2l_iolh_index { + RZG2L_IOLH_IDX_NA =3D -1, RZG2L_IOLH_IDX_1V8 =3D 0, RZG2L_IOLH_IDX_2V5 =3D 4, RZG2L_IOLH_IDX_3V3 =3D 8, @@ -445,7 +444,85 @@ struct rzg2l_pinctrl { u32 clone_offset; }; =20 -static const u16 available_ps[] =3D { 1800, 2500, 3300 }; +/** + * struct rzg2l_pinctrl_ps_desc - RZ/G2L power source descriptor + * @caps: Capabilities that applies to the power source + * @iolh_index: IOLH index + * @ps: Power source value + * @pwr_reg_val: Power source register value + */ +struct rzg2l_pinctrl_ps_desc { + u32 caps; + enum rzg2l_iolh_index iolh_index; + u16 ps; + u16 pwr_reg_val; +}; + +#define RZG2L_PINCTRL_PS_DESC(_ps, _pwr_reg_val, _caps, _iolh_index) \ + { \ + .ps =3D _ps, \ + .pwr_reg_val =3D _pwr_reg_val, \ + .caps =3D _caps, \ + .iolh_index =3D _iolh_index, \ + } + +static const struct rzg2l_pinctrl_ps_desc available_ps[] =3D { + /* Ethernet I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1, + RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(2500, 2, PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1, + RZG2L_IOLH_IDX_2V5), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1, + RZG2L_IOLH_IDX_3V3), + + /* SD I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_IO_VMC_SD0 | PIN_CFG_IO_VMC_SD1 | + PIN_CFG_IO_VMC_SD2, RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_IO_VMC_SD0 | PIN_CFG_IO_VMC_SD1 | + PIN_CFG_IO_VMC_SD2, RZG2L_IOLH_IDX_3V3), + + /* QSPI I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_IO_VMC_QSPI, RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_IO_VMC_QSPI, RZG2L_IOLH_IDX_3V3), + + /* AWO I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_PVDD1833_OTH_AWO_POC, + RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_PVDD1833_OTH_AWO_POC, + RZG2L_IOLH_IDX_3V3), + + /* ISO I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_PVDD1833_OTH_ISO_POC, + RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_PVDD1833_OTH_ISO_POC, + RZG2L_IOLH_IDX_3V3), + + /* WDTOVF I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_WDTOVF_N_POC, RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_WDTOVF_N_POC, RZG2L_IOLH_IDX_3V3), + + /* Software voltage domains */ + RZG2L_PINCTRL_PS_DESC(1800, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_1V8), + RZG2L_PINCTRL_PS_DESC(2500, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_2V5), + RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_3V3), +}; + +#define RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC(_name, _desc_member, _ca= ps) \ +static const struct rzg2l_pinctrl_ps_desc *_name(u16 _desc_member, u32 _ca= ps) \ +{ \ + for (unsigned int i =3D 0; i < ARRAY_SIZE(available_ps); i++) { \ + if (available_ps[i]._desc_member !=3D _desc_member) \ + continue; \ + \ + if (available_ps[i].caps & _caps) \ + return &available_ps[i]; \ + } \ + \ + return NULL; \ +} + +RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC(rzg2l_ps_to_desc, ps, caps) +RZG2L_PINCTRL_PS_DESC_MEMBER_TO_DESC_FUNC(rzg2l_pwr_reg_val_to_desc, pwr_r= eg_val, caps) =20 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, u64 pincfg, @@ -1126,34 +1203,26 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l= _register_offsets *regs, return -EINVAL; } =20 -static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) +static int rzg2l_pwr_reg_val_to_ps(u16 pwr_reg_val, u32 caps) { - switch (val) { - case PVDD_1800: - return 1800; - case PVDD_2500: - return 2500; - case PVDD_3300: - return 3300; - } + const struct rzg2l_pinctrl_ps_desc *desc; =20 - return -EINVAL; + desc =3D rzg2l_pwr_reg_val_to_desc(pwr_reg_val, caps); + if (!desc) + return -EINVAL; + + return desc->ps; } =20 -static int rzg2l_ps_to_pwr_reg_val(u32 ps, u32 caps) +static int rzg2l_ps_to_pwr_reg_val(u16 ps, u32 caps) { - switch (ps) { - case 1800: - return PVDD_1800; - case 2500: - if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) - return -EINVAL; - return PVDD_2500; - case 3300: - return PVDD_3300; - } + const struct rzg2l_pinctrl_ps_desc *desc; =20 - return -EINVAL; + desc =3D rzg2l_ps_to_desc(ps, caps); + if (!desc) + return -EINVAL; + + return desc->pwr_reg_val; } =20 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u3= 2 caps) @@ -1212,32 +1281,11 @@ static int rzg2l_set_power_source(struct rzg2l_pinc= trl *pctrl, u32 pin, u32 caps return 0; } =20 -static bool rzg2l_ps_is_supported(u16 ps) +static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps, u32 caps) { - unsigned int i; + const struct rzg2l_pinctrl_ps_desc *desc =3D rzg2l_ps_to_desc(ps, caps); =20 - for (i =3D 0; i < ARRAY_SIZE(available_ps); i++) { - if (available_ps[i] =3D=3D ps) - return true; - } - - return false; -} - -static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) -{ - unsigned int i; - - for (i =3D 0; i < ARRAY_SIZE(available_ps); i++) { - if (available_ps[i] =3D=3D ps) - break; - } - - /* - * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have - * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source - */ - return i * RZG2L_IOLH_MAX_DS_ENTRIES; + return desc ? desc->iolh_index : RZG2L_IOLH_IDX_NA; } =20 static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps,= u8 val) @@ -1622,7 +1670,11 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_= dev *pctldev, ret =3D rzg2l_get_power_source(pctrl, _pin, cfg); if (ret < 0) return ret; - iolh_idx =3D rzg2l_ps_to_iolh_idx(ret); + + iolh_idx =3D rzg2l_ps_to_iolh_idx(ret, cfg); + if (iolh_idx =3D=3D RZG2L_IOLH_IDX_NA) + return -EINVAL; + val =3D rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); arg =3D rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); break; @@ -1818,8 +1870,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_d= ev *pctldev, =20 /* Apply power source. */ if (settings.power_source !=3D pctrl->settings[_pin].power_source) { - ret =3D rzg2l_ps_is_supported(settings.power_source); - if (!ret) + if (!rzg2l_ps_to_desc(settings.power_source, cfg)) return -EINVAL; =20 /* Apply power source. */ @@ -1833,7 +1884,10 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_= dev *pctldev, enum rzg2l_iolh_index iolh_idx; int val; =20 - iolh_idx =3D rzg2l_ps_to_iolh_idx(settings.power_source); + iolh_idx =3D rzg2l_ps_to_iolh_idx(settings.power_source, cfg); + if (iolh_idx =3D=3D RZG2L_IOLH_IDX_NA) + return -EINVAL; + ret =3D rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, settings.drive_strength_ua); if (!ret) --=20 2.43.0 From nobody Sat Sep 26 04:38:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE7E7492520; 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charset="utf-8" From: Claudiu Beznea The I3C pins on the Renesas RZ/G3S SoC can be powered at either 1.2V or 1.8V. Document the missing 1.2V power source option. Acked-by: Conor Dooley Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v7: - none Changes in v6: - none (the Wolfram's Tb tag was not applied to this version since, based on previous discussions, the tag don't apply to a binding patch). Changes in v5: - collected tags Changes in v4: - none Changes in v3: - collected tags Changes in v2: - collected tags .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index fb1fe1ea759f..32864c9add4a 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -129,7 +129,7 @@ additionalProperties: enum: [ 33, 50, 66, 100 ] power-source: description: I/O voltage in millivolt. - enum: [ 1800, 2500, 3300 ] + enum: [ 1200, 1800, 2500, 3300 ] slew-rate: true gpio-hog: true gpios: true --=20 2.43.0 From nobody Sat Sep 26 04:38:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D5EC493633; Fri, 4 Sep 2026 12:54:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788526494; cv=none; b=D0zg5d9+xk779BG7htt8iB5Ft7p+fDAt20T51Vf7mLym9BkPF2MQwZgr994elKyiUaKJPVJlHrIvByBQ5K9av3KfixlW5HZMLgIUz/MK2kEyyuwOT17Dz2Z4SHh52W6LOtCB+4htTlP/KvbQWY6jxhoUI2/Kp0UMcRcQ5TYhcJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788526494; c=relaxed/simple; bh=hGvlZUn7/Ambf9YcNv/eAm7mw97nQrTLcReNYt6Uk4I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iLevpTQ7BsRrLwqydDtVALvW3Sd99pst9b3FMyw79LuZ9ECnUtSY8lVKTKkh/UxgAw0M0zuH8N60vfh2wat5KRYwv3QK7DNlsrFOwVNvFHyZ+8qRNOKkDjSMocsdiTu8bWybOOvOly12FAyR8aAhyi+V8q6z2sp2xtX5Ek26QbU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30C1A1F00A3E; Fri, 4 Sep 2026 12:54:49 +0000 (UTC) From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v7 5/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source Date: Fri, 4 Sep 2026 15:54:25 +0300 Message-ID: <20260904125425.412632-6-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260904125425.412632-1-claudiu.beznea+renesas@tuxon.dev> References: <20260904125425.412632-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V. The pin controller provides a register to select between these two options. Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S SoC. Tested-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v7: - collected tags Changes in v6: - used bit 23 to define PIN_CFG_IO_VMC_I3C - described the I3C power sources according to the new method; due to this didn't collect the Wolfram's Tb tag. Changes in v5: - due to patch 3 from this series: -- dropped the definitions for PVDD_I3C_1200, PVDD_I3C_1800 -- dropped available_i3c_ps[] array and fill everything in available_ps[] -- dropped the adjustments from rzg2l_pwr_reg_val_to_ps() and rzg2l_ps_to_pwr_reg_val(), rzg2l_ps_is_supported() and rzg2l_pinctrl_pinconf_set() -- dropped the tags Changes in v4: - none Changes in v3: - collected tags Changes in v2: - none drivers/pinctrl/renesas/pinctrl-rzg2l.c | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 6696e32909c3..9bf3743dc1ce 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -70,6 +70,7 @@ #define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ #define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ #define PIN_CFG_IO_VMC_SD2 BIT(22) /* known on RZ/G3L only */ +#define PIN_CFG_IO_VMC_I3C BIT(23) =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ @@ -256,6 +257,7 @@ static const struct pin_config_item renesas_rzv2h_conf_= items[] =3D { * @oen: OEN register offset * @qspi: QSPI register offset * @other_poc: OTHER_POC register offset + * @i3c_set: I3C_SET register offset */ struct rzg2l_register_offsets { u16 pwpr; @@ -265,6 +267,7 @@ struct rzg2l_register_offsets { u16 oen; u16 qspi; u16 other_poc; + u16 i3c_set; }; =20 /** @@ -272,6 +275,7 @@ struct rzg2l_register_offsets { * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask + * @i3c_set_poc: I3C_SET_POC mask */ struct rzg2l_register_masks { union { @@ -281,6 +285,11 @@ struct rzg2l_register_masks { u8 other_poc_pvdd1833_oth_iso_poc; u8 other_poc_wdtovf_n_poc; }; + + /* RZ/G3S masks */ + struct { + u8 i3c_set_poc; + }; }; }; =20 @@ -394,6 +403,7 @@ struct rzg2l_pinctrl_pin_settings { * @oen: Output Enable register cache * @other_poc: OTHER_POC register cache * @qspi: QSPI registers cache + * @i3c_set: I3C_SET register cache */ struct rzg2l_pinctrl_reg_cache { u8 *p; @@ -413,6 +423,7 @@ struct rzg2l_pinctrl_reg_cache { u8 oen; u8 other_poc; u8 qspi; + u8 i3c_set; }; =20 struct rzg2l_pinctrl { @@ -501,6 +512,10 @@ static const struct rzg2l_pinctrl_ps_desc available_ps= [] =3D { RZG2L_PINCTRL_PS_DESC(1800, 1, PIN_CFG_WDTOVF_N_POC, RZG2L_IOLH_IDX_1V8), RZG2L_PINCTRL_PS_DESC(3300, 0, PIN_CFG_WDTOVF_N_POC, RZG2L_IOLH_IDX_3V3), =20 + /* I3C I/O voltage domains */ + RZG2L_PINCTRL_PS_DESC(1200, 1, PIN_CFG_IO_VMC_I3C, RZG2L_IOLH_IDX_NA), + RZG2L_PINCTRL_PS_DESC(1800, 0, PIN_CFG_IO_VMC_I3C, RZG2L_IOLH_IDX_NA), + /* Software voltage domains */ RZG2L_PINCTRL_PS_DESC(1800, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_1V8), RZG2L_PINCTRL_PS_DESC(2500, 0, PIN_CFG_SOFT_PS, RZG2L_IOLH_IDX_2V5), @@ -1199,6 +1214,11 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_= register_offsets *regs, *mask =3D masks->other_poc_wdtovf_n_poc; return 0; } + if (caps & PIN_CFG_IO_VMC_I3C) { + *offset =3D regs->i3c_set; + *mask =3D masks->i3c_set_poc; + return 0; + } =20 return -EINVAL; } @@ -2570,6 +2590,8 @@ static const struct rzg2l_dedicated_configs rzg3s_ded= icated_pins[] =3D { { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) }, { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) }, { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_C= FG_SOFT_PS) }, + { "I3C_SDA", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C)) }, + { "I3C_SCL", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C)) }, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_= VMC_SD0)) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN= | PIN_CFG_IO_VMC_SD0)) }, @@ -3792,6 +3814,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); if (regs->other_poc) cache->other_poc =3D readb(pctrl->base + regs->other_poc); + if (regs->i3c_set) + cache->i3c_set =3D readb(pctrl->base + regs->i3c_set); =20 if (pctrl->syscon) { int ret; @@ -3834,6 +3858,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) writeb(cache->qspi, pctrl->base + regs->qspi); if (regs->other_poc) writeb(cache->other_poc, pctrl->base + regs->other_poc); + if (regs->i3c_set) + writeb(cache->i3c_set, pctrl->base + regs->i3c_set); =20 raw_spin_lock_irqsave(&pctrl->lock, flags); rzg2l_oen_write_with_pwpr(pctrl, cache->oen); @@ -3950,8 +3976,12 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .pwpr =3D 0x3000, .sd_ch =3D 0x3004, .eth_poc =3D 0x3010, + .i3c_set =3D 0x301c, .oen =3D 0x3018, }, + .masks =3D { + .i3c_set_poc =3D BIT(2), + }, .iolh_groupa_ua =3D { /* 1v8 power source */ [RZG2L_IOLH_IDX_1V8] =3D 2200, 4400, 9000, 10000, --=20 2.43.0