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(unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgDXKPWxYppqN_NZPw--.57876S2; Fri, 04 Sep 2026 14:18:25 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: jingoohan1@gmail.com, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org Cc: robh@kernel.org, a-garg7@ti.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com>, Feizhou Yu Subject: [PATCH] pci: dwc: Rename PCIE_PORT_LINK_CONTROL to PORT_LINK_CTRL_OFF Date: Fri, 4 Sep 2026 14:18:23 +0800 Message-ID: <20260904061823.592216-1-18255117159@163.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgDXKPWxYppqN_NZPw--.57876S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxuFyrAFy3Xr1ktFWUtFW3GFg_yoW5Cw4fpa y5tryFkF1DAa13Z3WYka4kZF1aq3ZxArWUGFs2gwnru3WfAry0gw18XFy3tr97XFWxtr4Y kr17ta47JFyfA3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUjPfPUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7BIGqWqaYrLRiwAA3r Content-Type: text/plain; charset="utf-8" The register at offset 0x710 is documented in the Synopsys DesignWare PCIe Controller Reference Manual as "PORT_LINK_CTRL_OFF" (Port Link Control Register). The current macro name PCIE_PORT_LINK_CONTROL does not match the documentation, making it difficult to cross-reference with the spec when debugging or maintaining the code. Rename the macro to PORT_LINK_CTRL_OFF to align with the Synopsys documentation, and update all usage sites accordingly. No functional change is intended. This improves code maintainability and eases future reference to the controller manual. Co-developed-by: Feizhou Yu Signed-off-by: Feizhou Yu Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware.c | 8 ++++---- drivers/pci/controller/dwc/pcie-designware.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 593388f29bdd..9a0d8f0be792 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -894,7 +894,7 @@ static void dw_pcie_link_set_max_link_width(struct dw_p= cie *pci, u32 num_lanes) return; =20 /* Set the number of lanes */ - plc =3D dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); + plc =3D dw_pcie_readl_dbi(pci, PORT_LINK_CTRL_OFF); plc &=3D ~PORT_LINK_FAST_LINK_MODE; plc &=3D ~PORT_LINK_MODE_MASK; =20 @@ -922,7 +922,7 @@ static void dw_pcie_link_set_max_link_width(struct dw_p= cie *pci, u32 num_lanes) dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); return; } - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); + dw_pcie_writel_dbi(pci, PORT_LINK_CTRL_OFF, plc); dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); =20 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -1295,10 +1295,10 @@ void dw_pcie_setup(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } =20 - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); + val =3D dw_pcie_readl_dbi(pci, PORT_LINK_CTRL_OFF); val &=3D ~PORT_LINK_FAST_LINK_MODE; val |=3D PORT_LINK_DLL_LINK_EN; - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); + dw_pcie_writel_dbi(pci, PORT_LINK_CTRL_OFF, val); =20 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 0735ae940924..77420230433b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -87,7 +87,7 @@ #define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27 #define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27) =20 -#define PCIE_PORT_LINK_CONTROL 0x710 +#define PORT_LINK_CTRL_OFF 0x710 #define PORT_LINK_DLL_LINK_EN BIT(5) #define PORT_LINK_FAST_LINK_MODE BIT(7) #define PORT_LINK_MODE_MASK GENMASK(21, 16) --=20 2.43.0