From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAB314F0549; Fri, 4 Sep 2026 15:58:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537529; cv=none; b=jf2RIRLVIMInSf7Jf70h8Hmm1bnonZkcQPK8wCxzg2lx9LfUsHgMTz0noXMAMxszzmGx5dRVM0zHb5DqU/o3isLSARMXdKl41e0Ipj7Y56UgmKBMV1cc+VlQzLwsetkSuzHTkxVRQJE30+xOu+ZZsdnuQ3Mb/wBIJj5UtW7Bn+c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537529; c=relaxed/simple; bh=rp96vQvpmzcYQQQawuTsiCW9FJPQfixEXB6+OjlKWjQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GLAUqVaZ5M02vvHeaG8XPyPOX6WUdre4nAkMlRt6zvNIowcfWg1zDMtP55RFqL7g0+uLFYGoFKJlXrk6LBFDktLNcp/WgSVHBAzATLRvg1NMjP/4XIgKQPieIbxXU+FVCRkBEgImqz6QQEaatAhO4tISL3Em7rhMKEB4Rg3zIYc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=hNseR17M; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="hNseR17M" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788537525; bh=rp96vQvpmzcYQQQawuTsiCW9FJPQfixEXB6+OjlKWjQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hNseR17Mr2FEeb7vpRS4ghWeyaEZjje7ZpG+YOxpbJTmU1zP4NKbrmqlmPx2ZCRTA 3vngaPHvBQTXjJFi1e59utE3AHU7iWD+J42nEKpLxqkq1Smh8zpKTdIDhQNDHwNov5 zBAnJj2zyT/jlGB26ZrEZx3AQcder/2vIa+oWS/r8n/OBwTolMgVdqYxuAxZJA6yIH 74Y6grh7tQOyZQ4CjUCLk15kpPZgxB3GmjoGEu+hfl08bRdQcVlsXWR/7tbP7X6OAE klkkS3i04YpYjWXKVtXgdj3tobPxxWo92c+Gq+S1sNgQlWT4cdLgyRBEPLSLMoUcwf Xez8zkb/TNOLA== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7102D17E092E; Fri, 04 Sep 2026 17:58:44 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:12 +0200 Subject: [PATCH v6 01/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-1-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Conor Dooley , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=1753; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=rp96vQvpmzcYQQQawuTsiCW9FJPQfixEXB6+OjlKWjQ=; b=8SAycckJbljlA++tM8/Zl3D8xPkyBNXedGFYjp8uxZtL1/v5djl2j5jekJ2JZYRPWnY85izZx MipjenfHAVCAx0UrhOhBDIMqs1i/2JhwfQ9aPs2CgMeBIA5MDEZ3pwB X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Both MT8186 clock controllers dt-bindings (clock and sys-clock) document the '#clock-cells' property but do not enforce it as required property. As clock provider nodes should define this property in devicetrees, add it to the required property list in both its dt-bindings files. Fixes: f113a51aa2cf ("dt-bindings: ARM: MediaTek: Add new document bindings= of MT8186 clock") Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml | 1= + Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml | 1= + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml index f4e58bfa504f..539149c945d0 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml @@ -44,6 +44,7 @@ properties: required: - compatible - reg + - '#clock-cells' =20 additionalProperties: false =20 diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cloc= k.yaml index 1c446fbc5108..f8acc02cafee 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml @@ -45,6 +45,7 @@ properties: required: - compatible - reg + - '#clock-cells' =20 additionalProperties: false =20 --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 596B04F0535; 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Fri, 04 Sep 2026 17:58:45 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:13 +0200 Subject: [PATCH v6 02/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-2-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Conor Dooley , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=1753; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=fUUtXLDjBk6CCgOqNBHxohDsqafdXykxd3de6nmxpT8=; b=aIjdsMEJzpueS6yVC7oUO/t9uSAatzb9wyY6+aXyIKgHKwk4Ql9sH6cN5up6Kmyuc3cj4qTNj 2KyFZeGz15QAtHZbsgi7ENriN7cA5fDt9qeyDucJimKKXUN1JMHVQwx X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Both MT8192 clock controllers dt-bindings (clock and sys-clock) document the '#clock-cells' property but do not enforce it as required property. As clock provider nodes should define this property in devicetrees, add it to the required property list in both its dt-bindings files. Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings= of MT8192 clock") Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml | 1= + Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml | 1= + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml index b8d690e28bdc..65e4c2fddf5b 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml @@ -46,6 +46,7 @@ properties: required: - compatible - reg + - '#clock-cells' =20 additionalProperties: false =20 diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-cloc= k.yaml index bf8c9aacdf1e..0ebd0d60e2f6 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml @@ -35,6 +35,7 @@ properties: required: - compatible - reg + - '#clock-cells' =20 additionalProperties: false =20 --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 901884F6473; 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Fri, 04 Sep 2026 17:58:47 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:14 +0200 Subject: [PATCH v6 03/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-3-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Conor Dooley , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=1753; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=m2yiWy5le2r+frQc8DgaYIgBdSKa3Pdp/bb9fJVyV0E=; b=1Q205bry8LCzKdRAN08IB2VG0Q/oataj2IJrc5YW1QC52QXClji4/giVbS32U+79GX6ryBFHN g2EfKkyHiD2AoLiAvUg1IRBP41GMql2gjYBzQ7t6z5q4N7kejTRLuaW X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Both MT8195 clock controllers dt-bindings (clock and sys-clock) document the '#clock-cells' property but do not enforce it as required property. As clock provider nodes should define this property in devicetrees, add it to the required property list in both its dt-bindings files. Fixes: 34d3ed3b9a00 ("dt-bindings: ARM: Mediatek: Add new document bindings= of MT8195 clock") Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml | 1= + Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml | 1= + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml index fcc963aff087..94dd29c2396c 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml @@ -58,6 +58,7 @@ properties: required: - compatible - reg + - '#clock-cells' =20 additionalProperties: false =20 diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-cloc= k.yaml index 69f096eb168d..ba1b36fa0169 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml @@ -43,6 +43,7 @@ properties: required: - compatible - reg + - '#clock-cells' =20 additionalProperties: false =20 --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC5944F30FC; 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Fri, 04 Sep 2026 17:58:48 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:15 +0200 Subject: [PATCH v6 04/27] dt-bindings: clock: mediatek: reorder MT8186 compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-4-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Conor Dooley , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=2561; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=3HvR2i0TeyW7ntE6wt26ah4Fl34lpJceNTjjoyWnRHM=; b=JcSw7/T9WbgeIvjqLLJHHfsNPqiszR8pn1ru20c5LJ4e21e40j1MdE++e9MvdmX2hDSUeTTv+ v+NVjpBs/3qA8/NKWx7FLGk3ymELYIhquT0AW71P9yetI/ZgmXOdVPn X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= In order to prepare regrouping several Mediatek SoC clock controller dt-bindings files into the MT8186 ones, reorder the MT8186 clock controller compatibles so they are sorted alphanumerically. Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- .../bindings/clock/mediatek,mt8186-clock.yaml | 17 +++++++++----= ---- .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 4 ++-- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml index 539149c945d0..756b937bb7c4 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml @@ -23,18 +23,19 @@ properties: compatible: items: - enum: - - mediatek,mt8186-imp_iic_wrap - - mediatek,mt8186-mfgsys - - mediatek,mt8186-wpesys - - mediatek,mt8186-imgsys1 - - mediatek,mt8186-imgsys2 - - mediatek,mt8186-vdecsys - - mediatek,mt8186-vencsys - mediatek,mt8186-camsys - mediatek,mt8186-camsys_rawa - mediatek,mt8186-camsys_rawb - - mediatek,mt8186-mdpsys + - mediatek,mt8186-imgsys1 + - mediatek,mt8186-imgsys2 + - mediatek,mt8186-imp_iic_wrap - mediatek,mt8186-ipesys + - mediatek,mt8186-mdpsys + - mediatek,mt8186-mfgsys + - mediatek,mt8186-vdecsys + - mediatek,mt8186-vencsys + - mediatek,mt8186-wpesys + reg: maxItems: 1 =20 diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cloc= k.yaml index f8acc02cafee..6733dafbde16 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml @@ -27,10 +27,10 @@ properties: compatible: items: - enum: + - mediatek,mt8186-apmixedsys + - mediatek,mt8186-infracfg_ao - mediatek,mt8186-mcusys - mediatek,mt8186-topckgen - - mediatek,mt8186-infracfg_ao - - mediatek,mt8186-apmixedsys - const: syscon =20 reg: --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70EB44FDE62; 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Fri, 04 Sep 2026 17:58:50 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:16 +0200 Subject: [PATCH v6 05/27] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-5-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Conor Dooley , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=9313; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=5biYHUgiVK09q5Z/FaZnJmBpPNku23Weol6v7oo8QhU=; b=WIlmlnH/+SRPz5U78ztsRhUY5j9JxVS4kGXTxUeNkZK1dOGkSUk9JCCt2NoktuwyTEPDdJadv ihddbZL3u1OBbi11LOvGQ4QFu5nHRZ+Cd9N4YFixwpDFbAm8fYljsYH X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Regroup the MT8188 clock and system clock dt-bindings into MT8186 ones to ease maintainability and have common files for several currently supported SoC or new future ones, that have the same kind of clock controller design. Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- .../bindings/clock/mediatek,mt8186-clock.yaml | 51 +++++++++++- .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 6 +- .../bindings/clock/mediatek,mt8188-clock.yaml | 93 ------------------= ---- .../bindings/clock/mediatek,mt8188-sys-clock.yaml | 58 -------------- 4 files changed, 55 insertions(+), 153 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml index 756b937bb7c4..6a6ce343fab0 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/mediatek,mt8186-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: MediaTek Functional Clock Controller for MT8186 +title: MediaTek Functional Clock Controller for Mediatek SoCs =20 maintainers: - Chun-Jie Chen @@ -35,6 +35,29 @@ properties: - mediatek,mt8186-vdecsys - mediatek,mt8186-vencsys - mediatek,mt8186-wpesys + - mediatek,mt8188-adsp-audio26m + - mediatek,mt8188-camsys + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-ccusys + - mediatek,mt8188-imgsys + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-imp-iic-wrap-c + - mediatek,mt8188-imp-iic-wrap-en + - mediatek,mt8188-imp-iic-wrap-w + - mediatek,mt8188-ipesys + - mediatek,mt8188-mfgcfg + - mediatek,mt8188-vdecsys + - mediatek,mt8188-vdecsys-soc + - mediatek,mt8188-vencsys + - mediatek,mt8188-wpesys + - mediatek,mt8188-wpesys-vpp0 =20 reg: maxItems: 1 @@ -42,11 +65,37 @@ properties: '#clock-cells': const: 1 =20 + '#reset-cells': + const: 1 + required: - compatible - reg - '#clock-cells' =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-ipesys + then: + required: + - '#reset-cells' + else: + properties: + '#reset-cells': false + additionalProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cloc= k.yaml index 6733dafbde16..199eac2034f2 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: MediaTek System Clock Controller for MT8186 +title: MediaTek System Clock Controller for Mediatek SoCs =20 maintainers: - Chun-Jie Chen @@ -31,6 +31,10 @@ properties: - mediatek,mt8186-infracfg_ao - mediatek,mt8186-mcusys - mediatek,mt8186-topckgen + - mediatek,mt8188-apmixedsys + - mediatek,mt8188-infracfg-ao + - mediatek,mt8188-pericfg-ao + - mediatek,mt8188-topckgen - const: syscon =20 reg: diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml deleted file mode 100644 index 5403242545ab..000000000000 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml +++ /dev/null @@ -1,93 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek Functional Clock Controller for MT8188 - -maintainers: - - Garmin Chang - -description: | - The clock architecture in MediaTek like below - PLLs --> - dividers --> - muxes - --> - clock gate - - The devices provide clock gate control in different IP blocks. - -properties: - compatible: - enum: - - mediatek,mt8188-adsp-audio26m - - mediatek,mt8188-camsys - - mediatek,mt8188-camsys-rawa - - mediatek,mt8188-camsys-rawb - - mediatek,mt8188-camsys-yuva - - mediatek,mt8188-camsys-yuvb - - mediatek,mt8188-ccusys - - mediatek,mt8188-imgsys - - mediatek,mt8188-imgsys-wpe1 - - mediatek,mt8188-imgsys-wpe2 - - mediatek,mt8188-imgsys-wpe3 - - mediatek,mt8188-imgsys1-dip-nr - - mediatek,mt8188-imgsys1-dip-top - - mediatek,mt8188-imp-iic-wrap-c - - mediatek,mt8188-imp-iic-wrap-en - - mediatek,mt8188-imp-iic-wrap-w - - mediatek,mt8188-ipesys - - mediatek,mt8188-mfgcfg - - mediatek,mt8188-vdecsys - - mediatek,mt8188-vdecsys-soc - - mediatek,mt8188-vencsys - - mediatek,mt8188-wpesys - - mediatek,mt8188-wpesys-vpp0 - - reg: - maxItems: 1 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - -required: - - compatible - - reg - - '#clock-cells' - -allOf: - - if: - properties: - compatible: - contains: - enum: - - mediatek,mt8188-camsys-rawa - - mediatek,mt8188-camsys-rawb - - mediatek,mt8188-camsys-yuva - - mediatek,mt8188-camsys-yuvb - - mediatek,mt8188-imgsys-wpe1 - - mediatek,mt8188-imgsys-wpe2 - - mediatek,mt8188-imgsys-wpe3 - - mediatek,mt8188-imgsys1-dip-nr - - mediatek,mt8188-imgsys1-dip-top - - mediatek,mt8188-ipesys - - then: - required: - - '#reset-cells' - -additionalProperties: false - -examples: - - | - clock-controller@11283000 { - compatible =3D "mediatek,mt8188-imp-iic-wrap-c"; - reg =3D <0x11283000 0x1000>; - #clock-cells =3D <1>; - }; - diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-cloc= k.yaml deleted file mode 100644 index db13d51a4903..000000000000 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml +++ /dev/null @@ -1,58 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek System Clock Controller for MT8188 - -maintainers: - - Garmin Chang - -description: | - The clock architecture in MediaTek like below - PLLs --> - dividers --> - muxes - --> - clock gate - - The apmixedsys provides most of PLLs which generated from SoC 26m. - The topckgen provides dividers and muxes which provide the clock source = to other IP blocks. - The infracfg_ao provides clock gate in peripheral and infrastructure IP = blocks. - The mcusys provides mux control to select the clock source in AP MCU. - The device nodes also provide the system control capacity for configurat= ion. - -properties: - compatible: - items: - - enum: - - mediatek,mt8188-apmixedsys - - mediatek,mt8188-infracfg-ao - - mediatek,mt8188-pericfg-ao - - mediatek,mt8188-topckgen - - const: syscon - - reg: - maxItems: 1 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - -required: - - compatible - - reg - - '#clock-cells' - -additionalProperties: false - -examples: - - | - clock-controller@10000000 { - compatible =3D "mediatek,mt8188-topckgen", "syscon"; - reg =3D <0x10000000 0x1000>; - #clock-cells =3D <1>; - }; --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC4E74FECCB; Fri, 4 Sep 2026 15:58:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537537; cv=none; b=QZEmIYUjA6Pt06OilRR/021DnZ5pSkp+AyPvBXwVMf7VLKv67RXzhX8eGB6geLJCDB+qn6DdInKOtpzCBdGA48Kvu/tibzShfd7NiWqtgNFqhq9/YErlNhU34rXL9MBb7ONcPXnpCntXg/bS4pGULJwmrghLQ9auKaPtDWiIBfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537537; c=relaxed/simple; bh=xfkJpiBKLOKPBcRPnYSa53dsnVxuw4SS6h888QCyp0k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=F6vI+rvKfsPbbellkWVqwHNmC3mWn2h2jHPisNJNv3SzFTZBTR11sikSSnmU20xNXzFP7WYNdspN6hvEIPJMcUjDulJrOuRnaUn25sNMV1zMoxfiQDW0wDN0Yqr7Fn4y18gf1mYaOcEDVv7TiE6jwme9EMzrkMtj0yWcdOq++gE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=M4E6K5a3; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="M4E6K5a3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788537532; bh=xfkJpiBKLOKPBcRPnYSa53dsnVxuw4SS6h888QCyp0k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=M4E6K5a34cFh6ZVugnuuXmFsk8AsBEzoV1qGhwYGBBU+ID0wEGy/GpE9wFqiUixuy +62rWvgjqw9SfEKVhKOBIQq0rzTV6d0T1uoNL6pNVkyCR+QSEkKDQ6KPuuGfS4wiHh 0PHkCNsADWQZ6GlmsXcmNt2201F86EY5MNKSLu7ZTtk8gdtSYl0pAlZxVNmRilHnig ZHpcVvd650BfoGgecnLP3iGEaWbJqObq091IAE4MV6FhIXAuZtLHENPwUgTsvNkDnY TfLfcEhAb71s5RD/gFAgXmAaB92oujsnGKL7PyzpFqu/TSVtty9VYol9fCKglcCcLn 8brCKScWOfphw== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id AC90917E1023; Fri, 04 Sep 2026 17:58:51 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:17 +0200 Subject: [PATCH v6 06/27] dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-6-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Conor Dooley , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=10330; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=xfkJpiBKLOKPBcRPnYSa53dsnVxuw4SS6h888QCyp0k=; b=LCFPPYr26expdlW7mubpwisdpkhLXWY1EX/k4RWl1HfYH+BMhSnG9z4drCbwb0hnbnaR9l1J9 ywMemWnldp8Dc0/8UiV5hH3kEH2wObyTHoJD1YYwSS8tiYEVKh9QidC X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Regroup the MT8192 clock and system clock dt-bindings into MT8186 ones to ease maintainability and have common files for several currently supported SoC or new future ones, that have the same kind of clock controller design. Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- .../bindings/clock/mediatek,mt8186-clock.yaml | 20 +++ .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 4 + .../bindings/clock/mediatek,mt8192-clock.yaml | 192 -----------------= ---- .../bindings/clock/mediatek,mt8192-sys-clock.yaml | 69 -------- 4 files changed, 24 insertions(+), 261 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml index 6a6ce343fab0..3db9e2953a0e 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml @@ -58,6 +58,26 @@ properties: - mediatek,mt8188-vencsys - mediatek,mt8188-wpesys - mediatek,mt8188-wpesys-vpp0 + - mediatek,mt8192-camsys + - mediatek,mt8192-camsys_rawa + - mediatek,mt8192-camsys_rawb + - mediatek,mt8192-camsys_rawc + - mediatek,mt8192-imgsys + - mediatek,mt8192-imgsys2 + - mediatek,mt8192-imp_iic_wrap_c + - mediatek,mt8192-imp_iic_wrap_e + - mediatek,mt8192-imp_iic_wrap_s + - mediatek,mt8192-imp_iic_wrap_ws + - mediatek,mt8192-imp_iic_wrap_w + - mediatek,mt8192-imp_iic_wrap_n + - mediatek,mt8192-ipesys + - mediatek,mt8192-mdpsys + - mediatek,mt8192-mfgcfg + - mediatek,mt8192-msdc_top + - mediatek,mt8192-scp_adsp + - mediatek,mt8192-vdecsys_soc + - mediatek,mt8192-vdecsys + - mediatek,mt8192-vencsys =20 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cloc= k.yaml index 199eac2034f2..41b8c61132e2 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml @@ -35,6 +35,10 @@ properties: - mediatek,mt8188-infracfg-ao - mediatek,mt8188-pericfg-ao - mediatek,mt8188-topckgen + - mediatek,mt8192-apmixedsys + - mediatek,mt8192-infracfg + - mediatek,mt8192-pericfg + - mediatek,mt8192-topckgen - const: syscon =20 reg: diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml deleted file mode 100644 index 65e4c2fddf5b..000000000000 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml +++ /dev/null @@ -1,192 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek Functional Clock Controller for MT8192 - -maintainers: - - Chun-Jie Chen - -description: - The Mediatek functional clock controller provides various clocks on MT81= 92. - -properties: - compatible: - items: - - enum: - - mediatek,mt8192-scp_adsp - - mediatek,mt8192-imp_iic_wrap_c - - mediatek,mt8192-imp_iic_wrap_e - - mediatek,mt8192-imp_iic_wrap_s - - mediatek,mt8192-imp_iic_wrap_ws - - mediatek,mt8192-imp_iic_wrap_w - - mediatek,mt8192-imp_iic_wrap_n - - mediatek,mt8192-msdc_top - - mediatek,mt8192-mfgcfg - - mediatek,mt8192-imgsys - - mediatek,mt8192-imgsys2 - - mediatek,mt8192-vdecsys_soc - - mediatek,mt8192-vdecsys - - mediatek,mt8192-vencsys - - mediatek,mt8192-camsys - - mediatek,mt8192-camsys_rawa - - mediatek,mt8192-camsys_rawb - - mediatek,mt8192-camsys_rawc - - mediatek,mt8192-ipesys - - mediatek,mt8192-mdpsys - - reg: - maxItems: 1 - - '#clock-cells': - const: 1 - -required: - - compatible - - reg - - '#clock-cells' - -additionalProperties: false - -examples: - - | - scp_adsp: clock-controller@10720000 { - compatible =3D "mediatek,mt8192-scp_adsp"; - reg =3D <0x10720000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imp_iic_wrap_c: clock-controller@11007000 { - compatible =3D "mediatek,mt8192-imp_iic_wrap_c"; - reg =3D <0x11007000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imp_iic_wrap_e: clock-controller@11cb1000 { - compatible =3D "mediatek,mt8192-imp_iic_wrap_e"; - reg =3D <0x11cb1000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imp_iic_wrap_s: clock-controller@11d03000 { - compatible =3D "mediatek,mt8192-imp_iic_wrap_s"; - reg =3D <0x11d03000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imp_iic_wrap_ws: clock-controller@11d23000 { - compatible =3D "mediatek,mt8192-imp_iic_wrap_ws"; - reg =3D <0x11d23000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imp_iic_wrap_w: clock-controller@11e01000 { - compatible =3D "mediatek,mt8192-imp_iic_wrap_w"; - reg =3D <0x11e01000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imp_iic_wrap_n: clock-controller@11f02000 { - compatible =3D "mediatek,mt8192-imp_iic_wrap_n"; - reg =3D <0x11f02000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - msdc_top: clock-controller@11f10000 { - compatible =3D "mediatek,mt8192-msdc_top"; - reg =3D <0x11f10000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - mfgcfg: clock-controller@13fbf000 { - compatible =3D "mediatek,mt8192-mfgcfg"; - reg =3D <0x13fbf000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imgsys: clock-controller@15020000 { - compatible =3D "mediatek,mt8192-imgsys"; - reg =3D <0x15020000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imgsys2: clock-controller@15820000 { - compatible =3D "mediatek,mt8192-imgsys2"; - reg =3D <0x15820000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - vdecsys_soc: clock-controller@1600f000 { - compatible =3D "mediatek,mt8192-vdecsys_soc"; - reg =3D <0x1600f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - vdecsys: clock-controller@1602f000 { - compatible =3D "mediatek,mt8192-vdecsys"; - reg =3D <0x1602f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - vencsys: clock-controller@17000000 { - compatible =3D "mediatek,mt8192-vencsys"; - reg =3D <0x17000000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - camsys: clock-controller@1a000000 { - compatible =3D "mediatek,mt8192-camsys"; - reg =3D <0x1a000000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - camsys_rawa: clock-controller@1a04f000 { - compatible =3D "mediatek,mt8192-camsys_rawa"; - reg =3D <0x1a04f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - camsys_rawb: clock-controller@1a06f000 { - compatible =3D "mediatek,mt8192-camsys_rawb"; - reg =3D <0x1a06f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - camsys_rawc: clock-controller@1a08f000 { - compatible =3D "mediatek,mt8192-camsys_rawc"; - reg =3D <0x1a08f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - ipesys: clock-controller@1b000000 { - compatible =3D "mediatek,mt8192-ipesys"; - reg =3D <0x1b000000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - mdpsys: clock-controller@1f000000 { - compatible =3D "mediatek,mt8192-mdpsys"; - reg =3D <0x1f000000 0x1000>; - #clock-cells =3D <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-cloc= k.yaml deleted file mode 100644 index 0ebd0d60e2f6..000000000000 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml +++ /dev/null @@ -1,69 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek System Clock Controller for MT8192 - -maintainers: - - Chun-Jie Chen - -description: - The Mediatek system clock controller provides various clocks and system = configuration - like reset and bus protection on MT8192. - -properties: - compatible: - items: - - enum: - - mediatek,mt8192-topckgen - - mediatek,mt8192-infracfg - - mediatek,mt8192-pericfg - - mediatek,mt8192-apmixedsys - - const: syscon - - reg: - maxItems: 1 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - -required: - - compatible - - reg - - '#clock-cells' - -additionalProperties: false - -examples: - - | - topckgen: syscon@10000000 { - compatible =3D "mediatek,mt8192-topckgen", "syscon"; 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Fri, 04 Sep 2026 17:58:53 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:18 +0200 Subject: [PATCH v6 07/27] dt-bindings: clock: mediatek: regroup MT8195 dt-bindings into MT8186 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-7-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Conor Dooley , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=12317; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=BYJ/MJSKAmgsMhlPd2fWQKUz/RyPSRX602avVUccxgY=; b=YIazDc9jMXl2n9RcD4HQttKE7e/dZIXg25WU1E7GgDmui4Q+z4GXcRouVPoZGk1o+i0L8FTSC 9ZYqaCzb2hDBsXTYbctL3AI8e+Z/iZGn6r3RJKy8RbjURd16TMq2p4K X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Regroup the MT8195 clock and system clock dt-bindings into MT8186 ones to ease maintainability and have common files for several currently supported SoC or new future ones, that have the same kind of clock controller design. Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- .../bindings/clock/mediatek,mt8186-clock.yaml | 25 +++ .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 4 + .../bindings/clock/mediatek,mt8195-clock.yaml | 239 -----------------= ---- .../bindings/clock/mediatek,mt8195-sys-clock.yaml | 77 ------- 4 files changed, 29 insertions(+), 316 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml index 3db9e2953a0e..5af9e2ed4eeb 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml @@ -78,6 +78,31 @@ properties: - mediatek,mt8192-vdecsys_soc - mediatek,mt8192-vdecsys - mediatek,mt8192-vencsys + - mediatek,mt8195-apusys_pll + - mediatek,mt8195-camsys + - mediatek,mt8195-camsys_rawa + - mediatek,mt8195-camsys_yuva + - mediatek,mt8195-camsys_rawb + - mediatek,mt8195-camsys_yuvb + - mediatek,mt8195-camsys_mraw + - mediatek,mt8195-ccusys + - mediatek,mt8195-imgsys + - mediatek,mt8195-imgsys1_dip_top + - mediatek,mt8195-imgsys1_dip_nr + - mediatek,mt8195-imgsys1_wpe + - mediatek,mt8195-imp_iic_wrap_s + - mediatek,mt8195-imp_iic_wrap_w + - mediatek,mt8195-ipesys + - mediatek,mt8195-mfgcfg + - mediatek,mt8195-scp_adsp + - mediatek,mt8195-vdecsys_soc + - mediatek,mt8195-vdecsys + - mediatek,mt8195-vdecsys_core1 + - mediatek,mt8195-vencsys + - mediatek,mt8195-vencsys_core1 + - mediatek,mt8195-wpesys + - mediatek,mt8195-wpesys_vpp0 + - mediatek,mt8195-wpesys_vpp1 =20 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cloc= k.yaml index 41b8c61132e2..4a9d3eea4316 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml @@ -39,6 +39,10 @@ properties: - mediatek,mt8192-infracfg - mediatek,mt8192-pericfg - mediatek,mt8192-topckgen + - mediatek,mt8195-apmixedsys + - mediatek,mt8195-infracfg_ao + - mediatek,mt8195-pericfg_ao + - mediatek,mt8195-topckgen - const: syscon =20 reg: diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml deleted file mode 100644 index 94dd29c2396c..000000000000 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml +++ /dev/null @@ -1,239 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek Functional Clock Controller for MT8195 - -maintainers: - - Chun-Jie Chen - -description: - The clock architecture in Mediatek like below - PLLs --> - dividers --> - muxes - --> - clock gate - - The devices except apusys_pll provide clock gate control in different IP= blocks. - The apusys_pll provides Plls which generated from SoC 26m for AI Process= ing Unit. - -properties: - compatible: - items: - - enum: - - mediatek,mt8195-scp_adsp - - mediatek,mt8195-imp_iic_wrap_s - - mediatek,mt8195-imp_iic_wrap_w - - mediatek,mt8195-mfgcfg - - mediatek,mt8195-wpesys - - mediatek,mt8195-wpesys_vpp0 - - mediatek,mt8195-wpesys_vpp1 - - mediatek,mt8195-imgsys - - mediatek,mt8195-imgsys1_dip_top - - mediatek,mt8195-imgsys1_dip_nr - - mediatek,mt8195-imgsys1_wpe - - mediatek,mt8195-ipesys - - mediatek,mt8195-camsys - - mediatek,mt8195-camsys_rawa - - mediatek,mt8195-camsys_yuva - - mediatek,mt8195-camsys_rawb - - mediatek,mt8195-camsys_yuvb - - mediatek,mt8195-camsys_mraw - - mediatek,mt8195-ccusys - - mediatek,mt8195-vdecsys_soc - - mediatek,mt8195-vdecsys - - mediatek,mt8195-vdecsys_core1 - - mediatek,mt8195-vencsys - - mediatek,mt8195-vencsys_core1 - - mediatek,mt8195-apusys_pll - reg: - maxItems: 1 - - '#clock-cells': - const: 1 - -required: - - compatible - - reg - - '#clock-cells' - -additionalProperties: false - -examples: - - | - scp_adsp: clock-controller@10720000 { - compatible =3D "mediatek,mt8195-scp_adsp"; - reg =3D <0x10720000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imp_iic_wrap_s: clock-controller@11d03000 { - compatible =3D "mediatek,mt8195-imp_iic_wrap_s"; - reg =3D <0x11d03000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imp_iic_wrap_w: clock-controller@11e05000 { - compatible =3D "mediatek,mt8195-imp_iic_wrap_w"; - reg =3D <0x11e05000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - mfgcfg: clock-controller@13fbf000 { - compatible =3D "mediatek,mt8195-mfgcfg"; - reg =3D <0x13fbf000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - wpesys: clock-controller@14e00000 { - compatible =3D "mediatek,mt8195-wpesys"; - reg =3D <0x14e00000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - wpesys_vpp0: clock-controller@14e02000 { - compatible =3D "mediatek,mt8195-wpesys_vpp0"; - reg =3D <0x14e02000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - wpesys_vpp1: clock-controller@14e03000 { - compatible =3D "mediatek,mt8195-wpesys_vpp1"; - reg =3D <0x14e03000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imgsys: clock-controller@15000000 { - compatible =3D "mediatek,mt8195-imgsys"; - reg =3D <0x15000000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imgsys1_dip_top: clock-controller@15110000 { - compatible =3D "mediatek,mt8195-imgsys1_dip_top"; - reg =3D <0x15110000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imgsys1_dip_nr: clock-controller@15130000 { - compatible =3D "mediatek,mt8195-imgsys1_dip_nr"; - reg =3D <0x15130000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - imgsys1_wpe: clock-controller@15220000 { - compatible =3D "mediatek,mt8195-imgsys1_wpe"; - reg =3D <0x15220000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - ipesys: clock-controller@15330000 { - compatible =3D "mediatek,mt8195-ipesys"; - reg =3D <0x15330000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - camsys: clock-controller@16000000 { - compatible =3D "mediatek,mt8195-camsys"; - reg =3D <0x16000000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - camsys_rawa: clock-controller@1604f000 { - compatible =3D "mediatek,mt8195-camsys_rawa"; - reg =3D <0x1604f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - camsys_yuva: clock-controller@1606f000 { - compatible =3D "mediatek,mt8195-camsys_yuva"; - reg =3D <0x1606f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - camsys_rawb: clock-controller@1608f000 { - compatible =3D "mediatek,mt8195-camsys_rawb"; - reg =3D <0x1608f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - camsys_yuvb: clock-controller@160af000 { - compatible =3D "mediatek,mt8195-camsys_yuvb"; - reg =3D <0x160af000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - camsys_mraw: clock-controller@16140000 { - compatible =3D "mediatek,mt8195-camsys_mraw"; - reg =3D <0x16140000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - ccusys: clock-controller@17200000 { - compatible =3D "mediatek,mt8195-ccusys"; - reg =3D <0x17200000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - vdecsys_soc: clock-controller@1800f000 { - compatible =3D "mediatek,mt8195-vdecsys_soc"; - reg =3D <0x1800f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - vdecsys: clock-controller@1802f000 { - compatible =3D "mediatek,mt8195-vdecsys"; - reg =3D <0x1802f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - vdecsys_core1: clock-controller@1803f000 { - compatible =3D "mediatek,mt8195-vdecsys_core1"; - reg =3D <0x1803f000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - vencsys: clock-controller@1a000000 { - compatible =3D "mediatek,mt8195-vencsys"; - reg =3D <0x1a000000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - vencsys_core1: clock-controller@1b000000 { - compatible =3D "mediatek,mt8195-vencsys_core1"; - reg =3D <0x1b000000 0x1000>; - #clock-cells =3D <1>; - }; - - - | - apusys_pll: clock-controller@190f3000 { - compatible =3D "mediatek,mt8195-apusys_pll"; - reg =3D <0x190f3000 0x1000>; - #clock-cells =3D <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-cloc= k.yaml deleted file mode 100644 index ba1b36fa0169..000000000000 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml +++ /dev/null @@ -1,77 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek System Clock Controller for MT8195 - -maintainers: - - Chun-Jie Chen - -description: - The clock architecture in Mediatek like below - PLLs --> - dividers --> - muxes - --> - clock gate - - The apmixedsys provides most of PLLs which generated from SoC 26m. - The topckgen provides dividers and muxes which provide the clock source = to other IP blocks. - The infracfg_ao and pericfg_ao provides clock gate in peripheral and inf= rastructure IP blocks. - -properties: - compatible: - items: - - enum: - - mediatek,mt8195-topckgen - - mediatek,mt8195-infracfg_ao - - mediatek,mt8195-apmixedsys - - mediatek,mt8195-pericfg_ao - - const: syscon - - reg: - maxItems: 1 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - -required: - - compatible - - reg - - '#clock-cells' - -additionalProperties: false - -examples: - - | - topckgen: syscon@10000000 { - compatible =3D "mediatek,mt8195-topckgen", "syscon"; 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Fri, 04 Sep 2026 17:58:54 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:19 +0200 Subject: [PATCH v6 08/27] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-8-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Conor Dooley , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=20096; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=MfQ+S4n9EeSEr5mdzHH6Iz8WVr8ktdLywEFydgAm/Zw=; b=IH0hPoplyrRGEuEQ0C8lHqIdQX7baeFqbVjNKumuw4QtAuDhJwtEyhHQZ+6qgH2+1AZ/BqFdO Zv5ncPWFbXlADFC2R5Pfnjozl4lasVJJ9gSbEIm/BRkLh134m8NLKs/ X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add compatible and binding headers files for system and base clock controllers and reset controllers support of MediaTek MT8189 SoC. The MT8189 clock IP provide clock control for main system (apmixedsys, topcksys and vlpcksys) and subsys (eg. peri, scp, ufs...). Also, add compatible for frequency hopping and spread spectrum clock functionality. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- .../bindings/clock/mediatek,mt8186-clock.yaml | 15 + .../bindings/clock/mediatek,mt8186-fhctl.yaml | 1 + .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 5 + include/dt-bindings/clock/mediatek,mt8189-clk.h | 433 +++++++++++++++++= ++++ include/dt-bindings/reset/mediatek,mt8189-resets.h | 17 + 5 files changed, 471 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml index 5af9e2ed4eeb..f5d97aa9ec16 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml @@ -58,6 +58,19 @@ properties: - mediatek,mt8188-vencsys - mediatek,mt8188-wpesys - mediatek,mt8188-wpesys-vpp0 + - mediatek,mt8189-dbg-ao + - mediatek,mt8189-dem + - mediatek,mt8189-dvfsrc-top + - mediatek,mt8189-iic-wrap-e + - mediatek,mt8189-iic-wrap-en + - mediatek,mt8189-iic-wrap-s + - mediatek,mt8189-iic-wrap-ws + - mediatek,mt8189-scp-clk + - mediatek,mt8189-scp-i2c-clk + - mediatek,mt8189-ufscfg-ao + - mediatek,mt8189-ufscfg-pdn + - mediatek,mt8189-vlpcfg + - mediatek,mt8189-vlpcfg-ao - mediatek,mt8192-camsys - mediatek,mt8192-camsys_rawa - mediatek,mt8192-camsys_rawb @@ -134,6 +147,8 @@ allOf: - mediatek,mt8188-imgsys1-dip-nr - mediatek,mt8188-imgsys1-dip-top - mediatek,mt8188-ipesys + - mediatek,mt8189-ufscfg-ao + - mediatek,mt8189-ufscfg-pdn then: required: - '#reset-cells' diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml index d00327d12e1e..824e3b2bd6c0 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt6795-fhctl - mediatek,mt8173-fhctl - mediatek,mt8186-fhctl + - mediatek,mt8189-fhctl - mediatek,mt8192-fhctl - mediatek,mt8195-fhctl =20 diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-cloc= k.yaml index 4a9d3eea4316..2575f84ef917 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml @@ -35,6 +35,11 @@ properties: - mediatek,mt8188-infracfg-ao - mediatek,mt8188-pericfg-ao - mediatek,mt8188-topckgen + - mediatek,mt8189-apmixedsys + - mediatek,mt8189-infra-ao + - mediatek,mt8189-peri-ao + - mediatek,mt8189-topckgen + - mediatek,mt8189-vlpckgen - mediatek,mt8192-apmixedsys - mediatek,mt8192-infracfg - mediatek,mt8192-pericfg diff --git a/include/dt-bindings/clock/mediatek,mt8189-clk.h b/include/dt-b= indings/clock/mediatek,mt8189-clk.h new file mode 100644 index 000000000000..ca433f969698 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8189-clk.h @@ -0,0 +1,433 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * Louis-Alexis Eyraud + */ + +#ifndef _DT_BINDINGS_CLK_MT8189_H +#define _DT_BINDINGS_CLK_MT8189_H + +/* TOPCKGEN */ +#define CLK_TOP_AXI_SEL 0 +#define CLK_TOP_AXI_PERI_SEL 1 +#define CLK_TOP_AXI_U_SEL 2 +#define CLK_TOP_BUS_AXIMEM_SEL 3 +#define CLK_TOP_DISP0_SEL 4 +#define CLK_TOP_MMINFRA_SEL 5 +#define CLK_TOP_UART_SEL 6 +#define CLK_TOP_SPI0_SEL 7 +#define CLK_TOP_SPI1_SEL 8 +#define CLK_TOP_SPI2_SEL 9 +#define CLK_TOP_SPI3_SEL 10 +#define CLK_TOP_SPI4_SEL 11 +#define CLK_TOP_SPI5_SEL 12 +#define CLK_TOP_MSDC_MACRO_0P_SEL 13 +#define CLK_TOP_MSDC50_0_HCLK_SEL 14 +#define CLK_TOP_MSDC50_0_SEL 15 +#define CLK_TOP_AES_MSDCFDE_SEL 16 +#define CLK_TOP_MSDC_MACRO_1P_SEL 17 +#define CLK_TOP_MSDC30_1_SEL 18 +#define CLK_TOP_MSDC30_1_HCLK_SEL 19 +#define CLK_TOP_MSDC_MACRO_2P_SEL 20 +#define CLK_TOP_MSDC30_2_SEL 21 +#define CLK_TOP_MSDC30_2_HCLK_SEL 22 +#define CLK_TOP_AUD_INTBUS_SEL 23 +#define CLK_TOP_ATB_SEL 24 +#define CLK_TOP_DISP_PWM_SEL 25 +#define CLK_TOP_USB_TOP_P0_SEL 26 +#define CLK_TOP_USB_XHCI_P0_SEL 27 +#define CLK_TOP_USB_TOP_P1_SEL 28 +#define CLK_TOP_USB_XHCI_P1_SEL 29 +#define CLK_TOP_USB_TOP_P2_SEL 30 +#define CLK_TOP_USB_XHCI_P2_SEL 31 +#define CLK_TOP_USB_TOP_P3_SEL 32 +#define CLK_TOP_USB_XHCI_P3_SEL 33 +#define CLK_TOP_USB_TOP_P4_SEL 34 +#define CLK_TOP_USB_XHCI_P4_SEL 35 +#define CLK_TOP_I2C_SEL 36 +#define CLK_TOP_SENINF_SEL 37 +#define CLK_TOP_SENINF1_SEL 38 +#define CLK_TOP_AUD_ENGEN1_SEL 39 +#define CLK_TOP_AUD_ENGEN2_SEL 40 +#define CLK_TOP_AES_UFSFDE_SEL 41 +#define CLK_TOP_U_SEL 42 +#define CLK_TOP_U_MBIST_SEL 43 +#define CLK_TOP_AUD_1_SEL 44 +#define CLK_TOP_AUD_2_SEL 45 +#define CLK_TOP_VENC_SEL 46 +#define CLK_TOP_VDEC_SEL 47 +#define CLK_TOP_PWM_SEL 48 +#define CLK_TOP_AUDIO_H_SEL 49 +#define CLK_TOP_MCUPM_SEL 50 +#define CLK_TOP_MEM_SUB_SEL 51 +#define CLK_TOP_MEM_SUB_PERI_SEL 52 +#define CLK_TOP_MEM_SUB_U_SEL 53 +#define CLK_TOP_EMI_N_SEL 54 +#define CLK_TOP_DSI_OCC_SEL 55 +#define CLK_TOP_AP2CONN_HOST_SEL 56 +#define CLK_TOP_IMG1_SEL 57 +#define CLK_TOP_IPE_SEL 58 +#define CLK_TOP_CAM_SEL 59 +#define CLK_TOP_CAMTM_SEL 60 +#define CLK_TOP_DSP_SEL 61 +#define CLK_TOP_SR_PKA_SEL 62 +#define CLK_TOP_DXCC_SEL 63 +#define CLK_TOP_MFG_REF_SEL 64 +#define CLK_TOP_MDP0_SEL 65 +#define CLK_TOP_DP_SEL 66 +#define CLK_TOP_EDP_SEL 67 +#define CLK_TOP_EDP_FAVT_SEL 68 +#define CLK_TOP_ETH_250M_SEL 69 +#define CLK_TOP_ETH_62P4M_PTP_SEL 70 +#define CLK_TOP_ETH_50M_RMII_SEL 71 +#define CLK_TOP_SFLASH_SEL 72 +#define CLK_TOP_GCPU_SEL 73 +#define CLK_TOP_MAC_TL_SEL 74 +#define CLK_TOP_VDSTX_DG_CTS_SEL 75 +#define CLK_TOP_PLL_DPIX_SEL 76 +#define CLK_TOP_ECC_SEL 77 +#define CLK_TOP_APLL_I2SIN0_MCK_SEL 78 +#define CLK_TOP_APLL_I2SIN1_MCK_SEL 79 +#define CLK_TOP_APLL_I2SIN2_MCK_SEL 80 +#define CLK_TOP_APLL_I2SIN3_MCK_SEL 81 +#define CLK_TOP_APLL_I2SIN4_MCK_SEL 82 +#define CLK_TOP_APLL_I2SIN6_MCK_SEL 83 +#define CLK_TOP_APLL_I2SOUT0_MCK_SEL 84 +#define CLK_TOP_APLL_I2SOUT1_MCK_SEL 85 +#define CLK_TOP_APLL_I2SOUT2_MCK_SEL 86 +#define CLK_TOP_APLL_I2SOUT3_MCK_SEL 87 +#define CLK_TOP_APLL_I2SOUT4_MCK_SEL 88 +#define CLK_TOP_APLL_I2SOUT6_MCK_SEL 89 +#define CLK_TOP_APLL_FMI2S_MCK_SEL 90 +#define CLK_TOP_APLL_TDMOUT_MCK_SEL 91 +#define CLK_TOP_MFG_SEL_MFGPLL 92 +#define CLK_TOP_APLL12_CK_DIV_I2SIN0 93 +#define CLK_TOP_APLL12_CK_DIV_I2SIN1 94 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT0 95 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT1 96 +#define CLK_TOP_APLL12_CK_DIV_FMI2S 97 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 98 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B 99 +#define CLK_TOP_MAINPLL_D3 100 +#define CLK_TOP_MAINPLL_D4 101 +#define CLK_TOP_MAINPLL_D4_D2 102 +#define CLK_TOP_MAINPLL_D4_D4 103 +#define CLK_TOP_MAINPLL_D4_D8 104 +#define CLK_TOP_MAINPLL_D5 105 +#define CLK_TOP_MAINPLL_D5_D2 106 +#define CLK_TOP_MAINPLL_D5_D4 107 +#define CLK_TOP_MAINPLL_D5_D8 108 +#define CLK_TOP_MAINPLL_D6 109 +#define CLK_TOP_MAINPLL_D6_D2 110 +#define CLK_TOP_MAINPLL_D6_D4 111 +#define CLK_TOP_MAINPLL_D6_D8 112 +#define CLK_TOP_MAINPLL_D7 113 +#define CLK_TOP_MAINPLL_D7_D2 114 +#define CLK_TOP_MAINPLL_D7_D4 115 +#define CLK_TOP_MAINPLL_D7_D8 116 +#define CLK_TOP_MAINPLL_D9 117 +#define CLK_TOP_UNIVPLL_D2 118 +#define CLK_TOP_UNIVPLL_D3 119 +#define CLK_TOP_UNIVPLL_D4 120 +#define CLK_TOP_UNIVPLL_D4_D2 121 +#define CLK_TOP_UNIVPLL_D4_D4 122 +#define CLK_TOP_UNIVPLL_D4_D8 123 +#define CLK_TOP_UNIVPLL_D5 124 +#define CLK_TOP_UNIVPLL_D5_D2 125 +#define CLK_TOP_UNIVPLL_D5_D4 126 +#define CLK_TOP_UNIVPLL_D6 127 +#define CLK_TOP_UNIVPLL_D6_D2 128 +#define CLK_TOP_UNIVPLL_D6_D4 129 +#define CLK_TOP_UNIVPLL_D6_D8 130 +#define CLK_TOP_UNIVPLL_D6_D16 131 +#define CLK_TOP_UNIVPLL_D7 132 +#define CLK_TOP_UNIVPLL_D7_D2 133 +#define CLK_TOP_UNIVPLL_D7_D3 134 +#define CLK_TOP_LVDSTX_DG_CTS 135 +#define CLK_TOP_UNIVPLL_192M 136 +#define CLK_TOP_UNIVPLL_192M_D2 137 +#define CLK_TOP_UNIVPLL_192M_D4 138 +#define CLK_TOP_UNIVPLL_192M_D8 139 +#define CLK_TOP_UNIVPLL_192M_D10 140 +#define CLK_TOP_UNIVPLL_192M_D16 141 +#define CLK_TOP_UNIVPLL_192M_D32 142 +#define CLK_TOP_APLL1_D2 143 +#define CLK_TOP_APLL1_D4 144 +#define CLK_TOP_APLL1_D8 145 +#define CLK_TOP_APLL1_D3 146 +#define CLK_TOP_APLL2_D2 147 +#define CLK_TOP_APLL2_D4 148 +#define CLK_TOP_APLL2_D8 149 +#define CLK_TOP_APLL2_D3 150 +#define CLK_TOP_MMPLL_D4 151 +#define CLK_TOP_MMPLL_D4_D2 152 +#define CLK_TOP_MMPLL_D4_D4 153 +#define CLK_TOP_VPLL_DPIX 154 +#define CLK_TOP_MMPLL_D5 155 +#define CLK_TOP_MMPLL_D5_D2 156 +#define CLK_TOP_MMPLL_D5_D4 157 +#define CLK_TOP_MMPLL_D6 158 +#define CLK_TOP_MMPLL_D6_D2 159 +#define CLK_TOP_MMPLL_D7 160 +#define CLK_TOP_MMPLL_D9 161 +#define CLK_TOP_TVDPLL1_D2 162 +#define CLK_TOP_TVDPLL1_D4 163 +#define CLK_TOP_TVDPLL1_D8 164 +#define CLK_TOP_TVDPLL1_D16 165 +#define CLK_TOP_TVDPLL2_D2 166 +#define CLK_TOP_TVDPLL2_D4 167 +#define CLK_TOP_TVDPLL2_D8 168 +#define CLK_TOP_TVDPLL2_D16 169 +#define CLK_TOP_ETHPLL_D2 170 +#define CLK_TOP_ETHPLL_D8 171 +#define CLK_TOP_ETHPLL_D10 172 +#define CLK_TOP_MSDCPLL_D2 173 +#define CLK_TOP_UFSPLL_D2 174 +#define CLK_TOP_F26M_CK_D2 175 +#define CLK_TOP_OSC_D2 176 +#define CLK_TOP_OSC_D4 177 +#define CLK_TOP_OSC_D8 178 +#define CLK_TOP_OSC_D16 179 +#define CLK_TOP_OSC_D3 180 +#define CLK_TOP_OSC_D7 181 +#define CLK_TOP_OSC_D10 182 +#define CLK_TOP_OSC_D20 183 +#define CLK_TOP_FMCNT_P0_EN 184 +#define CLK_TOP_FMCNT_P1_EN 185 +#define CLK_TOP_FMCNT_P2_EN 186 +#define CLK_TOP_FMCNT_P3_EN 187 +#define CLK_TOP_FMCNT_P4_EN 188 +#define CLK_TOP_USB_F26M_CK_EN 189 +#define CLK_TOP_SSPXTP_F26M_CK_EN 190 +#define CLK_TOP_USB2_PHY_RF_P0_EN 191 +#define CLK_TOP_USB2_PHY_RF_P1_EN 192 +#define CLK_TOP_USB2_PHY_RF_P2_EN 193 +#define CLK_TOP_USB2_PHY_RF_P3_EN 194 +#define CLK_TOP_USB2_PHY_RF_P4_EN 195 +#define CLK_TOP_USB2_26M_CK_P0_EN 196 +#define CLK_TOP_USB2_26M_CK_P1_EN 197 +#define CLK_TOP_USB2_26M_CK_P2_EN 198 +#define CLK_TOP_USB2_26M_CK_P3_EN 199 +#define CLK_TOP_USB2_26M_CK_P4_EN 200 +#define CLK_TOP_F26M_CK_EN 201 +#define CLK_TOP_AP2CON_EN 202 +#define CLK_TOP_EINT_N_EN 203 +#define CLK_TOP_TOPCKGEN_FMIPI_CSI_UP26M_CK_EN 204 +#define CLK_TOP_EINT_E_EN 205 +#define CLK_TOP_EINT_W_EN 206 +#define CLK_TOP_EINT_S_EN 207 + +/* INFRACFG_AO */ +#define CLK_IFRAO_CQ_DMA_FPC 0 +#define CLK_IFRAO_DEBUGSYS 1 +#define CLK_IFRAO_DBG_TRACE 2 +#define CLK_IFRAO_CQ_DMA 3 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL_LL 0 +#define CLK_APMIXED_ARMPLL_BL 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_UNIVPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_MFGPLL 6 +#define CLK_APMIXED_APLL1 7 +#define CLK_APMIXED_APLL2 8 +#define CLK_APMIXED_EMIPLL 9 +#define CLK_APMIXED_APUPLL2 10 +#define CLK_APMIXED_APUPLL 11 +#define CLK_APMIXED_TVDPLL1 12 +#define CLK_APMIXED_TVDPLL2 13 +#define CLK_APMIXED_ETHPLL 14 +#define CLK_APMIXED_MSDCPLL 15 +#define CLK_APMIXED_UFSPLL 16 + +/* PERICFG_AO */ +#define CLK_PERAO_UART0 0 +#define CLK_PERAO_UART1 1 +#define CLK_PERAO_UART2 2 +#define CLK_PERAO_UART3 3 +#define CLK_PERAO_PWM_H 4 +#define CLK_PERAO_PWM_B 5 +#define CLK_PERAO_PWM_FB1 6 +#define CLK_PERAO_PWM_FB2 7 +#define CLK_PERAO_PWM_FB3 8 +#define CLK_PERAO_PWM_FB4 9 +#define CLK_PERAO_DISP_PWM0 10 +#define CLK_PERAO_DISP_PWM1 11 +#define CLK_PERAO_SPI0_B 12 +#define CLK_PERAO_SPI1_B 13 +#define CLK_PERAO_SPI2_B 14 +#define CLK_PERAO_SPI3_B 15 +#define CLK_PERAO_SPI4_B 16 +#define CLK_PERAO_SPI5_B 17 +#define CLK_PERAO_SPI0_H 18 +#define CLK_PERAO_SPI1_H 19 +#define CLK_PERAO_SPI2_H 20 +#define CLK_PERAO_SPI3_H 21 +#define CLK_PERAO_SPI4_H 22 +#define CLK_PERAO_SPI5_H 23 +#define CLK_PERAO_AXI 24 +#define CLK_PERAO_AHB_APB 25 +#define CLK_PERAO_TL 26 +#define CLK_PERAO_REF 27 +#define CLK_PERAO_I2C 28 +#define CLK_PERAO_DMA_B 29 +#define CLK_PERAO_SSUSB0_REF 30 +#define CLK_PERAO_SSUSB0_FRMCNT 31 +#define CLK_PERAO_SSUSB0_SYS 32 +#define CLK_PERAO_SSUSB0_XHCI 33 +#define CLK_PERAO_SSUSB0_F 34 +#define CLK_PERAO_SSUSB0_H 35 +#define CLK_PERAO_SSUSB1_REF 36 +#define CLK_PERAO_SSUSB1_FRMCNT 37 +#define CLK_PERAO_SSUSB1_SYS 38 +#define CLK_PERAO_SSUSB1_XHCI 39 +#define CLK_PERAO_SSUSB1_F 40 +#define CLK_PERAO_SSUSB1_H 41 +#define CLK_PERAO_SSUSB2_REF 42 +#define CLK_PERAO_SSUSB2_FRMCNT 43 +#define CLK_PERAO_SSUSB2_SYS 44 +#define CLK_PERAO_SSUSB2_XHCI 45 +#define CLK_PERAO_SSUSB2_F 46 +#define CLK_PERAO_SSUSB2_H 47 +#define CLK_PERAO_SSUSB3_REF 48 +#define CLK_PERAO_SSUSB3_FRMCNT 49 +#define CLK_PERAO_SSUSB3_SYS 50 +#define CLK_PERAO_SSUSB3_XHCI 51 +#define CLK_PERAO_SSUSB3_F 52 +#define CLK_PERAO_SSUSB3_H 53 +#define CLK_PERAO_SSUSB4_REF 54 +#define CLK_PERAO_SSUSB4_FRMCNT 55 +#define CLK_PERAO_SSUSB4_SYS 56 +#define CLK_PERAO_SSUSB4_XHCI 57 +#define CLK_PERAO_SSUSB4_F 58 +#define CLK_PERAO_SSUSB4_H 59 +#define CLK_PERAO_MSDC0 60 +#define CLK_PERAO_MSDC0_H 61 +#define CLK_PERAO_MSDC0_FAES 62 +#define CLK_PERAO_MSDC0_MST_F 63 +#define CLK_PERAO_MSDC0_SLV_H 64 +#define CLK_PERAO_MSDC1 65 +#define CLK_PERAO_MSDC1_H 66 +#define CLK_PERAO_MSDC1_MST_F 67 +#define CLK_PERAO_MSDC1_SLV_H 68 +#define CLK_PERAO_MSDC2 69 +#define CLK_PERAO_MSDC2_H 70 +#define CLK_PERAO_MSDC2_MST_F 71 +#define CLK_PERAO_MSDC2_SLV_H 72 +#define CLK_PERAO_SFLASH 73 +#define CLK_PERAO_SFLASH_F 74 +#define CLK_PERAO_SFLASH_H 75 +#define CLK_PERAO_SFLASH_P 76 +#define CLK_PERAO_AUDIO0 77 +#define CLK_PERAO_AUDIO1 78 +#define CLK_PERAO_AUDIO2 79 +#define CLK_PERAO_AUXADC_26M 80 + +/* UFSCFG_AO_REG */ +#define CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM 0 +#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0 1 +#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1 2 +#define CLK_UFSCFG_AO_REG_UNIPRO_SYS 3 +#define CLK_UFSCFG_AO_REG_U_SAP_CFG 4 +#define CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS 5 + +/* UFSCFG_PDN_REG */ +#define CLK_UFSCFG_REG_UFSHCI_UFS 0 +#define CLK_UFSCFG_REG_UFSHCI_AES 1 +#define CLK_UFSCFG_REG_UFSHCI_U_AHB 2 +#define CLK_UFSCFG_REG_UFSHCI_U_AXI 3 + +/* IMP_IIC_WRAP_WS */ +#define CLK_IMPWS_I2C2 0 + +/* IMP_IIC_WRAP_E */ +#define CLK_IMPE_I2C0 0 +#define CLK_IMPE_I2C1 1 + +/* IMP_IIC_WRAP_S */ +#define CLK_IMPS_I2C3 0 +#define CLK_IMPS_I2C4 1 +#define CLK_IMPS_I2C5 2 +#define CLK_IMPS_I2C6 3 + +/* IMP_IIC_WRAP_EN */ +#define CLK_IMPEN_I2C7 0 +#define CLK_IMPEN_I2C8 1 + +/* VLPCFG_REG */ +#define CLK_VLPCFG_REG_SCP 0 +#define CLK_VLPCFG_REG_RG_R_APXGPT_26M 1 +#define CLK_VLPCFG_REG_DPMSRCK_TEST 2 +#define CLK_VLPCFG_REG_RG_DPMSRRTC_TEST 3 +#define CLK_VLPCFG_REG_DPMSRULP_TEST 4 +#define CLK_VLPCFG_REG_SPMI_P_MST 5 +#define CLK_VLPCFG_REG_SPMI_P_MST_32K 6 +#define CLK_VLPCFG_REG_PMIF_SPMI_P_SYS 7 +#define CLK_VLPCFG_REG_PMIF_SPMI_P_TMR 8 +#define CLK_VLPCFG_REG_PMIF_SPMI_M_SYS 9 +#define CLK_VLPCFG_REG_PMIF_SPMI_M_TMR 10 +#define CLK_VLPCFG_REG_DVFSRC 11 +#define CLK_VLPCFG_REG_PWM_VLP 12 +#define CLK_VLPCFG_REG_SRCK 13 +#define CLK_VLPCFG_REG_SSPM_F26M 14 +#define CLK_VLPCFG_REG_SSPM_F32K 15 +#define CLK_VLPCFG_REG_SSPM_ULPOSC 16 +#define CLK_VLPCFG_REG_VLP_32K_COM 17 +#define CLK_VLPCFG_REG_VLP_26M_COM 18 + +/* VLP_CKSYS */ +#define CLK_VLP_CK_SCP_SEL 0 +#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 1 +#define CLK_VLP_CK_SPMI_P_MST_SEL 2 +#define CLK_VLP_CK_DVFSRC_SEL 3 +#define CLK_VLP_CK_PWM_VLP_SEL 4 +#define CLK_VLP_CK_AXI_VLP_SEL 5 +#define CLK_VLP_CK_SYSTIMER_26M_SEL 6 +#define CLK_VLP_CK_SSPM_SEL 7 +#define CLK_VLP_CK_SSPM_F26M_SEL 8 +#define CLK_VLP_CK_SRCK_SEL 9 +#define CLK_VLP_CK_SCP_SPI_SEL 10 +#define CLK_VLP_CK_SCP_IIC_SEL 11 +#define CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL 12 +#define CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL 13 +#define CLK_VLP_CK_SSPM_ULPOSC_SEL 14 +#define CLK_VLP_CK_APXGPT_26M_SEL 15 +#define CLK_VLP_CK_VADSP_SEL 16 +#define CLK_VLP_CK_VADSP_VOWPLL_SEL 17 +#define CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL 18 +#define CLK_VLP_CK_CAMTG0_SEL 19 +#define CLK_VLP_CK_CAMTG1_SEL 20 +#define CLK_VLP_CK_CAMTG2_SEL 21 +#define CLK_VLP_CK_AUD_ADC_SEL 22 +#define CLK_VLP_CK_KP_IRQ_GEN_SEL 23 +#define CLK_VLP_CK_VADSYS_VLP_26M_EN 24 +#define CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN 25 + +/* SCP_IIC */ +#define CLK_SCP_IIC_I2C0_W1S 0 +#define CLK_SCP_IIC_I2C1_W1S 1 + +/* SCP */ +#define CLK_SCP_SET_SPI0 0 +#define CLK_SCP_SET_SPI1 1 + +/* VLPCFG_AO_REG */ +#define CLK_VLPCFG_AO_APEINT_RX 0 + +/* DVFSRC_TOP */ +#define CLK_DVFSRC_TOP_DVFSRC_EN 0 + +/* DBGAO */ +#define CLK_DBGAO_ATB_EN 0 + +/* DEM */ +#define CLK_DEM_ATB_EN 0 +#define CLK_DEM_BUSCLK_EN 1 +#define CLK_DEM_SYSCLK_EN 2 + +#endif /* _DT_BINDINGS_CLK_MT8189_H */ diff --git a/include/dt-bindings/reset/mediatek,mt8189-resets.h b/include/d= t-bindings/reset/mediatek,mt8189-resets.h new file mode 100644 index 000000000000..0f31984374be --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt8189-resets.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2026 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8189 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8189 + +/* UFS resets */ +#define MT8189_UFSAO_RST_UFS_MPHY 0 + +#define MT8189_UFSPDN_RST_UFS_UNIPRO 0 +#define MT8189_UFSPDN_RST_UFS_CRYPTO 1 +#define MT8189_UFSPDN_RST_UFS_HCI 2 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8189 */ --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1504501F2D; Fri, 4 Sep 2026 15:58:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537542; cv=none; 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requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 054FD17E1298; Fri, 04 Sep 2026 17:58:55 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:20 +0200 Subject: [PATCH v6 09/27] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-9-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Brian Masney , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=4045; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=0D+0oi/WBwfqLpHH6F3fD5da8wlJsqjrCr/tqNkivPM=; b=yEWFTBIx6LNS1j6uJyf9hc0+BKZGAQ35f0OwqVDvM3hi+zdzO1OPztdZ9GniO39YRjRtB7uJA fMqF1L/V65XCCHKWvghpl9m4b3aSs3SXKUatu8BESwv65LWE+PXnobG X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= To prepare for the new clock ops set addition, with support for set/clr enable logic only, rename mtk_pll_fenc_setclr_ops and its callback names to harmonize the naming with the same suffix. Reviewed-by: Brian Masney Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +- drivers/clk/mediatek/clk-pll.c | 16 ++++++++-------- drivers/clk/mediatek/clk-pll.h | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8196-apmixedsys.c index c4ebb0170b82..41c5117b18f8 100644 --- a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c @@ -83,7 +83,7 @@ .en_set_reg =3D PLLEN_ALL_SET, \ .en_clr_reg =3D PLLEN_ALL_CLR, \ .pll_en_bit =3D _pll_en_bit, \ - .ops =3D &mtk_pll_fenc_clr_set_ops, \ + .ops =3D &mtk_pll_fenc_setclr_ops, \ } =20 struct mtk_pll_desc { diff --git a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c b/drivers/clk/media= tek/clk-mt8196-vlpckgen.c index ee88dc4a231a..814709db2924 100644 --- a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c +++ b/drivers/clk/mediatek/clk-mt8196-vlpckgen.c @@ -162,7 +162,7 @@ .en_set_reg =3D VLP_PLLEN_ALL_SET, \ .en_clr_reg =3D VLP_PLLEN_ALL_CLR, \ .pll_en_bit =3D _pll_en_bit, \ - .ops =3D &mtk_pll_fenc_clr_set_ops, \ + .ops =3D &mtk_pll_fenc_setclr_ops, \ } =20 static DEFINE_SPINLOCK(mt8196_clk_vlp_lock); diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index e97064868908..ee478bc64085 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -38,7 +38,7 @@ int mtk_pll_is_prepared(struct clk_hw *hw) return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) !=3D 0; } =20 -static int mtk_pll_fenc_is_prepared(struct clk_hw *hw) +static int mtk_pll_is_prepared_fenc_setclr(struct clk_hw *hw) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); =20 @@ -285,7 +285,7 @@ void mtk_pll_unprepare(struct clk_hw *hw) writel(r, pll->pwr_addr); } =20 -static int mtk_pll_prepare_setclr(struct clk_hw *hw) +static int mtk_pll_prepare_fenc_setclr(struct clk_hw *hw) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); =20 @@ -297,7 +297,7 @@ static int mtk_pll_prepare_setclr(struct clk_hw *hw) return 0; } =20 -static void mtk_pll_unprepare_setclr(struct clk_hw *hw) +static void mtk_pll_unprepare_fenc_setclr(struct clk_hw *hw) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); =20 @@ -313,15 +313,15 @@ const struct clk_ops mtk_pll_ops =3D { .set_rate =3D mtk_pll_set_rate, }; =20 -const struct clk_ops mtk_pll_fenc_clr_set_ops =3D { - .is_prepared =3D mtk_pll_fenc_is_prepared, - .prepare =3D mtk_pll_prepare_setclr, - .unprepare =3D mtk_pll_unprepare_setclr, +const struct clk_ops mtk_pll_fenc_setclr_ops =3D { + .is_prepared =3D mtk_pll_is_prepared_fenc_setclr, + .prepare =3D mtk_pll_prepare_fenc_setclr, + .unprepare =3D mtk_pll_unprepare_fenc_setclr, .recalc_rate =3D mtk_pll_recalc_rate, .determine_rate =3D mtk_pll_determine_rate, .set_rate =3D mtk_pll_set_rate, }; -EXPORT_SYMBOL_GPL(mtk_pll_fenc_clr_set_ops); +EXPORT_SYMBOL_GPL(mtk_pll_fenc_setclr_ops); =20 struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, const struct mtk_pll_data *data, diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index f49dc2732ffe..d6d34840c09d 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -85,7 +85,7 @@ void mtk_clk_unregister_plls(const struct mtk_pll_data *p= lls, int num_plls, struct clk_hw_onecell_data *clk_data); =20 extern const struct clk_ops mtk_pll_ops; -extern const struct clk_ops mtk_pll_fenc_clr_set_ops; +extern const struct clk_ops mtk_pll_fenc_setclr_ops; =20 static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) { --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D32F4F30CC; Fri, 4 Sep 2026 15:59:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537543; cv=none; b=K7yJF6zks9BwKAwjHwB9RtTV5hW6G5rugx+fNFfyN2AoXmsjyWE3JbNteLnJ3Yn7LF7P4iLXeFmzhkNsXgULYaR2PLLcKLkKJ6EB+l4tYnwjN1AjIRyRgr+Wq1Wj4nc2fmtyA5ohgJjWB+Pw/u6OpaE52qlIyDxO6iu34mT9SPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-10-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Brian Masney , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=3030; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=Pun6ZjnCACSM6H6YEIdyZa1UW6LNXui7X4S9jiGkUhs=; b=iNjRtQ8bEKVg9Fb/PcDszQrR4yYwUcrp0+hvXza6bRDxWpUaPCSTaoHKogN2GQypkBZaLXxbZ sH00hPj3K3tARCpEysbABjvfNKhbAGjcrnRSp8aYNChoTUqv9hwCQ4G X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Currently, the register offset to handle BAR reset, for PLLs that support it, is hardcoded to CON0. On MT8189 SoC, there are separate status, set and clr registers to handle this, so differents offsets are needed. Add the new fields for offsets and addresses to the MTK PLL data structure and modify mtk_clk_register_pll_ops function to compute the new register addresses so they are available for clock operation usage. Also, replace reset BAR address computing by its computed address from MTK PLL data structure in prepare/unprepare callbacks. Reviewed-by: Brian Masney Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-pll.c | 18 ++++++++++++++---- drivers/clk/mediatek/clk-pll.h | 6 ++++++ 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index ee478bc64085..4b0f7e2bfc5a 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -249,9 +249,9 @@ int mtk_pll_prepare(struct clk_hw *hw) udelay(20); =20 if (pll->data->flags & HAVE_RST_BAR) { - r =3D readl(pll->base_addr + REG_CON0); + r =3D readl(pll->rst_bar_addr); r |=3D pll->data->rst_bar_mask; - writel(r, pll->base_addr + REG_CON0); + writel(r, pll->rst_bar_addr); } =20 return 0; @@ -263,9 +263,9 @@ void mtk_pll_unprepare(struct clk_hw *hw) u32 r; =20 if (pll->data->flags & HAVE_RST_BAR) { - r =3D readl(pll->base_addr + REG_CON0); + r =3D readl(pll->rst_bar_addr); r &=3D ~pll->data->rst_bar_mask; - writel(r, pll->base_addr + REG_CON0); + writel(r, pll->rst_bar_addr); } =20 __mtk_pll_tuner_disable(pll); @@ -352,6 +352,16 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk= _pll *pll, pll->en_set_addr =3D base + data->en_set_reg; if (data->en_clr_reg) pll->en_clr_addr =3D base + data->en_clr_reg; + + if (data->rst_bar_reg) + pll->rst_bar_addr =3D base + data->rst_bar_reg; + else + pll->rst_bar_addr =3D pll->base_addr + REG_CON0; + if (data->rst_bar_set_reg) + pll->rst_bar_set_addr =3D base + data->rst_bar_set_reg; + if (data->rst_bar_clr_reg) + pll->rst_bar_clr_addr =3D base + data->rst_bar_clr_reg; + pll->hw.init =3D &init; pll->data =3D data; =20 diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index d6d34840c09d..3aaf3a7654b5 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -49,6 +49,9 @@ struct mtk_pll_data { u32 en_reg; u32 en_set_reg; u32 en_clr_reg; + u32 rst_bar_reg; + u32 rst_bar_set_reg; + u32 rst_bar_clr_reg; u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ u8 pcw_chg_bit; u8 fenc_sta_bit; @@ -75,6 +78,9 @@ struct mtk_clk_pll { void __iomem *en_set_addr; void __iomem *en_clr_addr; void __iomem *fenc_addr; + void __iomem *rst_bar_addr; + void __iomem *rst_bar_set_addr; + void __iomem *rst_bar_clr_addr; const struct mtk_pll_data *data; }; =20 --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15427501F4B; Fri, 4 Sep 2026 15:59:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537544; cv=none; b=RxptD66pR4QSW9asJvbrZbqLHbJ1uA3fd0oxKZzjbz8vrfvTUOfPt4ILnIk8hypY0CWqBLizWEfow+QfV42MQHI3kFVsBBff1KXXlv7dXjiV3oN2lfksrQuRFAVpz/A0A9Q6qqr5M/zcnLR3zMrJ7vckd5sBkZyUKIcyjLc/A+E= ARC-Message-Signature: i=1; a=rsa-sha256; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-11-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Brian Masney , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=2061; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=5r6DxrE7zrZMVgoolkWus+HukdRlhbqUOz9ok20ajpM=; b=KE5Pv3Qj6DFnkoSUCpTkq8rs0H1dNBtaec57IdUZvg1GB9ONoPJ06FxF/aqbb9f2vEOyjZMik pd/kw6TJjgtBQ2WyQEQiUYYgX6qcqAf+HwYppaatZeKyqtT8pLFP3KK X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= In order to prepare the MT8189 SoC support, that requires different registers to control PLL status and perform reset BAR, and so a different sets of clock operations, split the pll power on and off sequences from mtk_pll_prepare/unprepare functions into private subfunctions. Reviewed-by: Brian Masney Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-pll.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 4b0f7e2bfc5a..2aaf2871ecf6 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -223,9 +223,8 @@ int mtk_pll_determine_rate(struct clk_hw *hw, struct cl= k_rate_request *req) return 0; } =20 -int mtk_pll_prepare(struct clk_hw *hw) +static void mtk_pll_power_on(struct mtk_clk_pll *pll) { - struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); u32 r; =20 r =3D readl(pll->pwr_addr) | CON0_PWR_ON; @@ -235,6 +234,25 @@ int mtk_pll_prepare(struct clk_hw *hw) r =3D readl(pll->pwr_addr) & ~CON0_ISO_EN; writel(r, pll->pwr_addr); udelay(1); +} + +static void mtk_pll_power_off(struct mtk_clk_pll *pll) +{ + u32 r; + + r =3D readl(pll->pwr_addr) | CON0_ISO_EN; + writel(r, pll->pwr_addr); + + r =3D readl(pll->pwr_addr) & ~CON0_PWR_ON; + writel(r, pll->pwr_addr); +} + +int mtk_pll_prepare(struct clk_hw *hw) +{ + struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); + u32 r; + + mtk_pll_power_on(pll); =20 r =3D readl(pll->en_addr) | BIT(pll->data->pll_en_bit); writel(r, pll->en_addr); @@ -278,11 +296,7 @@ void mtk_pll_unprepare(struct clk_hw *hw) r =3D readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit); writel(r, pll->en_addr); =20 - r =3D readl(pll->pwr_addr) | CON0_ISO_EN; - writel(r, pll->pwr_addr); - - r =3D readl(pll->pwr_addr) & ~CON0_PWR_ON; - writel(r, pll->pwr_addr); + mtk_pll_power_off(pll); } =20 static int mtk_pll_prepare_fenc_setclr(struct clk_hw *hw) --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89B8E503BF9; Fri, 4 Sep 2026 15:59:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 04 Sep 2026 17:59:00 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:23 +0200 Subject: [PATCH v6 12/27] clk: mediatek: pll: Add PLL stabilization delay definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-12-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Brian Masney , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=1541; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=1piwe291SJzHCvmYgTYe5CleobD/ifmr/BhtwFBgFOM=; b=Hf+3XAUnkaNPFk/JON0jY6so4Hv87b2O1iV3DYnqgYm8uFi+Du6QhH8HQpCO/XJDS9hI+0Kg2 hwnCoRpqfwxC4+9BVkswxVMtOnypcRDcNJHern4dddIasH0USa5ryN6 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Several functions uses a hardcoded value (20), to represent the needed delay to stabilize a PLL. Add a common define for this value. Reviewed-by: Brian Masney Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-pll.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 2aaf2871ecf6..9a197a657dce 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -31,6 +31,8 @@ /* default 7 bits integer, can be overridden with pcwibits. */ #define INTEGER_BITS 7 =20 +#define PLL_STABILIZATION_DELAY 20 /* in us */ + int mtk_pll_is_prepared(struct clk_hw *hw) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); @@ -131,7 +133,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *p= ll, u32 pcw, /* restore tuner_en */ __mtk_pll_tuner_enable(pll); =20 - udelay(20); + udelay(PLL_STABILIZATION_DELAY); } =20 /* @@ -264,7 +266,7 @@ int mtk_pll_prepare(struct clk_hw *hw) =20 __mtk_pll_tuner_enable(pll); =20 - udelay(20); + udelay(PLL_STABILIZATION_DELAY); =20 if (pll->data->flags & HAVE_RST_BAR) { r =3D readl(pll->rst_bar_addr); @@ -306,7 +308,7 @@ static int mtk_pll_prepare_fenc_setclr(struct clk_hw *h= w) writel(BIT(pll->data->pll_en_bit), pll->en_set_addr); =20 /* Wait 20us after enable for the PLL to stabilize */ - udelay(20); + udelay(PLL_STABILIZATION_DELAY); =20 return 0; } --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA048509F01; Fri, 4 Sep 2026 15:59:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537547; cv=none; b=OXWN5f0aCj5MftnLi4EYR/5o9m8tc5PRLqRtAMbFVb4+Ba6V6pfD0WHQk6ZJtuFdKmGXO3RpLXPeAkF50o2KfRCOY/KEv0pvVw5rxNjTd72fL2xtvvNSF2/5bNiDgmJmMA8nt+VIMHBjNVHkYWPt3JOllQQ5YS07poUxPN/9ogE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-13-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Brian Masney , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=4559; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=yyN8kGE+J/DS18+i2Sn6ERdizi7ZNzizwXys/5jFoLA=; b=cVnxk3EsDnP4Qyo5Ymqbx0XGSMPcLwZWTvi24mpl4PYGG5rK6PkYIAy2NGjH+SDwSYTD2J7Dr dAPOpTtTfBwAbHLuryNPaH1PRnK+g0rENN53RL0Ld3vXqDDOOaToaDA X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= MT8189 SoC uses a new combination of status and set/clr registers to control its PLL enable state and perform BAR reset, that are different than the current default clock prepare/unprepare operations are using. Add new set of PLL clock operations to support this logic that relies on the following registers for prepare/unprepare operations: - en/en_set/en_clr, rather than en register, for PLL enable control - rst_bar/rst_bar_set/rst_bar_clr, rather than default rst_bar register for BAR reset control Also, handle rst_bar register setting/clearing with a timeout, to verify the operation was correctly performed. Reviewed-by: Brian Masney Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-pll.c | 67 ++++++++++++++++++++++++++++++++++++++= ++++ drivers/clk/mediatek/clk-pll.h | 5 ++++ 2 files changed, 72 insertions(+) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 9a197a657dce..f32b9145f256 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,7 @@ #define INTEGER_BITS 7 =20 #define PLL_STABILIZATION_DELAY 20 /* in us */ +#define RST_BAR_TIMEOUT 20 /* in us */ =20 int mtk_pll_is_prepared(struct clk_hw *hw) { @@ -301,6 +303,61 @@ void mtk_pll_unprepare(struct clk_hw *hw) mtk_pll_power_off(pll); } =20 +int mtk_pll_prepare_setclr(struct clk_hw *hw) +{ + struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); + u32 val =3D 0; + int ret; + + mtk_pll_power_on(pll); + + writel(BIT(pll->data->pll_en_bit), pll->en_set_addr); + + __mtk_pll_tuner_enable(pll); + + udelay(PLL_STABILIZATION_DELAY); + + if (pll->data->flags & HAVE_RST_BAR) { + writel(pll->data->rst_bar_mask, pll->rst_bar_set_addr); + + ret =3D readl_poll_timeout(pll->rst_bar_addr, val, + (val & pll->data->rst_bar_mask), 1, + RST_BAR_TIMEOUT); + if (ret) { + mtk_pll_unprepare_setclr(hw); + return ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(mtk_pll_prepare_setclr); + +void mtk_pll_unprepare_setclr(struct clk_hw *hw) +{ + struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); + u32 val =3D 0; + + if (pll->data->flags & HAVE_RST_BAR) { + writel(pll->data->rst_bar_mask, pll->rst_bar_clr_addr); + + /* + * Ignore return code to continue unpreparing the PLL if + * an error occurs on register read poll. + */ + readl_poll_timeout(pll->rst_bar_addr, val, + !(val & pll->data->rst_bar_mask), 1, + RST_BAR_TIMEOUT); + } + + __mtk_pll_tuner_disable(pll); + + writel(BIT(pll->data->pll_en_bit), pll->en_clr_addr); + + mtk_pll_power_off(pll); +} +EXPORT_SYMBOL_GPL(mtk_pll_unprepare_setclr); + static int mtk_pll_prepare_fenc_setclr(struct clk_hw *hw) { struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); @@ -329,6 +386,16 @@ const struct clk_ops mtk_pll_ops =3D { .set_rate =3D mtk_pll_set_rate, }; =20 +const struct clk_ops mtk_pll_setclr_ops =3D { + .is_prepared =3D mtk_pll_is_prepared, + .prepare =3D mtk_pll_prepare_setclr, + .unprepare =3D mtk_pll_unprepare_setclr, + .recalc_rate =3D mtk_pll_recalc_rate, + .determine_rate =3D mtk_pll_determine_rate, + .set_rate =3D mtk_pll_set_rate, +}; +EXPORT_SYMBOL_GPL(mtk_pll_setclr_ops); + const struct clk_ops mtk_pll_fenc_setclr_ops =3D { .is_prepared =3D mtk_pll_is_prepared_fenc_setclr, .prepare =3D mtk_pll_prepare_fenc_setclr, diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index 3aaf3a7654b5..296bed073290 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -92,6 +92,7 @@ void mtk_clk_unregister_plls(const struct mtk_pll_data *p= lls, int num_plls, =20 extern const struct clk_ops mtk_pll_ops; extern const struct clk_ops mtk_pll_fenc_setclr_ops; +extern const struct clk_ops mtk_pll_setclr_ops; =20 static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) { @@ -104,6 +105,10 @@ int mtk_pll_prepare(struct clk_hw *hw); =20 void mtk_pll_unprepare(struct clk_hw *hw); =20 +int mtk_pll_prepare_setclr(struct clk_hw *hw); + +void mtk_pll_unprepare_setclr(struct clk_hw *hw); + unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_= rate); =20 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7430750AC1C; Fri, 4 Sep 2026 15:59:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; 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Fri, 04 Sep 2026 17:59:03 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:25 +0200 Subject: [PATCH v6 14/27] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-14-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Brian Masney , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=1957; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=GZT4Tprcj/cd8JTciRawSozIscP5ax133CBUIJ7G/TE=; b=rSIeVlaiKUPL4Z84GRg4Kqkc0Zl93GkEnK5ZmjNv6niMwTaO03+XlMdyN3Esej8b9rTSMMSO2 0b4dHRmkrQGCmJtSEoKPgFHE2YLrC4FTTtCPtZ/ETAU0kbP5kDoHYpn X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Currently, the mtk_clk_register_pllfh functions always registers the default PLL clock operation set (mtk_pllfh_ops). This does not allow use a custom one, for SoC such as MT8189, that needs different set with support for set/clr enable. Add a new field for the ops to register in mtk_pllfh_data structure and use this new field to either register it when not null or the default ops otherwise. Reviewed-by: Brian Masney Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-pllfh.c | 5 +++-- drivers/clk/mediatek/clk-pllfh.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pl= lfh.c index 6249fb87b1f5..cc73eb4f87e6 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -153,6 +153,8 @@ static struct clk_hw * mtk_clk_register_pllfh(struct device *dev, const struct mtk_pll_data *pll_= data, struct mtk_pllfh_data *pllfh_data, void __iomem *base) { + const struct clk_ops *pllfh_ops =3D pllfh_data->data.ops ? + pllfh_data->data.ops : &mtk_pllfh_ops; struct clk_hw *hw; struct mtk_fh *fh; int ret; @@ -169,8 +171,7 @@ mtk_clk_register_pllfh(struct device *dev, const struct= mtk_pll_data *pll_data, =20 fh->clk_pll.dev =3D dev; =20 - hw =3D mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, - &mtk_pllfh_ops); + hw =3D mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, pllfh_ops); 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a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add new set of PLL FHCTL clock operations, that uses the new prepare and unprepare methods, added in PLL for MT8189 SoC to support this logic. Reviewed-by: Brian Masney Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-pllfh.c | 10 ++++++++++ drivers/clk/mediatek/clk-pllfh.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pl= lfh.c index cc73eb4f87e6..f36dbc7fa06d 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -47,6 +47,16 @@ static const struct clk_ops mtk_pllfh_ops =3D { .set_rate =3D mtk_fhctl_set_rate, }; =20 +const struct clk_ops mtk_pllfh_setclr_ops =3D { + .is_prepared =3D mtk_pll_is_prepared, + .prepare =3D mtk_pll_prepare_setclr, + .unprepare =3D mtk_pll_unprepare_setclr, + .recalc_rate =3D mtk_pll_recalc_rate, + .determine_rate =3D mtk_pll_determine_rate, + .set_rate =3D mtk_fhctl_set_rate, +}; +EXPORT_SYMBOL_GPL(mtk_pllfh_setclr_ops); + static struct mtk_pllfh_data *get_pllfh_by_id(struct mtk_pllfh_data *pllfh= s, int num_fhs, int pll_id) { diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pl= lfh.h index d32bfe194ec4..a9eb7558de1c 100644 --- a/drivers/clk/mediatek/clk-pllfh.h +++ b/drivers/clk/mediatek/clk-pllfh.h @@ -69,6 +69,8 @@ struct fh_operation { int (*ssc_enable)(struct mtk_fh *fh, u32 rate); }; =20 +extern const struct clk_ops mtk_pllfh_setclr_ops; + int mtk_clk_register_pllfhs(struct device *dev, const struct mtk_pll_data *plls, int num_plls, struct mtk_pllfh_data *pllfhs, int num_pllfhs, --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E8C650C2AC; Fri, 4 Sep 2026 15:59:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537551; cv=none; b=kjm3bOaNXuPNZe4UWPKQP2k5mU8jC53mY8o+X3xwpI5nEsmcGt4LA1WTyEHZecjCc5/b4EONkAqyCxzwUsA59M1Hum0sOhhNP6TpEsAgoeEJRjQ1TOCnUZaYP5CXHpt93P7F7z3tzQGq0dOR4HIHhLpsZZgYUAqkm9V64P2baDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537551; c=relaxed/simple; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-16-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=7115; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=nMeyY06EOfx0vESy7Xk1OSBkWXqd9xnXY6V0LsKPumI=; b=1SKsMeMoCDyzxqq0sn/6HXcDLmGa7Byn+TqzhC1ivIqdHMA9HOha2Y6aUfeud7WgV8eW58+sl duQqiRnNvGPAVBDAGv/zQs9rSPmJ4Y+Gx40aIK3GFFeQ7w6y+Tvi8jc X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Currently, in the probe functions of apmixedsys drivers with PLL frequency hopping support (FHCTL), the call to mtk_clk_register_pllfh is always preceded by a call to fhctl_parse_dt. This function purpose is to prepare FHCTL-related internal data, that are then used by mtk_clk_register_pllfhs. It is not used in another case and both functions are implemented in the same source file (clk-pllfh.c). There is little interest to keep as it this call sequence in the several probe functions. So, add an additional parameter (compatible name string) in mtk_clk_register_pllfhs and move the fhctl_parse_dt call into it. Finally, make this function private by removing it from clk-pllfh.h include, remove its EXPORT_SYMBOL_GPL macro use and add the static keyword. Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 3 +-- drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 5 ++--- drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 4 +--- drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 4 +--- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 4 +--- drivers/clk/mediatek/clk-pllfh.c | 10 ++++++---- drivers/clk/mediatek/clk-pllfh.h | 5 +---- 7 files changed, 13 insertions(+), 22 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/med= iatek/clk-mt6795-apmixedsys.c index 123d5d7fea85..a860708ef908 100644 --- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c @@ -151,8 +151,7 @@ static int clk_mt6795_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - ret =3D mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls), + ret =3D mtk_clk_register_pllfhs(dev, fhctl_node, plls, ARRAY_SIZE(plls), pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (ret) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8173-apmixedsys.c index d7d416172ab3..8920eb1c3fa6 100644 --- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c @@ -156,9 +156,8 @@ static int clk_mt8173_apmixed_probe(struct platform_dev= ice *pdev) goto unmap_io; } =20 - fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - r =3D mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls), pllfhs, - ARRAY_SIZE(pllfhs), clk_data); + r =3D mtk_clk_register_pllfhs(dev, fhctl_node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8186-apmixedsys.c index d35dd2632e43..e8fc6bd90fcb 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -149,9 +149,7 @@ static int clk_mt8186_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - - r =3D mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls), + r =3D mtk_clk_register_pllfhs(&pdev->dev, fhctl_node, plls, ARRAY_SIZE(pl= ls), pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_apmixed_data; diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8192-apmixedsys.c index b0563a285bd6..2e4f5aff9eee 100644 --- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c @@ -160,9 +160,7 @@ static int clk_mt8192_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - - r =3D mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls), + r =3D mtk_clk_register_pllfhs(&pdev->dev, fhctl_node, plls, ARRAY_SIZE(pl= ls), pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8195-apmixedsys.c index a120c3305547..12e51b39b764 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -178,9 +178,7 @@ static int clk_mt8195_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - - r =3D mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls), + r =3D mtk_clk_register_pllfhs(&pdev->dev, fhctl_node, plls, ARRAY_SIZE(pl= ls), pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_apmixed_data; diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pl= lfh.c index f36dbc7fa06d..398edad2a69e 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -69,8 +69,9 @@ static struct mtk_pllfh_data *get_pllfh_by_id(struct mtk_= pllfh_data *pllfhs, return NULL; } =20 -void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllf= hs, - int num_fhs) +static void fhctl_parse_dt(const u8 *compatible_node, + struct mtk_pllfh_data *pllfhs, + int num_fhs) { void __iomem *base; struct device_node *node; @@ -121,7 +122,6 @@ void fhctl_parse_dt(const u8 *compatible_node, struct m= tk_pllfh_data *pllfhs, iounmap(base); goto out_node_put; } -EXPORT_SYMBOL_GPL(fhctl_parse_dt); =20 static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data) { @@ -252,7 +252,7 @@ static void mtk_clk_cleanup_pllfhs(void __iomem *iomem_= base, } =20 =20 -int mtk_clk_register_pllfhs(struct device *dev, +int mtk_clk_register_pllfhs(struct device *dev, const u8 *fhctl_node, const struct mtk_pll_data *plls, int num_plls, struct mtk_pllfh_data *pllfhs, int num_fhs, struct clk_hw_onecell_data *clk_data) @@ -261,6 +261,8 @@ int mtk_clk_register_pllfhs(struct device *dev, int i; struct clk_hw *hw; =20 + fhctl_parse_dt(fhctl_node, pllfhs, num_fhs); + base =3D of_iomap(dev->of_node, 0); if (!base) { pr_err("%s(): ioremap failed\n", __func__); diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pl= lfh.h index a9eb7558de1c..07269e467e34 100644 --- a/drivers/clk/mediatek/clk-pllfh.h +++ b/drivers/clk/mediatek/clk-pllfh.h @@ -71,7 +71,7 @@ struct fh_operation { =20 extern const struct clk_ops mtk_pllfh_setclr_ops; =20 -int mtk_clk_register_pllfhs(struct device *dev, +int mtk_clk_register_pllfhs(struct device *dev, const u8 *fhctl_node, const struct mtk_pll_data *plls, int num_plls, struct mtk_pllfh_data *pllfhs, int num_pllfhs, struct clk_hw_onecell_data *clk_data); @@ -80,7 +80,4 @@ void mtk_clk_unregister_pllfhs(const struct mtk_pll_data = *plls, int num_plls, struct mtk_pllfh_data *pllfhs, int num_fhs, struct clk_hw_onecell_data *clk_data); =20 -void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllf= hs, - int num_pllfhs); - #endif /* __CLK_PLLFH_H */ --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B94350EBE9; Fri, 4 Sep 2026 15:59:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537552; cv=none; b=svtrCp2XWdi8UaQkDvQvtGZB561OYfR+cT8mVH3q9F65vO31lItdvwNXrK8PYTLasxSzl1pBomFAgwuTx8u9ltn7wC5R9qtyLo12P2p1ozNk1Cb4eYWc+U3bE7CtkM3itpHUFlM8/ywkcyeN1NFd5Di7UHBOilzG2eWUQ/DQ8ew= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-17-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=1162; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=AjWZadrtSiC8GDg0pLJcG+NWHWGZanfk+LgDY0etyOM=; b=w4ppgXFeiUJ/ZE3L7QLNPm/6CukSJEtWcDH58QkUDxCepyfL1dLJumsqpG34qMYMXVrl3jPc9 h98KyNf6ZFNAIwcOKpVzZg/mxqiS35y1nv2x/Fw7tr+0dUdb9Jjeqeu X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Currently, fhctl_parse_dt function sets some state variables that are never cleared in the unregister nominal path or register error one. As they are stored in a static array variable, given as parameter from the caller function, they retain their values until they are initialized again by another fhctl_parse_dt call. So, add a loop to clear these state variables in mtk_clk_cleanup_pllfhs function. Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-pllfh.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pl= lfh.c index 398edad2a69e..ae56d4ad66dc 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -244,6 +244,14 @@ static void mtk_clk_cleanup_pllfhs(void __iomem *iomem= _base, clk_data->hws[pll->id] =3D ERR_PTR(-ENOENT); } =20 + for (i =3D 0; i < num_fhs; i++) { + struct mtk_pllfh_data *pllfh =3D &pllfhs[i]; + + pllfh->state.fh_enable =3D 0; + pllfh->state.ssc_rate =3D 0; + pllfh->state.base =3D NULL; + } + if (fhctl_base) iounmap(fhctl_base); =20 --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4071A50EBFA; Fri, 4 Sep 2026 15:59:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537553; cv=none; b=vAqifC6m4VHFkqE2ue2tnAfiS0UIVOS+YEOce6uJDR4neNXvLUNG4WIS3F+qyKDTxvtAOI9IwNtLvOe1hAwlFQPtKSIxYucswXbdo3xa6hdP1yvAzwTm89oUoviI1Q9hg2fz0FAMs+6RfNLFNoKFNVUyoH8IIs13Gi+eFQe0Uyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537553; c=relaxed/simple; bh=GuUn8E5bHCFmuECVsnIr+eEHhTiELVVqPbfT6QAL8tU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XLQPkAXRn4XMxCb0l9dnzfTJ6pLV4HG2X7QLFuXWcNWu/JuERf4rCIAKcO1GGvlhGvP9UVG7zXzX2OYsC4jbWZT6UZ8pB1+lr60hwns+KBDShTLq6I80QHtp4hGHr/rOp32IilwWg2RY74s2vK/9hzlU5LyiMEsXCr2WboTX4Oc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=WBQcrmTC; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="WBQcrmTC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788537549; bh=GuUn8E5bHCFmuECVsnIr+eEHhTiELVVqPbfT6QAL8tU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=WBQcrmTCrk/DlCZdR7aShla98sIyRbSgYnyG/exl3upWmG6UkGvHJ1Ch3rJvXBxuG L/KFEgsynlMX+BhH08EUCPNwfs6TAlfgdmzI5sKEaWoV1WsBtsUzykpmodQJbPzoZ+ WOsWaRFbsCkH5ZnAGEwvaRLKZBPzayu9BomzRSz6R2WQix7jXMsRfi65Lc/VCGzP5H knF2WMkkpJHb40UM45kGM9hCyXYbl7+f7oBK2wRpkWkiXgqZ/qEv046N0UxvgwuJdJ /xLG8pLAjJrY4ioOWtcIqtQY99oVxwynfbg8vRrpLGZ69yqD+85k8muh7td1ko42Iv wXM/yd88AnEHA== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8E4B017E092E; Fri, 04 Sep 2026 17:59:08 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:29 +0200 Subject: [PATCH v6 18/27] clk: mediatek: Add MT8189 apmixedsys clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-18-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=9994; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=GuUn8E5bHCFmuECVsnIr+eEHhTiELVVqPbfT6QAL8tU=; b=/aYCm3gSBGyTA+6OQVeyRuKemmy0XyIGa+JQSiZXppNgRllGbEpPmgIWISQY/HlXMSdQgSNwe FLLLTMR6mcFA10erd03DagPdCwedursszCTzq2hK6E+qKOh/MVYBOYS X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 apmixedsys clock controller, which provides PLLs generated from SoC 26m. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Kconfig | 13 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-apmixedsys.c | 202 +++++++++++++++++++++++= ++++ 3 files changed, 216 insertions(+) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index b059d44577f1..d1200be0166c 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -825,6 +825,19 @@ config COMMON_CLK_MT8188_WPESYS help This driver supports MediaTek MT8188 Warp Engine clocks. =20 +config COMMON_CLK_MT8189 + tristate "Clock driver for MediaTek MT8189" + depends on ARM64 || COMPILE_TEST + select COMMON_CLK_MEDIATEK + select COMMON_CLK_MEDIATEK_FHCTL + default ARCH_MEDIATEK + help + Enable this option to support the clock management for MediaTek MT8189 = SoC. This + includes handling of all primary clock functions and features specific = to the MT8189 + platform. Enabling this driver ensures that the system's clock function= ality aligns + with the MediaTek MT8189 hardware capabilities, providing efficient man= agement of + clock speeds and power consumption. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 892a54eeb281..79b8ee47a867 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -124,6 +124,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) +=3D clk-mt8188-= vdo0.o clk-mt8188-vdo1.o obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) +=3D clk-mt8188-venc.o obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) +=3D clk-mt8188-vpp0.o clk-mt8188-v= pp1.o obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) +=3D clk-mt8188-wpe.o +obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8189-apmixedsys.c new file mode 100644 index 000000000000..7399a444ec4d --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-apmixedsys.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include + +#include +#include +#include + +#include "clk-fhctl.h" +#include "clk-mtk.h" +#include "clk-pll.h" + +#define MT8189_PLL_FMAX (3800UL * MHZ) +#define MT8189_PLL_FMIN (1500UL * MHZ) +#define MT8189_PLLEN_OFS 0x70 +#define MT8189_PLLEN_SET_OFS 0x74 +#define MT8189_PLLEN_CLR_OFS 0x78 +#define MT8189_RSTBAR_OFS 0x80 +#define MT8189_RSTBAR_SET_OFS 0x84 +#define MT8189_RSTBAR_CLR_OFS 0x88 +#define MT8189_INTEGER_BITS 8 + +#define PLL_SETCLR(_id, _name, _reg, _pwr_reg, _en_setclr_bit, \ + _rstb_setclr_bit, _flags, _pd_reg, \ + _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _pcwbits) { \ + .id =3D _id, \ + .name =3D _name, \ + .en_reg =3D MT8189_PLLEN_OFS, \ + .en_set_reg =3D MT8189_PLLEN_SET_OFS, \ + .en_clr_reg =3D MT8189_PLLEN_CLR_OFS, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .pll_en_bit =3D _en_setclr_bit, \ + .rst_bar_reg =3D MT8189_RSTBAR_OFS, \ + .rst_bar_set_reg =3D MT8189_RSTBAR_SET_OFS, \ + .rst_bar_clr_reg =3D MT8189_RSTBAR_CLR_OFS, \ + .rst_bar_mask =3D BIT(_rstb_setclr_bit), \ + .flags =3D _flags, \ + .fmax =3D MT8189_PLL_FMAX, \ + .fmin =3D MT8189_PLL_FMIN, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .tuner_en_reg =3D _tuner_en_reg, \ + .tuner_en_bit =3D _tuner_en_bit, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .pcwbits =3D _pcwbits, \ + .pcwibits =3D MT8189_INTEGER_BITS, \ + .ops =3D &mtk_pll_setclr_ops, \ + } + +static const struct mtk_pll_data apmixed_plls[] =3D { + PLL_SETCLR(CLK_APMIXED_ARMPLL_LL, "armpll-ll", 0x204, 0x210, 18, + 0, PLL_AO, 0x208, 24, 0, 0, 0, 0x208, 0, 22), + PLL_SETCLR(CLK_APMIXED_ARMPLL_BL, "armpll-bl", 0x214, 0x220, 17, + 0, PLL_AO, 0x218, 24, 0, 0, 0, 0x218, 0, 22), + PLL_SETCLR(CLK_APMIXED_CCIPLL, "ccipll", 0x224, 0x230, 16, + 0, PLL_AO, 0x228, 24, 0, 0, 0, 0x228, 0, 22), + PLL_SETCLR(CLK_APMIXED_MAINPLL, "mainpll", 0x304, 0x310, 15, + 2, HAVE_RST_BAR | PLL_AO, + 0x308, 24, 0, 0, 0, 0x308, 0, 22), + PLL_SETCLR(CLK_APMIXED_UNIVPLL, "univpll", 0x314, 0x320, 14, + 1, HAVE_RST_BAR, 0x318, 24, 0, 0, 0, 0x318, 0, 22), + PLL_SETCLR(CLK_APMIXED_MMPLL, "mmpll", 0x324, 0x330, 13, + 0, HAVE_RST_BAR, 0x328, 24, 0, 0, 0, 0x328, 0, 22), + PLL_SETCLR(CLK_APMIXED_MFGPLL, "mfgpll", 0x504, 0x510, 7, + 0, 0, 0x508, 24, 0, 0, 0, 0x508, 0, 22), + PLL_SETCLR(CLK_APMIXED_APLL1, "apll1", 0x404, 0x414, 11, + 0, 0, 0x408, 24, 0x040, 0x00c, 0, 0x40c, 0, 32), + PLL_SETCLR(CLK_APMIXED_APLL2, "apll2", 0x418, 0x428, 10, + 0, 0, 0x41c, 24, 0x044, 0x00c, 1, 0x420, 0, 32), + PLL_SETCLR(CLK_APMIXED_EMIPLL, "emipll", 0x334, 0x340, 12, + 0, PLL_AO, 0x338, 24, 0, 0, 0, 0x338, 0, 22), + PLL_SETCLR(CLK_APMIXED_APUPLL2, "apupll2", 0x614, 0x620, 2, + 0, 0, 0x618, 24, 0, 0, 0, 0x618, 0, 22), + PLL_SETCLR(CLK_APMIXED_APUPLL, "apupll", 0x604, 0x610, 3, + 0, 0, 0x608, 24, 0, 0, 0, 0x608, 0, 22), + PLL_SETCLR(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x42c, 0x438, 9, + 0, 0, 0x430, 24, 0, 0, 0, 0x430, 0, 22), + PLL_SETCLR(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x43c, 0x448, 8, + 0, 0, 0x440, 24, 0, 0, 0, 0x440, 0, 22), + PLL_SETCLR(CLK_APMIXED_ETHPLL, "ethpll", 0x514, 0x520, 6, + 0, 0, 0x518, 24, 0, 0, 0, 0x518, 0, 22), + PLL_SETCLR(CLK_APMIXED_MSDCPLL, "msdcpll", 0x524, 0x530, 5, + 0, 0, 0x528, 24, 0, 0, 0, 0x528, 0, 22), + PLL_SETCLR(CLK_APMIXED_UFSPLL, "ufspll", 0x534, 0x540, 4, + 0, 0, 0x538, 24, 0, 0, 0, 0x538, 0, 22), +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V2, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D 0x6003c97, \ + .slope1_value =3D 0x6003c97, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + .ops =3D &mtk_pllfh_setclr_ops, \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_ARMPLL_LL, 0, 0x003C), + FH(CLK_APMIXED_ARMPLL_BL, 1, 0x0050), + FH(CLK_APMIXED_CCIPLL, 2, 0x0064), + FH(CLK_APMIXED_MAINPLL, 3, 0x0078), + FH(CLK_APMIXED_MMPLL, 4, 0x008C), + FH(CLK_APMIXED_MFGPLL, 5, 0x00A0), + FH(CLK_APMIXED_EMIPLL, 6, 0x00B4), + FH(CLK_APMIXED_TVDPLL1, 7, 0x00C8), + FH(CLK_APMIXED_TVDPLL2, 8, 0x00DC), + FH(CLK_APMIXED_MSDCPLL, 9, 0x00F0), + FH(CLK_APMIXED_UFSPLL, 10, 0x0104), + FH(CLK_APMIXED_APUPLL, 11, 0x0118), + FH(CLK_APMIXED_APUPLL2, 12, 0x012c), +}; + +static const struct of_device_id of_match_clk_mt8189_apmixed[] =3D { + { .compatible =3D "mediatek,mt8189-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_apmixed); + +static int clk_mt8189_apmixed_probe(struct platform_device *pdev) +{ + const u8 *fhctl_node =3D "mediatek,mt8189-fhctl"; + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data; + int r; + + clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls)); + if (!clk_data) + return -ENOMEM; + + r =3D mtk_clk_register_pllfhs(&pdev->dev, fhctl_node, apmixed_plls, + ARRAY_SIZE(apmixed_plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); + if (r) + goto free_apmixed_data; + + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + goto unregister_plls; + + platform_set_drvdata(pdev, clk_data); + + return 0; + +unregister_plls: + mtk_clk_unregister_pllfhs(apmixed_plls, ARRAY_SIZE(apmixed_plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); +free_apmixed_data: + mtk_free_clk_data(clk_data); + return r; +} + +static void clk_mt8189_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_pllfhs(apmixed_plls, ARRAY_SIZE(apmixed_plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); + mtk_free_clk_data(clk_data); +} + +static struct platform_driver clk_mt8189_apmixed_drv =3D { + .probe =3D clk_mt8189_apmixed_probe, + .remove =3D clk_mt8189_apmixed_remove, + .driver =3D { + .name =3D "clk-mt8189-apmixed", + .of_match_table =3D of_match_clk_mt8189_apmixed, + }, +}; +module_platform_driver(clk_mt8189_apmixed_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 apmixed clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E61A5111A0; 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Fri, 04 Sep 2026 17:59:09 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:30 +0200 Subject: [PATCH v6 19/27] clk: mediatek: Add MT8189 topckgen clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-19-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=34568; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=TyQ9kKvNP6z0h7jJvcgHi3L6GivB7Vxoxc38QyoK9PE=; b=kjZljLd2M51N2F6F0SXvFayHiU43wt3PyjAPRSVeiD9dPPWCm5IChuzs0T5ricXDIl71tpr4N vbe1NFV5SPyCpZgNuw3EuhFPEYe8MYssXqUNY+ZyR4aUBRsmEVRlY1Z X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 topckgen clock controller, which provides muxes and dividers for clock selection in other IP blocks. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8189-topckgen.c | 1019 ++++++++++++++++++++++++= ++++ 2 files changed, 1020 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 79b8ee47a867..eb9a1f3efebe 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -124,7 +124,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) +=3D clk-mt8188-= vdo0.o clk-mt8188-vdo1.o obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) +=3D clk-mt8188-venc.o obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) +=3D clk-mt8188-vpp0.o clk-mt8188-v= pp1.o obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) +=3D clk-mt8188-wpe.o -obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o +obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o clk-mt8189-to= pckgen.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-topckgen.c b/drivers/clk/media= tek/clk-mt8189-topckgen.c new file mode 100644 index 000000000000..6ed7661119b8 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-topckgen.c @@ -0,0 +1,1019 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-mux.h" +#include "clk-gate.h" + +static DEFINE_SPINLOCK(mt8189_clk_lock); + +static const struct mtk_fixed_factor top_divs[] =3D { + FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), + FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), + FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll", 1, 8), + FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll", 1, 16), + FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll", 1, 32), + FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), + FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll", 1, 10), + FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll", 1, 20), + FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll", 1, 40), + FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6), + FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll", 1, 12), + FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll", 1, 24), + FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll", 1, 48), + FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), + FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll", 1, 14), + FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll", 1, 28), + FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll", 1, 56), + FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9), + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), + FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4), + FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll", 1, 8), + FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll", 1, 16), + FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll", 1, 32), + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), + FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll", 1, 10), + FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll", 1, 20), + FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6), + FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll", 1, 12), + FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll", 1, 24), + FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll", 1, 48), + FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll", 1, 96), + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), + FACTOR(CLK_TOP_UNIVPLL_D7_D2, "univpll_d7_d2", "univpll", 1, 14), + FACTOR(CLK_TOP_UNIVPLL_D7_D3, "univpll_d7_d3", "univpll", 1, 21), + FACTOR(CLK_TOP_LVDSTX_DG_CTS, "lvdstx_dg_cts", "univpll", 1, 21), + FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13), + FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll", 1, 26), + FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll", 1, 52), + FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll", 1, 104), + FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll", 1, 130), + FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll", 1, 208), + FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll", 1, 416), + FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), + FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), + FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3), + FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), + FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), + FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3), + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), + FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll", 1, 8), + FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll", 1, 16), + FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix", "mmpll", 1, 16), + FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), + FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll", 1, 10), + FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll", 1, 20), + FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), + FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12), + FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), + FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9), + FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2), + FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4), + FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8), + FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16), + FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2), + FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4), + FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8), + FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16), + FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2), + FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8), + FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10), + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), + FACTOR(CLK_TOP_UFSPLL_D2, "ufspll_d2", "ufspll", 1, 2), + FACTOR(CLK_TOP_F26M_CK_D2, "f26m_d2", "clk26m", 1, 2), + FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2), + FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4), + FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8), + FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16), + FACTOR(CLK_TOP_OSC_D3, "osc_d3", "ulposc", 1, 3), + FACTOR(CLK_TOP_OSC_D7, "osc_d7", "ulposc", 1, 7), + FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10), + FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20), +}; + +static const char * const ap2conn_host_parents[] =3D { + "clk26m", + "mainpll_d7_d4" +}; + +static const char * const apll_m_parents[] =3D { + "aud_1_sel", + "aud_2_sel" +}; + +static const char * const aud_1_parents[] =3D { + "clk26m", + "apll1" +}; + +static const char * const aud_2_parents[] =3D { + "clk26m", + "apll2" +}; + +static const char * const mfg_sel_mfgpll_parents[] =3D { + "mfg_ref_sel", + "mfgpll" +}; + +static const char * const pwm_parents[] =3D { + "clk26m", + "univpll_d4_d8" +}; + +static const char * const snps_eth_250m_parents[] =3D { + "clk26m", + "ethpll_d2" +}; + +static const char * const snps_eth_50m_rmii_parents[] =3D { + "clk26m", + "ethpll_d10" +}; + +static const char * const uart_parents[] =3D { + "clk26m", + "univpll_d6_d8" +}; + +static const char * const atb_parents[] =3D { + "clk26m", + "mainpll_d4_d2", + "mainpll_d5_d2" +}; + +static const char * const aud_intbus_parents[] =3D { + "clk26m", + "mainpll_d4_d4", + "mainpll_d7_d4" +}; + +static const char * const msdc5hclk_parents[] =3D { + "clk26m", + "mainpll_d4_d2", + "mainpll_d6_d2" +}; + +static const char * const pcie_mac_tl_parents[] =3D { + "clk26m", + "mainpll_d4_d4", + "univpll_d5_d4" +}; + +static const char * const pll_dpix_parents[] =3D { + "clk26m", + "vpll_dpix", + "mmpll_d4_d4" +}; + +static const char * const usb_parents[] =3D { + "clk26m", + "univpll_d5_d4", + "univpll_d6_d4" +}; + +static const char * const vdstx_dg_cts_parents[] =3D { + "clk26m", + "lvdstx_dg_cts", + "univpll_d7_d3" +}; + +static const char * const audio_h_parents[] =3D { + "clk26m", + "univpll_d7_d2", + "apll1", + "apll2" +}; + +static const char * const aud_engen1_parents[] =3D { + "clk26m", + "apll1_d2", + "apll1_d4", + "apll1_d8" +}; + +static const char * const aud_engen2_parents[] =3D { + "clk26m", + "apll2_d2", + "apll2_d4", + "apll2_d8" +}; + +static const char * const axi_peri_parents[] =3D { + "clk26m", + "mainpll_d4_d4", + "mainpll_d7_d2", + "osc_d4" +}; + +static const char * const axi_u_parents[] =3D { + "clk26m", + "mainpll_d4_d8", + "mainpll_d7_d4", + "osc_d8" +}; + +static const char * const camtm_parents[] =3D { + "clk26m", + "osc_d2", + "univpll_d6_d2", + "univpll_d6_d4" +}; + +static const char * const dsi_occ_parents[] =3D { + "clk26m", + "univpll_d6_d2", + "univpll_d5_d2", + "univpll_d4_d2" +}; + +static const char * const dxcc_parents[] =3D { + "clk26m", + "mainpll_d4_d8", + "mainpll_d4_d4", + "mainpll_d4_d2" +}; + +static const char * const i2c_parents[] =3D { + "clk26m", + "mainpll_d4_d8", + "univpll_d5_d4", + "mainpll_d4_d4" +}; + +static const char * const mcupm_parents[] =3D { + "clk26m", + "univpll_d6_d2", + "mainpll_d5_d2", + "mainpll_d6_d2" +}; + +static const char * const mfg_ref_parents[] =3D { + "clk26m", + "mainpll_d6_d2", + "mainpll_d6", + "mainpll_d5_d2" +}; + +static const char * const msdc30_h_parents[] =3D { + "clk26m", + "msdcpll_d2", + "mainpll_d4_d4", + "mainpll_d6_d4" +}; + +static const char * const msdc_macro_p_parents[] =3D { + "clk26m", + "msdcpll", + "mmpll_d5_d4", + "univpll_d4_d2" +}; + +static const char * const snps_eth_62p4m_ptp_parents[] =3D { + "clk26m", + "ethpll_d8", + "apll1_d3", + "apll2_d3" +}; + +static const char * const ufs_mbist_parents[] =3D { + "clk26m", + "mainpll_d4_d2", + "univpll_d4_d2", + "ufspll_d2" +}; + +static const char * const aes_msdcfde_parents[] =3D { + "clk26m", + "mainpll_d4_d2", + "mainpll_d6", + "mainpll_d4_d4", + "msdcpll" +}; + +static const char * const bus_aximem_parents[] =3D { + "clk26m", + "mainpll_d7_d2", + "mainpll_d5_d2", + "mainpll_d4_d2", + "mainpll_d6" +}; + +static const char * const dp_parents[] =3D { + "clk26m", + "tvdpll1_d16", + "tvdpll1_d8", + "tvdpll1_d4", + "tvdpll1_d2" +}; + +static const char * const msdc30_parents[] =3D { + "clk26m", + "univpll_d6_d2", + "mainpll_d6_d2", + "mainpll_d7_d2", + "msdcpll_d2" +}; + +static const char * const ecc_parents[] =3D { + "clk26m", + "univpll_d6_d2", + "univpll_d4_d2", + "univpll_d6", + "mainpll_d4", + "univpll_d4" +}; + +static const char * const emi_n_parents[] =3D { + "clk26m", + "osc_d2", + "mainpll_d9", + "mainpll_d6", + "mainpll_d5", + "emipll" +}; + +static const char * const sr_pka_parents[] =3D { + "clk26m", + "mainpll_d4_d4", + "mainpll_d4_d2", + "mainpll_d7", + "mainpll_d6", + "mainpll_d5" +}; + +static const char * const aes_ufsfde_parents[] =3D { + "clk26m", + "mainpll_d4", + "mainpll_d4_d2", + "mainpll_d6", + "mainpll_d4_d4", + "univpll_d4_d2", + "univpll_d6" +}; + +static const char * const axi_parents[] =3D { + "clk26m", + "mainpll_d4_d4", + "mainpll_d7_d2", + "mainpll_d4_d2", + "mainpll_d5_d2", + "mainpll_d6_d2", + "osc_d4" +}; + +static const char * const disp_pwm_parents[] =3D { + "clk26m", + "univpll_d6_d4", + "osc_d2", + "osc_d4", + "osc_d16", + "univpll_d5_d4", + "mainpll_d4_d4" +}; + +static const char * const edp_parents[] =3D { + "clk26m", + "tvdpll2_d16", + "tvdpll2_d8", + "tvdpll2_d4", + "tvdpll2_d2" +}; + +static const char * const gcpu_parents[] =3D { + "clk26m", + "mainpll_d6", + "mainpll_d4_d2", + "univpll_d4_d2", + "univpll_d5_d2", + "univpll_d5_d4", + "univpll_d6" +}; + +static const char * const msdc50_0_parents[] =3D { + "clk26m", + "msdcpll", + "msdcpll_d2", + "mainpll_d6_d2", + "mainpll_d4_d4", + "mainpll_d6", + "univpll_d4_d4" +}; + +static const char * const ufs_parents[] =3D { + "clk26m", + "mainpll_d4_d8", + "mainpll_d4_d4", + "mainpll_d5_d2", + "mainpll_d6_d2", + "univpll_d6_d2", + "msdcpll_d2" +}; + +static const char * const dsp_parents[] =3D { + "clk26m", + "osc_d4", + "osc_d3", + "osc_d2", + "univpll_d7_d2", + "univpll_d6_d2", + "mainpll_d6", + "univpll_d5" +}; + +static const char * const mem_sub_peri_u_parents[] =3D { + "clk26m", + "univpll_d4_d4", + "mainpll_d5_d2", + "mainpll_d4_d2", + "mainpll_d6", + "mainpll_d5", + "univpll_d5", + "mainpll_d4" +}; + +static const char * const seninf_parents[] =3D { + "clk26m", + "osc_d2", + "univpll_d6_d2", + "mainpll_d4_d2", + "univpll_d4_d2", + "mmpll_d7", + "univpll_d6", + "univpll_d5" +}; + +static const char * const sflash_parents[] =3D { + "clk26m", + "mainpll_d7_d8", + "univpll_d6_d8", + "mainpll_d7_d4", + "mainpll_d6_d4", + "univpll_d6_d4", + "univpll_d7_d3", + "univpll_d5_d4" +}; + +static const char * const spi_parents[] =3D { + "clk26m", + "univpll_d6_d2", + "univpll_192m", + "mainpll_d6_d2", + "univpll_d4_d4", + "mainpll_d4_d4", + "univpll_d5_d4", + "univpll_d6_d4" +}; + +static const char * const img1_parents[] =3D { + "clk26m", + "univpll_d4", + "mmpll_d5", + "mmpll_d6", + "univpll_d6", + "mmpll_d7", + "mmpll_d4_d2", + "univpll_d4_d2", + "mainpll_d4_d2", + "mmpll_d6_d2", + "mmpll_d5_d2" +}; + +static const char * const ipe_parents[] =3D { + "clk26m", + "univpll_d4", + "mainpll_d4", + "mmpll_d6", + "univpll_d6", + "mainpll_d6", + "mmpll_d4_d2", + "univpll_d4_d2", + "mainpll_d4_d2", + "mmpll_d6_d2", + "mmpll_d5_d2" +}; + +static const char * const mem_sub_parents[] =3D { + "clk26m", + "univpll_d4_d4", + "mainpll_d6_d2", + "mainpll_d5_d2", + "mainpll_d4_d2", + "mainpll_d6", + "mmpll_d7", + "mainpll_d5", + "univpll_d5", + "mainpll_d4", + "univpll_d4" +}; + +static const char * const cam_parents[] =3D { + "clk26m", + "mainpll_d4", + "mmpll_d4", + "univpll_d4", + "univpll_d5", + "mmpll_d7", + "mmpll_d6", + "univpll_d6", + "univpll_d4_d2", + "mmpll_d9", + "mainpll_d4_d2", + "osc_d2" +}; + +static const char * const mmsys_parents[] =3D { + "clk26m", + "mainpll_d5_d2", + "univpll_d5_d2", + "mainpll_d4_d2", + "univpll_d4_d2", + "mainpll_d6", + "univpll_d6", + "mmpll_d6", + "tvdpll1", + "tvdpll2", + "univpll_d4", + "mmpll_d4" +}; + +static const char * const mminfra_parents[] =3D { + "clk26m", + "osc_d2", + "mainpll_d5_d2", + "mmpll_d6_d2", + "mainpll_d4_d2", + "mmpll_d4_d2", + "mainpll_d6", + "mmpll_d7", + "univpll_d6", + "mainpll_d5", + "mmpll_d6", + "univpll_d5", + "mainpll_d4", + "univpll_d4", + "mmpll_d4", + "emipll" +}; + +static const char * const vdec_parents[] =3D { + "clk26m", + "univpll_192m_d2", + "univpll_d5_d4", + "mainpll_d5", + "mainpll_d5_d2", + "mmpll_d6_d2", + "univpll_d5_d2", + "mainpll_d4_d2", + "univpll_d4_d2", + "univpll_d7", + "mmpll_d7", + "mmpll_d6", + "univpll_d6", + "mainpll_d4", + "univpll_d4", + "mmpll_d5_d2" +}; + +static const char * const venc_parents[] =3D { + "clk26m", + "mmpll_d4_d2", + "mainpll_d6", + "univpll_d4_d2", + "mainpll_d4_d2", + "univpll_d6", + "mmpll_d6", + "mainpll_d5_d2", + "mainpll_d6_d2", + "mmpll_d9", + "mmpll_d4", + "mainpll_d4", + "univpll_d4", + "univpll_d5", + "univpll_d5_d2", + "mainpll_d5" +}; + +static const struct mtk_mux top_muxes[] =3D { + /* CLK_CFG_0 */ + MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, "axi_sel", + axi_parents, 0x010, 0x014, 0x018, 0, 3, 0x04, 0), + MUX_CLR_SET_UPD(CLK_TOP_AXI_PERI_SEL, "axi_peri_sel", + axi_peri_parents, 0x010, 0x014, 0x018, + 8, 2, 0x04, 1), + MUX_CLR_SET_UPD(CLK_TOP_AXI_U_SEL, "axi_u_sel", + axi_u_parents, 0x010, 0x014, 0x018, + 16, 2, 0x04, 2), + MUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel", + bus_aximem_parents, 0x010, 0x014, 0x018, + 24, 3, 0x04, 3), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP0_SEL, "disp0_sel", + mmsys_parents, 0x020, 0x024, 0x028, + 0, 4, 7, 0x04, 4), + MUX_CLR_SET_UPD(CLK_TOP_MMINFRA_SEL, "mminfra_sel", + mminfra_parents, 0x020, 0x024, 0x028, + 8, 4, 0x04, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", + uart_parents, 0x020, 0x024, 0x028, + 16, 1, 23, 0x04, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI0_SEL, "spi0_sel", + spi_parents, 0x020, 0x024, 0x028, + 24, 3, 31, 0x04, 7), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI1_SEL, "spi1_sel", + spi_parents, 0x030, 0x034, 0x038, + 0, 3, 7, 0x04, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI2_SEL, "spi2_sel", + spi_parents, 0x030, 0x034, 0x038, + 8, 3, 15, 0x04, 9), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI3_SEL, "spi3_sel", + spi_parents, 0x030, 0x034, 0x038, + 16, 3, 23, 0x04, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI4_SEL, "spi4_sel", + spi_parents, 0x030, 0x034, 0x038, + 24, 3, 31, 0x04, 11), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI5_SEL, "spi5_sel", + spi_parents, 0x040, 0x044, 0x048, + 0, 3, 7, 0x04, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_0P_SEL, "msdc_macro_0p_sel", + msdc_macro_p_parents, 0x040, 0x044, 0x048, + 8, 2, 15, 0x04, 13), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk_sel", + msdc5hclk_parents, 0x040, 0x044, 0x048, + 16, 2, 23, 0x04, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", + msdc50_0_parents, 0x040, 0x044, 0x048, + 24, 3, 31, 0x04, 15), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel", + aes_msdcfde_parents, 0x050, 0x054, 0x058, + 0, 3, 7, 0x04, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_1P_SEL, "msdc_macro_1p_sel", + msdc_macro_p_parents, 0x050, 0x054, 0x058, + 8, 2, 15, 0x04, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", + msdc30_parents, 0x050, 0x054, 0x058, + 16, 3, 23, 0x04, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_HCLK_SEL, "msdc30_1_h_sel", + msdc30_h_parents, 0x050, 0x054, 0x058, + 24, 2, 31, 0x04, 19), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_2P_SEL, "msdc_macro_2p_sel", + msdc_macro_p_parents, 0x060, 0x064, 0x068, + 0, 2, 7, 0x04, 20), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", + msdc30_parents, 0x060, 0x064, 0x068, + 8, 3, 15, 0x04, 21), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_HCLK_SEL, "msdc30_2_h_sel", + msdc30_h_parents, 0x060, 0x064, 0x068, + 16, 2, 23, 0x04, 22), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", + aud_intbus_parents, 0x060, 0x064, 0x068, + 24, 2, 31, 0x04, 23), + /* CLK_CFG_6 */ + MUX_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", + atb_parents, 0x070, 0x074, 0x078, 0, 2, 0x04, 24), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", + disp_pwm_parents, 0x070, 0x074, 0x078, + 8, 3, 15, 0x04, 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P0_SEL, "usb_p0_sel", + usb_parents, 0x070, 0x074, 0x078, + 16, 2, 23, 0x04, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P0_SEL, "ssusb_xhci_p0_sel", + usb_parents, 0x070, 0x074, 0x078, + 24, 2, 31, 0x04, 27), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P1_SEL, "usb_p1_sel", + usb_parents, 0x080, 0x084, 0x088, + 0, 2, 7, 0x04, 28), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "ssusb_xhci_p1_sel", + usb_parents, 0x080, 0x084, 0x088, + 8, 2, 15, 0x04, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P2_SEL, "usb_p2_sel", + usb_parents, 0x080, 0x084, 0x088, + 16, 2, 23, 0x04, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P2_SEL, "ssusb_xhci_p2_sel", + usb_parents, 0x080, 0x084, 0x088, + 24, 2, 31, 0x08, 0), + /* CLK_CFG_8 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P3_SEL, "usb_p3_sel", + usb_parents, 0x090, 0x094, 0x098, + 0, 2, 7, 0x08, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P3_SEL, "ssusb_xhci_p3_sel", + usb_parents, 0x090, 0x094, 0x098, + 8, 2, 15, 0x08, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P4_SEL, "usb_p4_sel", + usb_parents, 0x090, 0x094, 0x098, + 16, 2, 23, 0x08, 3), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P4_SEL, "ssusb_xhci_p4_sel", + usb_parents, 0x090, 0x094, 0x098, + 24, 2, 31, 0x08, 4), + /* CLK_CFG_9 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", + i2c_parents, 0x0a0, 0x0a4, 0x0a8, + 0, 2, 7, 0x08, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", + seninf_parents, 0x0a0, 0x0a4, 0x0a8, + 8, 3, 15, 0x08, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel", + seninf_parents, 0x0a0, 0x0a4, 0x0a8, + 16, 3, 23, 0x08, 7), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", + aud_engen1_parents, 0x0a0, 0x0a4, 0x0a8, + 24, 2, 31, 0x08, 8), + /* CLK_CFG_10 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", + aud_engen2_parents, 0x0b0, 0x0b4, 0x0b8, + 0, 2, 7, 0x08, 9), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel", + aes_ufsfde_parents, 0x0b0, 0x0b4, 0x0b8, + 8, 3, 15, 0x08, 10), + MUX_CLR_SET_UPD(CLK_TOP_U_SEL, "ufs_sel", + ufs_parents, 0x0b0, 0x0b4, 0x0b8, + 16, 3, 0x08, 11), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U_MBIST_SEL, "ufs_mbist_sel", + ufs_mbist_parents, 0x0b0, 0x0b4, 0x0b8, + 24, 2, 31, 0x08, 12), + /* CLK_CFG_11 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", + aud_1_parents, 0x0c0, 0x0c4, 0x0c8, + 0, 1, 7, 0x08, 13), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", + aud_2_parents, 0x0c0, 0x0c4, 0x0c8, + 8, 1, 15, 0x08, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel", + venc_parents, 0x0c0, 0x0c4, 0x0c8, + 16, 4, 23, 0x08, 15), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", + vdec_parents, 0x0c0, 0x0c4, 0x0c8, + 24, 4, 31, 0x08, 16), + /* CLK_CFG_12 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", + pwm_parents, 0x0d0, 0x0d4, 0x0d8, + 0, 1, 7, 0x08, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel", + audio_h_parents, 0x0d0, 0x0d4, 0x0d8, + 8, 2, 15, 0x08, 18), + MUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, "mcupm_sel", + mcupm_parents, 0x0d0, 0x0d4, 0x0d8, + 16, 2, 0x08, 19), + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_SEL, "mem_sub_sel", + mem_sub_parents, 0x0d0, 0x0d4, 0x0d8, + 24, 4, 0x08, 20), + /* CLK_CFG_13 */ + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_PERI_SEL, "mem_sub_peri_sel", + mem_sub_peri_u_parents, 0x0e0, 0x0e4, 0x0e8, + 0, 3, 0x08, 21), + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_U_SEL, "mem_sub_u_sel", + mem_sub_peri_u_parents, 0x0e0, 0x0e4, 0x0e8, + 8, 3, 0x08, 22), + MUX_CLR_SET_UPD(CLK_TOP_EMI_N_SEL, "emi_n_sel", + emi_n_parents, 0x0e0, 0x0e4, 0x0e8, + 16, 3, 0x08, 23), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC_SEL, "dsi_occ_sel", + dsi_occ_parents, 0x0e0, 0x0e4, 0x0e8, + 24, 2, 31, 0x08, 24), + /* CLK_CFG_14 */ + MUX_CLR_SET_UPD(CLK_TOP_AP2CONN_HOST_SEL, "ap2conn_host_sel", + ap2conn_host_parents, 0x0f0, 0x0f4, 0x0f8, + 0, 1, 0x08, 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel", + img1_parents, 0x0f0, 0x0f4, 0x0f8, + 8, 4, 15, 0x08, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel", + ipe_parents, 0x0f0, 0x0f4, 0x0f8, + 16, 4, 23, 0x08, 27), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel", + cam_parents, 0x0f0, 0x0f4, 0x0f8, + 24, 4, 31, 0x08, 28), + /* CLK_CFG_15 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", + camtm_parents, 0x100, 0x104, 0x108, + 0, 2, 7, 0x08, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", + dsp_parents, 0x100, 0x104, 0x108, + 8, 3, 15, 0x08, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SR_PKA_SEL, "sr_pka_sel", + sr_pka_parents, 0x100, 0x104, 0x108, + 16, 3, 23, 0x0c, 0), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", + dxcc_parents, 0x100, 0x104, 0x108, + 24, 2, 31, 0x0c, 1), + /* CLK_CFG_16 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel", + mfg_ref_parents, 0x110, 0x114, 0x118, + 0, 2, 7, 0x0c, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP0_SEL, "mdp0_sel", + mmsys_parents, 0x110, 0x114, 0x118, + 8, 4, 15, 0x0c, 3), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DP_SEL, "dp_sel", + dp_parents, 0x110, 0x114, 0x118, + 16, 3, 23, 0x0c, 4), + MUX_CLR_SET_UPD(CLK_TOP_EDP_SEL, "edp_sel", + edp_parents, 0x110, 0x114, 0x118, + 24, 3, 0x0c, 5), + /* CLK_CFG_17 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_FAVT_SEL, "edp_favt_sel", + edp_parents, 0x180, 0x184, 0x188, + 0, 3, 7, 0x0c, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_250M_SEL, "snps_eth_250m_sel", + snps_eth_250m_parents, 0x180, 0x184, 0x188, + 8, 1, 15, 0x0c, 7), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_62P4M_PTP_SEL, + "snps_eth_62p4m_ptp_sel", + snps_eth_62p4m_ptp_parents, + 0x180, 0x184, 0x188, 16, 2, 23, 0x0c, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_50M_RMII_SEL, + "snps_eth_50m_rmii_sel", + snps_eth_50m_rmii_parents, + 0x180, 0x184, 0x188, 24, 1, 31, 0x0c, 9), + /* CLK_CFG_18 */ + MUX_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel", + sflash_parents, 0x190, 0x194, 0x198, + 0, 3, 0x0c, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", + gcpu_parents, 0x190, 0x194, 0x198, + 8, 3, 15, 0x0c, 11), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MAC_TL_SEL, "pcie_mac_tl_sel", + pcie_mac_tl_parents, 0x190, 0x194, 0x198, + 16, 2, 23, 0x0c, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDSTX_DG_CTS_SEL, "vdstx_dg_cts_sel", + vdstx_dg_cts_parents, 0x190, 0x194, 0x198, + 24, 2, 31, 0x0c, 13), + /* CLK_CFG_19 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PLL_DPIX_SEL, "pll_dpix_sel", + pll_dpix_parents, 0x240, 0x244, 0x248, + 0, 2, 7, 0x0c, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", + ecc_parents, 0x240, 0x244, 0x248, + 8, 3, 15, 0x0c, 15), + /* CLK_MISC_CFG_3 */ + GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MFG_SEL_MFGPLL, "mfg_sel_mfgpll", + mfg_sel_mfgpll_parents, + 0x510, 0x514, 0x0518, 16, 1, 0, -1, -1, + CLK_SET_RATE_PARENT, + mtk_mux_clr_set_upd_ops) +}; + +static const struct mtk_composite top_composites[] =3D { + /* CLK_AUDDIV_0 */ + MUX(CLK_TOP_APLL_I2SIN0_MCK_SEL, "apll_i2sin0_m_sel", + apll_m_parents, 0x0320, 16, 1), + MUX(CLK_TOP_APLL_I2SIN1_MCK_SEL, "apll_i2sin1_m_sel", + apll_m_parents, 0x0320, 17, 1), + MUX(CLK_TOP_APLL_I2SIN2_MCK_SEL, "apll_i2sin2_m_sel", + apll_m_parents, 0x0320, 18, 1), + MUX(CLK_TOP_APLL_I2SIN3_MCK_SEL, "apll_i2sin3_m_sel", + apll_m_parents, 0x0320, 19, 1), + MUX(CLK_TOP_APLL_I2SIN4_MCK_SEL, "apll_i2sin4_m_sel", + apll_m_parents, 0x0320, 20, 1), + MUX(CLK_TOP_APLL_I2SIN6_MCK_SEL, "apll_i2sin6_m_sel", + apll_m_parents, 0x0320, 21, 1), + MUX(CLK_TOP_APLL_I2SOUT0_MCK_SEL, "apll_i2sout0_m_sel", + apll_m_parents, 0x0320, 22, 1), + MUX(CLK_TOP_APLL_I2SOUT1_MCK_SEL, "apll_i2sout1_m_sel", + apll_m_parents, 0x0320, 23, 1), + MUX(CLK_TOP_APLL_I2SOUT2_MCK_SEL, "apll_i2sout2_m_sel", + apll_m_parents, 0x0320, 24, 1), + MUX(CLK_TOP_APLL_I2SOUT3_MCK_SEL, "apll_i2sout3_m_sel", + apll_m_parents, 0x0320, 25, 1), + MUX(CLK_TOP_APLL_I2SOUT4_MCK_SEL, "apll_i2sout4_m_sel", + apll_m_parents, 0x0320, 26, 1), + MUX(CLK_TOP_APLL_I2SOUT6_MCK_SEL, "apll_i2sout6_m_sel", + apll_m_parents, 0x0320, 27, 1), + MUX(CLK_TOP_APLL_FMI2S_MCK_SEL, "apll_fmi2s_m_sel", + apll_m_parents, 0x0320, 28, 1), + MUX(CLK_TOP_APLL_TDMOUT_MCK_SEL, "apll_tdmout_m_sel", + apll_m_parents, 0x0320, 29, 1), + /* CLK_AUDDIV_2 */ + DIV_GATE(CLK_TOP_APLL12_CK_DIV_I2SIN0, "apll12_div_i2sin0", + "apll_i2sin0_m_sel", 0x0320, 0, 0x0328, 8, 0), + DIV_GATE(CLK_TOP_APLL12_CK_DIV_I2SIN1, "apll12_div_i2sin1", + "apll_i2sin1_m_sel", 0x0320, 1, 0x0328, 8, 8), + /* CLK_AUDDIV_3 */ + DIV_GATE(CLK_TOP_APLL12_CK_DIV_I2SOUT0, "apll12_div_i2sout0", + "apll_i2sout0_m_sel", 0x0320, 6, 0x0334, 8, 16), + DIV_GATE(CLK_TOP_APLL12_CK_DIV_I2SOUT1, "apll12_div_i2sout1", + "apll_i2sout1_m_sel", 0x0320, 7, 0x0334, 8, 24), + /* CLK_AUDDIV_5 */ + DIV_GATE(CLK_TOP_APLL12_CK_DIV_FMI2S, "apll12_div_fmi2s", + "apll_fmi2s_m_sel", 0x0320, 12, 0x033c, 8, 0), + DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_M, "apll12_div_tdmout_m", + "apll_tdmout_m_sel", 0x0320, 13, 0x033c, 8, 8), + DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_B, "apll12_div_tdmout_b", + "apll12_div_tdmout_m", 0x0320, 14, 0x033c, 8, 16), +}; + +static const struct mtk_gate_regs top_cg_regs =3D { + .set_ofs =3D 0x514, + .clr_ofs =3D 0x518, + .sta_ofs =3D 0x510, +}; + +#define GATE_TOP_FLAGS(_id, _name, _parent, _shift, _flag) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &top_cg_regs, \ + .shift =3D _shift, \ + .flags =3D _flag, \ + .ops =3D &mtk_clk_gate_ops_setclr_inv, \ + } + +#define GATE_TOP(_id, _name, _parent, _shift) \ + GATE_TOP_FLAGS(_id, _name, _parent, _shift, 0) + +static const struct mtk_gate top_clks[] =3D { + GATE_TOP_FLAGS(CLK_TOP_FMCNT_P0_EN, "fmcnt_p0_en", "univpll_192m_d4", 0, = CLK_IS_CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_FMCNT_P1_EN, "fmcnt_p1_en", "univpll_192m_d4", 1, = CLK_IS_CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_FMCNT_P2_EN, "fmcnt_p2_en", "univpll_192m_d4", 2, = CLK_IS_CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_FMCNT_P3_EN, "fmcnt_p3_en", "univpll_192m_d4", 3, = CLK_IS_CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_FMCNT_P4_EN, "fmcnt_p4_en", "univpll_192m_d4", 4, = CLK_IS_CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_USB_F26M_CK_EN, "ssusb_f26m", "clk26m", 5, CLK_IS_= CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_SSPXTP_F26M_CK_EN, "sspxtp_f26m", "clk26m", 6, CLK= _IS_CRITICAL), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P0_EN, "usb2_phy_rf_p0_en", "ssusb_f26m", 7), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P1_EN, "usb2_phy_rf_p1_en", "ssusb_f26m", 10= ), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P2_EN, "usb2_phy_rf_p2_en", "ssusb_f26m", 11= ), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P3_EN, "usb2_phy_rf_p3_en", "ssusb_f26m", 12= ), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P4_EN, "usb2_phy_rf_p4_en", "ssusb_f26m", 13= ), + GATE_TOP_FLAGS(CLK_TOP_USB2_26M_CK_P0_EN, "usb2_26m_p0_en", "ssusb_f26m",= 14, CLK_IS_CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_USB2_26M_CK_P1_EN, "usb2_26m_p1_en", "ssusb_f26m",= 15, CLK_IS_CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_USB2_26M_CK_P2_EN, "usb2_26m_p2_en", "ssusb_f26m",= 18, CLK_IS_CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_USB2_26M_CK_P3_EN, "usb2_26m_p3_en", "ssusb_f26m",= 19, CLK_IS_CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_USB2_26M_CK_P4_EN, "usb2_26m_p4_en", "ssusb_f26m",= 20, CLK_IS_CRITICAL), + GATE_TOP(CLK_TOP_F26M_CK_EN, "pcie_f26m", "sspxtp_f26m", 21), + GATE_TOP_FLAGS(CLK_TOP_AP2CON_EN, "ap2con", "clk26m", 24, CLK_IS_CRITICAL= ), + GATE_TOP_FLAGS(CLK_TOP_EINT_N_EN, "eint_n", "clk26m", 25, CLK_IS_CRITICAL= ), + GATE_TOP_FLAGS(CLK_TOP_TOPCKGEN_FMIPI_CSI_UP26M_CK_EN, + "fmipi_csi_up26m", "osc_d10", 26, CLK_IS_CRITICAL), + GATE_TOP_FLAGS(CLK_TOP_EINT_E_EN, "eint_e", "clk26m", 28, CLK_IS_CRITICAL= ), + GATE_TOP_FLAGS(CLK_TOP_EINT_W_EN, "eint_w", "clk26m", 30, CLK_IS_CRITICAL= ), + GATE_TOP_FLAGS(CLK_TOP_EINT_S_EN, "eint_s", "clk26m", 31, CLK_IS_CRITICAL= ), +}; + +/* Register mux notifier for MFG mux */ +static int clk_mt8189_reg_mfg_mux_notifier(struct device *dev, + struct clk *clk) +{ + struct mtk_mux_nb *mfg_mux_nb; + + mfg_mux_nb =3D devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); + if (!mfg_mux_nb) + return -ENOMEM; + + mfg_mux_nb->ops =3D &mtk_mux_clr_set_upd_ops; + mfg_mux_nb->bypass_index =3D 0; /* Bypass to CLK_TOP_MFG_REF_SEL */ + + return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); +} + +static const struct mtk_clk_desc topck_desc =3D { + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .mux_clks =3D top_muxes, + .num_mux_clks =3D ARRAY_SIZE(top_muxes), + .composite_clks =3D top_composites, + .num_composite_clks =3D ARRAY_SIZE(top_composites), + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .clk_notifier_func =3D clk_mt8189_reg_mfg_mux_notifier, + .mfg_clk_idx =3D CLK_TOP_MFG_SEL_MFGPLL, + .clk_lock =3D &mt8189_clk_lock, +}; + +static const struct of_device_id of_match_clk_mt8189_topck[] =3D { + { .compatible =3D "mediatek,mt8189-topckgen", .data =3D &topck_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_topck); + +static struct platform_driver clk_mt8189_topck_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-topck", + .of_match_table =3D of_match_clk_mt8189_topck, + }, +}; +module_platform_driver(clk_mt8189_topck_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 topckgen clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8767851120E; Fri, 4 Sep 2026 15:59:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537556; cv=none; b=TpLW1kb/ou6788/WTDZ+lfu1gr85upNnwh6t04PZU121Cp/cR64WUbLhRXbBo7zdB+phRZioqi5n4LA3wFa4hxOWIKl+cJhQuP+BJqjNhqnO/bp/7dMCXelgyBdeiiMw1scRJQqzBMqNoZA299cEostMBQbJtWUelnPRaBHhh2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537556; 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support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-20-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=9918; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=LjxDRStl/SH+wCzXEFxW07v6rJLF6g/U+np170CJjnc=; b=13D9EECh9azTsa+1xmfe+3bvDYJ8lSUrQK07+QwXRWM3aOljxlTjxBklnNK7BsrofySP0kOUZ rwvIxAsiMQlAdUNSr8SR8AIZ6ctpi2u5bxczblHLC56hDojnotndlNi X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 vlpckgen clock controller, which provides muxes and dividers for clock selection in vlp domain for other IP blocks. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Makefile | 3 +- drivers/clk/mediatek/clk-mt8189-vlpckgen.c | 279 +++++++++++++++++++++++++= ++++ 2 files changed, 281 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index eb9a1f3efebe..8fc63b830467 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -124,7 +124,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) +=3D clk-mt8188-= vdo0.o clk-mt8188-vdo1.o obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) +=3D clk-mt8188-venc.o obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) +=3D clk-mt8188-vpp0.o clk-mt8188-v= pp1.o obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) +=3D clk-mt8188-wpe.o -obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o clk-mt8189-to= pckgen.o +obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o clk-mt8189-to= pckgen.o \ + clk-mt8189-vlpckgen.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-vlpckgen.c b/drivers/clk/media= tek/clk-mt8189-vlpckgen.c new file mode 100644 index 000000000000..971017f0fb99 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-vlpckgen.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-mux.h" +#include "clk-gate.h" + +static DEFINE_SPINLOCK(mt8189_vlpclk_lock); + +static const char * const vlp_26m_oscd10_parents[] =3D { + "clk26m", + "osc_d10" +}; + +static const char * const vlp_vadsp_vowpll_parents[] =3D { + "clk26m", + "vowpll" +}; + +static const char * const vlp_sspm_ulposc_parents[] =3D { + "ulposc", + "univpll_d5_d2", + "osc_d10" +}; + +static const char * const vlp_aud_adc_parents[] =3D { + "clk26m", + "vowpll", + "aud_adc_ext", + "osc_d10" +}; + +static const char * const vlp_scp_iic_spi_parents[] =3D { + "clk26m", + "mainpll_d5_d4", + "mainpll_d7_d2", + "osc_d10" +}; + +static const char * const vlp_vadsp_uarthub_b_parents[] =3D { + "clk26m", + "osc_d10", + "univpll_d6_d4", + "univpll_d6_d2" +}; + +static const char * const vlp_axi_kp_parents[] =3D { + "clk26m", + "osc_d10", + "osc_d2", + "mainpll_d7_d4", + "mainpll_d7_d2" +}; + +static const char * const vlp_sspm_parents[] =3D { + "clk26m", + "osc_d10", + "mainpll_d5_d2", + "ulposc", + "mainpll_d6" +}; + +static const char * const vlp_pwm_vlp_parents[] =3D { + "clk26m", + "osc_d4", + "clk32k", + "osc_d10", + "mainpll_d4_d8" +}; + +static const char * const vlp_pwrap_ulposc_parents[] =3D { + "clk26m", + "osc_d10", + "osc_d7", + "osc_d8", + "osc_d16", + "mainpll_d7_d8" +}; + +static const char * const vlp_vadsp_parents[] =3D { + "clk26m", + "osc_d20", + "osc_d10", + "osc_d2", + "ulposc", + "mainpll_d4_d2" +}; + +static const char * const vlp_scp_parents[] =3D { + "clk26m", + "univpll_d4", + "univpll_d3", + "mainpll_d3", + "univpll_d6", + "apll1", + "mainpll_d4", + "mainpll_d6", + "mainpll_d7", + "osc_d10" +}; + +static const char * const vlp_spmi_p_parents[] =3D { + "clk26m", + "f26m_d2", + "osc_d8", + "osc_d10", + "osc_d16", + "osc_d7", + "clk32k", + "mainpll_d7_d8", + "mainpll_d6_d8", + "mainpll_d5_d8" +}; + +static const char * const vlp_camtg_parents[] =3D { + "clk26m", + "univpll_192m_d8", + "univpll_d6_d8", + "univpll_192m_d4", + "osc_d16", + "osc_d20", + "osc_d10", + "univpll_d6_d16", + "tvdpll1_d16", + "f26m_d2", + "univpll_192m_d10", + "univpll_192m_d16", + "univpll_192m_d32" +}; + +static const struct mtk_mux vlp_ck_muxes[] =3D { + /* VLP_CLK_CFG_0 */ + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_SCP_SEL, "vlp_scp_sel", + vlp_scp_parents, 0x008, 0x00c, 0x010, + 0, 4, 7, 0x04, 0), + MUX_CLR_SET_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, "vlp_pwrap_ulposc_sel", + vlp_pwrap_ulposc_parents, 0x008, 0x00c, 0x010, + 8, 3, 0x04, 1), + MUX_CLR_SET_UPD(CLK_VLP_CK_SPMI_P_MST_SEL, "vlp_spmi_p_sel", + vlp_spmi_p_parents, 0x008, 0x00c, 0x010, + 16, 4, 0x04, 2), + MUX_CLR_SET_UPD(CLK_VLP_CK_DVFSRC_SEL, "vlp_dvfsrc_sel", + vlp_26m_oscd10_parents, 0x008, 0x00c, 0x010, + 24, 1, 0x04, 3), + /* VLP_CLK_CFG_1 */ + MUX_CLR_SET_UPD(CLK_VLP_CK_PWM_VLP_SEL, "vlp_pwm_vlp_sel", + vlp_pwm_vlp_parents, 0x014, 0x018, 0x01c, + 0, 3, 0x04, 4), + MUX_CLR_SET_UPD(CLK_VLP_CK_AXI_VLP_SEL, "vlp_axi_vlp_sel", + vlp_axi_kp_parents, 0x014, 0x018, 0x01c, + 8, 3, 0x04, 5), + MUX_CLR_SET_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, "vlp_timer_26m_sel", + vlp_26m_oscd10_parents, 0x014, 0x018, 0x01c, + 16, 1, 0x04, 6), + MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_SEL, "vlp_sspm_sel", + vlp_sspm_parents, 0x014, 0x018, 0x01c, + 24, 3, 0x04, 7), + /* VLP_CLK_CFG_2 */ + MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_F26M_SEL, "vlp_sspm_f26m_sel", + vlp_26m_oscd10_parents, 0x020, 0x024, 0x028, + 0, 1, 0x04, 8), + MUX_CLR_SET_UPD(CLK_VLP_CK_SRCK_SEL, "vlp_srck_sel", + vlp_26m_oscd10_parents, 0x020, 0x024, 0x028, + 8, 1, 0x04, 9), + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_SEL, "vlp_scp_spi_sel", + vlp_scp_iic_spi_parents, 0x020, 0x024, 0x028, + 16, 2, 0x04, 10), + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_SEL, "vlp_scp_iic_sel", + vlp_scp_iic_spi_parents, 0x020, 0x024, 0x028, + 24, 2, 0x04, 11), + /* VLP_CLK_CFG_3 */ + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, + "vlp_scp_spi_hs_sel", + vlp_scp_iic_spi_parents, 0x02c, 0x030, 0x034, + 0, 2, 0x04, 12), + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, + "vlp_scp_iic_hs_sel", + vlp_scp_iic_spi_parents, 0x02c, 0x030, 0x034, + 8, 2, 0x04, 13), + MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_ULPOSC_SEL, "vlp_sspm_ulposc_sel", + vlp_sspm_ulposc_parents, 0x02c, 0x030, 0x034, + 16, 2, 0x04, 14), + MUX_CLR_SET_UPD(CLK_VLP_CK_APXGPT_26M_SEL, "vlp_apxgpt_26m_sel", + vlp_26m_oscd10_parents, 0x02c, 0x030, 0x034, + 24, 1, 0x04, 15), + /* VLP_CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_SEL, "vlp_vadsp_sel", + vlp_vadsp_parents, 0x038, 0x03c, 0x040, + 0, 3, 7, 0x04, 16), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_VOWPLL_SEL, + "vlp_vadsp_vowpll_sel", + vlp_vadsp_vowpll_parents, 0x038, 0x03c, 0x040, + 8, 1, 15, 0x04, 17), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL, + "vlp_vadsp_uarthub_b_sel", + vlp_vadsp_uarthub_b_parents, + 0x038, 0x03c, 0x040, 16, 2, 23, 0x04, 18), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG0_SEL, "vlp_camtg0_sel", + vlp_camtg_parents, 0x038, 0x03c, 0x040, + 24, 4, 31, 0x04, 19), + /* VLP_CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG1_SEL, "vlp_camtg1_sel", + vlp_camtg_parents, 0x044, 0x048, 0x04c, + 0, 4, 7, 0x04, 20), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG2_SEL, "vlp_camtg2_sel", + vlp_camtg_parents, 0x044, 0x048, 0x04c, + 8, 4, 15, 0x04, 21), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_AUD_ADC_SEL, "vlp_aud_adc_sel", + vlp_aud_adc_parents, 0x044, 0x048, 0x04c, + 16, 2, 23, 0x04, 22), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_KP_IRQ_GEN_SEL, "vlp_kp_irq_sel", + vlp_axi_kp_parents, 0x044, 0x048, 0x04c, + 24, 3, 31, 0x04, 23), +}; + +static const struct mtk_gate_regs vlp_ck_cg_regs =3D { + .set_ofs =3D 0x1f4, + .clr_ofs =3D 0x1f8, + .sta_ofs =3D 0x1f0, +}; + +#define GATE_VLP_CK_FLAGS(_id, _name, _parent, _shift, _flag) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &vlp_ck_cg_regs, \ + .shift =3D _shift, \ + .flags =3D _flag, \ + .ops =3D &mtk_clk_gate_ops_setclr_inv, \ + } + +#define GATE_VLP_CK(_id, _name, _parent, _shift) \ + GATE_VLP_CK_FLAGS(_id, _name, _parent, _shift, 0) + +static const struct mtk_gate vlp_ck_clks[] =3D { + GATE_VLP_CK(CLK_VLP_CK_VADSYS_VLP_26M_EN, "vlp_vadsys_vlp_26m", "clk26m",= 1), + GATE_VLP_CK_FLAGS(CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN, "vlp_fmipi_csi_up26m", + "fmipi_csi_up26m", 11, CLK_IS_CRITICAL), +}; + +static const struct mtk_clk_desc vlpck_desc =3D { + .mux_clks =3D vlp_ck_muxes, + .num_mux_clks =3D ARRAY_SIZE(vlp_ck_muxes), + .clks =3D vlp_ck_clks, + .num_clks =3D ARRAY_SIZE(vlp_ck_clks), + .clk_lock =3D &mt8189_vlpclk_lock, +}; + +static const struct of_device_id of_match_clk_mt8189_vlpck[] =3D { + { .compatible =3D "mediatek,mt8189-vlpckgen", .data =3D &vlpck_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_vlpck); + +static struct platform_driver clk_mt8189_vlpck_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-vlpck", + .of_match_table =3D of_match_clk_mt8189_vlpck, + }, +}; +module_platform_driver(clk_mt8189_vlpck_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 vlpckgen clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C34B9511222; Fri, 4 Sep 2026 15:59:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537557; cv=none; b=VST1b0tCk9wPYyOKWenzvJepTHr04gTJDWRDbj/jOBYdPdPI0z/F4/AlR92n9KbK3eOUNlXwVVYFB1MStdnm4LK/ZyjT0chHKZFaUwdGs6vvy2TEjEpwfeswXZZISI8WhuCVPnNbGPtYWnYKLdbhAxIHZn0xv+LXnY7+a/KQCAg= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-21-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Brian Masney , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=6553; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=ux0vSSjTr+swLOAnTxERq/x2cUsinTHGXlrixCRPPo8=; b=h4C4te3Y39VUmlz3Mpf5kxwgosKtf8HEwWh6gEVCTxCwS/15wgsuulQMqFxf2F/37nNuNFb/t Fwtt48T01jGBGMZIr6cWYR4i02dXr5jxl7N3+qAVECquzOONrbhSZMP X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 vlpcfg clock controller, which provides clock gate control for vlp domain IPs. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Brian Masney Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8189-vlpcfg.c | 115 +++++++++++++++++++++++++++= ++++ 2 files changed, 116 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 8fc63b830467..b0fb36108179 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -125,7 +125,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) +=3D clk-mt8188= -venc.o obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) +=3D clk-mt8188-vpp0.o clk-mt8188-v= pp1.o obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) +=3D clk-mt8188-wpe.o obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o clk-mt8189-to= pckgen.o \ - clk-mt8189-vlpckgen.o + clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-vlpcfg.c b/drivers/clk/mediate= k/clk-mt8189-vlpcfg.c new file mode 100644 index 000000000000..5aa5b5179c15 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-vlpcfg.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +static const struct mtk_gate_regs vlpcfg_ao_reg_cg_regs =3D { + .set_ofs =3D 0x0, + .clr_ofs =3D 0x0, + .sta_ofs =3D 0x0, +}; + +#define GATE_VLPCFG_AO_REG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vlpcfg_ao_reg_cg_regs, _shift, &mtk_clk_ga= te_ops_no_setclr) + +static const struct mtk_gate vlpcfg_ao_reg_clks[] =3D { + GATE_VLPCFG_AO_REG(CLK_VLPCFG_AO_APEINT_RX, "vlpcfg_ao_apeint_rx", "clk26= m", 8), +}; + +static const struct mtk_clk_desc vlpcfg_ao_reg_mcd =3D { + .clks =3D vlpcfg_ao_reg_clks, + .num_clks =3D ARRAY_SIZE(vlpcfg_ao_reg_clks), +}; + +static const struct mtk_gate_regs vlpcfg_reg_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x4, +}; + +#define GATE_VLPCFG_REG_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vlpcfg_reg_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv, _flags) + +#define GATE_VLPCFG_REG(_id, _name, _parent, _shift) \ + GATE_VLPCFG_REG_FLAGS(_id, _name, _parent, _shift, 0) + +static const struct mtk_gate vlpcfg_reg_clks[] =3D { + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SCP, "vlpcfg_scp", + "vlp_scp_sel", 28, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_RG_R_APXGPT_26M, "vlpcfg_r_apxgpt_26= m", + "clk26m", 24, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_DPMSRCK_TEST, "vlpcfg_dpmsrck_test", + "clk26m", 23, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, "vlpcfg_dpmsrrtc_t= est", + "clk32k", 22, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_DPMSRULP_TEST, "vlpcfg_dpmsrulp_test= ", + "osc_d10", 21, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SPMI_P_MST, "vlpcfg_spmi_p", + "vlp_spmi_p_sel", 20, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SPMI_P_MST_32K, "vlpcfg_spmi_p_32k", + "clk32k", 18, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_PMIF_SPMI_P_SYS, "vlpcfg_pmif_spmi_p= _sys", + "vlp_pwrap_ulposc_sel", 13, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_PMIF_SPMI_P_TMR, "vlpcfg_pmif_spmi_p= _tmr", + "vlp_pwrap_ulposc_sel", 12, CLK_IS_CRITICAL), + GATE_VLPCFG_REG(CLK_VLPCFG_REG_PMIF_SPMI_M_SYS, "vlpcfg_pmif_spmi_m_sys", + "vlp_pwrap_ulposc_sel", 11), + GATE_VLPCFG_REG(CLK_VLPCFG_REG_PMIF_SPMI_M_TMR, "vlpcfg_pmif_spmi_m_tmr", + "vlp_pwrap_ulposc_sel", 10), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_DVFSRC, "vlpcfg_dvfsrc", + "vlp_dvfsrc_sel", 9, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_PWM_VLP, "vlpcfg_pwm_vlp", + "vlp_pwm_vlp_sel", 8, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SRCK, "vlpcfg_srck", + "vlp_srck_sel", 7, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SSPM_F26M, "vlpcfg_sspm_f26m", + "vlp_sspm_f26m_sel", 4, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SSPM_F32K, "vlpcfg_sspm_f32k", + "clk32k", 3, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SSPM_ULPOSC, "vlpcfg_sspm_ulposc", + "vlp_sspm_ulposc_sel", 2, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_VLP_32K_COM, "vlpcfg_vlp_32k_com", + "clk32k", 1, CLK_IS_CRITICAL), + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_VLP_26M_COM, "vlpcfg_vlp_26m_com", + "clk26m", 0, CLK_IS_CRITICAL), +}; + +static const struct mtk_clk_desc vlpcfg_reg_mcd =3D { + .clks =3D vlpcfg_reg_clks, + .num_clks =3D ARRAY_SIZE(vlpcfg_reg_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_vlpcfg[] =3D { + { .compatible =3D "mediatek,mt8189-vlpcfg", .data =3D &vlpcfg_reg_mcd }, + { .compatible =3D "mediatek,mt8189-vlpcfg-ao", .data =3D &vlpcfg_ao_reg_m= cd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_vlpcfg); + +static struct platform_driver clk_mt8189_vlpcfg_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-vlpcfg", + .of_match_table =3D of_match_clk_mt8189_vlpcfg, + }, +}; +module_platform_driver(clk_mt8189_vlpcfg_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 vlpcfg clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E343250C2A6; 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Fri, 04 Sep 2026 17:59:13 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:33 +0200 Subject: [PATCH v6 22/27] clk: mediatek: Add MT8189 bus clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-22-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=12189; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=4eaT9Eb8I87DyLuAZ1CJCPoOmHdIcdK9GPQimYQPgxc=; b=aoloe27b1SP/BspyirnBmDAQH/bj22e4pcNvRKF3YKpgw+VgP9is/fb0+kAFo7S93CAVPwFNv TGUsDs1NCe6AYk4bL8AVM5Iy25l7jpIzCys/gyMwxuXeHQW0/hjc7tg X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 bus clock controller, which provides clock gate control for infra/peri IPs (such as spi, uart, msdc, flashif ...). Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Kconfig | 11 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-bus.c | 199 ++++++++++++++++++++++++++++++= ++++ 3 files changed, 211 insertions(+) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index d1200be0166c..7b0810fb8491 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -838,6 +838,17 @@ config COMMON_CLK_MT8189 with the MediaTek MT8189 hardware capabilities, providing efficient man= agement of clock speeds and power consumption. =20 +config COMMON_CLK_MT8189_BUS + tristate "Clock driver for MediaTek MT8189 bus" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this configuration option to support the clock framework for + MediaTek MT8189 SoC bus clocks. It includes the necessary clock + management for bus-related peripherals and interconnects within the + MT8189 chipset, ensuring that all bus-related components receive the + correct clock signals for optimal performance. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index b0fb36108179..1a0de9364968 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -126,6 +126,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) +=3D clk-mt8188-= vpp0.o clk-mt8188-vpp1.o obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) +=3D clk-mt8188-wpe.o obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o clk-mt8189-to= pckgen.o \ clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o +obj-$(CONFIG_COMMON_CLK_MT8189_BUS) +=3D clk-mt8189-bus.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-bus.c b/drivers/clk/mediatek/c= lk-mt8189-bus.c new file mode 100644 index 000000000000..53afab58e1f4 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-bus.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +static const struct mtk_gate_regs ifrao0_cg_regs =3D { + .set_ofs =3D 0x80, + .clr_ofs =3D 0x84, + .sta_ofs =3D 0x90, +}; + +static const struct mtk_gate_regs ifrao1_cg_regs =3D { + .set_ofs =3D 0x88, + .clr_ofs =3D 0x8c, + .sta_ofs =3D 0x94, +}; + +static const struct mtk_gate_regs ifrao2_cg_regs =3D { + .set_ofs =3D 0xa4, + .clr_ofs =3D 0xa8, + .sta_ofs =3D 0xac, +}; + +#define GATE_IFRAO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifrao0_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) + +#define GATE_IFRAO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifrao1_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) + +#define GATE_IFRAO2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifrao2_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) + +static const struct mtk_gate ifrao_clks[] =3D { + /* IFRAO0 */ + GATE_IFRAO0(CLK_IFRAO_CQ_DMA_FPC, "ifrao_dma", "ap2con", 28), + /* IFRAO1 */ + GATE_IFRAO1(CLK_IFRAO_DEBUGSYS, "ifrao_debugsys", "axi_sel", 24), + GATE_IFRAO1(CLK_IFRAO_DBG_TRACE, "ifrao_dbg_trace", "axi_sel", 29), + /* IFRAO2 */ + GATE_IFRAO2(CLK_IFRAO_CQ_DMA, "ifrao_cq_dma", "axi_sel", 27), +}; + +static const struct mtk_clk_desc ifrao_mcd =3D { + .clks =3D ifrao_clks, + .num_clks =3D ARRAY_SIZE(ifrao_clks), +}; + +static const struct mtk_gate_regs perao0_cg_regs =3D { + .set_ofs =3D 0x24, + .clr_ofs =3D 0x28, + .sta_ofs =3D 0x10, +}; + +static const struct mtk_gate_regs perao1_cg_regs =3D { + .set_ofs =3D 0x2c, + .clr_ofs =3D 0x30, + .sta_ofs =3D 0x14, +}; + +static const struct mtk_gate_regs perao2_cg_regs =3D { + .set_ofs =3D 0x34, + .clr_ofs =3D 0x38, + .sta_ofs =3D 0x18, +}; + +#define GATE_PERAO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &perao0_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) + +#define GATE_PERAO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &perao1_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) + +#define GATE_PERAO2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &perao2_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) + +static const struct mtk_gate perao_clks[] =3D { + /* PERAO0 */ + GATE_PERAO0(CLK_PERAO_UART0, "perao_uart0", "uart_sel", 0), + GATE_PERAO0(CLK_PERAO_UART1, "perao_uart1", "uart_sel", 1), + GATE_PERAO0(CLK_PERAO_UART2, "perao_uart2", "uart_sel", 2), + GATE_PERAO0(CLK_PERAO_UART3, "perao_uart3", "uart_sel", 3), + GATE_PERAO0(CLK_PERAO_PWM_H, "perao_pwm_h", "axi_peri_sel", 4), + GATE_PERAO0(CLK_PERAO_PWM_B, "perao_pwm_b", "pwm_sel", 5), + GATE_PERAO0(CLK_PERAO_PWM_FB1, "perao_pwm_fb1", "pwm_sel", 6), + GATE_PERAO0(CLK_PERAO_PWM_FB2, "perao_pwm_fb2", "pwm_sel", 7), + GATE_PERAO0(CLK_PERAO_PWM_FB3, "perao_pwm_fb3", "pwm_sel", 8), + GATE_PERAO0(CLK_PERAO_PWM_FB4, "perao_pwm_fb4", "pwm_sel", 9), + GATE_PERAO0(CLK_PERAO_DISP_PWM0, "perao_disp_pwm0", "disp_pwm_sel", 10), + GATE_PERAO0(CLK_PERAO_DISP_PWM1, "perao_disp_pwm1", "disp_pwm_sel", 11), + GATE_PERAO0(CLK_PERAO_SPI0_B, "perao_spi0_b", "spi0_sel", 12), + GATE_PERAO0(CLK_PERAO_SPI1_B, "perao_spi1_b", "spi1_sel", 13), + GATE_PERAO0(CLK_PERAO_SPI2_B, "perao_spi2_b", "spi2_sel", 14), + GATE_PERAO0(CLK_PERAO_SPI3_B, "perao_spi3_b", "spi3_sel", 15), + GATE_PERAO0(CLK_PERAO_SPI4_B, "perao_spi4_b", "spi4_sel", 16), + GATE_PERAO0(CLK_PERAO_SPI5_B, "perao_spi5_b", "spi5_sel", 17), + GATE_PERAO0(CLK_PERAO_SPI0_H, "perao_spi0_h", "axi_peri_sel", 18), + GATE_PERAO0(CLK_PERAO_SPI1_H, "perao_spi1_h", "axi_peri_sel", 19), + GATE_PERAO0(CLK_PERAO_SPI2_H, "perao_spi2_h", "axi_peri_sel", 20), + GATE_PERAO0(CLK_PERAO_SPI3_H, "perao_spi3_h", "axi_peri_sel", 21), + GATE_PERAO0(CLK_PERAO_SPI4_H, "perao_spi4_h", "axi_peri_sel", 22), + GATE_PERAO0(CLK_PERAO_SPI5_H, "perao_spi5_h", "axi_peri_sel", 23), + GATE_PERAO0(CLK_PERAO_AXI, "perao_axi", "mem_sub_peri_sel", 24), + GATE_PERAO0(CLK_PERAO_AHB_APB, "perao_ahb_apb", "axi_peri_sel", 25), + GATE_PERAO0(CLK_PERAO_TL, "perao_tl", "pcie_mac_tl_sel", 26), + GATE_PERAO0(CLK_PERAO_REF, "perao_ref", "pcie_f26m", 27), + GATE_PERAO0(CLK_PERAO_I2C, "perao_i2c", "axi_peri_sel", 28), + GATE_PERAO0(CLK_PERAO_DMA_B, "perao_dma_b", "axi_peri_sel", 29), + /* PERAO1 */ + GATE_PERAO1(CLK_PERAO_SSUSB0_REF, "perao_ssusb0_ref", "usb2_26m_p0_en", 1= ), + GATE_PERAO1(CLK_PERAO_SSUSB0_FRMCNT, "perao_ssusb0_frmcnt", "fmcnt_p0_en"= , 2), + GATE_PERAO1(CLK_PERAO_SSUSB0_SYS, "perao_ssusb0_sys", "usb_p0_sel", 4), + GATE_PERAO1(CLK_PERAO_SSUSB0_XHCI, "perao_ssusb0_xhci", "ssusb_xhci_p0_se= l", 5), + GATE_PERAO1(CLK_PERAO_SSUSB0_F, "perao_ssusb0_f", "axi_peri_sel", 6), + GATE_PERAO1(CLK_PERAO_SSUSB0_H, "perao_ssusb0_h", "axi_peri_sel", 7), + GATE_PERAO1(CLK_PERAO_SSUSB1_REF, "perao_ssusb1_ref", "usb2_26m_p1_en", 8= ), + GATE_PERAO1(CLK_PERAO_SSUSB1_FRMCNT, "perao_ssusb1_frmcnt", "fmcnt_p1_en"= , 9), + GATE_PERAO1(CLK_PERAO_SSUSB1_SYS, "perao_ssusb1_sys", "usb_p1_sel", 11), + GATE_PERAO1(CLK_PERAO_SSUSB1_XHCI, "perao_ssusb1_xhci", "ssusb_xhci_p1_se= l", 12), + GATE_PERAO1(CLK_PERAO_SSUSB1_F, "perao_ssusb1_f", "axi_peri_sel", 13), + GATE_PERAO1(CLK_PERAO_SSUSB1_H, "perao_ssusb1_h", "axi_peri_sel", 14), + GATE_PERAO1(CLK_PERAO_SSUSB2_REF, "perao_ssusb2_ref", "usb2_26m_p2_en", 1= 5), + GATE_PERAO1(CLK_PERAO_SSUSB2_FRMCNT, "perao_ssusb2_frmcnt", "fmcnt_p2_en"= , 16), + GATE_PERAO1(CLK_PERAO_SSUSB2_SYS, "perao_ssusb2_sys", "usb_p2_sel", 18), + GATE_PERAO1(CLK_PERAO_SSUSB2_XHCI, "perao_ssusb2_xhci", "ssusb_xhci_p2_se= l", 19), + GATE_PERAO1(CLK_PERAO_SSUSB2_F, "perao_ssusb2_f", "axi_peri_sel", 20), + GATE_PERAO1(CLK_PERAO_SSUSB2_H, "perao_ssusb2_h", "axi_peri_sel", 21), + GATE_PERAO1(CLK_PERAO_SSUSB3_REF, "perao_ssusb3_ref", "usb2_26m_p3_en", 2= 3), + GATE_PERAO1(CLK_PERAO_SSUSB3_FRMCNT, "perao_ssusb3_frmcnt", "fmcnt_p3_en"= , 24), + GATE_PERAO1(CLK_PERAO_SSUSB3_SYS, "perao_ssusb3_sys", "usb_p3_sel", 26), + GATE_PERAO1(CLK_PERAO_SSUSB3_XHCI, "perao_ssusb3_xhci", "ssusb_xhci_p3_se= l", 27), + GATE_PERAO1(CLK_PERAO_SSUSB3_F, "perao_ssusb3_f", "axi_peri_sel", 28), + GATE_PERAO1(CLK_PERAO_SSUSB3_H, "perao_ssusb3_h", "axi_peri_sel", 29), + /* PERAO2 */ + GATE_PERAO2(CLK_PERAO_SSUSB4_REF, "perao_ssusb4_ref", "usb2_26m_p4_en", 0= ), + GATE_PERAO2(CLK_PERAO_SSUSB4_FRMCNT, "perao_ssusb4_frmcnt", "fmcnt_p4_en"= , 1), + GATE_PERAO2(CLK_PERAO_SSUSB4_SYS, "perao_ssusb4_sys", "usb_p4_sel", 3), + GATE_PERAO2(CLK_PERAO_SSUSB4_XHCI, "perao_ssusb4_xhci", "ssusb_xhci_p4_se= l", 4), + GATE_PERAO2(CLK_PERAO_SSUSB4_F, "perao_ssusb4_f", "axi_peri_sel", 5), + GATE_PERAO2(CLK_PERAO_SSUSB4_H, "perao_ssusb4_h", "axi_peri_sel", 6), + GATE_PERAO2(CLK_PERAO_MSDC0, "perao_msdc0", "msdc50_0_sel", 7), + GATE_PERAO2(CLK_PERAO_MSDC0_H, "perao_msdc0_h", "msdc5hclk_sel", 8), + GATE_PERAO2(CLK_PERAO_MSDC0_FAES, "perao_msdc0_faes", "aes_msdcfde_sel", = 9), + GATE_PERAO2(CLK_PERAO_MSDC0_MST_F, "perao_msdc0_mst_f", "axi_peri_sel", 1= 0), + GATE_PERAO2(CLK_PERAO_MSDC0_SLV_H, "perao_msdc0_slv_h", "axi_peri_sel", 1= 1), + GATE_PERAO2(CLK_PERAO_MSDC1, "perao_msdc1", "msdc30_1_sel", 12), + GATE_PERAO2(CLK_PERAO_MSDC1_H, "perao_msdc1_h", "msdc30_1_h_sel", 13), + GATE_PERAO2(CLK_PERAO_MSDC1_MST_F, "perao_msdc1_mst_f", "axi_peri_sel", 1= 4), + GATE_PERAO2(CLK_PERAO_MSDC1_SLV_H, "perao_msdc1_slv_h", "axi_peri_sel", 1= 5), + GATE_PERAO2(CLK_PERAO_MSDC2, "perao_msdc2", "msdc30_2_sel", 16), + GATE_PERAO2(CLK_PERAO_MSDC2_H, "perao_msdc2_h", "msdc30_2_h_sel", 17), + GATE_PERAO2(CLK_PERAO_MSDC2_MST_F, "perao_msdc2_mst_f", "axi_peri_sel", 1= 8), + GATE_PERAO2(CLK_PERAO_MSDC2_SLV_H, "perao_msdc2_slv_h", "axi_peri_sel", 1= 9), + GATE_PERAO2(CLK_PERAO_SFLASH, "perao_sflash", "sflash_sel", 20), + GATE_PERAO2(CLK_PERAO_SFLASH_F, "perao_sflash_f", "axi_peri_sel", 21), + GATE_PERAO2(CLK_PERAO_SFLASH_H, "perao_sflash_h", "axi_peri_sel", 22), + GATE_PERAO2(CLK_PERAO_SFLASH_P, "perao_sflash_p", "axi_peri_sel", 23), + GATE_PERAO2(CLK_PERAO_AUDIO0, "perao_audio0", "axi_peri_sel", 24), + GATE_PERAO2(CLK_PERAO_AUDIO1, "perao_audio1", "axi_peri_sel", 25), + GATE_PERAO2(CLK_PERAO_AUDIO2, "perao_audio2", "aud_intbus_sel", 26), + GATE_PERAO2(CLK_PERAO_AUXADC_26M, "perao_auxadc_26m", "clk26m", 27), +}; + +static const struct mtk_clk_desc perao_mcd =3D { + .clks =3D perao_clks, + .num_clks =3D ARRAY_SIZE(perao_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_bus[] =3D { + { .compatible =3D "mediatek,mt8189-infra-ao", .data =3D &ifrao_mcd }, + { .compatible =3D "mediatek,mt8189-peri-ao", .data =3D &perao_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_bus); + +static struct platform_driver clk_mt8189_bus_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-bus", + .of_match_table =3D of_match_clk_mt8189_bus, + }, +}; +module_platform_driver(clk_mt8189_bus_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 bus/peripheral clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CC124FDE7F; Fri, 4 Sep 2026 15:59:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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(No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 546C917E0C10; Fri, 04 Sep 2026 17:59:15 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:34 +0200 Subject: [PATCH v6 23/27] clk: mediatek: Add MT8189 dbgao clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-23-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=5565; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=wCAqQW2zue3J+JxZUL82vQU28yjCE/lKIbxCkIPKApw=; b=N6q0XVWb+IJ0Sr6uwBHTv7tr+DmGaMJi4rJMwJ6m3WRiwfya3fc42WP4+Q0snZ48Xhq3QQDi8 SXEVkJyPz38Deoq0EvYhxYq6eN0hY75/zkzKGR8pl/rulB+8VbYi2N/ X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 dbgao clock controller, which provides clock gate control for debug-system. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Kconfig | 10 ++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-dbgao.c | 97 +++++++++++++++++++++++++++++= ++++ 3 files changed, 108 insertions(+) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 7b0810fb8491..e92599016f3a 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -849,6 +849,16 @@ config COMMON_CLK_MT8189_BUS MT8189 chipset, ensuring that all bus-related components receive the correct clock signals for optimal performance. =20 +config COMMON_CLK_MT8189_DBGAO + tristate "Clock driver for MediaTek MT8189 debug ao" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the debug function + on MediaTek MT8189 SoCs. This includes enabling and disabling + vcore debug system clocks. If you want to control its clocks, say Y or M + to include this driver in your kernel build. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 1a0de9364968..3600dd72ab9e 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -127,6 +127,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) +=3D clk-mt8188-= wpe.o obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o clk-mt8189-to= pckgen.o \ clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o obj-$(CONFIG_COMMON_CLK_MT8189_BUS) +=3D clk-mt8189-bus.o +obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-dbgao.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-dbgao.c b/drivers/clk/mediatek= /clk-mt8189-dbgao.c new file mode 100644 index 000000000000..a74bbb2e62ae --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-dbgao.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +static const struct mtk_gate_regs dbgao_cg_regs =3D { + .set_ofs =3D 0x70, + .clr_ofs =3D 0x70, + .sta_ofs =3D 0x70, +}; + +#define GATE_DBGAO(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &dbgao_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) + +static const struct mtk_gate dbgao_clks[] =3D { + GATE_DBGAO(CLK_DBGAO_ATB_EN, "dbgao_atb_en", "atb_sel", 0), +}; + +static const struct mtk_clk_desc dbgao_mcd =3D { + .clks =3D dbgao_clks, + .num_clks =3D ARRAY_SIZE(dbgao_clks), +}; + +static const struct mtk_gate_regs dem0_cg_regs =3D { + .set_ofs =3D 0x2c, + .clr_ofs =3D 0x2c, + .sta_ofs =3D 0x2c, +}; + +static const struct mtk_gate_regs dem1_cg_regs =3D { + .set_ofs =3D 0x30, + .clr_ofs =3D 0x30, + .sta_ofs =3D 0x30, +}; + +static const struct mtk_gate_regs dem2_cg_regs =3D { + .set_ofs =3D 0x70, + .clr_ofs =3D 0x70, + .sta_ofs =3D 0x70, +}; + +#define GATE_DEM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &dem0_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) + +#define GATE_DEM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &dem1_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) + +#define GATE_DEM2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &dem2_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) + +static const struct mtk_gate dem_clks[] =3D { + /* DEM0 */ + GATE_DEM0(CLK_DEM_BUSCLK_EN, "dem_busclk_en", "axi_sel", 0), + /* DEM1 */ + GATE_DEM1(CLK_DEM_SYSCLK_EN, "dem_sysclk_en", "axi_sel", 0), + /* DEM2 */ + GATE_DEM2(CLK_DEM_ATB_EN, "dem_atb_en", "atb_sel", 0), +}; + +static const struct mtk_clk_desc dem_mcd =3D { + .clks =3D dem_clks, + .num_clks =3D ARRAY_SIZE(dem_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_dbgao[] =3D { + { .compatible =3D "mediatek,mt8189-dbg-ao", .data =3D &dbgao_mcd }, + { .compatible =3D "mediatek,mt8189-dem", .data =3D &dem_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dbgao); + +static struct platform_driver clk_mt8189_dbgao_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-dbgao", + .of_match_table =3D of_match_clk_mt8189_dbgao, + }, +}; +module_platform_driver(clk_mt8189_dbgao_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 dbgao system clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4C20511E8A; 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Fri, 04 Sep 2026 17:59:16 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:35 +0200 Subject: [PATCH v6 24/27] clk: mediatek: Add MT8189 dvfsrc clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-24-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=4437; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=KZ2aGw2z9TaYvzFKZSBv4047AGkQQAyaABS+rNEywEQ=; b=jmCeb5wAQpFh1uLlW25e7/Z+PJD4puuDNoTrfjL6hfrJWZb0VNJe5XHxOiy0G1VCzzv758mKq q06uFfmXNyBAVa77CLKhxahr0MEfPMDxgy7sWnZYEetS7Kxl+Y8MuHK X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 dvfsrc clock controller, which provides clock gate control for dram dvfs. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Kconfig | 10 ++++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-dvfsrc.c | 57 ++++++++++++++++++++++++++++= ++++ 3 files changed, 68 insertions(+) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index e92599016f3a..9ed3f7b155ff 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -859,6 +859,16 @@ config COMMON_CLK_MT8189_DBGAO vcore debug system clocks. If you want to control its clocks, say Y or M to include this driver in your kernel build. =20 +config COMMON_CLK_MT8189_DVFSRC + tristate "Clock driver for MediaTek MT8189 dvfsrc" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the dvfsrc + on MediaTek MT8189 SoCs. This includes enabling and disabling + vcore dvfs clocks. If you want to control its clocks, say Y or M + to include this driver in your kernel build. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 3600dd72ab9e..822abeae205b 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -128,6 +128,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixed= sys.o clk-mt8189-topckgen.o clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o obj-$(CONFIG_COMMON_CLK_MT8189_BUS) +=3D clk-mt8189-bus.o obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-dbgao.o +obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) +=3D clk-mt8189-dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-dvfsrc.c b/drivers/clk/mediate= k/clk-mt8189-dvfsrc.c new file mode 100644 index 000000000000..443e951a2299 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +static const struct mtk_gate_regs dvfsrc_top_cg_regs =3D { + .set_ofs =3D 0x0, + .clr_ofs =3D 0x0, + .sta_ofs =3D 0x0, +}; + +#define GATE_DVFSRC_TOP_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &dvfsrc_top_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv, _flags) + +static const struct mtk_gate dvfsrc_top_clks[] =3D { + GATE_DVFSRC_TOP_FLAGS(CLK_DVFSRC_TOP_DVFSRC_EN, "dvfsrc_dvfsrc_en", + "clk26m", 0, CLK_IS_CRITICAL), +}; + +static const struct mtk_clk_desc dvfsrc_top_mcd =3D { + .clks =3D dvfsrc_top_clks, + .num_clks =3D ARRAY_SIZE(dvfsrc_top_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_dvfsrc[] =3D { + { .compatible =3D "mediatek,mt8189-dvfsrc-top", .data =3D &dvfsrc_top_mcd= }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dvfsrc); + +static struct platform_driver clk_mt8189_dvfsrc_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-dvfsrc", + .of_match_table =3D of_match_clk_mt8189_dvfsrc, + }, +}; +module_platform_driver(clk_mt8189_dvfsrc_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 dvfsrc clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C7DF51354F; Fri, 4 Sep 2026 15:59:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537563; cv=none; b=LyeqbcpETj6ZLAichcHnpev4twNDreibb3G/0XN4ThErDreEP1OIWt97SR2snqkb0VjoeYuWMn7bJ3WFpUoGyH5i6zUzPV6X3lo9bxT3m/9WGDm9HKVL6DyJA6mV0tBEx+4oaooeBD3iYB67MKduPM4r6jTlK8CYmL91oO+aOu0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788537563; c=relaxed/simple; bh=S6RE8DMZLw3o8SY3x9yBDlGJ+lT5My7SLZmkJBI85oA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 04 Sep 2026 17:59:18 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:36 +0200 Subject: [PATCH v6 25/27] clk: mediatek: Add MT8189 i2c clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-25-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=6555; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=S6RE8DMZLw3o8SY3x9yBDlGJ+lT5My7SLZmkJBI85oA=; b=3BXQmqZbRN6avFT0oW6W5IzWF9yFB+K5Ay1Xcm2j+/UwDrpGJUxiTu5b2Z7Pzi+b/oQjEjFMq eV/Rtol0PIfC8Izm5aZt9oDX4JZaZUw46XdwYff6mHE675R/Qk9n+aQ X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 i2c clock controller, which provides clock gate control for i2c. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Kconfig | 13 ++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-iic.c | 121 ++++++++++++++++++++++++++++++= ++++ 3 files changed, 135 insertions(+) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 9ed3f7b155ff..7b3bc27edbe3 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -869,6 +869,19 @@ config COMMON_CLK_MT8189_DVFSRC vcore dvfs clocks. If you want to control its clocks, say Y or M to include this driver in your kernel build. =20 +config COMMON_CLK_MT8189_IIC + tristate "Clock driver for MediaTek MT8189 iic" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this option to support the clock framework for MediaTek MT8189 + integrated circuits (iic). This driver is responsible for managing + clock sources, dividers, and gates specifically designed for MT8189 + SoCs. Enabling this driver ensures that the system can correctly + manage clock frequencies and power for various components within + the MT8189 chipset, improving the overall performance and power + efficiency of the device. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 822abeae205b..5e35185d23b0 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -129,6 +129,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixed= sys.o clk-mt8189-topckgen.o obj-$(CONFIG_COMMON_CLK_MT8189_BUS) +=3D clk-mt8189-bus.o obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-dbgao.o obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) +=3D clk-mt8189-dvfsrc.o +obj-$(CONFIG_COMMON_CLK_MT8189_IIC) +=3D clk-mt8189-iic.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-iic.c b/drivers/clk/mediatek/c= lk-mt8189-iic.c new file mode 100644 index 000000000000..d574fa5f892e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-iic.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +static const struct mtk_gate_regs impe_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPE(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &impe_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) + +static const struct mtk_gate impe_clks[] =3D { + GATE_IMPE(CLK_IMPE_I2C0, "impe_i2c0", "i2c_sel", 0), + GATE_IMPE(CLK_IMPE_I2C1, "impe_i2c1", "i2c_sel", 1), +}; + +static const struct mtk_clk_desc impe_mcd =3D { + .clks =3D impe_clks, + .num_clks =3D ARRAY_SIZE(impe_clks), +}; + +static const struct mtk_gate_regs impen_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPEN(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &impen_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) + +static const struct mtk_gate impen_clks[] =3D { + GATE_IMPEN(CLK_IMPEN_I2C7, "impen_i2c7", "i2c_sel", 0), + GATE_IMPEN(CLK_IMPEN_I2C8, "impen_i2c8", "i2c_sel", 1), +}; + +static const struct mtk_clk_desc impen_mcd =3D { + .clks =3D impen_clks, + .num_clks =3D ARRAY_SIZE(impen_clks), +}; + +static const struct mtk_gate_regs imps_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPS(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &imps_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) + +static const struct mtk_gate imps_clks[] =3D { + GATE_IMPS(CLK_IMPS_I2C3, "imps_i2c3", "i2c_sel", 0), + GATE_IMPS(CLK_IMPS_I2C4, "imps_i2c4", "i2c_sel", 1), + GATE_IMPS(CLK_IMPS_I2C5, "imps_i2c5", "i2c_sel", 2), + GATE_IMPS(CLK_IMPS_I2C6, "imps_i2c6", "i2c_sel", 3), +}; + +static const struct mtk_clk_desc imps_mcd =3D { + .clks =3D imps_clks, + .num_clks =3D ARRAY_SIZE(imps_clks), +}; + +static const struct mtk_gate_regs impws_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPWS(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &impws_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) + +static const struct mtk_gate impws_clks[] =3D { + GATE_IMPWS(CLK_IMPWS_I2C2, "impws_i2c2", "i2c_sel", 0), +}; + +static const struct mtk_clk_desc impws_mcd =3D { + .clks =3D impws_clks, + .num_clks =3D ARRAY_SIZE(impws_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_iic[] =3D { + { .compatible =3D "mediatek,mt8189-iic-wrap-e", .data =3D &impe_mcd }, + { .compatible =3D "mediatek,mt8189-iic-wrap-en", .data =3D &impen_mcd }, + { .compatible =3D "mediatek,mt8189-iic-wrap-s", .data =3D &imps_mcd }, + { .compatible =3D "mediatek,mt8189-iic-wrap-ws", .data =3D &impws_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_iic); + +static struct platform_driver clk_mt8189_iic_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-iic", + .of_match_table =3D of_match_clk_mt8189_iic, + }, +}; +module_platform_driver(clk_mt8189_iic_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 iic clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 838494FECCC; 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Fri, 04 Sep 2026 17:59:19 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:37 +0200 Subject: [PATCH v6 26/27] clk: mediatek: Add MT8189 scp clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-26-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=4970; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=Ay44pYArtbKhsePk0Zo5kYWyEZr8Y2LAZ5HauRRXQSE=; b=M01tcSBwTZSCieVUXJ+UZWyJ+cvDOggj2geUli+9isaO60ETk/EqbXbUABAr+YohALGbn1aIg 1SwDlhmiProCvIZqqHbgY7SzoYL+2GFzZPVgHPuoDcjxBdQn3xCePGi X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 scp clock controller, which provides clock gate control for System Control Processor. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Kconfig | 10 +++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-scp.c | 76 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 87 insertions(+) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 7b3bc27edbe3..17e0bfa695fe 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -882,6 +882,16 @@ config COMMON_CLK_MT8189_IIC the MT8189 chipset, improving the overall performance and power efficiency of the device. =20 +config COMMON_CLK_MT8189_SCP + tristate "Clock driver for MediaTek MT8189 scp" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock framework for the System Control + Processor (SCP) in the MediaTek MT8189 SoC. This includes clock + management for SCP-related features, ensuring proper clock + distribution and gating for power efficiency and functionality. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 5e35185d23b0..e712815f7572 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -130,6 +130,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_BUS) +=3D clk-mt8189-bus= .o obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-dbgao.o obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) +=3D clk-mt8189-dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8189_IIC) +=3D clk-mt8189-iic.o +obj-$(CONFIG_COMMON_CLK_MT8189_SCP) +=3D clk-mt8189-scp.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-scp.c b/drivers/clk/mediatek/c= lk-mt8189-scp.c new file mode 100644 index 000000000000..75f087d819c0 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-scp.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +static const struct mtk_gate_regs scp_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x4, +}; + +#define GATE_SCP(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &scp_cg_regs, _shift, &mtk_clk_gate_ops_set= clr_inv) + +static const struct mtk_gate scp_clks[] =3D { + GATE_SCP(CLK_SCP_SET_SPI0, "scp_set_spi0", "clk26m", 0), + GATE_SCP(CLK_SCP_SET_SPI1, "scp_set_spi1", "clk26m", 1), +}; + +static const struct mtk_clk_desc scp_mcd =3D { + .clks =3D scp_clks, + .num_clks =3D ARRAY_SIZE(scp_clks), +}; + +static const struct mtk_gate_regs scp_iic_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_SCP_IIC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &scp_iic_cg_regs, _shift, &mtk_clk_gate_ops= _setclr_inv) + +static const struct mtk_gate scp_iic_clks[] =3D { + GATE_SCP_IIC(CLK_SCP_IIC_I2C0_W1S, "scp_iic_i2c0_w1s", "vlp_scp_iic_sel",= 0), + GATE_SCP_IIC(CLK_SCP_IIC_I2C1_W1S, "scp_iic_i2c1_w1s", "vlp_scp_iic_sel",= 1), +}; + +static const struct mtk_clk_desc scp_iic_mcd =3D { + .clks =3D scp_iic_clks, + .num_clks =3D ARRAY_SIZE(scp_iic_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_scp[] =3D { + { .compatible =3D "mediatek,mt8189-scp-clk", .data =3D &scp_mcd }, + { .compatible =3D "mediatek,mt8189-scp-i2c-clk", .data =3D &scp_iic_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_scp); + +static struct platform_driver clk_mt8189_scp_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-scp", + .of_match_table =3D of_match_clk_mt8189_scp, + }, +}; +module_platform_driver(clk_mt8189_scp_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 scp clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Sat Sep 26 03:57:32 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 776164FECD8; Fri, 4 Sep 2026 15:59:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 04 Sep 2026 17:59:20 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 04 Sep 2026 17:58:38 +0200 Subject: [PATCH v6 27/27] clk: mediatek: Add MT8189 ufs clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-mt8189-clocks-system-base-v6-27-5df247f56938@collabora.com> References: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Chen-Yu Tsai , Philipp Zabel , Edward-JW Yang Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Irving-CH Lin , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788537522; l=7212; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=EGj2aW5bcUNOlKPHbeNUQG61OkeUalWoaaxG01CFuNE=; b=+GKwMOkeKwczgutIQSXD7JgbCNYLSCVDjCl4OhjCGryvx1aUYUQV6rMaZo1PtkjblIC+ndb1K XzvaoXZexZ/DI9CJh9An/kwwhkD48CoIbtFEGsTSXccj0eJcyk+GoYJ X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for the MT8189 ufs clock controller, which provides clock gate control for Universal Flash Storage. Co-developed-by: Irving-CH Lin Signed-off-by: Irving-CH Lin Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Kconfig | 12 ++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-ufs.c | 132 ++++++++++++++++++++++++++++++= ++++ 3 files changed, 145 insertions(+) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 17e0bfa695fe..d26c07afd085 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -892,6 +892,18 @@ config COMMON_CLK_MT8189_SCP management for SCP-related features, ensuring proper clock distribution and gating for power efficiency and functionality. =20 +config COMMON_CLK_MT8189_UFS + tristate "Clock driver for MediaTek MT8189 ufs" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the Universal Flash + Storage (UFS) interface on MediaTek MT8189 SoCs. This includes + clock sources, dividers, and gates that are specific to the UFS + feature of the MT8189 platform. It is recommended to enable this + option if the system includes a UFS device that relies on the MT8189 + SoC for clock management. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e712815f7572..a0bba466bb93 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -131,6 +131,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-d= bgao.o obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) +=3D clk-mt8189-dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8189_IIC) +=3D clk-mt8189-iic.o obj-$(CONFIG_COMMON_CLK_MT8189_SCP) +=3D clk-mt8189-scp.o +obj-$(CONFIG_COMMON_CLK_MT8189_UFS) +=3D clk-mt8189-ufs.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-ufs.c b/drivers/clk/mediatek/c= lk-mt8189-ufs.c new file mode 100644 index 000000000000..ec98fe01a598 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-ufs.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025-2026 MediaTek Inc. + * Qiqi Wang + * Irving-CH Lin + * Copyright (C) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * Louis-Alexis Eyraud + */ + +#include +#include + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#define MT8189_UFSCFG_AO_RST0_SET_OFFSET 0x48 +#define MT8189_UFSCFG_PDN_RST0_SET_OFFSET 0x48 + +static const struct mtk_gate_regs ufscfg_ao_reg_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0xc, + .sta_ofs =3D 0x4, +}; + +#define GATE_UFSCFG_AO_REG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ufscfg_ao_reg_cg_regs, _shift, &mtk_clk_ga= te_ops_setclr) + +static const struct mtk_gate ufscfg_ao_reg_clks[] =3D { + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM, + "ufscfg_ao_unipro_tx_sym", "clk26m", 1), + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0, + "ufscfg_ao_unipro_rx_sym0", "clk26m", 2), + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1, + "ufscfg_ao_unipro_rx_sym1", "clk26m", 3), + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_SYS, + "ufscfg_ao_unipro_sys", "ufs_sel", 4), + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_U_SAP_CFG, + "ufscfg_ao_u_sap_cfg", "clk26m", 5), + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS, + "ufscfg_ao_u_phy_ahb_s_bus", "axi_u_sel", 6), +}; + +static u16 ufscfg_ao_rst_ofs[] =3D { + MT8189_UFSCFG_AO_RST0_SET_OFFSET, +}; + +static u16 ufscfg_ao_rst_idx_map[] =3D { + [MT8189_UFSAO_RST_UFS_MPHY] =3D 8, +}; + +static const struct mtk_clk_rst_desc ufscfg_ao_rst_desc =3D { + .version =3D MTK_RST_SET_CLR, + .rst_bank_ofs =3D ufscfg_ao_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(ufscfg_ao_rst_ofs), + .rst_idx_map =3D ufscfg_ao_rst_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(ufscfg_ao_rst_idx_map), +}; + +static const struct mtk_clk_desc ufscfg_ao_reg_mcd =3D { + .clks =3D ufscfg_ao_reg_clks, + .num_clks =3D ARRAY_SIZE(ufscfg_ao_reg_clks), + .rst_desc =3D &ufscfg_ao_rst_desc, +}; + +static const struct mtk_gate_regs ufscfg_pdn_reg_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0xc, + .sta_ofs =3D 0x4, +}; + +#define GATE_UFSCFG_PDN_REG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ufscfg_pdn_reg_cg_regs, _shift, &mtk_clk_g= ate_ops_setclr) + +static const struct mtk_gate ufscfg_pdn_reg_clks[] =3D { + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_UFS, + "ufscfg_ufshci_ufs", "ufs_sel", 0), + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_AES, + "ufscfg_ufshci_aes", "aes_ufsfde_sel", 1), + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AHB, + "ufscfg_ufshci_u_ahb", "axi_u_sel", 3), + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AXI, + "ufscfg_ufshci_u_axi", "mem_sub_u_sel", 5), +}; + +static u16 ufscfg_pdn_rst_ofs[] =3D { + MT8189_UFSCFG_PDN_RST0_SET_OFFSET, +}; + +static u16 ufscfg_pdn_rst_idx_map[] =3D { + [MT8189_UFSPDN_RST_UFS_UNIPRO] =3D 0, + [MT8189_UFSPDN_RST_UFS_CRYPTO] =3D 1, + [MT8189_UFSPDN_RST_UFS_HCI] =3D 2, +}; + +static const struct mtk_clk_rst_desc ufscfg_pdn_rst_desc =3D { + .version =3D MTK_RST_SET_CLR, + .rst_bank_ofs =3D ufscfg_pdn_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(ufscfg_pdn_rst_ofs), + .rst_idx_map =3D ufscfg_pdn_rst_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(ufscfg_pdn_rst_idx_map), +}; + +static const struct mtk_clk_desc ufscfg_pdn_reg_mcd =3D { + .clks =3D ufscfg_pdn_reg_clks, + .num_clks =3D ARRAY_SIZE(ufscfg_pdn_reg_clks), + .rst_desc =3D &ufscfg_pdn_rst_desc, +}; + +static const struct of_device_id of_match_clk_mt8189_ufs[] =3D { + { .compatible =3D "mediatek,mt8189-ufscfg-ao", .data =3D &ufscfg_ao_reg_m= cd }, + { .compatible =3D "mediatek,mt8189-ufscfg-pdn", .data =3D &ufscfg_pdn_reg= _mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_ufs); + +static struct platform_driver clk_mt8189_ufs_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-ufs", + .of_match_table =3D of_match_clk_mt8189_ufs, + }, +}; +module_platform_driver(clk_mt8189_ufs_drv); + +MODULE_DESCRIPTION("MediaTek MT8189 ufs clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.55.0