From nobody Sat Sep 26 06:28:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0E31355F57; Thu, 3 Sep 2026 23:16:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788477388; cv=none; b=TEBZmDt+ly6qtq5MWIN7w/Vb9WrmfBe/nT+NvhWl0d++6a51m7hknQe6OkugrfloInIgNgsIeQwYwSYIhaeXgFyn4v0upg9vc10UuGUUxsujBDIFlEHRbaPg5JCwWR+pzgdXs6vyNteue6axq27g7Fl4h55i18bhElqI1O4fm6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788477388; c=relaxed/simple; bh=m2xwmDCjNgWapd/DEecgRupRw6i0Ywty5yfM9Aq18Uk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E0RY9MnJQFMHXKj/pYygOU9PfmxqEpbzIQFro4uoT5lVQ8H1amRowv7PTjat/6PfwrhxbBJJwzf351AmZZ5oQRtBc2p4eP7zypN4Pys9Zpki1Wb5ixqyPRzwt4a4xXVHvHBABqqqxb9EWO0c9VGwMZ91EyuVLe/MR2oCbN/90yI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Nt6kkVtA; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Nt6kkVtA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B86731F00A3D; Thu, 3 Sep 2026 23:16:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788477387; bh=IFXug7lt8O1DzPVNSLJUroR3QNnmHPKu1MT97rRTHaI=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Nt6kkVtA9GEBFnhLv5rntBAtwXiFyMBlvFGneZw/deS78alUdT3x0vc84DvuE403a uYiwheisInO80mYHppExAc6Zy7R4U+I/XABcMKLEmvHs5OGKLL9gBAwBcZu9OeY7hY 5OCUZHdO3MijyIG/RFROkPbbuIylJVBYpP3D+lERVIeu7jviba4Ey6g11LOwghh8EA EBGPqVCvxYPQiR/J3SUd8YAyoQ7X3cVs9TTl9jAilZA0SP9vDH883zV1pfZgbv00vs vJoYAj6df6fSDfny+y9THzsWSg6IYynIJkv7K68tx5TblDEwoYGMvgngW1CbAvtHpb gIIblV5JlnP8g== From: Mark Brown Date: Fri, 04 Sep 2026 00:14:41 +0100 Subject: [PATCH 1/2] KVM: arm64: Initialise TCR2_EL2 for nVHE mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-kvm-arm64-nvhe-pie-v1-1-29d59f245e6c@kernel.org> References: <20260904-kvm-arm64-nvhe-pie-v1-0-29d59f245e6c@kernel.org> In-Reply-To: <20260904-kvm-arm64-nvhe-pie-v1-0-29d59f245e6c@kernel.org> To: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3946; i=broonie@kernel.org; h=from:subject:message-id; bh=m2xwmDCjNgWapd/DEecgRupRw6i0Ywty5yfM9Aq18Uk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqmf/CUtTD7h0oTf9EXg27od/qlpYCgCmNjCV3J HePuiZ+yiWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapn/wgAKCRAk1otyXVSH 0ObDB/9hgGOVRyo/uPUF/+4Mo1doU0+FGEjbCtpUX7IaL8wc2xbegIwVwesJfM2K9Jilr7Lq+xf lOWkYaTmbkh8fryhSLXwly8DBfAYcTAs21QXD008RptY5vkdPvKanUdT28OSIWtCVS7FRrOcPiy KdOwzQXtgGTK/pSyNVWLsWcUkDfxMAyLTUbFhyykzeTLeYWz7vINz2x8h7CF2+Ge6la3HbrCdN8 J/YkHzlksjPXWTs+/8DQGEWPdoGTxqYqiTnZBxLonYQRWz21CvGCXhrPZe4B3iiv9jHvZhXuZOC f6rSUxNkxOpjZO4I/rwhVu/k1JEPMmOtaaINHUml2bLhomy3 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB We currently only configure TCR2_EL2 in VHE mode, this is done in __finalise_el2 which only runs for VHE. While all systems with TCR2_EL2 should have VHE support users may wish to run them in nVHE mode, for example in order to use protected VMs. Determine the value to load for TCR2_EL2 in C code in a similar manner to TCR_EL2, further patches will configure some bits in the register. When resetting back to the hypervisor stub clear all bits in the register in case something without support for TCR2_EL2 runs later. The only practical impact should be if we are started with a misconfigured TCR2_EL2. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_asm.h | 1 + arch/arm64/kernel/asm-offsets.c | 1 + arch/arm64/kvm/arm.c | 5 ++++- arch/arm64/kvm/hyp/nvhe/hyp-init.S | 18 ++++++++++++++++-- 4 files changed, 22 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_= asm.h index e5b92ac09e69..eb796436d6eb 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -208,6 +208,7 @@ extern void *__vhe_undefined_symbol; struct kvm_nvhe_init_params { unsigned long mair_el2; unsigned long tcr_el2; + unsigned long tcr2_el2; unsigned long tpidr_el2; unsigned long stack_hyp_va; unsigned long stack_pa; diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offset= s.c index 9c853ed3ceab..baffe58015d6 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -118,6 +118,7 @@ int main(void) DEFINE(HOST_DATA_CONTEXT, offsetof(struct kvm_host_data, host_ctxt)); DEFINE(NVHE_INIT_MAIR_EL2, offsetof(struct kvm_nvhe_init_params, mair_el= 2)); DEFINE(NVHE_INIT_TCR_EL2, offsetof(struct kvm_nvhe_init_params, tcr_el2)= ); + DEFINE(NVHE_INIT_TCR2_EL2, offsetof(struct kvm_nvhe_init_params, tcr2_el= 2)); DEFINE(NVHE_INIT_TPIDR_EL2, offsetof(struct kvm_nvhe_init_params, tpidr_= el2)); DEFINE(NVHE_INIT_STACK_HYP_VA, offsetof(struct kvm_nvhe_init_params, sta= ck_hyp_va)); DEFINE(NVHE_INIT_PGD_PA, offsetof(struct kvm_nvhe_init_params, pgd_pa)); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 8b080804bc90..88eb0459ad4b 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -2158,7 +2158,7 @@ static int kvm_init_vector_slots(void) static void __init cpu_prepare_hyp_mode(int cpu, u32 hyp_va_bits) { struct kvm_nvhe_init_params *params =3D per_cpu_ptr_nvhe_sym(kvm_init_par= ams, cpu); - unsigned long tcr; + unsigned long tcr, tcr2; =20 /* * Calculate the raw per-cpu offset without a translation from the @@ -2186,6 +2186,9 @@ static void __init cpu_prepare_hyp_mode(int cpu, u32 = hyp_va_bits) tcr |=3D TCR_T0SZ(hyp_va_bits); params->tcr_el2 =3D tcr; =20 + tcr2 =3D 0; + params->tcr2_el2 =3D tcr2; + params->pgd_pa =3D kvm_mmu_get_httbr(); if (is_protected_kvm_enabled()) params->hcr_el2 =3D HCR_HOST_NVHE_PROTECTED_FLAGS; diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S b/arch/arm64/kvm/hyp/nvhe/h= yp-init.S index 0b3e0b28dfc7..a39de9c20d27 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S @@ -137,8 +137,13 @@ alternative_if ARM64_HAS_CNP alternative_else_nop_endif msr ttbr0_el2, x2 =20 - ldr x0, [x0, #NVHE_INIT_TCR_EL2] - msr tcr_el2, x0 + ldr x1, [x0, #NVHE_INIT_TCR_EL2] + msr tcr_el2, x1 + +alternative_if ARM64_HAS_TCR2 + ldr x1, [x0, #NVHE_INIT_TCR2_EL2] + msr REG_TCR2_EL2, x1 +alternative_else_nop_endif =20 isb =20 @@ -250,6 +255,15 @@ reset: mov_q x5, INIT_SCTLR_EL2_MMU_OFF pre_disable_mmu_workaround msr sctlr_el2, x5 + +alternative_if ARM64_HAS_TCR2 + /* + * Disable any features we enabled in case the next user doesn't + * have TCR2_EL2 support. + */ + msr REG_TCR2_EL2, xzr +alternative_else_nop_endif + isb =20 /* Install stub vectors */ --=20 2.47.3 From nobody Sat Sep 26 06:28:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4ED62BF3D7; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V0sOiIJl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BB4961F00ACA; Thu, 3 Sep 2026 23:16:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788477390; bh=1eCbjHGbmxY/nyhCGTf6AjBb73myEnvNrgKOPddYfLc=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=V0sOiIJl+Q4WYRSLBHQQCYXNXd1mkSUq1Ai4YFDLpQQE3qRaBMjwFlDrR1ykfcMPL l9JbcetfjVDOkH8WzBWYL7WaenYjhGj7k2GSD1nYngreBruQfMZya5KbFpxYUr2u+n md+E8+kj1pvQcb8+MF6GqzRy4jvvdwu4Yn3iQPofHPQNhc1N28DLD6ZdAvKx6qMbMY MOF6amkqk+WbsZaZdlRDZ6ZN7PDKyIUT9Y+9XeMz4HMaDblb2z1c/ynkd034bqdQk5 JWDw5yxjC7+wPQINwiKJmoTk7ZM69cXbrWi1CVKaKq/+gbVLpmVu/3yxnL0UiHYO3v FQ8b87VLOlpWQ== From: Mark Brown Date: Fri, 04 Sep 2026 00:14:42 +0100 Subject: [PATCH 2/2] KVM: arm64: Enable S1PIE for nVHE and hVHE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260904-kvm-arm64-nvhe-pie-v1-2-29d59f245e6c@kernel.org> References: <20260904-kvm-arm64-nvhe-pie-v1-0-29d59f245e6c@kernel.org> In-Reply-To: <20260904-kvm-arm64-nvhe-pie-v1-0-29d59f245e6c@kernel.org> To: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6525; i=broonie@kernel.org; h=from:subject:message-id; bh=auU/64QYK97UJ+W8d5NRmp7HuSu6f7a4bUmrsCK67sI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqmf/DAb6imbGe0CtFU8o5PlrQ8qR72YyrstXxr DOvUqh80kaJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCapn/wwAKCRAk1otyXVSH 0BzSB/0Q1kNJ7CX3D5G+qsEnycMEw+tYeFqnMe+/JJknVwiIynh6vJXOlxzCCDRuM7JP/U083UJ DckcW4IdjP83iUebosR89QqFikUKBJKJZIIZkRmEyvS22C41pL3QrfYJyDdGa3v1sryhu721Y9c aVEYER3PLZP3DEdrjqcg1gwh7Z/UtRkhIzsNAVvoZ4TJf/2hXgOowZtD0EyUhCDoQIqRrBi/OiV 6Puo+f5NXhCy7X0X+b95v+2RDgx52kiMBgG+t/dvxHRY5YxXr7vJCIB1IopR90StUEZ1bDoma19 l0PUzRwhKcDalJby8in5HYg0uUE9v9kuP3KG6CR9tNdgHsN2 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB When FEAT_S1PIE (stage 1 permission indirection) is supported we currently enable and use it in the hypervisor when running in VHE mode but not when running in nVHE or hVHE mode. While systems with FEAT_S1PIE would normally use VHE users can configure them for nVHE or hVHE, for example in order to run protected guests. Enable FEAT_S1PIE with nVHE and hVHE. AP[1] is one of the bits used to encode the indirected permissions. Since for hVHE this is always 0 and for nVHE it is always 1 we only configure the subset of indirected permissions that the system is expected to use. With permission indirection read only permissions must be encoded in the bits used by PIE, set DBM for read only mappings. Only do this when using S1PIE, the hypervisor does not otherwise use DBM and if we were actually using DBM it would be for writable mappings. This should have no practical impact other than causing any unexpected encodings to map to no permissions instead of their default meanings. It will mean that the configuration is closer to that in VHE mode, and will be required for future work enabling features like D128 and GCS which are only available via indirection. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_asm.h | 1 + arch/arm64/include/asm/kvm_pgtable.h | 26 ++++++++++++++++++++++++++ arch/arm64/kernel/asm-offsets.c | 1 + arch/arm64/kvm/arm.c | 8 ++++++++ arch/arm64/kvm/hyp/nvhe/hyp-init.S | 6 ++++++ arch/arm64/kvm/hyp/pgtable.c | 7 +++++++ 6 files changed, 49 insertions(+) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_= asm.h index eb796436d6eb..bc587be33703 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -207,6 +207,7 @@ extern void *__vhe_undefined_symbol; =20 struct kvm_nvhe_init_params { unsigned long mair_el2; + unsigned long pir_el2; unsigned long tcr_el2; unsigned long tcr2_el2; unsigned long tpidr_el2; diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/= kvm_pgtable.h index 41a8687938eb..7c5c87c6745e 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -93,6 +93,7 @@ typedef u64 kvm_pte_t; =20 #define KVM_PTE_LEAF_ATTR_HI_S2_XN GENMASK(54, 53) =20 +#define KVM_PTE_LEAF_ATTR_HI_S1_DBM BIT(51) #define KVM_PTE_LEAF_ATTR_HI_S1_GP BIT(50) =20 #define KVM_PTE_LEAF_ATTR_S2_PERMS (KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R | \ @@ -297,6 +298,31 @@ enum kvm_pgtable_prot { #define PAGE_HYP_RO (KVM_PGTABLE_PROT_R) #define PAGE_HYP_DEVICE (PAGE_HYP | KVM_PGTABLE_PROT_DEVICE) =20 +/* + * Permission indirection configuration for the nVHE hypervisor when we + * have FEAT_S1PIE. Like the host kernel we configure a mapping + * equivalent to the non-PIE meanings of the bits so the page table + * manipulation code does not need to account for PIE. + * + * Since nVHE and hVHE fix AP[1] as 1 or 0 respectively we define + * separate PIE mappings for each. These mappings are minimal with + * only things used from the hypervisor. Write permission is + * controlled via DBM. + */ + +#define KVM_HYP_PIR_IDX(uxn, pxn, dbm, ap1) (((uxn) << 3) | ((pxn) << 2) |= \ + ((dbm) << 1) | (ap1)) + +#define KVM_NVHE_PIR_EL2 ( \ + PIRx_ELx_PERM_PREP(KVM_HYP_PIR_IDX(0, 0, 0, 1), PIE_RX) | \ + PIRx_ELx_PERM_PREP(KVM_HYP_PIR_IDX(1, 0, 0, 1), PIE_RW) | \ + PIRx_ELx_PERM_PREP(KVM_HYP_PIR_IDX(1, 0, 1, 1), PIE_R)) + +#define KVM_HVHE_PIR_EL2 ( \ + PIRx_ELx_PERM_PREP(KVM_HYP_PIR_IDX(0, 0, 0, 0), PIE_RX) | \ + PIRx_ELx_PERM_PREP(KVM_HYP_PIR_IDX(1, 1, 1, 0), PIE_R) | \ + PIRx_ELx_PERM_PREP(KVM_HYP_PIR_IDX(1, 1, 0, 0), PIE_RW)) + typedef bool (*kvm_pgtable_force_pte_cb_t)(u64 addr, u64 end, enum kvm_pgtable_prot prot); =20 diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offset= s.c index baffe58015d6..fab949435aae 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -117,6 +117,7 @@ int main(void) DEFINE(HOST_CONTEXT_VCPU, offsetof(struct kvm_cpu_context, __hyp_running= _vcpu)); DEFINE(HOST_DATA_CONTEXT, offsetof(struct kvm_host_data, host_ctxt)); DEFINE(NVHE_INIT_MAIR_EL2, offsetof(struct kvm_nvhe_init_params, mair_el= 2)); + DEFINE(NVHE_INIT_PIR_EL2, offsetof(struct kvm_nvhe_init_params, pir_el2)= ); DEFINE(NVHE_INIT_TCR_EL2, offsetof(struct kvm_nvhe_init_params, tcr_el2)= ); DEFINE(NVHE_INIT_TCR2_EL2, offsetof(struct kvm_nvhe_init_params, tcr2_el= 2)); DEFINE(NVHE_INIT_TPIDR_EL2, offsetof(struct kvm_nvhe_init_params, tpidr_= el2)); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 88eb0459ad4b..9232b4581723 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -2187,6 +2187,14 @@ static void __init cpu_prepare_hyp_mode(int cpu, u32= hyp_va_bits) params->tcr_el2 =3D tcr; =20 tcr2 =3D 0; + if (cpus_have_final_cap(ARM64_HAS_S1PIE)) { + if (cpus_have_final_cap(ARM64_KVM_HVHE)) + params->pir_el2 =3D KVM_HVHE_PIR_EL2; + else + params->pir_el2 =3D KVM_NVHE_PIR_EL2; + + tcr2 |=3D TCR2_EL2_PIE; + } params->tcr2_el2 =3D tcr2; =20 params->pgd_pa =3D kvm_mmu_get_httbr(); diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S b/arch/arm64/kvm/hyp/nvhe/h= yp-init.S index a39de9c20d27..20f926276688 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S @@ -140,6 +140,12 @@ alternative_else_nop_endif ldr x1, [x0, #NVHE_INIT_TCR_EL2] msr tcr_el2, x1 =20 +alternative_if ARM64_HAS_S1PIE + ldr x1, [x0, #NVHE_INIT_PIR_EL2] + msr REG_PIR_EL2, x1 + msr REG_PIRE0_EL2, xzr +alternative_else_nop_endif + alternative_if ARM64_HAS_TCR2 ldr x1, [x0, #NVHE_INIT_TCR2_EL2] msr REG_TCR2_EL2, x1 diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index b74dd5ce1efd..fd6854913549 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -349,6 +349,13 @@ static int hyp_set_prot_attr(enum kvm_pgtable_prot pro= t, kvm_pte_t *ptep) =20 if (system_supports_bti_kernel()) attr |=3D KVM_PTE_LEAF_ATTR_HI_S1_GP; + } else if (cpus_have_final_cap(ARM64_HAS_S1PIE) && + !(prot & KVM_PGTABLE_PROT_W)) { + /* + * When using S1PIE for nVHE set DBM for read only + * mappings since AP[2] is ineffective. + */ + attr |=3D KVM_PTE_LEAF_ATTR_HI_S1_DBM; } =20 if (cpus_have_final_cap(ARM64_KVM_HVHE)) { --=20 2.47.3